Datasheet AD5583 Datasheet (ANALOG DEVICES)

Quad, Parallel Input, Voltage Output,

44

VOD

–

+

33

A1

32

A0

31

DB11

30

DB10

29

DB9

28

DB8

26

DB7

25

DB6

24

DB5

23

DB4

21

DB3

20

DB2

19

DB1

18

DB0

34

CS

35

R/W

14

DV

DD

17

MSB

16

RS

15

LDAC

I
N
T
E
R
F
A
C
E

OE

CONTROL

LOGIC

22

DGND127DGND236DGND340V

REFHD

39

V

REFLD

41

V

REFHC

42

V

REFLC

45

V

SS2

46

V

DD2

D

O

IN

REG

D

I

47

VOC

3

V

DD1

4

V

SS1

5

VOA

2

VOB

11

R1

12

RCT

13

R2

20k

20k

1

AGND1

48

AGND2

DAC
REG

ADDR

DECODE

38

V

DD3

37

V

SS3

4 4

AD5582

–

+

10

V

REFLA

9

V

REFHA

7

V

REFLB

8

V

REFHB

a

12-/10-Bit Digital-to-Analog Converters

FEATURES
12-Bit Linearity and Monotonic AD5582
10-Bit Linearity and Monotonic AD5583
Wide Operating Range: Single 5 V to 15 V or

Dual 5 V Supply
Unipolar or Bipolar Operation
Double Buffered Registers Enable Independent or

Simultaneous Multichannel Update
4 Independent Rail-to-Rail Reference Inputs
20 mA High Current Output Drive
Parallel Interface
Data Readback Capability
5 s Settling Time
Built-In Matching Resistor Simplifies

Negative Reference
Unconditionally Stable Under Any Capacitive Loading
Compact Footprint: TSSOP-48
Extended Temperature Range: 40C to 125C

APPLICATIONS
Process Control Equipment
Closed-Loop Servo Control
Data Acquisition Systems
Digitally Controlled Calibration
Optical Network Control Loops
4 m to 20 mA Current Transmitter

AD5582/AD5583

AD5582 FUNCTIONAL BLOCK DIAGRAM

GENERAL DESCRIPTION

The AD5582/AD5583 family of quad, 12-/10-bit, voltage output
digital-to-analog converters is designed to operate from a single
5 V to 15 V or dual ± 5 V supply. It offers the user ease of use in
single- or dual-supply systems. Built using an advance BiCMOS
process, this high performance DAC is dynamically stable, capable
of high current drive, and in small form factor.

The applied external reference V
put voltage ranges from V
of full-scale outputs. For multiplying and wide dynamic appli­cations, ac reference inputs can be as high as |V

SS

built-in precision trimmed resistors
configured easily to provide four-

A doubled-buffered parallel interface offers a fast settling time.
A common level sensitive load DAC strobe (LDAC) input allows
additional simultaneous update of all DAC outputs. An external
asynchronous reset (RS) forces all registers to the zero code state
when the MSB = 0 or to midscale when the MSB = 1.

Both parts are offered in the same pinout and package to allow
users to select the appropriate resolution for a given application
without PCB layout changes.

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.

determines the full-scale out-

REF

to VDD, resulting in a wide selection

are available and can be

DD

– VSS|. Two

quadrant multiplications.

ADR421

REF

R1

R2

RCT

–

+

2.5V

DIGITAL CIRCUITRY OMITTED FOR CLARITY

V

REFHA

V

REFHB

V

REFHC

V

REFHD

V

REFLA

V

REFLB

V

REFLC

V

REFLD

DAC A

DAC B

DAC C

DAC D

2.5V

2.5V

2.5V

2.5V

AD5582/AD5583

2.5V

Figure 1. Using Built-In Matching Resistors
to Generate a Negative Voltage Reference

The AD5582 is well suited for DAC8412 replacement in medium
voltage applications in new designs, as well as any other general
purpose multichannel 10- to 12-bit applications.

The AD5582/AD5583 are specified over the extended industrial
(–40∞C to +125∞C) temperature range and offered in a thin and
compact 1.1 mm TSSOP-48 package.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2003 Analog Devices, Inc. All rights reserved.

AD5582/AD5583–SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

(VDD = +5 V, VSS = –5 V, DVDD = +5 V  10%, V
–40C < TA < +125C, unless otherwise noted.)

= +2.5 V, V

REFH

= –2.5 V,

REFL

Parameter Symbol Condition Min Typ1Max Unit

STATIC PERFORMANCE

Resolution

Relative Accuracy

2

3

N AD5582 12 Bits

AD5583 10 Bits

INL –1 +1 LSB
Differential Nonlinearity3DNL Monotonic –1 LSB
Zero-Scale Error V

ZSE

Data = 000H for AD5582 –2 +2 LSB
and AD5583

Gain Error V

Gain Error V
Full-Scale Tempco

4

GE

V

GE

GE

TCV

FS

Data = 0xFFFH for AD5582 –2 +2 LSB
Data = 0x3FFH for AD5583 –4 +4 LSB
VDD = 2.7 V to 4.5 V –4 +4 LSB

1.5 ppm/∞C

REFERENCE INPUT

V

Input Range V

REFH

Input Range

V

REFL

5

Input Resistance R

Input Capacitance

4

REF Input Current I

V

C

REF

REFH

REFL

REF

REF

REF Multiplying Bandwidth BW

REF

Data = 555H (Minimum R

)12 20 kW

REF

for AD5582 and 155H for AD5583

Data = 555H for AD5582 500 mA
Code = Full Scale 1.3 MHz

V

+ 0.5 V

REFL

V

SS

V

V

DD

REFH

– 0.5 V

80 pF

1

R1–R2 Matching R1/R2 AD5582 ± 0.025 %

AD5583 ± 0.100 %

ANALOG OUTPUT

Output Current

Output Current

Capacitive Load

6

6

4, 7

I

OUT

I

OUT

C

Data = 800H for AD5582 and ± 2mA
200

for AD5583, V

H

OUT

£ 2 mV

Data = 800H for AD5582 and

for AD5583, V

200

H

£ ± 15 mV –20 mA

V

OUT

L

No Oscillation Note 7 pF

£ |–8 mV| +20 mA

OUT

LOGIC INPUTS

Logic Input Low Voltage V

Logic Input High Voltage V

Input Leakage Current I
Input Capacitance

4

Output Voltage High V
Output Voltage Low V

IL

IH

IL

C

IL

OH

OL

DVDD = 5 V ± 10% 0.8 V

= 3 V ± 10% 0.4 V

DV

DD

DVDD = 5 V ± 10% 2.4 V
DV

= 3 V ± 10% 2.1 V

DD

0.01 1 mA

5pF
IOH = –0.8 mA 2.4 V
IOL = 1.2 mA, TA = 85∞C, 0.4 V

= 0.6 mA, DVDD = 3 V

I

OL

I

= 1.0 mA, TA = 125∞C, 0.4 V

OL

IOL = 0.5 mA, DVDD = 3 V

AC CHARACTERISTICS

Output Slew Rate SR Data = Zero Scale to Full Scale 2 V/ms

to Zero Scale
To ± 0.1% of Full Scale 5 ms

to 800H to 7FF

H

for AD5582 and 1FF

to 200

H

H

H

100 nV-s

Settling Time

8

t

S

DAC Glitch Q Code 7FF

to 1FFH for AD5583

Digital Feedthrough V

OUT/tCS

Data = Midscale, CS Toggles at 5 nV-s
f = 16 MHz

Analog Crosstalk V

Output Noise e

OUT/VREFVREF

N

= 1.5 V dc + 1 V p-p, –80 dB

Data = 000

, f = 100 kHz

H

f = 1 kHz 33 nV/÷Hz

REV. A–2–

AD5582/AD5583

Parameter Symbol Condition Min Typ

1

Max Unit

SUPPLY CHARACTERISTICS

Single-Supply Voltage Range V
Dual-Supply Voltage Range V

Digital Logic Supply DV
Positive Supply Current

6

Negative Supply Current I
Power Dissipation P
Power Supply Sensitivity P

NOTES

1

Typical specifications represent average readings measured at 25∞C.

2

DAC Output Equation: V
AD5582 = 12 bits, AD5583 = 10 bits. One LSB step voltage = (V

3

The first two codes (000H, 001H) of the AD5583 and the first four codes (000H, 001H, 002H, 003H) of the AD5582 are excluded from the linearity error measurement
in single-supply operation.

4

These parameters are guaranteed by design and not subject to production testing.

5

Dual-supply operation, V

6

Short circuit output and supply currents are 24 mA and 25 mA, respectively.

7

Part is stable under any capacitive loading conditions.

8

The settling time specification does not apply for negative-going transitions within the last 3 LSBs of ground in single-supply operation.

Specifications subject to change without notice.

= V

OUT

REFL

= VSS, exclude the lowest eight codes for the AD5582 and two codes for the AD5583 for INL and DNL errors.

REFL

+ [(V

DD

DD/VSS

I

DD

SS

DISS

SS

REFH

DD

– V

ELECTRICAL CHARACTERISTICS

VSS = 0 V 3 18 V
VDD = +2.7 V to +6.5 V, –9 +9 V

= –6.5 V to –2.7 V

V

SS

2.7 8 V
VIL = 0 V, No Load 1.7 3 mA
VIL = 0 V, No Load 1.5 3 mA
VIL = 0 V, No Load 16 30 mW
VDD = ± 5% 30 ppm/V

)  D/2N], where D = data loaded in corresponding DAC Register A, B, C, D, and N equals the number of bits;

REFL

– V

REFH

)/4096 V and (V

REFL

REFH

– V

)/1024 V for AD5582 and AD5583, respectively.

REFL

(VDD = 15 V, VSS = 0 V, DVDD = 5 V  10%, V

= 10 V, V

REFH

REFL

= 0 V,

–40C < TA < +125C, unless otherwise noted.)

Parameter Symbol Condition Min Typ1Max Unit

STATIC PERFORMANCE

Resolution

Relative Accuracy
Differential Nonlinearity
Zero-Scale Error V

2

3

N AD5582 12 Bits

AD5583 10 Bits

INL –1 +1 LSB

3

DNL Monotonic –1 LSB

ZSE

Data = 000H for AD5582 –2 +2 LSB
and AD5583

Gain Error V

Full-Scale Tempco

4

GE

V

GE

TCV

FS

Data = 0xFFFH for AD5582 –2 +2 LSB
Data = 0x3FFH for AD5583 –4 +4 LSB

1.5 ppm/∞C

REFERENCE INPUT

V

Input Range V

REFH

V

Input Range

REFL

5

Input Resistance R

Input Capacitance

4

REF Input Current I

V

C

REF

REFH

REFL

REF

REF

REF Multiplying Bandwidth BW

REF

Data = 555H (Minimum R

)12 20 kW

REF

for AD5582 and 155H for AD5583

Data = 555H for AD5582 1000 mA
Code = Full Scale 1.3 MHz

V

+ 0.5 V

REFL

V

SS

V

V

DD

REFH

– 0.5 V

80 pF

1

R1–R2 Matching R1/R2 AD5582 ± 0.025 %

AD5583 ± 0.100 %

ANALOG OUTPUT

Output Current

Output Current

Capacitive Load

6

6

4, 7

I

OUT

I

OUT

C

Data = 800H for AD5582 and 2 mA

for AD5583, V

200

H

OUT

£ 2 mV

Data = 800H for AD5582 and
200

for AD5583, V

H

£ 15 mV –20 mA

V

OUT

L

No Oscillation Note 7 pF

£ |–8 mV| +20 mA

OUT

REV. A

–3–

AD5582/AD5583

ELECTRICAL CHARACTERISTICS

(continued)

Parameter Symbol Condition Min Typ1Max Unit

LOGIC INPUTS/OUTPUTS

Logic Input Low Voltage V

Logic Input High Voltage V

Input Leakage Current I
Input Capacitance

4

Output Voltage High V
Output Voltage Low V

IL

IH

IL

C

IL

OH

OL

V

OL

= 3 V ± 10% 0.4 V

DV

DD

2.4 V

= 3 V ± 10% 2.1 V

DV

DD

IOH = –0.8 mA 2.4 V
IOL = 1.2 mA, TA = 85C, 0.4 V

= 0.6 mA, DVDD = 3 V

I

OL

IOL = 1.0 mA, TA = 125C, 0.4 V

0.8 V

mA
pF

IOL = 0.5 mA, DVDD = 3 V

AC CHARACTERISTICS

Output Slew Rate SR Data = Zero Scale to Full Scale 2 V/ms

to Zero Scale
To ± 0.1% of Full Scale 14 ms

to 800H to 7FFH for 100 nV-s

AD5582 and 1FF

H

for AD5583

1FF

H

to 200H to

H

Data = Midscale, CS Toggles at 5 nV-s

Settling Time

8

t

S

DAC Glitch Q Code 7FF

Digital Feedthrough V

OUT/tCS

f = 16 MHz
V

Analog Crosstalk V

Output Noise e

OUT/VREF

N

= 1.5 V dc + 1 V p-p, –80 dB

REF

Data = 000

, f = 100 kHz

H

f = 1 kHz 33 nV/÷Hz

SUPPLY CHARACTERISTICS

Single-Supply Voltage Range V
Dual-Supply Voltage Range V

Digital Logic Supply DV
Positive Supply Current

6

Power Dissipation P

DD

DD/VSS

I

DD

DISS

DD

VSS = 0 V 3 16.5 V
VDD = +2.7 V to +6.5 V, –6.5 +6.5 V

= –6.5 V to –2.7 V

V

SS

2.7 6.5 V
VIL = 0 V, No Load 2.3 3.5 mA
VIL = 0 V, No Load 34.5 52.5 mW

Power Supply Sensitivity PSS VDD = ± 5% 30 ppm/V

NOTES

1

Typical specifications represent average readings measured at 25∞C.

2

DAC Output Equation: V
bits; AD5582 = 12 bits, AD5583 = 10 bits. One LSB step voltage = (V

3

The first two codes (000H, 001H) of the AD5583 and the first four codes (000H, 001H, 002H, 003H) of the AD5582 are excluded from the linearity error measurement
in single-supply operation.

4

These parameters are guaranteed by design and not subject to production testing.

5

Dual-supply operation, V

6

Short circuit output and supply currents are 24 mA and 25 mA, respectively.

7

Part is stable under any capacitive loading conditions.

8

The settling time specification does not apply for negative-going transitions within the last 3 LSBs of ground in single-supply operation.

Specifications subject to change without notice.

= V

OUT

REFL

+ [(V

REFL

= VSS, exclude the lowest eight codes for the AD5582 and two codes for the AD5583 for INL and DNL errors.

REFH

– V

)  D/2N], where D = data in decimal loaded in corresponding DAC Register A, B, C, D, and N equals the number of

REFL

REFH

– V

)/4096 V and = (V

REFL

REFH

– V

)/1024 V for AD5582 and AD5583, respectively.

REFL

REV. A–4–

AD5582/AD5583

TIMING CHARACTERISTICS

(VDD = 15 V or 5 V, VSS = 0 V, DVDD = 5 V  10%, V
unless otherwise noted.)

= 10 V, V

REFH

= 0 V, –40C < TA < +125C,

REFL

Parameter Symbol Condition Min Typ Max Unit

INTERFACE TIMING*

Chip Select Write Pulse Width t
Chip Select Read Pulse Width t
Write Setup t
Write Hold t
Address Setup t
Address Hold t
Load Setup t
Load Hold t
Write Data Setup t
Write Data Hold t
Load Data Pulse Width t
Reset Pulse Width t
Read Data Hold t
Read Data Setup t
Data to Hi-Z t
Chip Select to Data t
Chip Select Repetitive Pulse Width t
Load Setup in Double Buffer Mode t
Load Data Hold t

*All input control signals are specified with tR = tF = 2 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.
Specifications subject to change without notice.

WCS

RCS

WS

WH

AS

AH

LS

LH

WDS

WDH

LDW

RESET

RDH

RDS

DZ

CSD

CSP

LDS

LDH

CL = 10 pF 100 ns
CL = 10 pF 100 ns

20 ns
130 ns
35 ns
0ns
35 ns
0ns
0ns
0ns
35 ns
0ns
20 ns
20 ns
0ns
0ns

10 ns
20 ns
0ns

TIMING CHARACTERISTICS

(VDD = 15 V or 5 V, VSS = 0 V, DVDD = 3 V  10%, V
unless otherwise noted.)

= 10 V, V

REFH

= 0 V, –40C < TA < +125C,

REFL

Parameter Symbol Condition Min Typ Max Unit

INTERFACE TIMING*

Chip Select Write Pulse Width t
Chip Select Read Pulse Width t
Write Setup t
Write Hold t
Address Setup t
Address Hold t
Load Setup t
Load Hold t
Write Data Setup t
Write Data Hold t
Load Data Pulse Width t
Reset Pulse Width t
Read Data Hold t
Read Data Setup t
Data to Hi-Z t
Chip Select to Data t
Chip Select Repetitive Pulse Width t
Load Setup in Double Buffer Mode t
Load Data Hold t

*All input control signals are specified with tR = tF = 2 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.
Specifications subject to change without notice.

WCS

RCS

WS

WH

AS

AH

LS

LH

WDS

WDH

LDW

RESET

RDH

RDS

DZ

CSD

CSP

LDS

LDH

CL = 10 pF 80 100 ns
CL = 10 pF 80 100 ns

35 ns
130 ns
50 ns
0ns
50 ns
0ns
0ns
0ns
50 ns
0ns
35 ns
35 ns
0ns
0ns

20 ns
35 ns
0ns

REV. A

–5–

AD5582/AD5583

ABSOLUTE MAXIMUM RATINGS*

VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +18 V

to GND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +18 V

V

DD

V

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –9 V

SS

to V

V

DD

to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +18 V

V

REF–

to V

V

REFH

. . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +18 V

REF+

. . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +18 V

REFL

DVDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 V

Logic Inputs to GND . . . . . . . . . . . V

to GND . . . . . . . . . . . . . . . . . VSS – 0.3 V, VDD + 0.3 V

V

OUT

I

Short Circuit to GND . . . . . . . . . . . . . . . . . . . . . . 24 mA

OUT

Thermal Resistance Junction to Ambient, 

– 0.3 V, VDD + 0.3 V

SS

. . . . . . 115∞C/W

JA

ORDERING GUIDE

Thermal Resistance Junction to Case, JC . . . . . . . . . . 42∞C/W

Maximum Junction Temperature (T

Package Power Dissipation = (T

Max) . . . . . . . . . . 150∞C

J

Max – TA)/

J

JA

Operating Temperature Range . . . . . . . . . . –40∞C to +125∞C

Storage Temperature Range . . . . . . . . . . . . –65∞C to +150∞C

Lead Temperature

RV-48 (Soldering, 60 secs) . . . . . . . . . . . . . . . . . . . . 300∞C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

1

Resolution Temperature Package Package Container Top

Model (Bits) Range Description Option Quantity Marking

AD5582YRV-REEL112 –40∞C to +125∞CTSSOP-48 RV-48 2500 AD5582Y
AD5583YRV-REEL 10 –40∞C to +125∞CTSSOP-48 RV-48 2500 AD5583Y
AD5582YRV

1

12 –40∞C to +125∞CTSSOP-48 RV-48 39 AD5582Y

AD5583YRV 10 –40∞C to +125∞CTSSOP-48 RV-48 39 AD5583Y

NOTES

1

The AD5582 contains 4116 transistors. The die size measures 108 mil  144 mil.

2

First row marking is shown in the table above. Second row marking contains date code in YYWW format. Third row marking contains the lot number.

2

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD5582/AD5583 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

REV. A–6–

AD5582 PIN CONFIGURATION

AD5582/AD5583

AGND1

VOB

V

DD1

V

SS1

VOA

NC

V

REFLB

V

REFHB

V

REFHA

V

REFLA

R1

RCT

R2

DV

DD

LDAC

RS

MSB

DB0

DB1

DB2

DB3

DGND1

DB4

DB5

1

2

3

4

5

6

7

8

9

10

AD5582

11

TOP VIEW

(Not to Scale)

12

13

14

15

16

17

18

19

20

21

22

23

24

NC = NO CONNECT

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

AGND2

VOC

V

DD2

V

SS2

VOD

NC

V

REFLC

V

REFHC

V

REFHD

V

REFLD

V

DD3

V

SS3

DGND3

R/W

CS

A1

A0

DB11

DB10

DB9

DB8

DGND2

DB7

DB6

AD5582 PIN FUNCTION DESCRIPTIONS*

Pin
No. Mnemonic Description

1 AGND1 Analog Ground for DAC A and B
2 VOB DAC B Output
3V

DD1

4V

SS1

Positive Power Supply for DAC A and B

Negative Power Supply for DAC A and B
5 VOA DAC A Output
6NCNo Connect
7V
8V
9V

10 V

REFLB

REFHB

REFHA

REFLA

DAC B Voltage Reference Low Terminal

DAC B Voltage Reference High Terminal

DAC A Voltage Reference High Terminal

DAC A Voltage Reference Low Terminal

11 R1 R1 Terminal (for Negative Reference)
12 RCT Center Tap Terminal (for Negative Reference)
13 R2 R2 Terminal (for Negative Reference)
14 DV

DD

Power Supply for Digital Circuits

15 LDAC DAC Register Load, Active Low Level Sensitive
16 RS Reset Strobe
17 MSB MSB = 0, Reset to 000

MSB = 1, Reset to 800

.

H

.

H

18 DB0 Data Bit 0
19 DB1 Data Bit 1
20 DB2 Data Bit 2
21 DB3 Data Bit 3
22 DGND1 Digital Ground 1
23 DB4 Data Bit 4

Pin
No. Mnemonic Description

25 DB6 Data Bit 6
26 DB7 Data Bit 7
27 DGND2 Digital Ground 2
28 DB8 Data Bit 8
29 DB9 Data Bit 9
30 DB10 Data Bit 10
31 DB11 Data Bit 11
32 A0 Address Input 0
33 A1 Address Input 1
34 CS Chip Select, Active Low
35 R/W Read/Write Mode Select
36 DGND3 Digital Ground 3
37 V
38 V
39 V
40 V
41 V
42 V

SS3

DD3

REFLD

REFHD

REFHC

REFLC

Negative Power Supply for Analog Switches
Positive Power Supply for Analog Switches
DAC D Voltage Reference Low Terminal
DAC D Voltage Reference High Terminal
DAC C Voltage Reference High Terminal

DAC C Voltage Reference Low Terminal
43 NC No Connect
44 VOD DAC D Output
45 V
46 V

SS2

DD2

Negative Power Supply for DAC C and D

Positive Power Supply for DAC C and D
47 VOC DAC C Output
48 AGND2 Analog Ground for DAC C and D

24 DB5 Data Bit 5

*AD5582 optimizes internal layout design to reduce die area so that all supply voltage pins are required to be connected externally. See Figure 5.

REV. A

–7–

AD5582/AD5583

AD5583 PIN CONFIGURATION

AGND1

VOB

V

DD1

V

SS1

VOA

NC

V

REFLB

V

REFHB

V

REFHA

V

REFLA

R1

RCT

R2

DV

LDAC

RS

MSB

NC

NC

DB0

DB1

DGND1

DB2

DB3

DD

1

2

3

4

5

6

7

8

9

10

AD5583

11

TOP VIEW

(Not to Scale)

12

13

14

15

16

17

18

19

20

21

22

23

24

NC = NO CONNECT

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

AGND2

VOC

V

DD2

V

SS2

VOD

NC

V

REFLC

V

REFHC

V

REFHD

V

REFLD

V

DD3

V

SS3

DGND3

R/W

CS

A1

A0

DB9

DB8

DB7

DB6

DGND2

DB5

DB4

AD5583 PIN FUNCTION DESCRIPTIONS*

Pin
No. Mnemonic Description

1 AGND1 Analog Ground for DAC A and B
2 VOB DAC B Output
3V

DD1

4V

SS1

Positive Power Supply for DAC A and B

Negative Power Supply for DAC A and B
5 VOA DAC A Output
6NCNo Connect (Do Not Connect Anything

other than Dummy Pad)
7V
8V
9V

10 V

REFLB

REFHB

REFHA

REFLA

DAC B Voltage Reference Low Terminal

DAC B Voltage Reference High Terminal

DAC A Voltage Reference High Terminal

DAC A Voltage Reference Low Terminal

11 R1 R1 Terminal (for Negative Reference)
12 RCT Center Tap Terminal (for Negative Reference)
13 R2 R2 Terminal (for Negative Reference)
14 DV

DD

Power Supply for Digital Circuits

15 LDAC DAC Register Load, Active Low Level Sensitive
16 RS Reset Strobe
17 MSB MSB = 0, Reset to 000

MSB = 1, Reset to 200

.

H

.

H

18 NC No Connect (Do Not Connect Anything

other than Dummy Pad)

19 NC No Connect (Do Not Connect Anything

other than Dummy Pad)

20 DB0 Data Bit 0
21 DB1 Data Bit 1

Pin
No. Mnemonic Description

25 DB4 Data Bit 4
26 DB5 Data Bit 5
27 DGND2 Digital Ground 2
28 DB6 Data Bit 6
29 DB7 Data Bit 7
30 DB8 Data Bit 8
31 DB9 Data Bit 9
32 A0 Address Input 0
33 A1 Address Input 1
34 CS Chip Select, Active Low
35 R/W Read/Write Mode Select
36 DGND3 Digital Ground 3
37 V
38 V
39 V
40 V
41 V
42 V

SS3

DD3

REFLD

REFHD

REFHC

REFLC

Negative Power Supply for Analog Switches
Positive Power Supply for Analog Switches
DAC D Voltage Reference Low Terminal
DAC D Voltage Reference High Terminal
DAC C Voltage Reference High Terminal
DAC C Voltage Reference Low Terminal

43 NC No Connect (Do Not Connect Anything

other than Dummy Pad)
44 VOD DAC D Output
45 V
46 V

SS2

DD2

Negative Power Supply for DAC C and D

Positive Power Supply for DAC C and D
47 VOC DAC C Output
48 AGND2 Analog Ground for DAC C and D

22 DGND1 Digital Ground 1
23 DB2 Data Bit 2
24 DB3 Data Bit 3

*AD5583 optimizes internal layout design to reduce die area so that all supply voltage pins are required to be connected externally. See Figure 5.

REV. A–8–

TIMING DIAGRAMS

R/W

ADDRESS

LDAC

CS

t

20ns

WCS =

t

WS =

t

AS =

ADDRESS

ONE

t

LS =

t

WDS =

35ns

35ns

0ns

t

CSP =

35ns

10ns

ADDRESS

TWO

ADDRESS

THREE

ADDRESS

t

LH =

t

WDH =

FOUR

0ns

0ns

AD5582/AD5583

t

0ns

WH =

DATA IN

CS

R/W

ADDRESS

LDAC

DATA1
VA LI D

DATA2
VA LI D

DATA3

VA LI D

DATA4
VA LI D

Figure 2a. Single Buffer Mode, Output Updated Individually, DVDD = 5 V

t

10ns

CSP =

t

20ns

WCS =

t

35ns

WS =

t

35ns

AS =

ADDRESS

ONE

t

WDS =

35ns

ADDRESS

TWO

ADDRESS

t

LDS =

THREE

0ns

ADDRESS

FOUR

t

0ns

LDH =

t

LDW =

20ns

t

t

WH =

WDH =

0ns

0ns

REV. A

DATA IN

DATA1

VA LI D

DATA2
VA LI D

DATA3
VA LI D

DATA4
VA LI D

Figure 2b. Double Buffer Mode, Output Updated Simultaneously, DVDD = 5 V

–9–

AD5582/AD5583

CS

R/W

A0/A1

LDAC

DATA IN

RS

t

LS =

t

WDS =

0ns

35ns

t

RESET =

20ns

t

WS =

t

AS =

t

WCS =

35ns

35ns

20ns

t

LH =

0ns

t

WDH =

t

AH =

t

WH =

0ns

0ns

0ns

t

LDW =

20ns

CS

R/W

A0/A1

DATA OUT

Figure 2c. Data Write (Input and Output Registers) Timing

t

130ns

RCS =

t

35ns

RDS =

t

35ns

AS =

t

100ns MAX

CSD =

HI-Z DATA VALID HI-Z

t

RDH =

t

AH =

0ns

0ns

t

DZ =

100ns MAX

Figure 2d. Data Output (Read Timing)

REV. A–10–

Typical Performance Characteristics–AD5582/AD5583

1.0

0.8

0.6

0.4

0.2

0

INL (LSB)

–0.2

–0.4

–0.6

–0.8

–1.0

0512 1024 2048 3072 4096

1536 2560 3584

CODE (Decimal)

TPC 1. AD5582 Integral Nonlinearity Error

1.0

0.8

0.6

0.4

0.2

0

DNL ( LSB)

–0.2

–0.4

–0.6

–0.8

–1.0

0 512 1024 2048 3072 4096

1536 2560 3584

CODE (Decimal)

TPC 2. AD5582 Differential Nonlinearity Error

1.0

0.8

0.6

0.4

0.2

0

DNL (LSB)

–0.2

–0.4

–0.6

–0.8

–1.0

01282565127681024

384 640 896

CODE (Decimal)

TPC 4. AD5583 Differential Nonlinearity Error

6

4

2

ZSE

0

DNL

ERROR (LSB)

–2

–4

–6

0510 20 30

INL

GE

15 25

VDD – V

REFH

(mV)

V

= 5V

DD

= 0V

V

SS

= 0V

V

REFL

NO LOAD

TPC 5. AD5582 INL, DNL, ZSE, and GE at Positive
Rail-to-Rail Operation

REV. A

1.0

0.8

0.6

0.4

0.2

0

INL (LSB)

–0.2

–0.4

–0.6

–0.8

–1.0

0128 256 512 768 1024

DAC-A

DAC-B

DAC-C

DAC-D

384 640 896

CODE (Decimal)

TPC 3. AD5583 Integral Nonlinearity Error

–11–

4

3

2

1

0

ERROR (LSB)

–1

–2

–3

–4

0510 20 35

DNL

GE

ZSE

INL

15 25

V

– VSS (mV)

REFL

V

= +5V

DD

= –5V

V

SS

= +4V

V

REFH

NO LOAD

30

TPC 6. AD5582 INL, DNL, GE, and ZSE at Negative
Rail-to-Rail Operation

AD5582/AD5583

1.0
V

= 5V

DD

0.8

= 5V

V

SS

= 4V

V

REFH

0.6

0.4

0.2

INL (LSB)

–0.2

–0.4

–0.6

–0.8

–1.0

= 0V

V

REFL

0

RESISTIVE LOAD RL IS BETWEEN

AND GND

V

OUT

0 512 1024 2048 4096

1536 2560

CODE (Decimal)

= 260

R

L

R

= 790

L

RL = 390

RL = NO LOAD

3072

3584

TPC 7. AD5582 INL at Various Resistive Loads

0.5
V

= 5V

DD

0.4

= 5V

V

SS

= 4V

V

REFH

0.3

0.2

0.1

DNL (LSB)

–0.1

–0.2

–0.3

–0.4

–0.5

= 0V

V

REFL

RL = NO LOAD

0

= 260

R

L

RESISTIVE LOAD RL IS BETWEEN

AND GND

V

OUT

0 512 1024 2048 4096

1536 2560

CODE (Decimal)

3072

3584

40

ZERO

30

20

10

ERROR (LSB)

–10

–20

–30

–40

SCALE
ERROR

V

> V

REFL

SS

0

GAIN
ERROR

100 1k 1M

RL_PU ()

ZERO
SCALE
ERROR

V

= V

REFL

SS

GAIN
ERROR

PULL-UP RESISTIVE LOAD R
IS BETWEEN V

10k

100k

DD

AND V

OUT

L

TPC 10. AD5582 Gain and Zero-Scale Error vs.
Pull-Up Resistive Loads

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

LINEARITY ERROR (LSB)

INL

1.0

0.5

0

02 12

DNL

V

REFH

– V

6

(V)

REFL

10

84

TPC 8. AD5582 DNL at Various Resistive Loads

0

–2

–4

–6

–8

–10

GAIN ERROR (LSB)

–12

–14

–16

100 1k 100k

= +5V OR +15V

V

DD

= –5V OR 0V

V

SS

= +4V

V

REFH

= 0V

V

REFL

V

= +15V

DD

= 0V

V

SS

= +10V

V

REFH

= 0V

V

REFL

RESISTIVE LOAD RL IS BETWEEN

AND GND

V

OUT

()

R

L

10k

TPC 9. AD5582 Gain Error vs. Resistive Load

TPC 11. AD5582 Linearity Errors vs. Differential
Reference Ranges

2.00

1.95

1.90

1.85

1.80

1.75

(mA)

DD

I

1.70

V
V
V

DD

SS

REFH

= +5V
= –5V

= +4V

V
V
V

SS

REFH

REFL

= 0V

= +4V
= 0V

1.65

1.60

1.55

1.50
02 16

6

1410

1284

VDD (V)

TPC 12. AD5582 Supply Current vs. Supply Voltage

REV. A–12–

AD5582/AD5583

3.5

3.0

2.5

= +15V

V

= +5V

V

DD

= –5V

V

SS

= –5V

V

REFL

= +5V

V

DD

= 0V

V

SS

= 0V

V

REFL

0

–10 –5 20

V

REFH

5

(V)

(mA)

DD

I

2.0

1.5

1.0

0.5

DD

= 0V

V

SS

= 0V

V

REFL

100

15

TPC 13. AD5582 Supply Current vs. Reference Voltage

4.0

3.5

3.0

2.5

2.0

(mA)

DD

I

1.5

1.0

0.5

VDD = 15V

= 0V

V

SS

= 10V

V

REFH

= 0V

V

REFL

V
V
V
V

DD

SS

REFH

REFL

= 5V

= 5V

= 4V
= 0V

300

V

= 5V

DD

= 0V

V

SS

250

200

150

100

REFERENCE CURRENT (A)

50

0

= 4V

V

REFH

= 0V

V

REFL

0 512 4096

1536

CODE (Decimal)

2560

30721024 2048

TPC 16. AD5582 Reference Current

140

120

100

80

(k)

REF

60

R

40

20

3584

0

–60 –40 140

20

TEMPERATURE (C)

60–20

100 12004080

TPC 14. AD5582 Supply Current vs. Temperature

20

VDD = 5V OR 15V

(mA)

DD

I

18

16

14

12

10

= 3V

DV

DD

= 0V

V

SS

V

= 5V OR 15V

DD

= 5V

DV

DD

= 0V

V

SS

8

6

4

2

0

01 5

2

3

VIH (V)

4

TPC 15. AD5582 Supply Current vs. Logic Input Voltage

0

0 512 4096

1536

CODE (Decimal)

2560 30721024 2048

3584

TPC 17. AD5582 Referenced Input Resistance

6

VDD = 5V 0.5V

= 0V

V

SS

= 4V

V

5

REF

DATA = 800

4

3

2

SUPPLY CURRENT (mA)

1

0

10k 100k 100M

H

CLOCK FREQUENCY (Hz)

1M

10M

TPC 18. AD5582 Supply Current vs. Clock Frequency

REV. A

–13–

AD5582/AD5583

–100

–90

–80

–70

–60

–50

PSRR (dB)

–40

–30

–20

–10

0

110 1M

100

1k

FREQUENCY (Hz)

VDD = 5V  0.5V

= 0V

V

SS

= 4V

V

REF

DATA = 800

10k 100k

H

TPC 19. AD5582 PSRR vs. Frequency

V

200mV/DIV

OUT

DATA 5V/DIV

100

90

VDD = 5V
V

= 0V

SS

V

= 2.5V

REFH

10

0

V

0.5V/DIV5s/DIV

OUT

GRAPH <1> : CL = 0
GRAPH <2> w/RINGING : C

= 10nF

L

TPC 22. Large Signal Settling When Loaded
(See Test Circuit 1)

V

5s/DIV

200mV/DIV

REF

TPC 20. Small Signal Response Operating
at Near Rail, C

100

90

10

0

= 2 nF (See Test Circuit 1)

L

VDD = 15V

V

SS

V

REFH

V

2V/DIV

OUT

5s/DIV

DATA 5V/DIV

= 0V

= 10V

TPC 21. Large Signal Settling

V

0.1V/DIV2s/DIV

OUT

TPC 23. Midscale Transition Glitch

3980

1260

398

126

39.90

12.60

4.00

AMPLITUDE (V)

1.26

0.40

0.13

0.04
1Hz 2kHz

33nV/

TPC 24. AD5582 Output Noise Density

RBW = 30Hz

Hz @ 1kHz

–

–

–

23004

7285

2300

730

230

73

23

7.3

NOISE DENSITY (nV/ Hz)

REV. A–14–

AD5582/AD5583

–

+

V

O

R

2R

2R

SW0

b0

2R

SW1

b1

2R

SW2

b2

2R

SWn–3

bn–2

2R

SWn–1

bn–1

2R

R R R

V

REFL

+

–

V

REFH

+

–

FFF

H

800

H

400

H

200

H

100

H

080

H

040

H

020

H

010

H

008

H

004

H

002

H

001

H

000

H

100 1k 10k 100k 1M 10M

TPC 25. AD5582 Multiplying Bandwidth

Test Circuit

FREQUENCY (Hz)

V

DAC

OUT

0

–24

–48

–72

ATTENUATION (dB)

–96

0.8
VDD = +5V

= –5V

V

SS

0.6
V

= +4V

REFH

= –4V

V

REFL

0.4

200

ZSE DRIFT

300

+3

+3

–3

400 500

0.2

0

ERROR (LSB)

–0.2

–0.4

–0.6

–0.8

0 100 600

HOURS OF OPERATION AT 150C

–3

GE DRIFT

TPC 26. AD5582 Long-Term Drift

V

DD

1k

C

1k

L

Test Circuit 1

THEORY OF OPERATION

The AD5582/AD5583 are quad, voltage output, 12-/10-bit parallel
input DACs in compact TSSOP-48 packages.

Each DAC is a voltage switching, high impedance (R = 20 kW),
R-2R ladder configuration with segmentation to optimize die
area and precision. Figure 3 shows a simplified R-2R structure
without the segmentation. The 2R resistances are switched
between V

REFH

and V

, and the output is obtained from

REFL

These DACs feature double buffers, which allow both synchro­nous and asynchronous channels update with additional data
readback capability. These parts can be reset to zero scale or mid­scale controlled by the RS and MSB pins. When RS is activated,
the MSB of 0 resets the DACs to zero scale and the MSB of 1
resets the DACs to midscale. The ability to operate from wide
supply voltages, +5 V to +15 V or ± 5 V, with multiplying bipolar
references is another key feature of these DACs.

the rightmost ladder node. As the code is sequenced through
all possible states, the voltage of this node changes in steps of

– V

(2/3 V

REFH

)/(2N – 1) starting from the lowest V

REFL

going to the highest V

– DUTLSB. Buffering it with an

REFH

REFL

and

amplifier with a gain of 1.5 brings the output to:

=

D

VV V

–

()

N

21–

REFH REFL REFL

+

()

(1)

V

OUT

where D is the decimal equivalent of the data bits and N is the
numbers of bits.

If –V

is equal to V

REFL

REFH

as V

REF

, V

is simplified to:

OUT

Figure 3. Simplified R-2R Architecture
(Segmentation Not Shown)

2

D

2

D

ˆ

1–

V

˜
¯

ˆ

1–

V

˜
¯

(For AD5582) (2)

(For AD5583) (3)

Power Supplies

There are three separate power supplies needed for the opera­tion of the DACs. For dual supply, V
to –2.7 V and V
supply, V

SS

can be set from +2.7 V to +6.5 V. For single

DD

should be set at 0 V while VDD is set from 3 V to

16.5 V. However, setting the single supply of V

can be set from –6.5 V

SS

below 4.5 V

DD

can impact the overall accuracy of the device.

V

V

The advantage of this scheme is that it allows the DAC to inter-

Ê

=

Á

OUT REF

Ë

4095

Ê

=

Á

OUT REF

Ë

1023

polate between two voltages for differential references or
single-ended reference.

REV. A

–15–

AD5582/AD5583

Since these DACs can be operated at high voltages, the digital
signal levels are therefore controlled separately by the provision
of DV

. DVDD can be set as low as 2.7 V but no greater than

DD

6.5 V. This allows the DAC to be operable from low level digital
signals generated from a wide range of microcontrollers, FPGA,
and signal processors.

Reference Input

All four channels of DACs allow independent and differential
reference voltages. The flexibility of independent references
allows users to apply a unique reference voltage to each channel.
Similarly, bipolar references can be applied across the differential
references. To maintain optimum accuracy, the difference between
V

REFH

and V

should be greater than 1 V. See TPC 11.

REFL

The voltages applied to these reference inputs set the output
voltage limits of all four channels of the DACs, and V
always be higher than V

+ 0.5 V to VDD, while V

V

REFL

to V

V

SS

– 0.5 V. In addition, a symmetrical negative reference

REFH

REFL

. V

can be set at any voltage from

REFH

can be set at any voltage from

REFL

REFH

must

can be generated easily by an external op amp in an inverting
mode with a pair of built-in precision resistors, R1 and R2. These
resistors are matched within ± 0.025% for the AD5582 and 0.1%
for the AD5583, which is equivalent to less than 1 LSB mis­match. Figure 4 shows a simple configuration.

Common reference or references can be applied to all four chan­nels, but each reference pin should be decoupled with a 0.1 mF
ceramic capacitor mounted close to the pin.

V

REFHA

V

REFHB

V

REFHC

V

REFHD

V

REFLA

V

REFLB

V

REFLC

V

REFLD

AD5582

DAC A

DAC B

DAC C

DAC D

2.5V

2.5V

2.5V

2.5V

RCT

ADR421

REF

R1

R2

–

+

+2.5V

–2.5V

Figure 4. Using On-Board Matching Resistors
to Generate a Negative Voltage REF

Digital I/O

Digital I/O consists of a 12-/10-bit bidirectional data bus, two
register select inputs, A0 and A1, an R/W input, a Reset (RS), a
Chip Select (CS), and a Load DAC (LDAC) input. Control of
the DACs and the bus direction is determined by these inputs
as shown in Table I. All digital pins are TTL/CMOS compat­ible and all internal registers are level triggered.

The register selects inputs A0 and A1. Decoding of the registers
is enabled by the CS input. When CS is high, no decoding is
taking place and neither the writing nor the reading of the input
registers is enabled. The loading of the second bank of registers
is controlled by the asynchronous LDAC input. By taking LDAC
low while CS is enabled, the individual channel is updated as
single buffer mode, Figure 2a. If CS is enabled sequentially to
load data into all input registers, then a subsequent LDAC pulse
will allow all channels to be updated simultaneously as double
buffer mode, Figure 2b.

R/W controls the writing to and reading from the input register.

Reset

The RS function can be used either at power-up or at any time
during operation. The RS function has priority over any other
digital inputs. This pin is active low and sets the DAC output
registers to either zero scale or midscale, determined by the state
of the MSB. The reset to midscale is useful when the DAC is
configured for bipolar references and the output will be reset to 0 V.

Output Amplifiers

Unlike many voltage output DACs, the AD5582/AD5583 feature
buffered voltage outputs with high output current driving capa­bility. Each output is capable of both sourcing and sinking ±20 mA,
eliminating the need for external buffers when driving any capaci­tive loads without oscillation. These amplifiers also have short
circuit protection.

Glitch

The worst-case glitch of the AD5582 occurs at the transitions
between midscale (1000 0000 0000
(0111 1111 1111

), or vice versa. The glitch energy is mea-

B

) to midscale minus 1

B

sured as 100 mV  1 ms or equivalent to 100 nV-s. Such glitch
occurs in a shorter duration than the settling time and therefore
most applications will be immune to such an effect without a
deglitcher.

Layout and Power Supply Bypassing

It is a good practice to employ compact, minimum lead length
PCB layout design. The leads to the input should be as short as
possible to minimize IR drop and stray inductance.

It is also essential to bypass the power supplies with quality capaci­tors for optimum stability. Supply leads to the device should be
bypassed with 0.01 mF to 0.1 mF disc or chip ceramics capacitors.
Low ESR 1 mF to 10 mF tantalum or electrolytic capacitors should
also be applied at the supplies to minimize transient disturbance.
The AD5582/AD5583 optimize internal layout design to reduce
die area so that all analog supply pins are required to be con­nected externally. See Figure 5.

AD5582/

AD5583

V

DD

V

SS

DV

DD

10F

10F

+

C2

C1

0.1F

+

C4

C3

0.1F

C5

0.1F

V

DD1

V

DD2

V

DD3

AGND1

AGND2

V

SS1

V

SS2

V

SS3

DGND

Figure 5. Power Supply Configurations

APPLICATIONS
Programmable Current Source

AD5582/AD5583 high current capability allow them to be used
directly in programmable current source applications, such as
4 m to 20 mA current transmitter and other general purpose
applications. For higher compliance voltage that is higher than
15 V, Figure 6 shows a versatile V-I conversion circuit using an
improved Howland Current Pump. In addition to the precision
current conversion it provides, this circuit enables a bidirec­tional current flow and high voltage compliance. The voltage

REV. A–16–

AD5582/AD5583

Table I. AD5582/AD5583 Logic Table

INPUT DAC OPERATION SELECTED

A1 A0 R/WCS LDAC RS REGISTER REGISTER MODE DAC

000001Write Transparent Transparent A
010001Write Transparent Transparent B
100001Write Transparent Transparent C
110001Write Transparent Transparent D
000011Write Hold Write Input A
010011Write Hold Write Input B
100011Write Hold Write Input C
110011Write Hold Write Input D
001011Read Hold Readback to D0 to DN A
011011Read Hold Readback to D0 to DN B
101011Read Hold Readback to D0 to DN C
111011Read Hold Readback to D0 to DN D
XXX101Hold Update All Registers Update All Registers All
XXX 1 1 1 Hold Hold Hold All
XXXXX0All registers reset to midscale or zero scale. All
XXX 1 X ≠ All registers latched to midscale or zero scale. All

MSB = 0 resets to zero scale, MSB = 1 resets to midscale. X: Don’t Care. Input and output registers are transparent when asserted.

compliance is mainly limited by the op amp supply voltages.
This circuit can be used in 4 to 20 mA current transmitters with
up to 500 W of load.

R2'

15k

C1

10pF

+15V

–

U4

AD8510

+

–15V

R1

R2

15k

LOAD

R3'
50

R3
50

VL

IL

+5V

U1

ADR421

+5V

–

OP1177

+

–5V

R1'

150k

+2.5V

–2.5V

+5V

V

V

V

REFH

R1
RCT
R2
V

DD

U2

AD5582

V

SS

REFL

–5V

DECOUPLING CAPS ARE OMITTED FOR CLARITY

DAC

150k

Figure 6. Programmable Current Source with Bidirectional
Current Control and High Voltage Compliance Capabilities

Figure 6 shows that if the resistor network is matched, the load
current is:

This circuit is versatile, but users must pay attention to the
compensation. Without C1, it can be shown that the output
impedance becomes:

131 2

'

Z

=

O

RR R R

+

12 3 1 2 3

''–'

RR R R R R

()

+

()

+

()

(5)

If the resistors are perfectly matched, ZO is infinite, which is
highly desirable. On the other hand, if they are not matched, Z

O

can either be positive or negative. The latter, because of the
pole in the right S-plane, can cause oscillation. As a result, C1
in the range of a few pF is needed to prevent the oscillation. For
critical applications, C1 should be found empirically without
overcompensating.

Boosted Programmable Voltage Source

For users who need higher than 20 mA current driving capabil­ity, they can add an external op amp and power transistors. The
capacitive loading capability will change, but it can still drive
100 nF capacitive load without oscillation in this circuit. Figure 7
shows a programmable power supply with 200 mA capability.

FDV30IN

LOAD

V

O

V

+5V

DD

U1

REF198

1F

C1

+4.096V

V

REFH

AD5582

V

REFL

V

DD

U2

V

SS

+15V

+

U3

OP1177

–

N1

RRR

+

231

()

I

=

L DAC

/

R

V

3

(4)

R3 in theory can be made small to achieve the current needed
within the U4 output current driving capability. In this circuit,
the AD8510 can deliver ± 20 mA in both directions and the
voltage compliance approaches ± 15 V.

REV. A

–17–

DECOUPLING CAPS ARE OMITTED FOR CLARITY

Figure 7. Boosted Programmable Voltage Source

AD5582/AD5583

V

DD

V

DD

U1

V+

U5

AD603

V–

FDBK

COMM

OUT

DV

DD

50k

50k

10k

ADR510

G+

V

DD

R3

R4

V

DD

R2

+IN

U3

–IN

V

100

+

U4

AD8565

–

R1

10k

+IN

U2

ADR510

–IN

DECOUPLING CAPS ARE OMITTED FOR CLARITY

C1

IN

R1

2.0V

VINP

0.1F
G–

VOA VOB VDD1-TO-3 VOC VOD

V

REFHA

V

REFHB

V

REFHC

V

REFHD

AD5582

V

REFLA

1.0V

V

REFLB

V

REFLC

V

REFLD

VSS1-TO-3

Figure 8. Programmable PGA

In this circuit, the inverting input of the op amp forces the VO to
be equal to the DAC output. The load current is then delivered by
the supply via the N-Ch FET N1. U3 needs to be a rail-to-rail
input type. With a V

of 5 V, this circuit can source a maximum

DD

of 200 mA at 4.096 V full scale, 100 mA at midscale, and 50 mA
near zero-scale outputs. Higher current can be achieved with N1
in a larger package mounted on a heat sink.

Programmable PGA

The AD603 is a low noise, voltage controlled amplifier for use in
RF and IF AGC (automatic gain control) systems. It provides
accurate, pin selectable gains of –11 dB to +31 dB with a band­width of 90 MHz, or 9 dB to 51 dB with a bandwidth of 9 MHz.
Any intermediate gain range may be arranged using one external
resistor between Pin 5 and Pin 7. The input referred noise spectral
density is only 1.3 nV/÷Hz and power consumption is 125 mW
at the recommended ± 5 V supplies.

V

DD

+10V+10V

C2

0.1F

G+

VINP

G–

V+

U6

AD603

V–

FDBK

COMM

OUT

C3

0.1F

V

O

The decibel gain is linear in dB, accurately calibrated, and stable
over temperature and supply. The gain is controlled at a high
impedance (50 MW), low bias (200 nA) differential input; the
scaling is 25 mV/dB, requiring a gain control voltage of only 1 V
to span the central 40 dB of the gain range. An overrange and
underrange of 1 dB is provided whatever the selected range. The
gain control response time is less than 1 ms for a 40 dB change.

The differential gain control interface allows the use of either
differential or single-ended positive or negative control voltages,
where the common-mode range is –1.2 V to +2.0 V. The
AD5582/AD5583 is ideally suited to provide the differential
input range of 1 V within the common-mode range of 0 V to 2 V.
To accomplish this, place V

REFH

at 2.0 V and V

at 1.0 V,

REFL

then all 4096 V levels of the AD5582 will fall within the gain
control range of the AD603. Please refer to the AD603 data
sheet for further information regarding gain control, layout, and
general operation.

REV. A–18–

OUTLINE DIMENSIONS

48-Lead Thin Shrink Small Outline Package [TSSOP]

(RV-48)

Dimensions shown in millimeters

12.60

12.50

12.40

AD5582/AD5583

0.15

0.05

PIN 1

1.20 MAX

SEATING

PLANE

25

6.20

6.10

6.00

8.10 BSC

241

0.75

0.60

0.45

0.20

0.09

8
0

48

0.5

BSC

0.27

0.17

COMPLIANT TO JEDEC STANDARDS MO-153ED

REV. A

–19–

AD5582/AD5583

Revision History

Location Page

8/03—Data Sheet changed from REV. 0 to REV. A.

Change to Figure 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Changes to TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Changes to PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Changes to Figures 2a, 2b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

C03040–0–8/03(A)

–20–

REV. A