Page 1
True Accuracy, 16-Bit ±12 V/±15 V,
FEATURES
Full 16-bit performance
1 LSB max INL and DNL
Output voltage range up to ±14 V
On-board reference buffers, eliminating the need for a
negative reference
Controlled output during power-on
Temperature range of −40°C to +85°C/−40°C to +125°C
Settling time of 10 µs to 0.003%
Clear function to 0 V
LDAC
Asynchronous update of outputs (
Power-on reset
Serial data output for daisy chaining
Data readback facility
APPLICATIONS
Industrial automation
Automatic test equipment
Process control
Data acquisition systems
General-purpose instrumentation
GENERAL DESCRIPTION
The AD5570 is a single 16-bit serial input, voltage output DAC
that operates from supply voltages of ±12 V up to ±15 V.
Integral linearity (INL) and differential nonlinearity (DNL) are
accurate to 1 LSB. During power-up (when the supply voltages
are changing), V
The AD5570 DAC comes complete with a set of reference
buffers. The reference buffers allow a single, positive reference
to be used. The voltage on REFIN is gained up and inverted
internally to give the positive and negative reference for the
DAC core. Having the reference buffers on-chip eliminates the
need for external components such as inverters, precision
amplifiers, and resistors, thereby reducing the overall solution
size and cost.
is clamped to 0 V via a low impedance path.
OUT
pin)
Serial Input Voltage Output DAC
AD5570
FUNCTIONAL BLOCK DIAGRAM
DGND
V
V
DD
SS
AD5570
REFGND
R
R
R
R
REFIN
LDAC
SDIN
16-BIT
DAC
DAC REGISTER
SHIFT REGISTER
SCLK
SYNC
Figure 1.
SDO
purposes. Data readback allows the user to read the contents of
the DAC register via the SDO pin.
LDAC
Features on the AD5570 include
, which may be used to
update the output of the DAC. The device also has a powerdown pin (
power state, and a
PD
), which allows the DAC to be put into a low
CLR
pin that allows the output to be cleared
to 0 V.
The AD5570 is available in a 16-lead SSOP package.
PRODUCT HIGHLIGHTS
1. 1 LSB maximum INL and DNL.
2. Buffered voltage output up to ±14 V.
POWER-ON
RESET
POWER-DOWN
CONTROL LOGIC
CLR
V
OUT
AGND
AGNDS
PD
03760-0-001
The AD5570 uses a versatile 3-wire interface that is compatible
with SPI®, QSPI™, MICROWIRE™, and DSP® interface standards.
Data is presented to the part in the format of a 16-bit serial
word. Serial data is available on the SDO pin for daisy-chaining
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
3. Output controlled during power-up.
4. On-board reference buffers.
5. Wide temperature range of −40°C to +125°C.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703 © 2003 Analog Devices, Inc. All rights reserved.
www.analog.com
Page 2
AD5570
TABLE OF CONTENTS
Specifications..................................................................................... 3
CLEAR (
CLR
)............................................................................. 17
Standalone Timing Characteristics ................................................ 4
Daisy Chaining and Readback Timing Characteristics............... 6
Absolute Maximum Ratings............................................................ 8
ESD Caution.................................................................................. 8
Pin Configuration and Function Descriptions............................. 9
Te r m in o l o g y .................................................................................... 10
Typical Performance Characteristics ........................................... 11
General Description....................................................................... 16
DAC Architecture .......................................................................16
Reference Buffers........................................................................ 16
Serial Interface............................................................................ 16
Transfe r Fu ncti o n ....................................................................... 17
REVISION HISTORY
Revision 0: Initial Version
Power-Down (
Power-On Reset .......................................................................... 17
Serial Data Output (SDO)......................................................... 17
Applications Information.............................................................. 19
Typical O p e rating Circ u i t ......................................................... 19
Layout Guidelines....................................................................... 20
Opto-Coupler Interface ............................................................. 20
Microprocessor Interfacing....................................................... 20
Evaluation Board ........................................................................ 22
Outline Dimensions....................................................................... 24
Ordering Guide .......................................................................... 24
PD
) ..................................................................... 17
Rev. 0 | Page 2 of 24
Page 3
AD5570
SPECIFICATIONS
VDD = +11.4 V to +16.5 V; VSS = −11.4 V to −16.5 V; V
specifications T
MIN
to T
, unless otherwise noted.
MAX
Table 1.
A/W Grade
Parameter
Min Typ
3
ACCURACY
Resolution * 16 Bits
Monotonicity * 16 Bits
Relative Accuracy (INL) ±0.6 ±0.4 ±1 LSB At 25°C
±0.6 ±2 −1 ±0.4 +1.25 LSB
Differential Nonlinearity
* * * −1 ±0.3 +1 LSB
(DNL)
Negative Full-Scale Error * * ±0.9 ±7.5 mV
Full-Scale Error * * ±1.8 ± 6 mV
Bipolar Zero Error * * ±0.9 ±7.5 mV
Gain Error * * ±1.8 ±7.5 mV
Gain Temperature
Coefficient
4
* * 0.25 ±1.5
REFERENCE INPUT
Reference Input Range4 * * * 4 5 5 V With ±11.4 V supplies
* * * 4 5 7 V With ±16.5 V supplies
Input Current * ±0.1 µA
OUTPUT CHARACTERISTICS
4
Output Voltage Range * * VSS + 1.4 V VDD − 1.4 V V ±11.4 V supplies
* * VSS + 2.5 V VDD − 2.5 V V ±16.5 V supplies
Output Voltage Settling Time * * 12 16 µs At 16 bits to ±0.5 LSB
* * 10 13 µs To 0.003%
* * 6 7 µs 512 LSB code change
Slew Rate * 6.5 V/µs Measured from 10% to 90%
Digital-to-Analog Glitch
* 15 nV-s
Impulse
Bandwidth * 20 kHz
Short Circuit Current * 25 mA
Output Noise Voltage Density * 85 nV/Hz f = 1 kHz; midscale loaded
DAC Output Impedance
4
* * 0.35 0.5 Ω
Digital Feedthrough * 0.5 nV-s
WARMUP TIME
5
* 12 s
LOGIC INPUTS
Input Current * ±0.1 µA
V
, Input High Voltage * 2 V
INH
V
, Input Low Voltage * 0.8 V
INL
CIN, Input Capacitance
4
* 3 pF
LOGIC OUTPUTS
VOL, Output Low Voltage * 0.4 V I
Floating-State Output
* 8 pF
Capacitance
= 5 V; REFGND = GND = 0 V; RL = 5 kΩ and CL = 200 pF to GND; all
REF
1, 2
Max Min Typ
B/Y Grade
2
3
Max
Unit Test Conditions/Comments
ppm
FSR/°C
±12 V supplies; 1 LSB change
around the major carry
= 1 mA
SINK
Rev. 0 | Page 3 of 24
Page 4
AD5570
Parameter
A/W Grade
Min Typ
3
1, 2
B/Y Grade
Max Min Typ
2
3
Max
Unit Test Conditions/Comments
POWER REQUIREMENTS
VDD/V
I
DD
I
SS
SS
* * ±11.4 ±16.5 V
* 4 5 mA V
* 3.5 5 mA V
Power-Down Current * 16 µA V
Power Supply Sensitivity
Power Dissipation * 100 mW V
1
Asterisk (*) = specifications same as B/Y grade.
2
Temperature range: A and B = −40°C to +85°C; W and Y = –40°C to +125°C.
3
Typical specifications at ±12 V/±15 V, 25°C.
4
Guaranteed by design.
5
Warmup time is required for the device to reach thermal equilibrium, thus achieving rated performance.
6
Sensitivity of negative full-scale error and positive full-scale error to VDD, VSS variations.
6
* 0.1 LSB/V
unloaded
OUT
unloaded
OUT
unloaded
OUT
±15 V supplies ±10%;
full scale loaded
unloaded
OUT
Rev. 0 | Page 4 of 24
Page 5
AD5570
STANDALONE TIMING CHARACTERISTICS
VDD = +12 V ± 5%, VSS = −12 V ± 5% or VDD = +15 V ± 10%, VSS = −15 V ± 10%; V
= 200 pF to GND; all specifications T
and C
L
MIN
to T
, unless other wise noted.
MAX
Table 2.
Parameter Limit at T
f
10 MHz max SCLK frequency
MAX
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
t
11
t
12
t
13
All parameters guaranteed by design and characterization. Not production tested.
All input signals are measured with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL +VIH)/2.
100 ns min SCLK cycle time
35 ns min SCLK high time
35 ns min SCLK low time
10 ns min
35 ns min Data setup time
0 ns min Data hold time
45 ns min
45 ns min
0 ns min
50 ns min
0 ns min
0 ns min
20 ns min
MIN
, T
Unit Description
MAX
SYNC to SCLK falling edge setup time
SCLK falling edge to
Minimum
SYNC rising edge to LDAC falling edge
LDAC pulse width
LDAC falling edge to SYNC falling edge (no update)
LDAC rising edge to SYNC rising edge (no update)
CLR pulse width
SYNC high time
= 5 V; REFGND = GND = 0 V; RL = 5 kΩ;
REF
SYNC rising edge
t
1
SCLK
t
t
8
t
4
SYNC
t
6
t
5
SDIN
1
LDAC
2
LDAC
CLR
NOTES
1. ASYNCHRONOUS LDAC UPDATE MODE. UPDATE ON FALLING EDGE OF LDAC.
2. SYNCHRONOUS LDAC UPDATE MODE. UPDATE ON RISING EDGE OF SYNC.
DB15
t
11
2
t
3
t
7
DB0
t
9
t
10
t
12
t
13
03760-0-002
Figure 2. Serial Interface Timing Diagram
Rev. 0 | Page 5 of 24
Page 6
AD5570
DAISY-CHAINING AND READBACK TIMING CHARACTERISTICS
V
= +12 V ± 5%, VSS = −12 V ± 5% or VDD = +15 V ± 10%, VSS = −15 V ± 10%; V
DD
= 200 pF to GND; all specifications T
and C
L
MIN
to T
, unless other wise noted.
MAX
Table 3.
Parameter Limit at T
f
MAX
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
1
t
14
All parameters guaranteed by design and characterization. Not production tested.
All input signals are measured with tr = tf = 5 ns (10% to 90% of V
SDO; R
PULLUP
1
With CL = 0 pF, t15 = 100 ns.
SCLK
2 MHz max SCLK frequency
500 ns min SCLK cycle time
200 ns min SCLK high time
200 ns min SCLK low time
10 ns min
35 ns min Data setup time
0 ns min Data hold time
45 ns min
45 ns min
0 ns min
50 ns min
200 ns max
= 5 kΩ, CL = 15 pF.
t
8
, T
MIN
Unit Description
MAX
SYNC to SCLK falling edge setup time
SCLK falling edge to
Minimum
SYNC high time
SYNC rising edge to LDAC falling edge
LDAC pulse width
Data delay on
) and timed from a voltage level of (VIL +VIH)/2.
DD
t
1
t
4
t
3
SDO
t
= 5 V; REFGND = GND = 0 V; RL = 5 kΩ,
REF
SYNC rising edge
2
t
7
SYNC
t
LDAC
LDAC
SDIN
SDO
1
2
t
5
DB15 (N)
NOTES
1. ASYNCHRONOUS LDAC UPDATE MODE
2. SYNCHRONOUS LDAC UPDATE MODE
t
6
DB0 (N)
DB0
(N+1)
DB15
(N+1)
DB0 (N)
DB15 (N)
DB15
(N+1)
10
t
9
t
14
03760-0-003
Figure 3. Daisy-Chaining Timing Diagram
Rev. 0 | Page 6 of 24
Page 7
AD5570
t
1
SCLK
t
2
t
8
t
4
SYNC
t
6
t
5
SDIN
LDAC
SDO
DB15 (N) DB0 (N)
t
3
t
7
DB15
(N+1)
t
10
t
9
t
14
Figure 4. Readback Timing Diagram
DB0
(N+1)
DB0 (N)DB14 (N)DB15 (N)
03760-0-004
Rev. 0 | Page 7 of 24
Page 8
AD5570
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 4.
Parameter Rating
VDD to AGND, AGNDS, DGND −0.3 V, +17 V
VSS to AGND, AGNDS, DGND +0.3 V, −17 V
AGND, AGNDS to DGND −0.3 V to +0.3 V
REFGND to AGND, ADNDS VSS − 0.3 V to VDD + 0.3 V
REFIN to AGND, AGNDS VSS − 0.3 V to VDD + 0.3 V
REFIN to REFGND −0.3 V to +17 V
Digital Inputs to DGND −0.3 V to VDD + 0.3 V
V
to AGND, AGNDS −0.3 V to VDD + 0.3 V
OUT
SDO to DGND −0.3 V to +6.5 V
Operating Temperature Range: −40°C to +125°C
W, Y Grades −40°C to +125°C
A, B Grades −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Maximum Junction Temperature
(TJ Max) 150°C
16-Lead SSOP Package
Power Dissipation (TJ max – TA)/θ
θJA Thermal Impedance 139°C/W
Lead Temperature (Soldering 10 s) 300°C
IR Reflow, Peak Temperature 230°C
JA
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may
affect device reliability.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 8 of 24
Page 9
AD5570
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
V
SS
2
V
DD
CLR
3
AD5570
4
LDAC
SYNC
SCLK
SDIN
SDO
TOP VIEW
5
(Not to Scale)
6
7
8
Figure 5. 16-Lead SSOP Pin Configuration (RS-16)
Table 5. Pin Function Descriptions
Pin No. Mnemonic Description
1 V
2 V
3
SS
DD
CLR Level Sensitive, Active Low Input. A falling edge of CLR resets V
Negative Analog Supply Voltage. −12 V ± 5% to −15 V ± 10% for specified performance.
Positive Analog Supply Voltage. 12 V ± 5% to 15 V ± 10% for specified performance.
untouched.
4
LDAC Active Low Control Input. Transfers the contents of the input register to the DAC register. LDAC may be tied
permanently low, enabling the outputs to be updated on the rising edge of
5
SYNC Active Low Control Input. This is the frame synchronization signal for the data. When SYNC goes low, it powers
on the SCLK and SDIN buffers and enables the input shift register. Data is transferred in on the falling edges of
the following 16 clocks.
6 SCLK
Serial Clock Input. Data is clocked into the input register on the falling edge of the serial clock input. Data can
be transferred at rates of up to 8 MHz.
7 SDIN
Serial Data Input. This device has a 16-bit register. Data is clocked into the register on the falling edge of the
serial clock input.
8 SDO
Serial Data Output. Can be used for daisy chaining a number of devices together or for reading back the data in
the shift register for diagnostic purposes. This is an open-drain output; it should be pulled to logic high with an
external pull-up resistor of ~5 kΩ.
9 DGND Digital Ground. Ground reference for all digital circuitry.
10
PD
Active Low Control Input. Allows the DAC to be put into a power-down state.
11 AGND Analog Ground. Ground reference for all analog circuitry.
12 AGNDS Analog Ground Sense. This is normally tied to AGND.
13 V
OUT
Analog Output Voltage.
14 REFGND This pin should be tied to 0 V.
15 REFIN
Voltage Reference Input. This is internally buffered before being applied to the DAC. For bipolar ±10 V output
range, REFIN is 5 V.
16 REFGND This pin should be tied to 0 V.
16
15
14
13
12
11
10
9
REFGND
REFIN
REFGND
V
OUT
AGNDS
AGND
PD
DGND
03760-0-005
to AGND. The contents of the registers are
OUT
SYNC.
Rev. 0 | Page 9 of 24
Page 10
AD5570
TERMINOLOGY
Relative Accuracy or Integral Nonlinearity (INL)
Output Voltage Settling Time
Relative accuracy or integral nonlinearity is a measure of the
maximum deviation, in LSBs, from a straight line passing
through the endpoints of the DAC transfer function.
Monotonicity
A DAC is monotonic, if the output either increases or remains
constant for increasing digital inputs. The AD5570 is monotonic
over its full operating temperature range.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ±1 LSB maximum
ensures monotonicity.
Gain Error
Gain error is the difference between the actual and ideal analog
output range, expressed as a percent of the full-scale range. It is
the deviation in slope of the DAC transfer characteristic from
the ideal.
Gain Error Temperature Coefficient
Gain error temperature coefficient is a measure of the change in
gain error with changes in temperature. It is expressed in
ppm/°C.
Negative Full-Scale Error / Zero Scale Error
Negative full-scale error is the error in the DAC output voltage
when all 0s are loaded into the DAC latch. Ideally, the output
− 1 LSB.
REF
REF
.
voltage, with all 0s in the DAC latch, should be −2 V
Full-Scale Error
Full-scale error is the error in the DAC output voltage when all
1s are loaded to the DAC latch. Ideally the output voltage, with
all 1s loaded into the DAC latch, should be 2 V
Output voltage settling time is the amount of time it takes for
the output to settle to a specified level for a full-scale input
change.
Slew Rate
The slew rate of a device is a limitation in the rate of change of
output voltage. The output slewing speed of a voltage-output
D/A converter is usually limited by the slew rate of the amplifier
used at its output. Slew rate is measured from 10% to 90% of the
output signal and is given in V/µs.
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the amount of charge injected into the analog output when the input codes in the DAC
register change state. It is specified as the area of the glitch in
nV-s and is measured when the digital input code changes by
1 LSB at the major carry transition, that is, from code 0x7FFF to
0x8000.
Bandwidth
The reference amplifiers within the DAC have a finite bandwidth to optimize noise performance. To measure it, a sine
wave is applied to the reference input (REFIN), with full-scale
code loaded to the DAC. The bandwidth is the frequency at
which the output amplitude falls to 3 dB below the input.
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital inputs of the
DAC, but is measured when the DAC output is not updated.
is held high, while the CLK and SDIN signals are toggled.
SYNC
It is specified in nV-s and is measured with a full-scale code
change on the data bus, that is, from all 0s to all 1s and vice
versa.
Power Supply Sensitivity
Bipolar Zero Error
Bipolar zero error is the deviation of the analog input from the
ideal half-scale output of 0.0000 V when the inputs are loaded
with 0x8000.
Rev. 0 | Page 10 of 24
Power supply sensitivity indicates how the output of the DAC is
affected by changes in the power supply voltage.
Page 11
AD5570
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
TA = 25°C
0.8
V
= ±15V
DD/VSS
REFIN = 5V
0.6
0.4
0.2
0
–0.2
INL (LSB)
–0.4
–0.6
–0.8
–1.0
0
CODE
Figure 6. Integral Nonlinearity vs. Code, V
1.0
TA = 25°C
0.8
0.6
0.4
0.2
0
–0.2
DNL (LSB)
–0.4
–0.6
–0.8
–1.0
0
V
DD/VSS
REFIN = 5V
= ±15V
CODE
Figure 7. Differential Nonlinearity vs. Code, V
1.0
TA = 25°C
INL (LSB)
0.8
0.6
0.4
0.2
–0.2
–0.4
–0.6
–0.8
–1.0
0
0
V
DD/VSS
REFIN = 5V
= ±12V
CODE
Figure 8. Integral Nonlinearity vs. Code, V
50k40k30k20k10k 60k
= ±15 V
DD/VSS
50k40k30k20k10k 60k
DD/VSS
50k40k30k20k10k 60k
= ±12 V
DD/VSS
03760-0-006
03760-0-007
= ±15 V
03760-0-008
1.0
TA = 25°C
0.8
V
= ±12V
DD/VSS
REFIN = 5V
0.6
0.4
0.2
0
–0.2
DNL (LSB)
–0.4
–0.6
–0.8
–1.0
0
CODE
Figure 9. Differential Nonlinearity vs. Code, V
50k40k30k20k10k 60k
= ±12 V
DD/VSS
1.0
VDD/VSS = ±15V
0.8
REFIN = 5V
0.6
0.4
0.2
0
–0.2
INL (LSB)
–0.4
–0.6
–0.8
–1.0
–40
TEMPERATURE (°C)
100806040200–20 120
Figure 10. Integral Nonlinearity vs. Temperature, ±15 V Supplies
1.0
VDD/VSS = ±15V
0.8
REFIN = 5V
0.6
0.4
0.2
0
–0.2
DNL (LSB)
–0.4
–0.6
–0.8
–1.0
–40
TEMPERATURE (°C)
100806040200–20 120
Figure 11. Differential Nonlinearity vs. Temperature, ±15 V Supplies
03760-0-009
03760-0-018
03760-0-019
Rev. 0 | Page 11 of 24
Page 12
AD5570
1.0
VDD/VSS = ±12V
0.8
REFIN = 5V
0.6
0.4
0.2
0
–0.2
INL (LSB)
–0.4
–0.6
–0.8
–1.0
–40
TEMPERATURE (°C)
Figure 12. Integral Nonlinearity vs. Temperature, ±12 V Supplies
1.0
VDD/VSS = ±12V
0.8
REFIN = 5V
0.6
0.4
0.2
0
–0.2
DNL (LSB)
–0.4
–0.6
–0.8
–1.0
–40
TEMPERATURE (°C)
Figure 13. Differential Nonlinearity vs. Temperature, ±12 V Supplies
1.0
TA = 25°C
0.8
REFIN = 5V
0.6
0.4
0.2
0
–0.2
INL (LSB)
–0.4
–0.6
–0.8
–1.0
11.4 15.014.013.012.0 16.0 16.5
SUPPLY VOLTAGE (V)
Figure 14. Integral Nonlinearity vs. Supply Voltage
100806040200–20 120
100806040200–20 120
03760-0-020
03760-0-021
03760-0-023
1.0
TA = 25°C
0.8
REFIN = 5V
0.6
0.4
0.2
0
–0.2
DNL (LSB)
–0.4
–0.6
–0.8
–1.0
11.4 15.014.013.012.0 16.0 16.5
SUPPLY VOLTAGE (V)
03760-0-024
Figure 15. Differential Nonlinearity vs. Supply Voltage
2.0
VDD/VSS = ±12V
= 25°C
T
A
1.5
1.0
0.5
0
INL ERROR (LSB)
–0.5
–1.0
2.0
REFERENCE VOLTAGE (V)
4.54.03.53.02.5 5.0 5.5
03760-0-026
Figure 16. Integral Nonlinearity Error vs. Reference Voltage, ±12 V Supplies
0.5
VDD/VSS = ±12V
0.4
TA = 25°C
0.3
0.2
0.1
0
–0.1
DNL ERROR (LSB)
–0.2
–0.3
–0.4
–0.5
2.0
REFERENCE VOLTAGE (V)
4.54.03.53.02.5 5.0 5.5
03760-0-027
Figure 17. Differential Nonlinearity Error vs. Reference Voltage,
±12 V Supplies
Rev. 0 | Page 12 of 24
Page 13
AD5570
10.0
VDD/VSS = ±15V OR ±12V
= 25°C
T
A
7.5
5.0
4.5
TA = 25°C
REFIN = 5V
5.0
2.5
0
TUE ERROR (LSB)
–2.5
–5.0
2.0
Figure 18. TUE Error vs. Reference Voltage
2.0
VDD/VSS = ±15V
= 25°C
T
A
1.5
1.0
0.5
0
–0.5
INL ERROR (LSB)
–1.0
–1.5
–2.0
2.0 2.5
REFERENCE VOLTAGE (V)
4.54.03.53.02.5 5.0 5.5
3.53.0 5.0 5.5 6.04.54.0 6.5
REFERENCE VOLTAGE (V)
03760-0-028
03760-0-048
4.0
3.5
CURRENT (mA)
3.0
2.5
2.0
25
20
15
10
POWER-DOWN CURRENT (µA)
11.4
TA = 25°C
REFIN = 5V
5
0
11.4
Figure 21. I
|I
DD IN POWER-DOWN
|I
SS IN POWER-DOWN
|IDD|
|
|I
SS
14.413.412.4 15.4 16.4
VDD/VSS (V)
vs.VDD/V
DD/ISS
SS
|
|
14.413.412.4 15.4 16.4
IDD/ISS (V)
03760-0-029
03760-0-030
Figure 19. Integral Nonlinearity Error vs. Reference Voltage, ± 15 V Supplies
1.0
VDD/VSS = ±15V
0.8
T
= 25°C
A
0.6
0.4
0.2
0
–0.2
INL ERROR (LSB)
–0.4
–0.6
–0.8
–1.0
2.0 2.5
3.53.0 5.0 5.5 6.04.54.0 6.5
REFERENCE VOLTAGE (V)
03760-0-049
Figure 20. Differential Nonlinearity Error vs. Reference Voltage,
± 15 V Supplies
Rev. 0 | Page 13 of 24
Figure 22. I
0
VDD/VSS = ±12V OR ±15V
–1
REFIN = 5V
–2
–3
–4
–5
–6
–7
OFFSET ERROR (LSB)
–8
–9
–10
–40
in Power-Down vs. Supply Voltage
DD/ISS
TEMPERATURE (°C)
Figure 23. Offset Error vs. Temperature
100806040200–20 120
03760-0-031
Page 14
AD5570
0
–1
–2
–3
–4
–5
–6
–7
–8
BIPOLAR ZERO ERROR (LSB)
–9
–10
–40
REFIN = 5V
VDD/VSS = ±15V
VDD/VSS = ±12V
TEMPERATURE (°C)
100806040200–20 120
03760-0-032
11.0
10.0
8.0
6.0
4.0
2.0
–2.0
–4.0
–6.0
–8.0
–10.0
0
1µs/DIV
V
= +15V
DD
V
= –15V
SS
REFIN = 5V
T
= 25°C
A
03760-0-046
Figure 24. Bipolar Zero Error vs. Temperature
10
REFIN = 5V
0
6
4
2
0
–2
GAIN ERROR (LSB)
–4
–6
–8
–10
–40
VDD/VSS = ±15V
VDD/VSS = ±12V
TEMPERATURE (°C)
Figure 25. Gain Error vs. Temperature
4.15
TA = 25°C
REFIN = 5V
4.10
4.05
4.00
3.95
DECREASING
(mA)
DD
I
3.90
INCREASING
3.85
3.80
3.75
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
15V SUPPLIES
DECREASING
INCREASING
12V SUPPLIES
V
(V)
LOGIC
100806040200–20 120
5.0
03760-0-034
03760-0-035
Figure 27. Settling Time
40
TA = 25°C
REFIN = 5V
35
30
25
s)
µ
20
TIME (
15
10
5
0
012345 6789
VDD/VSS = ±12V
VDD/VSS = ±15V
CAPACITANCE (nF)
Figure 28.14-Bit Settling Time vs. Load Capacitance
10.0000
OUTPUT VOLTAGE (V)
TA = 25°C
9.9997
REFIN = 5V
9.9994
9.9991
9.9988
9.9985
9.9982
9.9979
9.9976
9.9973
9.9970
9.9967
9.9964
9.9961
9.9958
9.9955
9.9952
–10–8–6–4–202468
15V SUPPLIES
12V SUPPLIES
SINK CURRENT (mA)SOURCE CURRENT (mA)
03760-0-037
9.4
03760-0-038
10
Figure 26. Supply Current vs. Logic Input Current for SCLK,
LDAC
and
Increasing and Decreasing
SYNC
, SDIN,
Rev. 0 | Page 14 of 24
Figure 29. Source and Sink Capability of Output Amplifier
with Full Scale Loaded
Page 15
AD5570
V
–9.9973
–9.9976
–9.9979
–9.9982
–9.9985
–9.9988
–9.9991
OUTPUT VOLTAGE (V)
–9.9994
–9.9997
–10.0000
TA = 25°C
REFIN = 5V
12V SUPPLIES
15V SUPPLIES
–10–8–6–4–202468
SINK CURRENT (mA)SOURCE CURRENT (mA)
Figure 30. Source and Sink Capability of Output Amplifier
with Zero Scale Loaded
–0.05
–0.06
–0.07
(V)
OUT
V
–0.08
03760-0-039
10
VDD = +15V
= –15V
V
SS
MIDSCALE LOADED
20µV/DIV
= 0V
V
REFIN
CH1 20µV/DIV 20µs/PTM 1.0Ωms 500kS/s
A CH1 0.0V
Figure 33. Peak-to-Peak Noise (100 kHz Bandwidth)
VDD = +15V
V
= –15V
SS
REFIN = 5V
T
= 25°C
A
V
RAMP TIME = 100µs
DD
V
SS
03760-0-047
VDD = +15V
V
–0.09
–0.10
= –15V
SS
REFIN = 5V
= 25°C
T
A
7 FFF
→
8000H
1µs/DIV
Figure 31. Major Code Transition Glitch Energy, ±15 V Supplies
–0.022
–0.027
–0.032
–0.037
–0.042
–0.047
–0.052
VOLTAGE (V)
–0.057
VDD = +12V
V
–0.062
–0.067
–0.072
= –12V
SS
REFIN = 5V
TA= 25°C
8000 → 7FFFH
1µs (DIV)
Figure 32. Major Code Transition Glitch Energy, ±12 V Supplies
03760-0-040
03760-0-051
OUT
V
DD/VSS
= 10mV/DIV
V
OUT
100µs/DIV
= 10V/DIV
Figure 34. V
vs. VDD/VSS on Power-Up
OUT
03760-0-042
Rev. 0 | Page 15 of 24
Page 16
AD5570
GENERAL DESCRIPTION
The AD5570 is a single 16-bit, serial input, voltage output DAC.
It operates from supply voltages of ±11.4 V to ±16.5 V, and has a
buffered voltage output of up to ±13.6 V. Data is written to the
AD5570 in a 16-bit word format, via a 3-wire serial interface.
The device also offers an SDO pin, which is available for daisy
chaining or readback.
The AD5570 incorporates a power-on reset circuit, which
ensures that the DAC output powers up to 0 V. The device also
has a power-down pin, which reduces the typical current
consumption to 16 µA.
DAC ARCHITECTURE
The DAC architecture of the AD5570 consists of a 16-bit
current-mode segmented R-2R DAC. The simplified circuit
diagram for the DAC section is shown in Figure 35.
The four MSBs of the 16-bit data word are decoded to drive
15 switches, E1 to E15. Each of these switches connects one of
the 15 matched resistors to either AGND or IOUT. The remaining 12 bits of the data word drive switches S0 to S11 of the
12-bit R-2R ladder network.
V
ref
2R
2R
E15
E14 E1
RR R
2R
S11
2R
2R
S10
2RS02R
R/8
SERIAL INTERFACE
The AD5570 is controlled over a versatile 3-wire serial interface
that operates at clock rates up to 10 MHz and is compatible with
SPI, QSPI, MICROWIRE, and DSP interface standards.
Input Shift Register
The input shift register is 16 bits wide. Data is loaded into the
device as a 16-bit word under the control of a serial clock input,
SCLK. The timing diagram for this operation is shown in
Figure 2.
Upon power-up, the input shift register and DAC register are
loaded with midscale (0x8000). The DAC coding is straight
binary; all 0s produce an output of −2 V
output of +2 V
The
SYNC
− 1 LSB.
REF
input is a level-triggered input that acts as a frame
synchronization signal and chip enable.
serial word being loaded into the device. Data can be transferred into the device only while
data transfer,
minimum
SYNC
SYNC
goes low, serial data on SDIN is shifted into the device’s
should be taken low, observing the
SYNC
to SCLK falling edge setup time, t4. After
SYNC
input shift register on the falling edges of SCLK.
taken high after the falling edge of the 16th SCLK pulse,
observing the minimum SCLK falling edge to
time, t
.
7
; all 1s produce an
REF
must frame the
SYNC
is low. To start the serial
may be
SYNC
rising edge
SYNC
V
OUT
4 MSBs DECODED INTO
15 EQUAL SEGMENTS
Figure 35. DAC Ladder Structure
AGND
12 BIT R-2R LADDER
REFERENCE BUFFERS
The AD5570 operates with an external reference. The reference
input (REFIN) has an input range of up to 7 V. This input
voltage is then used to provide a buffered positive and negative
reference for the DAC core. The positive reference is given by
V2V ×=+
REFINREF
while the negative reference to the DAC core is given by
V2V ×=−
REFINREF
These positive and negative reference voltages define the DAC
output range.
After the end of the serial data transfer, data is automatically
transferred from the input shift register to the input register of
03760-0-010
the DAC.
When data has been transferred into the input register of the
DAC, the DAC register and DAC output can be updated by
taking LDAC low while SYNC is high.
Load DAC Input (
LDAC
)
When data has been transferred into the input register of the
DAC, there are two ways in which the DAC register and DAC
output can be updated. Depending on the status of both
and
Synchronous
, one of two update modes is selected.
LDAC
LDAC
: In this mode,
is low while data is
LDAC
SYNC
being clocked into the input shift register. The DAC output is
updated when
the rising edge of
is taken high. The update here occurs on
SYNC
.
SYNC
Rev. 0 | Page 16 of 24
Page 17
AD5570
Asynchronous
being clocked in. The DAC output is updated by taking
low any time after
occurs on the falling edge of
LDAC
: In this mode,
SYNC
is high while data is
LDAC
LDAC
has been taken high. The update now
.
LDAC
Figure 36 shows a simplified block diagram of the input loading
circuitry.
OUTPUT
I/V AMPLIFIER
V
REFIN
LDAC
SYNC
Figure 36. Simplified Serial Interface Showing Input Loading Circuitry
16-BIT
DAC
DAC
REGISTER
INPUT SHIFT
REGISTER
V
OUT
SDOSDIN
03760-0-012
TRANSFER FUNCTION
Table 6 shows the ideal input code to output voltage relationship
for the AD5570.
Table 6. Binary Code Table
Digital Input Analog Output
MSB LSB V
1111 1111 1111 1111 +2 V
1000 0000 0000 0001 +2 V
1000 0000 0000 0000 0 V
0111 1111 1111 1111 −2 V
0000 0000 0000 0000 −2 V
The output voltage expression is given by
OUT
×+−=
where:
D is the decimal equivalent of the code loaded to the DAC.
V
is the reference voltage available at the REFIN pin.
REFIN
OUT
× (32,767/32,768)
REF
× (1/32,768)
REF
× (1/32,768)
REF
REF
REFINREFIN
]65536/[42 DVVV
CLEAR (CLR)
is an active low digital input that allows the output to be
CLR
cleared to 0 V. When the
output stays at 0 V until
between
LDAC
and
CLR
Table 7. Relationships among
PD CLR LDAC
0 x x
signal is brought back high, the
CLR
is brought low. The relationship
LDAC
is explained further in Table 7.
PD, CLR
, and
LDAC
Comments
PD has priority over LDAC and CLR. The
output remains at 0 V through an internal
20 kΩ resistor. It is still possible to address
both the input register and DAC register
when the AD5570 is in power-down.
1 0 0
Data is written to the input register and
DAC register.
CLR has higher priority over
LDAC; therefore, the output is at 0 V.
1 0 1
Data is written to the input register only.
The output is at 0 V and remains at 0 V,
CLR is taken back high.
when
1 1 0
Data is written to the input register and
the DAC register. The output is driven to
the DAC level.
1 1 1
Data is written to the input register only.
The output of the DAC register is
unchanged.
POWER-DOWN (PD)
The power-down pin allows the user to place the AD5570 into a
power-down mode. When in this mode, power consumption is
at a minimum; the device consumes only 16 µA typically.
POWER-ON RESET
The AD5570 contains a power-on reset circuit that controls the
output during power-up and power-down. This is useful in
applications where the known state of the output of the DAC
during power-up is important. On power-up and power-down,
the output of the DAC, V
, is held at AGND.
OUT
Rev. 0 | Page 17 of 24
Page 18
AD5570
SERIAL DATA OUTPUT (SDO)
The serial data output (SDO) is the internal shift register’s
output. For the AD5570, SDO is an internal pull-down only; an
external pull-up resistor of ~5 kΩ to external logic high is
required. SDO pull-down is disabled when the device is in
power-down, thus saving current.
The availability of SDO allows any number of AD5570s to be
daisy-chained together. It also allows for the contents of the
DAC register, or any number of DACs daisy-chained together,
to be read back for diagnostic purposes.
Daisy Chaining
This mode of operation is designed for multi-DAC systems,
where several AD5570s may be connected in cascade as shown
in Figure 37. This is done by connecting the control inputs in
parallel and then daisy chaining the SDIN and SDO I/Os of
each device. An external pull-up resistor of ~5 kΩ on SDO is
required when using the part in daisy-chain mode.
As before, when
into the input shift register on the falling edge of SCLK. If more
than 16 clock pulses are applied, the data ripples out of the shift
resister and appears on the SDO line. By connecting this line to
the SDIN input on the next AD5570 in the chain, a multi-DAC
interface may be constructed.
One data transfer cycle of 16 SCLK pulses is required for each
DAC in the system. Therefore, the total number of clock cycles
must equal 16 N, where N is the total number of devices in the
chain. The first data transfer cycle written into the chain
appears at the last DAC in the system on the final data transfer
cycle.
When the serial transfer to all devices is complete,
be taken high. This prevents any further data from being
clocked into the devices.
A continuous SCLK source may be used, if it can be arranged
that
is held low for the correct number of clock cycles.
SYNC
Alternatively, a burst clock containing the exact number of
clock cycles may be used and
The outputs of all the DACs in the system can be updated
simultaneously using the
goes low, serial data on SDIN is shifted
SYNC
taken high some time later.
SYNC
signal.
LDAC
SYNC
should
68HC11*
MOSI
SCK
PC7
PC6
MISO
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 37. Daisy Chaining Using the AD5570
SDIN
SCLK
SYNC
LDAC
SCLK
SYNC
LDAC
SCLK
SYNC
LDAC
AD5570*
SDO
SDIN
AD5570*
SDO
SDIN
AD5570*
SDO
V
LOGIC
R
R
R
03760-0-013
Readback
The AD5570 allows the data contained in the DAC register to
be read back, if required. As with daisy chaining, an external
pull-up resistor of ~5 kΩ on SDO is required. The data in the
DAC register is available on SDO on the falling edges of SCLK
when
is low. On the sixteenth SCLK edge, SDO is
SYNC
updated to repeat SDIN with a delay of 16 clock cycles.
To read back the contents of the DAC register without writing
to the part,
should be taken low while LDAC is held high.
SYNC
Daisy-chaining readback is also possible through the SDO pin
of the last device in the DAC chain, because the DAC data
passes through the DAC chain with the appropriate latency.
Rev. 0 | Page 18 of 24
Page 19
AD5570
APPLICATIONS INFORMATION
TYPICAL OPERATING CIRCUIT
Figure 38 shows the typical operating circuit for the AD5570.
The only external component needed for this precision 16-bit
DAC is a single external positive reference. Because the device
incorporates reference buffers, it eliminates the need for a
negative reference, external inverters, precision amplifiers, and
resistors. This leads to an overall saving in both cost and board
space.
In the circuit below, V
but V
and VSS can operate supplies from +11.4 V to +16.5 V.
DD
In Figure 38, AGNDS is connected to AGND, but the option of
Force/Sense is included on this device, if required by the user.
0.1µF10µF
–15V
+15V
0.1µF10µF
LDAC
SYNC
SCLK
SDIN
SDO
Force/Sense of AGND
Because of the extremely high accuracy of this device, system
design issues such as grounding and contact resistance are very
important. The AD5570, with ±10 V output, has an LSB size of
305 µV. Therefore, series wiring and connector resistances of
very small values could cause voltage drops of an LSB. For this
reason, the AD5570 offers a Force/Sense output configuration.
Figure 39 shows how to connect the AD5570 to the Force/Sense
amplifier. Where accuracy of the output is important, an amplifier such as the OP177 is ideal. The OP177 is ultraprecise with
offset voltages of 10 µV maximum at room temperature, and
offset drift of 0.1 µV/°C maximum. Alternative recommended
amplifiers are the OP1177 and the OP77. For applications where
optimization of the circuit for settling time is needed, the
AD845 is recommended.
Precision Voltage Reference Selection
To achieve the optimum performance from the AD5570,
thought should be given to the selection of a precision voltage
reference. The AD5570 has just one reference input, REFIN.
This voltage on REFIN is used to provide a buffered positive
and negative reference for the DAC core. Therefore, any error in
the voltage reference is reflected in the output of the device.
and VSS are both connected to ±15 V,
DD
5kΩ
Figure 38.
1
V
SS
2
V
DD
3
CLR
4
LDAC
AD5570
5
SYNC
6
SCLK
7
SDIN
8
SDO
Typical Operating Circuit
REFGND
REFIN
REFGND
V
OUT
AGNDS
AGND
DGND
16
15
14
13
12
11
10
PD
ADR435
V
OUT
9
5V
There are four possible sources of error to consider when
choosing a voltage reference for high accuracy applications:
initial accuracy, temperature coefficient of the output voltage,
long term drift, and output voltage noise.
Initial accuracy on the output voltage of an external reference
could lead to a full-scale error in the DAC. Therefore, to
minimize these errors, a reference with low initial accuracy
specification is preferred. Also, choosing a reference with an
03760-0-044
output trim adjustment, such as the ADR425, allows a system
designer to trim system errors out by setting the reference
voltage to a voltage other than the nominal. The trim adjustment can also be used at temperature to trim out any error.
Long term drift (LTD) is a measure of how much the reference
drifts over time. A reference with a tight long-term drift
specification ensures that the overall solution remains relatively
stable over its entire lifetime.
The temperature coefficient of a reference’s output voltage
affects INL, DNL, and TUE. A reference with a tight temperature coefficient specification should be chosen to reduce the
dependence of the DAC output voltage on ambient conditions.
In high accuracy applications, which have a relatively low noise
budget, reference output voltage noise needs to be considered.
Choosing a reference with as low an output noise voltage as
practical for the system resolution required is important. Precision voltage references such as the ADR435 (XFET design)
produce low output noise in the 0.1 Hz to 10 Hz region.
However, as the circuit bandwidth increases, filtering the output
of the reference may be required to minimize the output noise.
1
V
SS
V
2
DD
CLR
3
4
LDAC
5
SYNC
6
SCLK
7
SDIN
8
SDO
(OTHER CONNECTIONS OMITTED
FOR CLARITY)
*FOR OPTIMUM SETTLING TIME PERFORMANCE,
THE AD845 IS RECOMMENDED.
AD5570
REFGND
REFIN
REFGND
V
OUT
AGNDS
AGND
DGND
PD
16
15
14
13
12
11
OP177*
10
9
2
6
3
03760-0-045
Figure 39. Driving AGND and AGNDS Using a Force/Sense Amplifier
Rev. 0 | Page 19 of 24
Page 20
AD5570
Table 8. Partial List of Precision References Recommended
for Use with the AD5570
Initial
1
Accuracy
(mV max)
± 6
± 6
±5
±6
±2.5
Part No.
ADR435
ADR425
ADR02
ADR395
AD586
1
Available in SC70 package.
LAYOUT GUIDELINES
In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to
ensure the rated performance. The printed circuit board on
which the AD5570 is mounted should be designed so that the
analog and digital sections are separated and confined to
certain areas of the board. If the AD5570 is in a system where
multiple devices require an AGND-to-DGND connection, the
connection should be made at one point only. The star ground
point should be established as close as possible to the device.
The AD5570 should have ample supply bypassing of 10 µF in
parallel with 0.1 µF on each supply located as close to the package as possible, ideally right up against the device. The 10 µF
capacitors are the tantalum bead type. The 0.1 µF capacitor
should have low effective series resistance (ESR) and effective
series inductance (ESI) such as the common ceramic types,
which provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching.
The power supply lines of the AD5570 should use as large a
trace as possible to provide low impedance paths and reduce the
effects of glitches on the power supply line. Fast switching
signals such as clocks should be shielded with digital ground to
avoid radiating noise to other parts of the board, and should
never be run near the reference inputs. A ground line routed
between the SDIN and SCLK lines helps reduce crosstalk
between them (not required on a multilayer board, which has a
separate ground plane, but separating the lines helps). It is
essential to minimize noise on the REFIN line, because it
couples through to the DAC output.
Avoid crossover of digital and analog signals. Traces on opposite
sides of the board should run at right angles to each other. This
reduces the effects of feed through the board. A microstrip
technique is by far the best, but not always possible with a
double-sided board. In this technique, the component side of
the board is dedicated to ground plane, while signal traces are
placed on the solder side.
Long-Term
Drift
(ppm typ)
30 3 3.4
50 3 3.4
50 3 15
50 25 5
15 10 4
Temp Drift
(ppm/
°C max)
0.1 Hz to
10 Hz Noise
(µV p-p typ)
OPTO-COUPLER INTERFACE
In many process control applications, it is necessary to provide
an isolation barrier between the controller and the unit being
controlled. Opto-isolators can provide voltage isolation in
excess of 3 kV. The serial loading structure of the AD5570
makes it ideal for opto-isolated interfaces, because the number
of interface lines is kept to a minimum. Figure 40 shows a
4-channel isolated interface to the AD5570. To reduce the
number of opto-isolators, if the simultaneous updating of the
DAC is not required, the LDAC pin may be tied permanently
low. The DAC can then be updated on the rising edge of SYNC.
V
CC
µCONTROLLER
CONTROL OUT
SYNC OUT
SERIAL CLOCK OUT
SERIAL DATA OUT
OPTO-COUPLER
Figure 40. Opto-Isolated Interface
TO LDAC
TO SYNC
TO SCLK
TO SDIN
03760-0-050
MICROPROCESSOR INTERFACING
Microprocessor interfacing to the AD5570 is via a serial bus
that uses standard protocol compatible with microcontrollers
and DSP processors. The communications channel is a 3-wire
(minimum) interface consisting of a clock signal, a data signal,
and a synchronization signal. The AD5570 requires a 16-bit
data word with data valid on the falling edge of SCLK.
For all the interfaces, the DAC output update may be done
automatically when all the data is clocked in, or it may be done
under the control of
may be read using the readback function.
. The contents of the DAC register
LDAC
Rev. 0 | Page 20 of 24
Page 21
AD5570
AD5570 to MC68HC11 Interface
Figure 41 shows an example of a serial interface between the
AD5570 and the MC68HC11 microcontroller. The serial
peripheral interface (SPI) on the MC68HC11 is configured for
master mode (MSTR = 1), clock polarity bit (CPOL = 0), and
the clock phase bit (CPHA = 1). The SPI is configured by
writing to the SPI control register (SPCR)—see the 68HC11
User Manual. SCK of the 68HC11 drives the SCLK of the
AD5570, the MOSI output drives the serial data line (DIN) of
the AD5570, and the MISO input is driven from SDO. The
is driven from one of the port lines, in this case PC7.
SYNC
When data is being transmitted to the AD5570, the SYNC line
(PC7) is taken low and data is transmitted MSB first. Data
appearing on the MOSI output is valid on the falling edge of
SCK. Eight falling clock edges occur in the transmit cycle, so, in
order to load the required 16-bit word, PC7 is not brought high
until the second 8-bit word has been transferred to the DAC’s
input shift register.
MC68HC11*
MISO
MOSI
SCLK
PC7
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 41. AD5570 to MC68HC11 Interface
is controlled by the PC6 port output. The DAC can be
LDAC
updated after each 2-byte transfer by bringing
example does not show other serial lines for the DAC. If
AD5570*
SDO
DIN
SCLK
SYNC
LDAC
03760-0-014
low. This
CLR
were used, it could be controlled by port output PC5, for
example.
AD5570 to 8051 Interface
The AD5570 requires a clock synchronized to the serial data.
For this reason, the 8051 must be operated in Mode 0. In this
mode, serial data enters and exits through RxD, and a shift clock
is output on RxD.
P3.3 and P3.4 are bit programmable pins on the serial port and
are used to drive
SYNC
and
LDAC
, respectively.
The 8051 provides the LSB of its SBUF register as the first bit in
the data stream. The user must ensure that the data in the SBUF
register is arranged correctly, because the DAC expects MSB
first.
V
8xC51*
LOGIC
RxD
TxD
P3.3
P3.4
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 42. AD5570 to 8051 Interface
AD5570*
SDO
DIN
SCLK
SYNC
LDAC
03760-0-015
When data is to be transmitted to the DAC, P3.3 is taken low.
Data on RxD is clocked out of the microcontroller on the rising
edge of TxD and is valid on the falling edge. As a result, no glue
logic is required between this DAC and the microcontroller
interface.
The 8051 transmits data in 8-bit bytes with only eight falling
clock edges occurring in the transmit cycle. Because the DAC
expects a 16-bit word, SYNC (P3.3) must be left low after the
first eight bits are transferred. After the second byte has been
transferred, the P3.3 line is taken high. The DAC may be
updated using
via P3.4 of the 8051.
LDAC
AD5570 to ADSP2101/ADSP2103
An interface between the AD5570 and the ADSP2101/
ADSP2103 is shown in Figure 43. The ADSP2101/ADSP2103
should be set up to operate in the SPORT transmit alternate
framing mode. The ADSP2101/ADSP2103 are programmed
through the SPORT control register and should be configured
as follows: internal clock operation, active low framing, and
16-bit word length.
Transmission is initiated by writing a word to the Tx register
after the SPORT has been enabled. As the data is clocked out of
the DSP on the rising edge of SCLK, no glue logic is required to
interface the DSP to the DAC. In the interface shown, the DAC
output is updated using the
tively, the
input could be tied permanently low, and then
LDAC
the update takes place automatically when
ADSP2101/
ADSP2103*
DR
DT
SCLK
TFS
RFS
FO
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 43. AD5570 to ADSP2101/ADSP2103 Interface
pin via the DSP. Alterna-
LDAC
TFS
AD5570*
SDO
DIN
SCLK
SYNC
LDAC
is taken high.
03760-0-016
Rev. 0 | Page 21 of 24
Page 22
AD5570
AD5570 to PIC16C6x/7x
The PIC16C6x/7x synchronous serial port (SSP) is configured
as an SPI master with the clock polarity bit set to 0. This is done
by writing to the synchronous serial port control register
(SSPCON). See the PIC16/17 Microcontroller User Manual. In
this example, I/O port RA1 is being used to pulse
enable the serial port of the AD5570. This microcontroller
transfers only eight bits of data during each serial transfer
operation; therefore, two consecutive write operations are
needed. Figure 44 shows the connection diagram.
PIC16C6x/7x*
SDI/RC4
SDO/RC5
SCLK/RC3
RA1
AD5570*
SDO
DIN
SCLK
SYNC
SYNC
and
EVALUATION BOARD
The AD5570 comes with a full evaluation board to aid designers
in evaluating the high performance of the part with a minimum
of effort. All that is required with the evaluation board is a
power supply, a PC, and an oscilloscope.
The AD5570 evaluation kit includes a populated, tested AD5570
printed circuit board. The evaluation board interfaces to the
parallel interface of the PC. Software is available with the
evaluation board, which allows the user to easily program the
AD5570. A schematic of the evaluation board is shown in
Figure 45. The software runs on any PC that has Microsoft
Windows® 95/98/ME/2000 installed.
An application note is available that gives full details on
operating the evaluation board.
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 44. AD5570 to PIC16C6x/7x Interface
03760-0-017
Rev. 0 | Page 22 of 24
Page 23
AD5570
VOUT
REF/2
03760-0-043
J1
R2
AVDD
5
TRIM
U2
GND
ADR435
VOUT +VIN
62
LK3
TP4
C16
C34
REF
0.1µF
U1
+
C35
10µF
0.1µF
J2
AVDD
12 15
VSS
TP10TP7TP1TP2TP9TP3TP8
WHITE PLASTIC SSOP CLAMP
REFIN
VDD
VSS
PD
SDO
87654
10
13
VOUT
AD5570
DIN
SCLK
SYNC
LDAC
CLR
3
C1
R1
TP5
REFGND
REFGND
AGND
AGNDS
11 16 14
912
LK1
LK5
LK2
AVDD
10k
REF
C3
0.1µF
6
OP
7
–
V+
V
OP177
U3
3
2
REF/2
4
VSS
DGND
C18
10µF
AGND
+
R3
10k
C5
+
10µF
C36
0.1µF
C17
2
VIN
REFIN
3
GND DGND
18
VDD
C4
123
VOUT
GND1
0.01µF
4
GND2
SCLK
SDATA
BUSY
CONVST
U5
456
7
0.1µF
REF/2
DVDD
VIN
GND4U6GND3
LM78L05ACM AD7895-10
876
AVDD
975
OE
Y0Y1Y2
A0A1A2
1119131517
3
Y3
A3
74ACT244
PD LDAC SYNC CLR
21468
A0A1A2
A3
OE
U4–A
Y0
Y1Y2Y3
74ACT244
181614
12
DVDD
+
181614
12
Y0Y1Y2
Y3
U9–A
A0A1A2
A3
OE
21468
R4
4k7
74ACT244
DVDD DVDD
DVDD
U9–B
R6
4k7
R7
4k7
R5
4k7
J4 J5 J6 J7 J8 J9 J10
SDO DIN SCLK
LK4
SCLK_ADC
SDATA_ADC
SCLK
DIN
DOUT
SYNC
CLRPDCONVST
LDAC
DATA
DVDD
J13–1
C33
C32
C31
C30
0.1µF
0.1µF
0.1µF
10µF
0.33µF
20V
DGND
5
AVDD
U4–B
OE
1119131517
A0A1A2
Y0
Y1Y2Y3
753
9
A3
74ACT244
C2
AVDD
DGND
J13–2
AVDD
C14
0.1µF
C6
0.1µF
C7
0.1µF
C8
0.1µF
+
C9
10µF
+
C10
10µF
+
C11
10µF
++++
C12
10µF
AGND
J12–1
J12–2
AGND
C15
C24
C23
C22
C21
C13
VSS
0.1µF
0.1µF
0.1µF
10µF
10µF
10µF
VSS
J12–3
J11 – CENTRONICS CONNECTOR
J11–3
J11–13
J11–2
J11–5
J11–4
J11–6
J11–7
J11–8
J11–12
J11–10
Figure 45. Evaluation Board Schematic
Rev. 0 | Page 23 of 24
J11–9
J11–19
J11–20
J11–21
J11–22
J11–23
J11–24
J11–25
J11–26
J11–27
J11–28
J11–29
J11–30
Page 24
AD5570
OUTLINE DIMENSIONS
6.50
6.20
5.90
16 9
5.60
5.30
8.20
5.00
7.80
2.00 MAX
0.05 MIN
0.65
BSC
COPLANARITY
0.10
1
COMPLIANT TO JEDEC STANDARDS MO-150AC
0.38
0.22
1.85
1.75
1.65
8
0.25
0.09
SEATING
PLANE
7.40
Figure 46. 16-Lead Shrink Small Outline Package [SSOP]
(RS-16)
Dimensions shown in millimeters
8°
4°
0°
0.95
0.75
0.55
ORDERING GUIDE
Model Temperature Range Package Description Package Option
AD5570ARS −40 °C to +85 °C 16-Lead SSOP RS-16
AD5570ARS-REEL −40 °C to +85 °C 16-Lead SSOP RS-16
AD5570ARS-REEL7 −40 °C to +85 °C 16-Lead SSOP RS-16
AD5570BRS −40 °C to +85 °C 16-Lead SSOP RS-16
AD5570BRS-REEL −40 °C to +85 °C 16-Lead SSOP RS-16
AD5570BRS-REEL7 −40 °C to +85 °C 16-Lead SSOP RS-16
AD5570WRS −40 °C to +125 °C 16-Lead SSOP RS-16
AD5570WRS-REEL −40 °C to +125 °C 16-Lead SSOP RS-16
AD5570WRS-REEL7 −40 °C to +125 °C 16-Lead SSOP RS-16
AD5570YRS −40 °C to +125 °C 16-Lead SSOP RS-16
AD5570YRS-REEL −40 °C to +125 °C 16-Lead SSOP RS-16
AD5570YRS-REEL7 −40 °C to +125 °C 16-Lead SSOP RS-16
Eval-AD5570EB Evaluation Board
© 2003 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C03760–0–11/03(0)
Rev. 0 | Page 24 of 24
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