Datasheet AD5554, AD5544 Datasheet (Analog Devices)

Quad, Current-Output

57344491524096032768245761638481920 65536

CODE – Decimal

1.0

0.5

0.0

–0.5

–1.0

1.0

0.5

0.0

–0.5

–1.0

1.0

0.5

0.0

–0.5

–1.0

1.0

0.5

0.0

–0.5

–1.0

INL – LSB

DAC A

DAC B

DAC C

DAC D

a

FEATURES
AD5544 16-Bit Resolution
AD5554 14-Bit Resolution
2 mA Full-Scale Current 20%, with V
2 s Settling Time

BIAS for Zero-Scale Error Reduction @ Temp

V

SS

Midscale or Zero-Scale Reset
Four Separate 4Q Multiplying Reference Inputs
SPI-Compatible 3-Wire Interface
Double Buffered Registers Enable
Simultaneous Multichannel Change
Internal Power ON Reset
Compact SSOP-28 Package

APPLICATIONS
Automatic Test Equipment
Instrumentation
Digitally-Controlled Calibration

REF

= 10 V

Serial-Input, 16-Bit/14-Bit DACs

AD5544/AD5554

FUNCTIONAL BLOCK DIAGRAM

V

ABCD

REF

V

DD

RFBA

I

OUT

A

GND

RFBB

I

OUT

A

GND

R

FB

I

OUT

A

GND

R

FB

I

OUT

A

GND

A

GND

A

A

B

B

C

C

C

D

D

D

F

SDO

SDI

CLK

D0
D1
D2
D3
D4
D5
D6
D7
D8

16

D9
D10
D11
D12
D13
D14
D15

A0

A1

CS

EN

DAC A

B
C
D

2:4

DECODE

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

POWER-

ON

RESET

DAC A

REGISTER

R

DAC B

REGISTER

R

DAC C

REGISTER

R

DAC D

REGISTER

R

DAC A

R

DAC B

R

DAC C

R

DAC D

R

AD5544

GENERAL DESCRIPTION

The AD5544/AD5554 quad, 16-/14-bit, current-output, digital­to-analog converters are designed to operate from a single 5 V
supply.

The applied external reference input voltage (V
the full-scale output current. Integrated feedback resistors (R

) determines

REF

FB

)
provide temperature-tracking, full-scale voltage outputs when
combined with an external I-to-V precision amplifier.

A doubled-buffered serial-data interface offers high-speed,
3-wire, SPI- and microcontroller-compatible inputs using
serial-data-in (SDI), clock (CLK), and a chip-select (CS). In
addition, a serial-data-out pin (SDO) allows for daisy-chaining
when multiple packages are used. A common level-sensitive
load-DAC strobe (LDAC) input allows simultaneous update of
all DAC outputs from previously loaded input registers. Addi­tionally, an internal power ON reset forces the output voltage to
zero at system turn ON. An MSB pin allows system reset asser­tion (RS) to force all registers to zero code when MSB = 0, or
to half-scale code when MSB = 1.

AD5544/AD5554 are packaged in the compact SSOP-28.

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

LDACMSBRSDGND

V

SS

Figure 1. AD5544 INL vs. Code Plot (TA = 25°C)

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 2000

AD5544/AD5554–SPECIFICATIONS

AD5544 ELECTRICAL CHARACTERISTICS

(@ VDD = 5 V  10%, VSS = 0 V, I
V

A, B, C, D = 10 V, TA = Full Operating Temperature Range,

REF

unless otherwise noted.)

X = Virtual GND, A

OUT

X = 0 V,

GND

Parameter Symbol Condition Min Typ Max Unit

STATIC PERFORMANCE

Resolution N 1 LSB = V

1

/216 = 153 µV when V

REF

= 10 V 16 Bits

REF

Relative Accuracy INL ±4 LSB
Differential Nonlinearity DNL ±1.5 LSB
Output Leakage Current I

Full-Scale Gain Error G
Full-Scale Tempco

2

Feedback Resistor RFBXV

X Data = 0000H, TA = 25°C10nA

OUT

I

X Data = 0000H, TA = TA Max 20 nA

OUT

FSE

TCV

FS

Data = FFFF

H

±0.75 ±3mV
1 ppm/°C

= 5 V 4 6 8 kΩ

DD

REFERENCE INPUT

X Range V

V

REF

Input Resistance R
Input Resistance Match R
Input Capacitance

2

X –15 +15 V

REF

X468kΩ

REF

X Channel-to-Channel 1 %

REF

C

X5pF

REF

ANALOG OUTPUT

Output Current I
Output Capacitance

2

X Data = FFFF

OUT

C

X Code-Dependent 80 pF

OUT

H

1.25 2.5 mA

LOGIC INPUTS AND OUTPUT

Logic Input Low Voltage V
Logic Input High Voltage V
Input Leakage Current I
Input Capacitance

2

Logic Output Low Voltage V
Logic Output High Voltage V

INTERFACE TIMING

2, 3

Clock Width High t
Clock Width Low t
CS to Clock Setup t
Clock to CS Hold t
Clock to SDO Prop Delay t
Load DAC Pulsewidth t
Data Setup t
Data Hold t
Load Setup t
Load Hold t

IL

IH

IL

C

IL

OL

OH

CH

CL

CSS

CSH

PD

LDAC

DS

DH

LDS

LDH

2.4 V

IOL = 1.6 mA 0.4 V
IOH = 100 µA4V

25 ns
25 ns
0ns
25 ns
220ns
25 ns
20 ns
20 ns
5ns
25 ns

0.8 V

1 µA
10 pF

SUPPLY CHARACTERISTICS

Power Supply Range V
Positive Supply Current I
Negative Supply Current I
Power Dissipation P

DD RANGE

DD

SS

DISS

Logic Inputs = 0 V 50 250 µA
Logic Inputs = 0 V, VSS = –5 V 0.001 1 µA
Logic Inputs = 0 V 1.25 mW

4.5 5.5 V

Power Supply Sensitivity PSS ∆VDD = ±5% 0.006 %/%

NOTES

1

All static performance tests (except I
RFB terminal is tied to the amplifier output. Typical values represent average readings measured at 25 °C.

2

These parameters are guaranteed by design and not subject to production testing.

3

All input control signals are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.

Specifications subject to change without notice.

) are performed in a closed-loop system using an external precision OP177 I-to-V converter amplifier. The AD5544

OUT

–2–

REV. 0

AD5544/AD5554

(@ V

= 5 V  10%, VSS = –300 mV, I

DD

V

A, B, C, D = 10 V, TA = full operating temperature range, unless

AD5544 ELECTRICAL CHARACTERISTICS

REF

otherwise noted.)

Parameter Symbol Condition Min Typ Max Unit

AC CHARACTERISTICS

Output Voltage Settling Time t

Output Voltage Settling Time t

Reference Multiplying BW BW –3 dB V

DAC Glitch Impulse Q V
Feedthrough Error V
Crosstalk Error V

1

S

S

OUT

OUT

X/V
A/V

To ±0.1% of Full Scale, Data = 0000
to FFFF

to 0000

H

H

To ±0.0015% of Full Scale, Data = 0000
to FFFF

REF

C

FB

REF

X Data = 0000H, V

REF

B Data = 0000H, V

REF

to 0000

H

H

X = 100 mV rms, Data = FFFFH, 2 MHz

= 15 pF

X = 10 V, Data 0000H to 8000H to 0000

X = 100 mV rms, f = 100 kHz –65 dB

REF

B = 100 mV rms, –90 dB

REF

H

H

Adjacent Channel, f = 100 kHz

Digital Feedthrough Q CS = 1, and f
Total Harmonic Distortion THD V
Output Spot Noise Voltage e

NOTES

1

All ac characteristic tests are performed in a closed-loop system using an OP42 I-to-V converter amplifier.

Specifications subject to change without notice.

N

= 5 V p-p, Data = FFFFH, f = 1 kHz –90 dB

REF

f = 1 kHz, BW = 1 Hz 7 nV/√Hz

= 1 MHz 5 nV-s

CLK

X = Virtual GND, A

OUT

H

X = 0 V,

GND

1 µs

2 µs

1.2 nV-s

REV. 0

–3–

AD5544/AD5554–SPECIFICATIONS

AD5554 ELECTRICAL CHARACTERISTICS

= 5 V  10%, VSS = 0 V, I

DD

V

A, B, C, D = 10 V, TA = full operating temperature range,

REF

unless otherwise noted.)

X = Virtual GND, A

OUT

GND

X = 0 V,

(@ V

Parameter Symbol Condition Min Typ Max Unit

STATIC PERFORMANCE

Resolution N 1 LSB = V

1

/214 = 610 µV when V

REF

= 10 V 14 Bits

REF

Relative Accuracy INL ±1 LSB
Differential Nonlinearity DNL ±1 LSB
Output Leakage Current I

Full-Scale Gain Error G
Full-Scale Tempco

2

Feedback Resistor RFBXV

X Data = 0000H, TA = 25°C10nA

OUT

I

X Data = 0000H, TA = TA Max 20 nA

OUT

FSE

TCV

FS

Data = 3FFF

H

±2 ±10 mV
1 ppm/°C

= 5 V 4 6 8 kΩ

DD

REFERENCE INPUT

V

X Range V

REF

Input Resistance R
Input Resistance Match R
Input Capacitance

2

X –15 +15 V

REF

X468kΩ

REF

X Channel-to-Channel 1 %

REF

C

X5pF

REF

ANALOG OUTPUT

Output Current I
Output Capacitance

2

X Data = 3FFF

OUT

C

X Code-Dependent 80 pF

OUT

H

1.25 2.5 mA

LOGIC INPUTS AND OUTPUT

Logic Input Low Voltage V
Logic Input High Voltage V
Input Leakage Current I
Input Capacitance

2

Logic Output Low Voltage V
Logic Output High Voltage V

INTERFACE TIMING

2, 3

Clock Width High t
Clock Width Low t
CS to Clock Setup t
Clock to CS Hold t
Clock to SDO Prop Delay t
Load DAC Pulsewidth t
Data Setup t
Data Hold t
Load Setup t
Load Hold t

IL

IH

IL

C

IL

OL

OH

CH

CL

CSS

CSH

PD

LDAC

DS

DH

LDS

LDH

2.4 V

I

= 1.6 mA 0.4 V

OL

I

= 100 µA4V

OH

25 ns
25 ns
0ns
25 ns
220ns
25 ns
20 ns
20 ns
5ns
25 ns

0.8 V

1 µA
10 pF

SUPPLY CHARACTERISTICS

Power Supply Range V
Positive Supply Current I
Negative Supply Current I
Power Dissipation P

DD RANGE

DD

SS

DISS

Logic Inputs = 0 V 50 250 µA
Logic Inputs = 0 V, VSS = –5 V 0.001 1 µA
Logic Inputs = 0 V 1.25 mW

4.5 5.5 V

Power Supply Sensitivity PSS ∆VDD = ±5% 0.006 %/%

NOTES:

1

All static performance tests (except I
RFB terminal is tied to the amplifier output. Typical values represent average readings measured at 25 °C.

2

These parameters are guaranteed by design and not subject to production testing.

3

All input control signals are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.

Specifications subject to change without notice.

) are performed in a closed-loop system using an external precision OP177 I-to-V converter amplifier. The AD5554

OUT

–4–

REV. 0

AD5544/AD5554

WARNING!

ESD SENSITIVE DEVICE

(@ V

= 5 V  10%, VSS = –300 mV, I

DD

B, C, D = 10 V, TA = full operating temperature range, unless otherwise

AD5554 ELECTRICAL CHARACTERISTICS

noted.)

Parameter Symbol Condition Min Typ Max Unit

AC CHARACTERISTICS

Output Voltage Settling Time t

Output Voltage Settling Time t

Reference Multiplying BW BW –3 dB V
DAC Glitch Impulse Q V
Feedthrough Error V
Crosstalk Error V

1

S

S

OUT

OUT

X/V
A/V

To ±0.1% of Full Scale, Data = 0000
to 3FFF

to 0000

H

H

To ±0.0015% of Full Scale, Data = 0000
to 3FFF

REF

REF

X Data = 0000H, V

REF

B Data = 0000H, V

REF

to 0000

H

H

X = 100 mV rms, Data = 3FFFH, CFB = 15 pF 2 MHz
X = 10 V, Data 0000H to 2000H to 0000

X = 100 mV rms, f = 100 kHz –65 dB

REF

B = 100 mV rms,

REF

H

H

Adjacent Channel, f = 100 kHz –90 dB

Digital Feedthrough Q CS = 1, and f
Total Harmonic Distortion THD V
Output Spot Noise Voltage e

NOTES:

1

All ac characteristic tests are performed in a closed-loop system using an OP42 I-to-V converter amplifier.

Specifications subject to change without notice.

N

= 5 V p-p, Data = 3FFFH, f = 1 kHz –90 dB

REF

f = 1 kHz, BW = 1 Hz 7 nV/√Hz

= 1 MHz 5 nV-s

CLK

X = Virtual GND, A

OUT

H

X = 0 V, V

GND

1 µs

2 µs

1.2 nV-s

REF

A,

ABSOLUTE MAXIMUM RATINGS*

VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +8 V

V

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V, –7 V

SS

V

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 V, +18 V

REF

Logic Inputs and Output to GND . . . . . . . . . . . . –0.3 V, +8 V

) to GND . . . . . . . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V

V(I

OUT

A

X to DGND . . . . . . . . . . . . . . . . . . . . . . –0.3 V, + 0.3 V

GND

Input Current to Any Pin Except Supplies . . . . . . . . . ±50 mA

Package Power Dissipation . . . . . . . . . . . . (T

Thermal Resistance θ

JA

MAX – TA)/θ

J

28-Lead Shrink Surface-Mount (RS-28) . . . . . . . . 100°C/W

Maximum Junction Temperature (T

MAX) . . . . . . . . . 150°C

J

Operating Temperature Range

Model A . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C

Lead Temperature:

RS-28 (Vapor Phase, 60 secs) . . . . . . . . . . . . . . . . . . 215°C

RS-28 (Infrared, 15 secs) . . . . . . . . . . . . . . . . . . . . . . 220°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational

JA

sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

ORDERING GUIDE

RES INL DNL Temperature Package Package

Model Bit LSB LSB Range Description Option

AD5544ARS 16 ± 4 ± 1.5 –40/+85°C SSOP-28 RS-28
AD5554BRS 14 ± 1 ± 1 – 40/+85°C SSOP-28 RS-28

The AD5544/AD5554 contain 4196 transistors. The die size is 122 mil × 204 mil.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD5544/AD5554 features proprietary ESD protection circuitry, permanent damage may occur
on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.

REV. 0

–5–

AD5544/AD5554

SDI

CLK

CS

LDAC

SDI

CLK

CS

LDAC

A1 A0 D15 D14 D13 D12 D11 D10 D1 D0

t

t

t

CSS

t

DH

DS

t

CL

CH

t

LDS

t

SDO

t

PD

Figure 2. AD5544 Timing Diagram

A1 A0 D13 D12 D11 D10 D09 D08 D1 D0

t

t

t

CSS

t

DH

DS

t

CL

CH

t

LDS

t

SDO

t

PD

t

CSH

LDAC

t

CSH

LDAC

INPUT

REG

LD

INPUT

REG

LD

t

LDH

t

LDH

Figure 3. AD5554 Timing Diagram

Table I. AD5544 Control-Logic Truth Table

CS CLK LDAC RS MSB Serial Shift Register Function Input Register Function DAC Register

H X H H X No Effect Latched Latched
L L H H X No Effect Latched Latched
L ↑+ H H X Shift-Register-Data Advanced One Bit Latched Latched
L H H H X No Effect Latched Latched
↑+ L H H X No Effect Selected DAC Updated Latched

with Current SR Contents
H X L H X No Effect Latched Transparent
H X H H X No Effect Latched Latched
HX ↑+ H X No Effect Latched Latched
H X H L 0 No Effect Latched Data = 0000

Latched Data = 0000

H

H X H L H No Effect Latched Data = 8000HLatched Data = 8000

H

H

–6–

REV. 0

AD5544/AD5554

Table II. AD5554 Control-Logic Truth Table

CS CLK LDAC RS MSB Serial Shift Register Function Input Register Function DAC Register

H X H H X No Effect Latched Latched
L L H H X No Effect Latched Latched
L ↑+ H H X Shift-Register-Data Advanced One Bit Latched Latched
L H H H X No Effect Latched Latched
↑+ L H H X No Effect Selected DAC Updated Latched

with Current SR Contents
H X L H X No Effect Latched Transparent
H X H H X No Effect Latched Latched
HX ↑+ H X No Effect Latched Latched
H X H L 0 No Effect Latched Data = 0000
H X H L H No Effect Latched Data = 2000

NOTES

1. SR = Shift Register.

2. ↑+ positive logic transition; X = Don’t Care.

3. At power ON both the Input Register and the DAC Register are loaded with all zeros.

4. For AD5544, data appears at the SDO Pin 19 clock pulses after input at the SDI pin.

5. For AD5554, data appears at the SDO Pin 17 clock pulses after input at the SDI pin.

Table III. AD5544 Serial Input Register Data Format, Data Is Loaded in the MSB-First Format

MSB LSB

Bit Position B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

Data Word A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

NOTE
Only the last 18 bits of data clocked into the serial register (Address + Data) are inspected when the CS line’s positive edge returns to logic high. At this point an inter­nally generated load strobe transfers the serial register data contents (Bits D15–D0) to the decoded DAC-Input-Register address determined by bits A1 and A0. Any
extra bits clocked into the AD5544 shift register are ignored, only the last 18 bits clocked in are used. If double-buffered data is not needed, the LDAC pin can be tied
logic low to disable the DAC Registers.

Latched Data = 0000

H

Latched Data = 2000

H

H

H

Table IV. AD5554 Serial Input Register Data Format, Data Is Loaded in the MSB-First Format

MSB LSB

Bit Position B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

Data Word A1 A0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

NOTE
Only the last 16 bits of data clocked into the serial register (Address + Data) are inspected when the CS line’s positive edge returns to logic high. At this point an inter­nally generated load strobe transfers the serial register data contents (Bits D13–D0) to the decoded DAC-Input-Register address determined by bits A1 and A0. Any
extra bits clocked into the AD5554 shift register are ignored, only the last 16 bits clocked in are used. If double-buffered data is not needed, the LDAC pin can be tied
logic low to disable the DAC Registers.

Table V. Address Decode

A1 A0 DAC Decoded

0 0 DAC A
0 1 DAC B
1 0 DAC C
1 1 DAC D

REV. 0

–7–

AD5544/AD5554

AD5544/AD5554 PIN FUNCTION DESCRIPTIONS

Pin # Name Function

1A
2I
3V
4R
5 MSB MSB Bit Set Pin During a Reset Pulse (RS) or at System Power ON if Tied to Ground or V
6 RS Reset Pin, Active Low Input. Input registers and DAC registers are set to all zeros or half-scale code (8000

7V
8 CS Chip Select, Active Low Input. Disables shift register loading when high. Transfers serial register data to the Input

9 CLK Clock Input, Positive Edge Clocks Data into Shift Register.
10 SDI Serial Data Input, Input Data Loads Directly into the Shift Register.
11 R
12 V
13 I
14 A
15 A
16 I
17 V
18 R
19 NC No Connect. Leave pin unconnected.
20 SDO Serial Data Output, input data loads directly into the shift register. Data appears at SDO, 19 clock pulses for

21 LDAC Load DAC Register Strobe, Level Sensitive Active Low. Transfers all Input Register data to DAC registers. Asyn-

22 A
23 V
24 DGND Digital Ground Pin.
25 R
26 V
27 I
28 A

A DAC A Analog Ground.

GND

A DAC A Current Output.

OUT

A DAC A Reference Voltage Input Terminal. Establishes DAC A full-scale output voltage. Pin can be tied to VDD pin.

REF

A Establish Voltage Output for DAC A by Connecting to External Amplifier Output.

FB

.

DD

DD

AD5544 and 2000
= 0. Register Data = 8000

Positive Power Supply Input. Specified range of operation 5 V ± 10%.

for AD5554) determined by the voltage on the MSB pin. Register Data = 0000H when MSB

H

for AD5544 and 2000H for AD5554 when MSB = 1.

H

Register when CS/LDAC returns High. Does not effect LDAC operation.

B Establish Voltage Output for DAC B by Connecting to External Amplifier Output.

FB

B DAC B Reference Voltage Input Terminal. Establishes DAC B full-scale output voltage. Pin can be tied to VDD pin.

REF

B DAC B Current Output.

OUT

B DAC B Analog Ground.

GND

C DAC C Analog Ground.

GND

C DAC C Current Output.

OUT

C DAC C Reference Voltage Input Terminal. Establishes DAC C full-scale output voltage. Pin can be tied to VDD pin.

REF

C Establish voltage output for DAC C by connecting to external amplifier output.

FB

AD5544 and 17 clock pulses for AD5554 after input at the SDI pin.

chronous active low input. See Control Logic Truth Table for operation.

F High Current Analog Force Ground.

GND

SS

FB

REF

OUT

GND

Negative Bias Power Supply Input. Specified range of operation –0.3 V to –5.5 V.

D Establish Voltage Output for DAC D by Connecting to External Amplifier Output.

D DAC D Reference Voltage Input Terminal. Establishes DAC D full-scale output voltage. Pin can be tied to VDD pin.

D DAC D Current Output.

D DAC D Analog Ground.

for

H

AD5544/AD5554 PIN CONFIGURATION

1

A

AA

GND

2

AI

I

OUT

3

V

AV

REF

4

R

AR

FB

5

MSB DGND

CLK SDO

R

V

REF

I

OUT

A

GND

AD5544/

6

RS

AD5554

7

V

DD

TOP VIEW

(Not to Scale)

8

CS LDAC

9

10

SDI NC

11

BR

FB

12

BV

13

BI

14

BA

NC = NO CONNECT

28

D

GND

27

D

OUT

26

D

REF

25

D

FB

24

23

V

SS

22

A

F

GND

21

20

19

18

C

FB

17

C

REF

16

C

OUT

15

C

GND

–8–

REV. 0

Typical Performance Characteristics–AD5544/AD5554

OP AMP OFFSET VOLTAGE – V

2.0

INTEGRAL NONLINEARITY ERROR – LSB

–1500

1.5

1.0

0.5

0

–0.5

–1.0

–1.5

–2.0

–1000 –500

0

500 1000 1500

VDD = 5V
V

REF

= 10V

T

A

= 25C

F000

H

8000

H

0FFF

H

7FFF

H

0.50

0.25

0.00

–0.25

–0.50

0.50

0.25

0.00

–0.25

–0.50

0.50

DNL – LSB

0.25

0.00

–0.25

–0.50

0.50

0.25

0.00

–0.25

–0.50

CODE – Decimal

TPC 1. AD5544 DNL vs. Code (TA = 25°C)

–0.5

–1.0

–0.5

–1.0

INL – LSB

–0.5

–1.0

–0.5

–1.0

1.0

0.5

0.0

1.0

0.5

0.0

1.0

0.5

0.0

1.0

0.5

0.0

CODE – Decimal

DAC A

DAC B

DAC C

DAC D

TPC 2. AD5554 INL vs. Code (TA = 25°C)

DAC A

DAC B

DAC C

DAC D

57344491524096032768245761638481920 65536

14336122881024081926144409620480 16384

–0.25
–0.50
–0.75

–0.25
–0.50
–0.75

DNL – LSB

–0.25
–0.50
–0.75

–0.25
–0.50
–0.75

0.75

0.50

0.25

0.00

0.75

0.50

0.25

0.00

0.75

0.50

0.25

0.00

0.75

0.50

0.25

0.00

DAC A

DAC B

DAC C

DAC D

CODE – Decimal

14336122881024081926144409620480 16384

TPC 3. AD5554 DNL vs. Code (TA = 25°C)

TPC 4. AD5544 Integral Nonlinearity Error vs.
Op Amp Offset

REV. 0

–9–

AD5544/AD5554

0.75

VDD = 5V

= 10V

V

REF

0.50
= 25C

T

–0.25

–0.50

INTEGRAL NONLINEARITY ERROR – LSB

–0.75

0.25

0.00

–2000

A

–1500 –1000 –500

OP AMP OFFSET VOLTAGE – V

0

500 20001000 1500

3000

2000

1FFF

0FFF

H

H

H

H

TPC 5. AD5554 Integral Nonlinearity Error vs.
Op Amp Offset

1.00
VDD = 5V

= 10V

V

REF

–0.25

–0.50

–0.75

DIFFERENTIAL NONLINEARITY ERROR – LSB

–1.00

0.75

0.50

0.25

0.00

–1000

T

A

= 25C

–750 –500 –250

OP AMP OFFSET VOLTAGE – V

0

250 500 750 1000

8000

F000

0FFF

H

H

H

TPC 6. AD5544 Differential Nonlinearity Error vs.
Op Amp Offset

10.0

7.5

5.0

2.5

0.0

–2.5

GAIN ERROR – LSB

–5.0

–7.5

–10.0

–1500

–1000 –500

OP AMP OFFSET VOLTAGE – V

0

VDD = 5V

= 10V

V

REF

= 25C

T

A

500 1000 1500

TPC 8. AD5544 Gain Error vs. Op Amp Offset

–1

–2

GAIN ERROR – LSB

–3

–4

–5
–1500

4

3

2

1

0

–1000 –500

OP AMP OFFSET VOLTAGE – V

0

VDD = 5V

= 10V

V

REF

= 25C

T

A

500 1000 1500

TPC 9. AD5554 Gain Error vs. Op Amp Offset

0.3

–0.1

–0.2

DIFFERENTIAL NONLINEARITY ERROR – LSB

–0.3

0.2

0.1

0.0

–1500

VDD = 5V

= 10V

V

REF

= 25C

T

A

–1000 –500

ACCURACY DEGRADATION
DUE TO EXTERNAL OP AMP
INPUT OFFSET VOLTAGE
SPECIFICATION.

OP AMP OFFSET VOLTAGE – V

0

2000

3000

0FFF

500 15001000

H

H

H

TPC 7. AD5554 Differential Nonlinearity Error vs.
Op Amp Offset

–10–

30

SS = 120 UNITS

= 5V

V

DD

= 10V

V

REF

= –40C TO +85C

T

A

20

FREQUENCY

10

0

0

0.5 1.0 1.5

FULL-SCALE TEMPCO – ppm/C

TPC 10. AD5544 Full-Scale Tempco (ppm/C)

REV. 0

AD5544/AD5554

CLOCK FREQUENCY – Hz

10000

1k

I

DD

– A

1000

100

10

10k 100k 1M 10M 100M

VDD = 5V
V

REF

= 10V

T

A

= 25C

5555

H

FFFF

H

8000

H

0000

H

CLOCK FREQUENCY – Hz

10000

1k

I

DD

– A

1000

100

10

10k 100k 1M 10M 100M

VDD = 5V
V

REF

= 10V

T

A

= 25C

1555

H

3FFF

H

2000

H

0000

H

60

40

30

20

FREQUENCY

10

0

0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8

0.2
FULL-SCALE ERROR TEMPCO – ppm/C

TPC 11. AD5554 Full-Scale Tempco (ppm/C)

7FFFH ➔ 8000

H

SS = 180 UNITS

= 5V

V

DD

= 10V

V

REF

= –40C TO +85C

T

A

VDD = 5V

= 10V

V

REF

= 25C

T

A

CS

(5V/DIV)

V

OUT

(50mV/DIV)

1s/DIV

TPC 14. AD5544 Small Signal Settling Time

VDD = 5V

= 10V

V

REF

= 25C

T

A

= –343

A

V

1LSB = 52mV

V

OUT

(10V/DIV)

V

OUT

(50mV/DIV)

TPC 13. AD5544 Large Signal Settling Time

100ns/DIV

TPC 12. AD5544 Midscale Transition

0000H ➔ FFFF

H

2s/DIV

VDD = 5V

= 10V

V

REF

= 25C

T

A

CS

(5V/DIV)

V

OUT

(5V/DIV)

TPC 15. AD5544 Power Supply Current vs.
Clock Frequency

TPC 16. AD5554 Power Supply Current vs.

Clock Frequency

REV. 0

–11–

AD5544/AD5554

100

VDD = 5V 10%

90

T

= 25C

A

80

70

60

PSRR – dB

50

40

30

20

1k

CLOCK FREQUENCY – Hz

10k 100k 1M100

TPC 17. AD5544/AD5554 Power Supply Rejection
vs. Frequency

55

VDD = 5V

54

53

52

51

50

49

SUPPLY CURRENT – A

48

47

46

= 10V

V

REF

LOGIC = V

DD

–25 0 25 50 75 100 125 150

–50

TEMPERATURE – C

TPC 18. AD5544/AD5554 Power Supply Current
vs. Temperature

600

VDD = 5V
V

= 10V

REF

500

= 25C

T

A

400

300

– A

DD

I

200

100

0

0

12345

LOGIC INPUT VOLTAGE – Volts

TPC 19. AD5544/AD5554 Power Supply Current
vs. Logic Input Voltage

CIRCUIT OPERATION

The AD5544 and AD5554 contain four, 16-bit and 14-bit,
current-output, digital-to-analog converters respectively. Each
DAC has its own independent multiplying reference input. Both
AD5544/AD5554 use 3-wire SPI compatible serial data inter­face, with a configurable asynchronous RS pin for half-scale
(MSB = 1) or zero-scale (MSB = 0) preset. In addition, an
LDAC strobe enables four channel simultaneous updates for
hardware synchronized output voltage changes.

D/A Converter Section

Each part contains four current-steering R-2R ladder DACs.
Figure 4 shows a typical equivalent DAC. Each DAC contains
a matching feedback resistor for use with an external I-to-V
converter amplifier. The R
the external amplifier. The I
inverting input of the external amplifier. The A

X pin is connected to the output of

FB

X terminal is connected to the

OUT

X pin should

GND

be Kelvin-connected to the load point in the circuit requiring
the full 16-bit accuracy. These DACs are designed to operate

–12–

with both negative or positive reference voltages. The V

DD

power
pin is only used by the logic to drive the DAC switches ON and
OFF. Note that a matching switch is used in series with the
internal 5 kΩ feedback resistor. If users are attempting to mea­sure the value of R
achieve continuity. An additional V

, power must be applied to VDD in order to

FB

bias pin is used to guard

SS

the substrate during high temperature applications to minimize
zero-scale leakage currents that double every 10°C. The DAC
output voltage is determined by V

VV

=− ×

OUT REF

VV

=− ×

OUT REF

D

(For AD5544) (Equation 1)

65536

D

(For AD5554) (Equation 2)

16384

Note that the output polarity is opposite to the V

and the digital data (D) as:

REF

polarity for

REF

dc reference voltages.

REV. 0

AD5544/AD5554

FREQUENCY – Hz

1k

GAIN – 12dB/DIV

3FFF

H

10k 100k 1M 10M100

B13
B12
B11
B10

B9
B8
B7
B6
B5
B4
B3
B2
B1
B0

ZS

VDD = 5V
V

REF

= 100mV rms

T

A

= 25C

C

F

= 23pF

V

V

X

REF

DIGITAL INTERFACE CONNECTIONS OMITTED FOR CLARITY.
SWITCHES S1 AND S2 ARE CLOSED, V

RRR

FROM OTHER DACS A

V

DGND

SS

GND

MUST BE POWERED.

DD

R2R2R2R 5k

DD

RFBX

S1S2

X

I

OUT

A

F

GND

X

A

GND

Figure 4. Typical Equivalent DAC Channel

These DACs are also designed to accommodate ac reference
input signals. Both AD5544/AD5554 will accommodate input
reference voltages in the range of –12 V to +12 V. The reference
voltage inputs exhibit a constant nominal input resistance of
5kΩ, ± 30%. On the other hand, the DAC outputs I

OUT

A, B,
C, D are code-dependent and produce various output resis­tances and capacitances. The choice of external amplifier
should take into account the variation in impedance generated
by the AD5544/AD5554 on the amplifiers’ inverting input
node. The feedback resistance, in parallel with the DAC ladder
resistance, dominates output voltage noise. For multiplying
mode applications, an external feedback compensation capacitor

) may be needed to provide a critically damped output

(C

FB

response for step changes in reference input voltages. Figures 5
and 6 show the gain vs. frequency performance at various
attenuation settings using a 23 pF external feedback capacitor
connected across the I

X and RFBX terminals for AD5544

OUT

and AD5554 respectively. In order to maintain good analog
performance, power supply bypassing of 0.01 µF, in parallel
with 1 µF, is recommended. Under these conditions, clean
power supply with low ripple voltage capability should be used.
Switching power supplies is usually not suitable for this application
due to the higher ripple voltage and PSS frequency-dependent
characteristics. It is best to derive the AD5544/AD5554’s 5 V
supply from the systems’ analog supply voltages. (Do not use
the digital 5 V supply.) See Figure 7.

FFFF

H

B15
B14
B13
B12
B11
B10

B9
B8
B7
B6
B5
B4

GAIN – 12dB/DIV

B3
B2
B1

B0
ZS

1k

10k 100k 1M 10M100

FREQUENCY – Hz

VDD = 5V

= 100mV rms

V

REF

= 25C

T

A

Figure 5. AD5554 Reference Multiplying Bandwidth
vs. Code

Figure 6. AD5554 Reference Multiplying Bandwidth
vs. Code

15V

2R

+

R

ANALOG

POWER

SUPPLY

5V

REV. 0

V

X

REF

DIGITAL INTERFACE CONNECTIONS OMITTED.
FOR CLARITY SWITCHES S1 AND S2 ARE CLOSED,
V

DD

RRR

FROM OTHER DACS A

V

SS

MUST BE POWERED.

Figure 7. Recommended Kelvin-Sensed Hookup

V

DD

R2R2R2R 5k

GND

AD5544

DGND

–13–

RFBX

15V

S1S2

I

A

A

OUT

GND

GND

X

F

X

V

CC

V

A1

OUT

+

V

EE

LOAD

AD5544/AD5554

CS

EN

CLK

AD5544

V

REF

A B C D

V

DD

SDI

SDO

D10
D11
D12
D13
D14
D15

16

D0
D1
D2
D3
D4
D5
D6
D7
D8
D9

DAC A

2:4

DECODE

B
C
D

POWER-

ON

RESET

A0
A1

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

SET

MSB

R

R

R

R

DAC A

REGISTER

DAC B

REGISTER

DAC C

REGISTER

DAC D

REGISTER

SET

MSB

R

R

R

R

DAC A

DAC B

DAC C

DAC D

RFBA

I

OUT

A

GND

R

FB

I

OUT

A

GND

R

FB

I

OUT

A

GND

R

FB

I

OUT

A

GND

A

GND

A

A

B

B

B

C

C

C

D

D

D

F

DGND MSB

Figure 8. System Level Digital Interfacing

SERIAL DATA INTERFACE

The AD5544/AD5554 uses a 3-wire (CS, SDI, CLK) SPI com­patible serial data interface. Serial data of AD5544 and AD5554
is clocked into the serial input register in an 18-bit and 16-bit
data-word format respectively. MSB bits are loaded first. Table
II defines the 18 data-word bits for AD5544. Table III defines
the 16 data-word bits for AD5554. Data is placed on the SDI
pin, and clocked into the register on the positive clock edge of
CLK subject to the data setup and data hold time requirements
specified in the Interface Timing Specifications. Data can only
be clocked in while the CS chip select pin is active low. For
AD5544, only the last 18 bits clocked into the serial register will
be interrogated when the CS pin returns to the logic high state,
extra data bits are ignored. For AD5554, only the last 16 bits
clocked into the serial register will be interrogated when the CS
pin returns to the logic high state. Since most microcontrollers
output serial data in 8-bit bytes, three right-justified data bytes
can be written to the AD5544. Keeping the CS line low between
the first, second, and third byte transfers will result in a success­ful serial register update. Similarly, two right-justified data bytes

LDAC RS

V

SS

can be written to the AD5554. Keeping the CS line low between
the first and second byte transfer will result in a successful serial
register update.

Once the data is properly aligned in the shift register, the posi­tive edge of the CS initiates the transfer of new data to the target
DAC register, determined by the decoding of address bits A1
and A0. For AD5544, Tables I, III, V, and Figure 2 define the
characteristics of the software serial interface. For AD5554,
Tables II, IV, V, and Figure 3 define the characteristics of the
software serial interface. Figures 8 and 9 show the equivalent
logic interface for the key digital control pins for AD5544.
AD5554 has similar configuration, except with 14 data bits.

Two additional pins RS and MSB provide hardware control
over the preset function and DAC Register loading. If these
functions are not needed, the RS pin can be tied to logic high.
The asynchronous input RS pin forces all input and DAC regis­ters to either the zero-code state (MSB = 0), or the half-scale
state (MSB = 1)

–14–

REV. 0

AD5544/AD5554

V

D

V

OUT REF

=−











×

32768

1

TO INPUT REGISTER

A

CLOCK

B
C
D

TH

CS

CLK

SDI

SDO

EN

ADDRESS

DECODER

SHIFT REGISTER

19TH/17

Figure 9. AD5544/AD5554 Equivalent Logic Interface

POWER-ON RESET

When the VDD power supply is turned ON, an internal reset
strobe forces all the Input and DAC registers to the zero-code
state or half-scale, depending on the MSB pin voltage. The V

DD

power supply should have a smooth positive ramp without
drooping in order to have consistent results, especially in the
region of V

= 1.5 V to 2.3 V. The VSS supply has no effect on

DD

the power-ON reset performance. The DAC register data will
stay at zero or half-scale setting until a valid serial register data
load takes place.

ESD Protection Circuits

All logic-input pins contain back-biased ESD protection Zeners
connected to ground (DGND) and V

V

DD

DIGITAL

INPUTS

5k

as shown in Figure 9.

DD

DGND

Figure 10. Equivalent ESD Protection Circuits

PCB LAYOUT

In PCB layout, all analog ground, A

X, should be tied together.

GND

Amplifiers suitable for I-to-V conversion include:

• High Accuracy: OP97, OP297

• Speed and Accuracy: OP42

• ±5 V Applications: OP162/OP262/OP462, OP184/OP284/

OP484

APPLICATIONS

The AD5544/AD5554 are inherently 2-quadrant multiplying
D/A converters. That is, they can be easily set up for unipolar
output operation. The full-scale output polarity is the inverse of
the reference-input voltage.

In some applications it may be necessary to generate the full 4­quadrant multiplying capability or a bipolar output swing. This
is easily accomplished using an additional external amplifier
(A2) configured as a summing amplifier (see Figure 11). In this
circuit the first and second amplifiers (A1 and A2) provide a
total gain-of-2 which increases the output voltage span to 20 V.
Biasing the external amplifier with a 10 V offset from the refer­ence voltage results in a full 4-quadrant multiplying circuit. The
transfer equation of this circuit shows that both negative and
positive output voltages are created as the input data (D) is
incremented from code zero (V
= 0 V) to full-scale (V

= 10 V).

OUT

= –10 V) to midscale (V

OUT

OUT

(For AD5544) (Equation 3)

D

V

DD

ONE CHANNEL

VSSA



1




AD5544

×

V

(For AD5554) (Equation 4)

10k

A2

–10V < V

OUT

X

A1

REF

GND

R

X

FA

FB

GND

10k

5k

XV

I

OUT

X

V

OUT

< +10V

V



=−

OUT REF



8192



10V

V

REF

AD588

DIGITAL INTERFACE CONNECTIONS
OMITTED FOR CLARITY.

Figure 11. Four-Quadrant Multiplying Application Circuit

REV. 0

–15–

AD5544/AD5554

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

28-Lead SSOP

(RS-28)

0.407 (10.34)

0.397 (10.08)

28 15

0.311 (7.9)

0.301 (7.64)

0.078 (1.98)

0.068 (1.73)

0.008 (0.203)

0.002 (0.050)

PIN 1

0.0256
(0.65)

BSC

0.015 (0.38)

0.010 (0.25)

0.066 (1.67)

SEATING

PLANE

0.212 (5.38)

141

0.07 (1.79)

0.009 (0.229)

0.005 (0.127)

0.205 (5.21)

8°
0°

C3563–8–4/00 (rev. 0) 00943

0.03 (0.762)

0.022 (0.558)

–16–

PRINTED IN U.S.A.

REV. 0