Datasheet AD5545 Datasheet (Analog Devices)

K

Dual, Current-Output,

Serial-Input, 16-/14-Bit DAC

AD5545/AD5555

FEATURES

FUNCTIONAL BLOCK DIAGRAM

16-bit resolution AD5545 14-bit resolution AD5555 ±1 LSB DNL monotonic ±2 LSB INL AD5545 2 mA full-scale current ±20%, with V

= 10 V

REF

0.5 µs settling time 2Q multiplying reference-input 4 MHz BW Zero or midscale power-up preset Zero or midscale dynamic reset 3-wire interface Compact TSSOP-16 package

APPLICATIONS

V

DD

SDI

CS

CL

16 OR 14

D0..DX

EN

DAC A

B

ADDR

DECODE

DGND MSB

INPUT

REGISTER

INPUT

REGISTER

POWER-

ON

RESET

RS LDAC

R

Figure 1.

Automatic test equipment Instrumentation Digitally controlled calibration Industrial control PLCs Programmable attentuator

PRODUCT OVERVIEW

DAC A

REGISTER

DAC B

REGISTER

BV

A

V

REF

RFBA

I

DAC A

R

DAC B

R

AD5545/

AD5555

02918-0-001

OUT

A

RFBB

I

OUT

A

GND

B

GND

The AD5545/AD5555 are 16-bit/14-bit, current-output, digitalto-analog converters designed to operate from a single 5 V supply with bipolar output up to ±15 V capability.

An external reference is needed to establish the full-scale output-current. An internal feedback resistor (R

) enhances the

FB

resistance and temperature tracking when combined with an external op amp to complete the I-to-V conversion.

A serial data interface offers high speed, 3-wire microcontroller compatible inputs using serial data in (SDI), clock (CLK), and chip select (

). Additional

CS

function allows simultane-

LDAC

ous update operation. The internal reset logic allows power-on preset and dynamic reset at either zero or midscale, depending on the state of the MSB pin.

The AD5545/AD5555 are packaged in the compact TSSOP-16 package and can be operated from –40°C to +85°C.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective companies.

AD5545/AD5555

TABLE OF CONTENTS

AD5545/AD5555—Electrical Characteristics .............................. 3

Applications..................................................................................... 13

Absolute Maximum Ratings............................................................ 5

Pin Configuration And Functional Descriptions......................... 6

Typical Performance Characteristics ............................................. 9

Circuit Operation ...........................................................................11

D/A Converter Section .............................................................. 11

Serial Data Interface................................................................... 11

Power-Up Sequence ...................................................................12

Layout and Power Supply Bypassing .......................................12

Grounding................................................................................... 12

REVISION HISTORY

Revision 0: Initial Version

Stability ........................................................................................ 13

Positive Voltage Output ............................................................. 13

Bipolar Output............................................................................ 13

Programmable Current Source ................................................ 13

DAC with Programmable Input Reference Range................ 14

Outline Dimensions....................................................................... 16

ESD Caution................................................................................ 16

Ordering Guide .......................................................................... 16

Rev. 0 | Page 2 of 16

AD5545/AD5555

AD5545/AD5555—ELECTRICAL CHARACTERISTICS

Table 1. VDD = 5 V ± 10%, I unless otherwise noted.

Parameter Symbol Conditions 5 V ± 10% Units

STATIC PERFORMANCE1

Resolution N AD5545, 1 LSB = V Resolution N AD5555, 1 LSB = V Relative Accuracy INL AD5545 ±2 LSB max Relative Accuracy INL AD5555 ±1 LSB max Differential Nonlinearity DNL Monotonic ±1 LSB max Output Leakage Current I Output Leakage Current I Full-Scale Gain Error G Full-Scale Temperature Coefficient2 TCVFS 1 ppm/°C typ

REFERENCE INPUT

V

Range V

REF

Input Resistance R Input Capacitance2 C

ANALOG OUTPUT

Output Current I Output Capacitance2 C

LOGIC INPUTS AND OUTPUT

Logic Input Low Voltage VIL 0.8 V max Logic Input High Voltage VIH 2.4 V min Input Leakage Current IIL 10 µA max Input Capacitance2 C

INTERFACE TIMING

2, 4

Clock Input Frequency f Clock Width High tCH 10 ns min Clock Width Low tCL 10 ns min CS to Clock Setup Clock to CS Hold Data Setup tDS 5 ns min Data Hold tDH 10 ns min LDAC Setup

Hold

LDAC Width

SUPPLY CHARACTERISTICS

Power Supply Range V Positive Supply Current IDD Logic Inputs = 0 V 10 µA max Power Dissipation P Power Supply Sensitivity PSS ∆VDD = ±5% 0.006 %/% max

= Virtual GND, GND = 0 V, V

OUT

Data = 0x0000, TA = 25°C 10 nA max

OUT

Data = 0x0000, TA = TA Max 20 nA max

OUT

Data = Full Scale ±1/±4 mV typ/max

FSE

–12/+12 V min/V max

REF

5 kΩ typ3

REF

5 pF typ

REF

Data = Full Scale 2 mA typ

OUT

Code Dependent 200 pF typ

OUT

10 pF max

IL

50 MHz

CLK

0 ns min

t

CSS

10 ns min

t

CSH

5 ns min

t

LDS

10 ns min

t

LDH

10 ns min

t

LDAC

Range 4.5/5.5 V min/V max

DD

Logic Inputs = 0 V 0.055 mW max

DISS

= 10 V, TA = Full Operating Tempearture Range,

REF

/216 = 153 µV when V

REF

/214 = 610 µV when V

REF

= 10 V 16 Bits

REF

= 10 V 14 Bits

REF

1

All static performance tests (except I

is tied to the amplifier output. Typical values represent average readings measured at 25°C.

2

These parameters are guaranteed by design and not subject to production testing.

3

All ac characteristic tests are performed in a closed-loop system using an O42 I-to-V converter amplifier.

4

All input control signals are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.

) are performed in a closed-loop system using an external precision OP1177 I-to-V converter amplifier. The AD5545 RFB terminal

OUT

Rev. 0 | Page 3 of 16

AD5545/AD5555

Parameter Symbol Conditions 5 V ± 10% Units

AC CHARACTERISTICS

Output Voltage Setting Time

t

S

Reference Multiplying BW BW V DAC Glitch Impulse

Feedthrough Error

Digital Feedthrough

Q

V

OUT/VREF

Q Total Harmonic Distortion THD V Analog Crosstalk

C

TA

Output Spot Noise Voltage eN f = 1 kHz, BW = 1 Hz 12 nV/√Hz

To ±0.1% Full Scale, Data = Zero Scale to Full Scale to Zero Scale

= 5 V p-p, Data = Full Scale 4 MHz typ

REF

= 0 V, Data = Zero Scale to Midscale to Zero

V

REF

Scale Data = Zero Scale, V

f = 1 kHz, Same Channel CS

= Logic High and f

= 5 V p-p, Data = Full Scale, f = 1 kHz to 10 kHz –85 dB typ

REF

V

= 0 V, Measure V

REFB

= 100 mV rms,

REF

= 1 MHz

CLK

with V

OUTB

Wave, Data = Full Scale, f = 1 kHz to 10 kHz

= 5 V p-p Sine

REFA

0.5 µs typ

7 nV-s typ

–65 dB

7 nV-s typ

–95 dB typ

Rev. 0 | Page 4 of 16

AD5545/AD5555

ABSOLUTE MAXIMUM RATINGS

Table 2. AD5545/AD5555 Absolute Maximum Ratings

Parameter Rating

VDD to GND –0.3 V, +8 V V

to GND –18 V, +18 V

REF

Logic Inputs to GND –0.3 V, +8 V V(I

) to GND –0.3 V, VDD + 0.3 V

OUT

Input Current to Any Pin except Supplies ±50 mA Package Power Dissipation

Thermal Resistance θJA

16-Lead TSSOP 150°C/W Maximum Junction Temperature (TJ max) 150°C Operating Temperature Range –40°C to +85°C Storage Temperature Range –65°C to +150°C Lead Temperature

RU-16 (Vapor Phase, 60 sec) 215°C

RU-16 (Infrared, 15 sec) 220°C

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

max – TA)/ θJA

(T

J

Rev. 0 | Page 5 of 16

AD5545/AD5555

A

PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS

CLK

16

LDAC

15

MSB

14

V

13

DD

DGND

12

CS

11

RS

10

SDI

9

V

R

I

OUT

GND

I

OUT

R

REF

A

1

FB

A

2

A

3

4

5

6

7

8

AD5545/

AD5555

TOP VIEW

(Not to Scale)

02918-0-002

A

B

FB

Figure 2. 16-Lead TSSOP

Table 3. Pin Function Descriptions—16-Lead TSSOP

Pin No. Mnemonic Function

1 RFBA Establish voltage output for DAC A by connecting to external amplifier output. 2 V

3 I 4 A 5 A 6 I 7 V

REF

A

DAC A Reference Voltage Input Terminal. Establishes DAC A full-scale output voltage. Pin can be tied to V

A DAC A Current Output.

OUT

A DAC A Analog Ground.

GND

B DAC B Analog Ground.

GND

B DAC B Current Output.

OUT

REF

B

DAC B Reference Voltage Input Terminal. Establishes DAC B full-scale output voltage.

DD

pin.

Pin can be tied to VDD pin. 8 RFBB Establish voltage output for DAC B by connecting to external amplifier output. 9 SDI Serial Data Input. Input data loads directly into the shift register. 10

RESET Pin, Active Low Input. Input registers and DAC registers are set to all 0s or

RS

midscale. Register Data = 0x0000 when MSB = 0. Register Data = 0x8000 for AD5545 and

0x2000 for AD5555 when MSB = 1. 11

Chip Select, Active Low Input. Disables shift register loading when high. Transfers serial

CS

register data to the input register when CS/LDAC returns high. This does not affect

operation. 12 DGND Digital Ground Pin. 13 VDD Positive Power Supply Input. Specified range of operation 5 V ± 10% or 3 V ± 10%. 14 MSB

MSB bit sets output to either 0 or midscale during a RESET pulse (RS

) or at system power-

on. Output equals zero scale when MSB = 0 and midscale when MSB = 1. MSB pin can

.

DD

15

LDAC

also be tied permanently to ground or V

Load DAC Register Strobe, Level Sensitive Active Low. Transfers all input register data to

DAC registers. Asynchronous active low input. See Table 4 and Table 5 for operation. 16 CLK Clock Input. Positive edge clocks data into shift register.

LDAC

Rev. 0 | Page 6 of 16

AD5545/AD5555

A1SDI

A0

D1 D0D15 D14 D13 D12 D11 D10

CLK

CS

LDAC

CLK

CS

INPUT REG LD

t

DS

t

CSS

t

DH

t

CH

t

CL

t

CSH

t

02918-0-003

LDH

t

LDS

t

LDAC

Figure 3. AD5545 18-Bit Data Word Timing Diagram

A1SDI

A0

t

DS

t

CSS

t

DH

t

CH

t

CL

D1 D0D13 D12 D11 D10 D09 D08

INPUT REG LD

t

CSH

LDAC

t

LDS

t

LDAC

02918-0-004

t

LDH

Figure 4. AD5555 16-Bit Data Word Timing Diagram

Table 4. AD5545 Control Logic Truth Table

CLK

CS

LDAC

MSB Serial Shift Register Function Input Register Function DAC Register

RS

H X H H X No Effect Latched Latched L L H H X No Effect Latched Latched L

↑+

H H X

Shift Register Data

Latched Latched

Advanced One Bit

L H H H X No Effect Latched Latched

L H H X No Effect

↑+

Selected DAC Updated

Latched

with Current SR Current H X L H X No Effect Latched Transparent H X H H X No Effect Latched Latched H X

↑+

H X No Effect Latched Latched

H X H L 0 No Effect Latched Data = 0x0000 Latched Data = 0x0000 H X H L H No Effect Latched Data = 0x8000 Latched Data = 0x8000

NOTES

1. SR = Shift Register, ↑+ = Positive Logic Transition, and X = Don’t Care.

2. At power-on, both the input register and the DAC register are loaded with all 0s.

Rev. 0 | Page 7 of 16

AD5545/AD5555

Table 5. AD5555 Control Logic Truth Table

CLK

CS

H X H H X No Effect Latched Latched L L H H X No Effect Latched Latched L

↑+

L H H H X No Effect Latched Latched

L H H X No Effect

↑+

H X L H X No Effect Latched Transparent H X H H X No Effect Latched Latched H X

H X H L 0 No Effect Latched Data = 0x0000 Latched Data = 0x0000 H X H L H No Effect Latched Data = 0x2000 Latched Data = 0x2000

LDAC

H H X

↑+

NOTES

1. SR = Shift Register, ↑+ = Positive Logic Transition, and X = Don’t Care.

2. At power-on, both the input register and the DAC register are loaded with all 0s.

Table 6. AD5545 Serial Input Register Data Format, Data Is Loaded in the MSB-First Format

Bit Position B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Data Word A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

MSB

Note that only the last 18 bits of data clocked into the serial register (Address + Data) are inspected when the CS line’s positive edge

returns to logic high. At this point, an internally generated load strobe transfers the serial register data contents (Bits D15–D0) to the decoded DAC input register address determined by Bits A1 and A0. Any extra bits clocked into the AD5545 shift register are ignored; only the last 18 bits clocked in are used. If double-buffered data is not needed, the

MSB Serial Shift Register Function Input Register Function DAC Register

RS

Shift Register Data Advanced One Bit

H X No Effect Latched Latched

Latched Latched

Selected DAC Updated with Current SR Current

LDAC

pin can be tied logic low to disable the DAC registers.

Latched

LSB

Table 7. AD5555 Serial Input Register Data Format, Data Is Loaded in the MSB-First Format

Bit Position B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Data Word A1 A0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

MSB

LSB

Note that only the last 16 bits of data clocked into the serial register (Address + Data) are inspected when the CS line’s positive edge

returns to logic high. At this point, an internally generated load strobe transfers the serial register data contents (Bits D13–D0) to the decoded DAC input register address determined by Bits A1 and A0. Any extra bits clocked into the AD5555 shift register are ignored; only the last 16 bits clocked in are used. If double-buffered data is not needed, the

LDAC

pin can be tied logic low to disable the DAC registers.

Table 8. Address Decode

A1 A0 DAC Decoded

0 0 None 0 1 DAC A 1 0 DAC B 1 1 DAC A and DAC B

Rev. 0 | Page 8 of 16

AD5545/AD5555

TYPICAL PERFORMANCE CHARACTERISTICS

1.0

0.8

0.6

0.4

0.2

0

INL (LSB)

–0.2

–0.4

–0.6

–0.8

–1.0

0 8192 16384 24576 32768 40960 49152 57344 65536

CODE (Decimal)

Figure 5. AD5545 Integral Nonlinearity Error

02918-0-009

1.0

0.8

0.6

0.4

0.2

0

DNL (LSB)

–0.2

–0.4

–0.6

–0.8

–1.0

0 0248 4096 6144 8192 10240 12288 14336 16384

CODE (Decimal)

Figure 8. AD5555 Differential Nonlinearity Error

02918-0-012

1.0

0.8

0.6

0.4

0.2

0

DNL (LSB)

–0.2

–0.4

–0.6

–0.8

–1.0

0 8192 16384 24576 32768 40960 49152 57344 65536

CODE (Decimal)

Figure 6. AD5545 Differential Nonlinearity Error

1.0

0.8

0.6

0.4

0.2

0

INL (LSB)

–0.2

–0.4

–0.6

–0.8

–1.0

0 2048 4096 6144 8192 10240 12288 14336 16384

CODE (Decimal)

Figure 7. AD5555 Integral Nonlinearity Error

02918-0-010

02918-0-011

1.5

1.0

0.5

–0.5

LINEARITY ERROR (LSB)

–1.0

–1.5

(LSB)

DD

SUPPLY CURRENT I

=2.5V

V

REF

TA=25°C

INL

0

24

SUPPLY VOLTAGE VDD (V)

Figure 9. Linearity Errors vs. V

5

VDD=5V

=25°C

T

A

4

3

2

1

0

0 0.5 1.0 1.5 2.0 3.0 3.52.5 4.0 4.5 5.0

LOGIC INPUT VOLTAGE VIH (V)

DNL

GE

68

02918-0-013

DD

02918-0-014

10

Figure 10. Supply Current vs. Logic Input Voltage

Rev. 0 | Page 9 of 16

AD5545/AD5555

3.0

2.5

2.0

1.5

1.0

SUPPLY CURRENT (mA)

0.5

0

10k 100k 1M 10M 100M

CLOCK FREQUENCY (Hz)

0x5555

0x8000

0xFFFF 0x0000

02918-0-015

Figure 11. Supply Current vs. Clock Frequency

90

80

70

60

50

40

PSSR (-dB)

30

20

10

0

10 100 1k 10k 100k 1M

FREQUENCY (Hz)

VDD= 5 V ± 10% V

=10V

REF

Figure 12. Power Supply Rejection Ration vs. Frequency

02918-0-016

CS

V

OUT

02918-0-018

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

Figure 14. Settling Time

VDD=5V

=10V

V

REF

CODES 0x8000 ↔ 0x7FFF

TIME (µs)

02918-0-019

CS (5V/DIV)

(50mV/DI V)

V

OUT

Figure 15. Midscale Transition and Digital Feedthrough

REF LEVEL

0.000dB

0xFFFF

0x8000 0x4000 –12dB 0x2000 0x1000 0x0800 0x0400 0x0200 0x0100 0x0080 0x0040 0x0020 0x0010 0x0008 0x0004 0x0002 0x0001

0x0000

10 100 1k 100k10k 1M 10M

START 10.000Hz STOP 50 000 000.000Hz

/DIV

12.000dB

MARKER 4 41 677.200Hz MAG (A/R) – 2. 93 9db

02918-0-017

Figure 13. Reference Multiplying Bandwidth

–24dB

–36dB

–48dB

–60dB

–72dB

–84dB

–96dB

–108dB

Rev. 0 | Page 10 of 16

AD5545/AD5555

CIRCUIT OPERATION

The AD5545/AD5555 contain a 16-/14-bit, current-output, digital-to-analog converter, a serial-input register, and a DAC register. Both parts require a minimum of a 3-wire serial data interface with additional

LDAC

for dual channel simultaneous

update.

D/A CONVERTER SECTION

The DAC architecture uses a current-steering R-2R ladder design. Figure 16 shows the typical equivalent DAC. The DAC contains a matching feedback resistor for use with an external I-to-V converter amplifier. The R output of the external amplifier. The I to the inverting input of the external amplifier. These DACs are designed to operate with both negative or positive reference voltages. The V

power pin is used only by the logic to drive

DD

the DAC switches ON and OFF. Note that a matching switch is used in series with the internal 5 kΩ feedback resistor. If users attempt to measure the R

value, power must be applied to VDD

FB

to achieve continuity. The V (D) loaded into the corresponding DAC register, according to Equation 1 and Equation 2, determine the DAC output voltage.

OUT

REF

384,16/– DVV

×= (2)

REF

536,65/– DVV

×= (1)

Note that the output full-scale polarity is the opposite of the V

polarity for dc reference voltages.

REF

V

REF

DIGITAL INTERFACE CONNECTIONS OMITTED FOR CLARITY: SWITCHES S1 AND S2 ARE CLOSED, V

R

2R 2R 2R R 5kΩ

Figure 16. Equivalent R-2R DAC Circuit

These DACs are also designed to accommodate ac reference input signals. The AD5545/AD5555 will accommodate input reference voltages in the range of –12 V to +12 V. The reference voltage inputs exhibit a constant nominal input-resistance value of 5 kΩ, ±30%. The DAC output (I producing various output resistances and capacitances. When choosing an external amplifier, the user should take into account the variation in impedance generated by the AD5545/AD5555 on the amplifiers inverting input node. The feedback resistance in parallel with the DAC ladder resistance dominates output voltage noise.

pin is connected to the

FB

terminal is connected

OUT

input voltage and the digital data

REF

V

RR

MUST BE POWERED

DD

) is code dependent,

OUT

S2 S1

02918-0-005

R

I

GND

DD

FB

OUT

V

IN

2.500V

V

A

REF

R

2R 2R 2R R 5kΩ

AD5545/AD5555

DIGITAL INTERFACE CONNECTIONS OMITTED FOR CLARITY: SWITCHES S1 AND S2 ARE CLOSED, V

V

OUT

ADR03

GND

RR

MUST BE POWERED

DD

S2 S1

Figure 17. Recommended System Connections

SERIAL DATA INTERFACE

The AD5545/AD5555 use a minimum 3-wire (CS, SDI, CLK)

serial data interface for single channel update operation. With Table 4 as an example (AD5545), users can tie

high, then pull CS low for an 18-bit duration. New serial data

RS is then clocked into the serial-input register in an 18-bit data-

word format with the MSB bit loaded first. Table 5 defines the truth table for the AD5555. Data is placed on the SDI pin and clocked into the register on the positive clock edge of CLK. For the AD5545, only the last 18-bits clocked into the serial register will be interrogated when the

ring the serial register data to the DAC register and updating the output. If the applied microcontroller outputs serial data in different lengths than the AD5545, such as 8-bit bytes, three right justified data bytes can be written to the AD5545. The AD5545 will ignore the six MSB and recognize the 18 LSB as valid data. After loading the serial register, the rising edge of

transfers the serial register data to the DAC register and

CS updates the output; during the

be toggled.

If users want to program each channel separately but update them simultaneously, they need to program initially, then pull

low for an 18-bit duration and program

CS DAC A with the proper address and data bits.

high to latch data to the DAC A register. At this time, the output is not updated. To load DAC B data, pull

tion and program DAC B with the proper address and data, then

high to latch data to the DAC B register. Finally, pull

pull

CS

LDAC

low and then high to update both the DAC A and DAC B

outputs simultaneously.

pin is strobed high, transfer-

CS

strobe, the CLK should not

CS

5V

V

DD

R

A

FB

I

A

OUT

AD8628

A

GND

LDAC

low and

LDAC

and RS high

is then pulled

CS

low for an 18-bit dura-

CS

+3V

V

CC

V

EE

–3V

02918-0-006

V

LOAD

OUT

Rev. 0 | Page 11 of 16

AD5545/AD5555

Table 8 shows that each DAC A and DAC B can be individually loaded with a new data value. In addition, a common new data value can be loaded into both DACs simultaneously by setting Bit A1 = A0 = high. This command enables the parallel combination of both DACs, with I

OUT

A and I

DAC with significant improved noise performance.

ESD Protection Circuits

All logic input pins contain back-biased ESD protection Zeners connected to digital ground (DGND) and VDD as shown in Figure 18.

V

DD

DIGITAL INPUTS

Figure 18. Equivalent ESD Protection Circuits

POWER-UP SEQUENCE

It is recommended to power-up VDD and ground prior to any reference voltages. The ideal power-up sequence is A

, V

DGND, V up sequence can elevate reference current, but the device will resume normal operation once V

X, and digital inputs. A noncompliance power-

DD

REF

B tied together, to act as one

OUT

5kΩ

DGND

02918-0-007

is powered.

DD

GND

X,

LAYOUT AND POWER SUPPLY BYPASSING

It is a good practice to employ compact, minimum lead length layout design. The input leads should be as direct as possible with a minimum conductor length. Ground paths should have low resistance and low inductance.

Similarly, it is also good practice to bypass the power supplies with quality capacitors for optimum stability. Supply leads to the device should be bypassed with 0.01 µF to 0.1 µF disc or chip ceramic capacitors. Low ESR 1 µF to 10 µF tantalum or electrolytic capacitors should also be applied at V transient disturbance and to filter any low frequency ripple (see Figure 19). Users should not apply switching regulators for

due to the power supply rejection ratio degradation over

V

DD

frequency.

V

DD

+

C1

C2

10µF 0.1µF

Figure 19. Power Supply Bypassing and Grounding Connection

to minimize any

DD

AD5545/ AD5555

V

DD

A

X

GND

DGND

02918-0-008

GROUNDING

The DGND and A digital and analog ground references. To minimize the digital ground bounce, the DGND terminal should be joined remotely

X pins of the AD5545/AD5555 refer to the

GND

at a single point to the analog ground plane (see Figure 19).

Rev. 0 | Page 12 of 16

AD5545/AD5555

V

(

=

(

=

(

+

(

′

APPLICATIONS

STABILITY

V

DD

U1

VDDR

FB

REF

V

REF

GND

AD5545/AD5555

Figure 20. Operational Compensation Capacitor for Gain Peaking Prevention

In the I-to-V configuration, the I ing node of the op amp must be connected as close as possible, and proper PCB layout techniques must be employed. Since every code change corresponds to a step function, gain peaking may occur if the op amp has limited GBP, and if there is excessive parasitic capacitance at the inverting node.

An optional compensation capacitor, C1, can be added for stability as shown in Figure 20. C1 should be found empirically, but 20 pF is generally more than adequate for the compensation.

POSITIVE VOLTAGE OUTPUT

To achieve the positive voltage output, an applied negative reference to the input of the DAC is preferred over the output inversion through an inverting amplifier because of the resistors’ tolerance errors. To generate a negative reference, the reference can be level shifted by an op amp such that the V and GND pins of the reference become the virtual ground and –2.5 V, respectively (see Figure 21).

ADR03

V

OUT

U4

+5V

V+

1/2 AD8620

V–

–5V

Figure 21. Positive Voltage Output Configuration

IN

GND

U3

–2.5V

AD5545/AD5555

BIPOLAR OUTPUT

The AD5545/AD5555 is inherently a 2-quadrant multiplying D/A converter. It can easily set up for unipolar output operation. The full-scale output polarity is the inverse of the reference input voltage.

C1

I

OUT

AD8628

U2

of the DAC and the invert-

OUT

+5V

U1

V

DD

V

REF

GND

C1

R

FB

I

OUT

AD8628

U2

02918-0-020

1/2

0 < VO < +2.5

02918-0-021

V

O

OUT

V

O

circuit, the second amplifier, U4, provides a gain of +2, which increases the output span magnitude to 5 V. Biasing the external amplifier with a 2.5 V offset from the reference voltage results in a full 4-quadrant multiplying circuit. The transfer equation of this circuit shows that both negative and positive output voltages are created because the input data (D) is incremented from code zero

= –2.5 V) to midscale (V

(V

OUT

= 0 V) to full scale (V

OUT

=

+2.5 V).

OUT

)(

×

REF

)(

×

REF

)

55451–768,32/ ADVDV

(3)

)

55551–384,16/ ADVDV

(4)

For the AD5545, the external resistance tolerance becomes the dominant error that users should be aware of.

R2

R1

10kΩ±0.01% 10kΩ±0.01%

C2

U4

V+

1/2 AD8620

V–

+5V

–5V

02918-0-022

V

O

5V

ADR03

V

OUT

GND

V

IN

U3

+5V

U1

V

R

DD

FB

REF

I

OUT

V

GND

AD5545/AD5555

5kΩ±0.01%

C1

1/2

AD8620

U2

R3

–2.5 < VO < +2.5

Figure 22. Four-Quadrant Multiplying Application Circuit

PROGRAMMABLE CURRENT SOURCE

Figure 23 shows a versatile V-to-I conversion circuit using improved Howland Current Pump. In addition to the precision current conversion it provides, this circuit enables a bidirectional current flow and high voltage compliance. This circuit can be used in a 4 mA to 20 mA current transmitter with up to a 500 Ω of load. In Figure 23, it shows that if the resistor network is matched, the load current is

32

RR

)

1

R

=

I

L

3

R

R3, in theory, can be made small to achieve the current needed

within the U3 output current driving capability. This circuit is versatile such that the AD8510 can deliver ±20 mA in both directions, and the voltage compliance approaches 15 V, which is mainly limited by the supply voltages of U3. However, users must pay attention to the compensation. Without C1, it can be shown that the output impedance becomes

DV

××

(5)

REF

+

2131

RRRR

In some applications, it may be necessary to generate the full 4-quadrant multiplying capability or a bipolar output swing. This

Z

= (6)

O

′

()

+

)

′′

()

321–321

RRRRRR

+

is easily accomplished by using an additional external amplifier, U4, configured as a summing amplifier (see Figure 22). In this

Rev. 0 | Page 13 of 16

AD5545/AD5555

−

C

V

If the resistors are perfectly matched, ZO is infinite, which is desirable, and the resistors behave as an ideal current source.

R1'

150kΩ

R1

REF

can be either

O

R2'

15kΩ

C1

10pF

V

DD

U3

V+

AD8510

V–

V

SS

R2

15kΩ

LOAD

02918-0-023

R

D

WB

A

××

N

R

2

WA

B

   

R3' 50Ω

R3 50Ω

V

L

(7)

I

L

On the other hand, if they are not matched, Z positive or negative. The latter can cause oscillation. As a result, C1 is needed to prevent the oscillation. For critical applications, C1 could be found empirically but typically falls in the range of a few pF.

V

DD

U1

V

R

DD

FB

V

REF

GND

AD5545/AD5555

Figure 23. Programmable Current Source with Bidirectional

Current Control and High Voltage Compliance Capabilities

I

OUT

AD8628

U2

150kΩ

DAC WITH PROGRAMMABLE INPUT REFERENCE RANGE

Since high voltage references can be costly, users may consider using one of the DACs, a digital potentiometer, and a low voltage reference to form a single-channel DAC with a programmable input reference range. This approach optimizes the programmable range as well as facilitates future system upgrades with just software changes. Figure 24 shows this implementation. V

VABV ––1

REFREF

where:

AB = Reference Voltage of V

V

REF

is in the feedback network, therefore,

REFAB



   



R

WB



  

V

 

A and V

REF

REF_AB

+×=

R

WA

and RWA are digital potentiometer 128-step programmable

R

WB

resistances and are given by

D

C

R

WB

R

WA

R

WB

R

WA

where D (0 ≤ D

C

R

≈ (8)

AB

128

D

128

C

≈ (9)

≈

128

= Digital Potentiometer Digital Code in Decimal

C

R

AB

128

D

C

(10)

D

−

≤ 127).

By putting Equations 7 through 10 together, the following results:

 

1

+



128



×=

VABV

REFREF

D

A

1

×−

N

2

Table 9 shows a few examples of V

Table 9. V

DC D

vs. DB and DC of the AD5555

REFAB

V

A

0 X V 32 0 1.33 V 32 8192 1.6 V 64 0 2 V 64 8192 4 V 96 0 4 V 96 8192 –8 V



D

C

 

−

D

C



(11)

D

C

128

D

−

C

AB of the 14-bit AD5555.

REF

AB

REF

The output of DAC B is, therefore,

D

B

ABVV2−=

REF

OB

where D

is the DAC B digital code in decimal.

B

The accuracy of V

(12)

N

AB will be affected by the matching of the

REF

input and feedback resistors and, therefore, a digital potentiometer is used for U4 because of its inherent resistance matching. The AD7376 is a 30 V or ±15 V, 128-step digital potentiometer. If 15 V or ±7.5 V is adequate for the application, a 256-step AD5260 digital potentiometer can be used instead.

= External Reference Voltage

V

REF

= DAC A Digital Code in Decimal

D

A

N = Number of Bits of DAC

Rev. 0 | Page 14 of 16

AD5545/AD5555

+5V

C1

OP4177

U2A

C3

OP4177

U2B

+15V

V+

V–

+15V

–15V

2

U3

V

IN

TRIMTEMP

V

GND

4

POT

U4

AB

AD7376

OUT

W

C2

2.2p

53 6

OP4177

V

REF

U2C

ADR03

VOB

02918-0-024

V

REF_AB

RFBA

V

DD

I

A

REF

OUT

A

U1A

A

GND

V

AD5555

B

R

FB

I

B

REF

OUT

B

U1B

B

A

GND

V

Figure 24. DAC with Programmable Input Reference Range

Rev. 0 | Page 15 of 16

AD5545/AD5555

OUTLINE DIMENSIONS

5.10

5.00

4.90

0.15

0.05

4.50

4.40

4.30

PIN 1

16

0.65 BSC

COPLANARITY

COMPLIANT TO JEDEC STANDARDS MO-153AB

0.10

0.30

0.19

9

81

1.20 MAX

6.40

BSC

SEATING

PLANE

0.20

0.09

0.75

8° 0°

0.60

0.45

Figure 25. 16-Lead Thin Shrink Small Outline Package [TSSOP] (RU-16)—Dimensions shown in millimeters

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

ORDERING GUIDE

AD5545/AD5555 Products

AD5545BRU* ±2 ±1 16 –40°C to +85°C TSSOP-16 RU–16 96

AD5545BRU–REEL7 ±2 ±1 16 –40°C to +85°C TSSOP-16 RU–16 1000

AD5555CRU ±1 ±1 14 –40°C to +85°C TSSOP-16 RU–16 96

AD5555CRU–REEL7 ±1 ±1 14 –40°C to +85°C TSSOP-16 RU–16 1000

*The AD5545/AD5555 contain 3131 transistors. The die size measures 71 mil. × 96 mil., 6816 sq. mil.

INL LSB DNL LSB RES (Bits)

Temperature Range

Package Description

Package Outline Qty

C02918-0-7/03(0)

Rev. 0 | Page 16 of 16

Datasheet AD5545 Datasheet (Analog Devices)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

FUNCTIONAL BLOCK DIAGRAM

APPLICATIONS

PRODUCT OVERVIEW

AD5545/AD5555—ELECTRICAL CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS

PIN CONFIGURATION AND FUNCTIONAL DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

CIRCUIT OPERATION

D/A CONVERTER SECTION

SERIAL DATA INTERFACE

ESD Protection Circuits

POWER-UP SEQUENCE

LAYOUT AND POWER SUPPLY BYPASSING

GROUNDING

APPLICATIONS

STABILITY

POSITIVE VOLTAGE OUTPUT

BIPOLAR OUTPUT

PROGRAMMABLE CURRENT SOURCE

DAC WITH PROGRAMMABLE INPUT REFERENCE RANGE

OUTLINE DIMENSIONS

ESD CAUTION

ORDERING GUIDE