Datasheet AD5544-EP Datasheet (ANALOG DEVICES)

Serial-Input 16-Bit DAC

AD5544-EP

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

Trademarks and registered trademarks are the property of their respective owners.

Fax: [phone] ©2012 Analog Devices, Inc. All rights reserved.

INPUT

REGISTER

R

16

DAC A

REGISTER

R

2:4

DECODE

DAC A

B
C
D

POWER-ON

RESET

D0
D1
D2
D3
D4
D5
D6
D7
D8

D9
D10
D11
D12
D13
D14
D15

A0

A1

EN

V

DD

R

FB

A

I

OUT

A

A

GND

A

A

GND

F

V

SS

LDAC

MSB

RS

DGND

CLK

CS

SDI

SDO

V

REF

A

V

REF

B

V

REF

C

R

FB

B

I

OUT

B

A

GND

B

R

FB

C

I

OUT

C

A

GND

C

R

FB

D

I

OUT

D

A

GND

D

AD5544-EP

INPUT

REGISTER

R

INPUT

REGISTER

R

INPUT

REGISTER

R

DAC B

REGISTER

R

DAC C

REGISTER

R

DAC D

REGISTER

R

V

REF

D

DAC A

DAC B

DAC D

DAC C

10083-001

Enhanced Product

FEATURES

2 mA full-scale current ± 20%, with V

0.9 µs settling time to ±0.1%
12 MHz multiplying bandwidth
Midscale glitch of −1 nV-sec
Midscale or zero-scale reset
4 separate, 4-quadrant multiplying reference inputs
SPI-compatible, 3-wire interface
Double-buffered registers enable
Simultaneous multichannel change
Internal power-on reset
Compact 28-lead SSOP

ENHANCED PRODUCT FEATURES

Supports defense and aerospace applications (AQEC)
Military temperature range (−55°C to +125°C)
Controlled manufacturing baseline
1 assembly/test site
1 fabrication site
Enhanced product change notification
Qualification data available on request

= ±10 V

REF

Quad, Current-Output,

FUNCTIONAL BLOCK DIAGRAM

Figure 1.

APPLICATIONS

Automatic test equipment
Instrumentation
Digitally controlled calibration

GENERAL DESCRIPTION

The AD5544-EP quad, 16-bit, current output, digital-to-analog
converter (DAC) is designed to operate from a 2.7 V to

5.5 V supply range.

The applied external reference input voltage (V
the full-scale output current. Integrated feedback resistors (R
provide temperature-tracking, full-scale voltage outputs when
combined with an external I-to-V precision amplifier.

A double-buffered serial data interface offers high speed, 3-wire,
SPI- and microcontroller-compatible inputs using serial data in
(SDI), a chip select (
serial data out pin (SDO) allows for daisy chaining when multiple

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

CS

), and clock (CLK) signals. In addition, a

REF

x) determines

FB

packages are used. A common, level-sensitive, load DAC strobe

LDAC

(

) input allows the simultaneous update of all DAC outputs
from previously loaded input registers. Additionally, an internal
power-on reset forces the output voltage to 0 at system turn-on.

)

The MSB pin allows system reset assertion (

RS

) to force all registers
to zero code when MSB = 0 or to half-scale code when MSB = 1.
The AD5544-EP is packaged in the compact 28-lead SSOP.

Additional application and technical information can be found
in the AD5544 data sheet.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]

www.analog.com

AD5544-EP Enhanced Product

TABLE OF CONTENTS

Features .............................................................................................. 1

Enhanced Product Features ............................................................ 1

Applications ....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

Timing Diagrams .......................................................................... 4

REVISION HISTORY

4/12—Revision 0: Initial Version

Absolute Maximum Ratings ............................................................5

ESD Caution...................................................................................5

Pin Configuration and Function Descriptions ..............................6

Typical Performance Characteristics ..............................................8

Outline Dimensions ....................................................................... 10

Ordering Guide .......................................................................... 10

Rev. 0 | Page 2 of 12

Enhanced Product AD5544-EP

REF

REF

OUT

FSE

REF

REF

REF

REF

REF

OUT

OUT

2, 3

LDAC

LDS

LDH

DD RANGE

SS

DISS

SPECIFICATIONS

VDD = 2.7 V to 5.5 V, VSS = 0 V, I
range of −55°C to +125°C, unless otherwise noted.

Table 1.

Parameter Symbol Test Condition/Comments Min Typ Max Unit

STATIC PERFORMANCE1

Resolution N 1 LSB = V
Relative Accuracy INL ±1.5 LSB
Differential Nonlinearity DNL ±1.5 LSB
Output Leakage Current I
Data = 0x0000, TA = 85°C 20 nA
Full-Scale Gain Error G
Full-Scale Tempco2 TCVFS 1 ppm/°C
Feedback Resistor RFBx VDD = 5 V 4 6 8 kΩ

REFERENCE INPUT

V

x Range V
Input Resistance R
Input Resistance Match R
Input Capacitance2 C

ANALOG OUTPUT

Output Current I
Output Capacitance2 C

LOGIC INPUT AND OUTPUT

Logic Input Low Voltage VIL 0.8 V
Logic Input High Voltage VIH 2.4 V
Input Leakage Current IIL 1 µA
Input Capacitance2 CIL 10 pF
Logic Output Low Voltage VOL IOL = 1.6 mA 0.4 V
Logic Output High Voltage VOH IOH = 100 µA 4 V

INTERFACE TIMING

Clock Width High tCH 25 ns
Clock Width Low tCL 25 ns

to Clock Setup t

CS
Clock to CS Hold t
Clock to SDO Propagation

Delay
Load DAC Pulse Width t
Data Setup tDS 20 ns
Data Hold tDH 20 ns
Load Setup t
Load Hold t

SUPPLY CHARACTERISTICS

Power Supply Range V
Positive Supply Current IDD Logic inputs = 0 V 5 µA
Negative Supply Current ISS Logic inputs = 0 V, V
Power Dissipation P
Power Supply Sensitivity PSS ∆VDD = ±5% 0.006 %/%

x = virtual GND, A

OUT

x = 0 V, V

GND

REF

x/216 = 153 µV when V

A = V

REF

B = V

REF

C = V

D = 10 V, TA = full operating temperature

REF

= 10 V 16 Bits

x Data = 0x0000, TA = 25°C 10 nA

Data = 0xFFFF ±0.75 ±4 mV

x −15 +15 V
x 4 6 8 kΩ
x Channel-to-channel 0.35 %
x 5 pF

x Data = 0xFFFF 1.25 2.5 mA

x Code dependent 35 pF

0 ns

CSS

25 ns

CSH

tPD 2 20 ns

25 ns

5 ns

25 ns

2.7 5.5 V

= −5 V 0.001 9 µA

Logic inputs = 0 V 1.25 mW

Rev. 0 | Page 3 of 12

AD5544-EP Enhanced Product

REF

OUT

REF

REF

CLK

REF

t

LDH

t

LDS

t

LDAC

t

CSH

t

PD

t

CL

t

CH

t

DH

t

DS

t

CSS

SDI

CLK

CS

LDAC

SDO

INPUT

REG

LD

A1 A0 D15 D14 D13 D12 D11 D10 D1 D0

10083-004

Parameter Symbol Test Condition/Comments Min Typ Max Unit

AC CHARACTERISTICS4

Output Voltage Settling Time tS To ±0.1% of full scale, data = 0x0000 to 0xFFFF to 0x0000 0.9 µs
Reference Multiplying

Bandwidth (BW)
DAC Glitch Impulse Q V
Feedthrough Error V
Crosstalk Error V

Digital Feedthrough Q
Total Harmonic Distortion THD V
Output Spot Noise Voltage eN f = 1 kHz, BW = 1 Hz 7 nV/√Hz

1

All static performance tests (except I

is tied to the amplifier output. Typical values represent average readings measured at 25°C.

2

These parameters are guaranteed by design and not subject to production testing.

3

All input control signals are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.

4

All ac characteristic tests are performed in a closed-loop system using an AD8038 I-to-V converter amplifier.

TIMING DIAGRAMS

BW − 3 dB V

x = 5 V p-p, data = 0xFFFF, CFB = 2.0 pF, 12 MHz

REF

x = 8 V, data = 0x0000 to 0x8000 to 0x0000 −1 nV-sec

x/V

x Data = 0x0000, V

A/V

OUT

B Data = 0x0000, V

REF

x = 100 mV rms, f = 100 kHz −65 dB
B = 100 mV rms, adjacent channel,

REF

−90 dB

f = 100 kHz

= 1, f

CS

= 1 MHz 0.6 nV-sec

x = 5 V p-p, data = 0xFFFF, f = 1 kHz −98 dB

x) are performed in a closed-loop system using an external precision OP177 I-to-V converter amplifier. The AD5544 RFB terminal

OUT

Figure 2. Timing Diagram

Rev. 0 | Page 4 of 12

Enhanced Product AD5544-EP

REF

OUT

GND

Package Power Dissipation

(TJ max − TA)/θ

JA

JA

Operating Temperature Range, Enhanced

−55°C to +125°C

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

VDD to GND −0.3 V, +8 V

VSS to GND +0.3 V, −7 V

V

x to GND −18 V, +18 V
Logic Input and Output to GND −0.3 V, +8 V
V(I

x) to GND −0.3 V, VDD + 0.3 V

A

x to DGND −0.3 V, +0.3 V

Input Current to Any Pin Except Supplies ±50 mA

Thermal Resistance θ

28-Lead SSOP 100°C/W
32-Lead LFCSP 32.5°C/W

Maximum Junction Temperature (TJ Max) 150°C

Product (EP Version)
Storage Temperature Range −65°C to +150°C
Lead Temperature

Vapor Phase, 60 Sec 215°C

Infrared, 15 Sec 220°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may
affect device reliability.

ESD CAUTION

Rev. 0 | Page 5 of 12

AD5544-EP Enhanced Product

28
27
26
25
24
23
22
21
20
19
18
17
16
15

1
2
3
4
5
6
7
8

9
10
11
12
13
14

AD5544-EP

TOP VIEW

(Not to Scale)

A

GND

A

A

GND

D

I

OUT

A

I

OUT

D

V

REF

A

V

REF

D

R

FB

A R

FB

D

MSB DGND

V

SS

V

DD

A

GND

F

CLK SDO

SDI NC

R

FB

B

R

FB

C

V

REF

B

V

REF

C

I

OUT

B

I

OUT

C

A

GND

B A

GND

C

NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.

LDAC

CS

RS

10083-003

1

A

GND

A

DAC A Analog Ground.

OUT

DD

DD

9

CLK

Clock Input. Positive edge clocks data into the shift register.

DD

OUT

14

A

GND

B

DAC B Analog Ground.

GND

OUT

DD

GND

SS

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Table 3. Pin Function Descriptions

Pin No. Mnemonic Description

2 I
3 V

A DAC A Current Output.

A DAC A Reference Voltage Input Terminal. Establishes DAC A full-scale output voltage. This pin can be tied to the

REF

V

pin.
4 RFBA Establish the voltage output for DAC A by connecting to an external amplifier output.
5 MSB MSB Pin. Set pin during a reset pulse (RS) or at system power-on if tied to ground or VDD.

6

RS

Reset Pin, Active Low Input. Input registers and DAC registers are set to all 0s or half-scale code, determined by

the voltage on the MSB pin. Register data = 0x0000 when MSB = 0.
7 V
8

Positive Power Supply Input. Specified range of operation: 5 V ± 10%.

CS

Chip Select, Active Low Input. Disables shift register loading when high. Transfers serial register data to the

input register when

10 SDI Serial Data Input. Input data loads directly into the shift register.
11 RFBB Establish the voltage output for DAC B by connecting to an external amplifier output.
12 V

13 I

15 A
16 I
17 V

B DAC B Reference Voltage Input Terminal. Establishes DAC B full-scale output voltage. This pin can be tied to the

REF

V

pin.

B DAC B Current Output.

C DAC C Analog Ground.

C DAC C Current Output.

C DAC C Reference Voltage Input Terminal. Establishes DAC C full-scale output voltage. This pin can be tied to the

REF

V

pin.
18 RFBC Establish the voltage output for DAC C by connecting to an external amplifier output.
19 NC No Connect. Do not connect to this pin.
20 SDO Serial Data Output. Input data loads directly into the shift register. Data appears at SDO at 19 clock pulses for

21

22 A
23 V
24 DGND Digital Ground Pin.
25 RFBD Establish the voltage output for DAC D by connecting to an external amplifier output.

LDAC

F High Current Analog Force Ground.

Negative Bias Power Supply Input. Specified range of operation: −5.5 V to +0.3 V.

the AD5544-EP after input at the SDI pin.
Load DAC Register Strobe, Level Sensitive Active Low. Transfers all input register data to DAC registers.

Asynchronous active low input.

CS/LDAC

Figure 3. Pin Configuration

returns high. Does not affect

Rev. 0 | Page 6 of 12

LDAC

operation.

Enhanced Product AD5544-EP

DD

OUT

GND

Pin No. Mnemonic Description

26 V

27 I
28 A

D DAC D Reference Voltage Input Terminal. Establishes DAC D full-scale output voltage. This pin can be tied to the

REF

V

pin.

D DAC D Current Output.

D DAC D Analog Ground.

Rev. 0 | Page 7 of 12

AD5544-EP Enhanced Product

0.10

0

–0.05

–0.10

–0.15

–0.20

–0.25

–0.30

–0.35

–0.40

0 10,000 30,000 50,000 70,000

DNL ERROR (L S B)

CODE

0.05

20,000 40,000 60,000

10083-006

–1.5

–1.0

–0.5

0

0.5

1.0

1.5

–2000 –1500

–1000 –500 0 500 1000 1500 2000

0xF

000

0x8000

0x7FFF

0x0FFF

10083-009

OP AMP OFFSET (µV)

INL (LSB)

V

DD

= 5V

V

REF

= 10V

–1.00

–0.75

–0.50

–0.25

0

0.50

0.25

0.75

1.00

–1000 –750 –500 –250 0 250 500 750 1000

0xF000

0x8000

0x0FFF

10083-011

OP AMP OFFSET (µV)

DNL (LSB)

V

DD

= 5V

V

REF

= 10V

–1500 –1000 –500 0 500 1000 1500

–20

–15

–10

–5

0

5

10

10083-013

OP AMP OFFSET (µV)

GAIN ERROR ( LSB)

VDD = 5V
V

REF

= 10V

0.4 0.5 0.6 0.7 0.9 1.0 1.1 1.20.8
TIME (µs)

V

OUT

(V)

10083–012

–4.08

–4.06

–4.04

–4.02

–4.00

–3.98

–3.96

–3.94

–3.92

–3.90

–3.88

5V/DIV

VDD = 5V
V

REF

= 10V

V

OUT

LDAC

10083-018

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 4. DNL Error vs. Code, TA = 25°C

Figure 7. Gain Error vs. Op Amp Offset

Figure 5. INL Error vs. Op Amp Offset

Figure 6. DNL Error vs. Op Amp Offset

Figure 8. Midscale Transition

Figure 9. Large Signal Settling Time

Rev. 0 | Page 8 of 12

Enhanced Product AD5544-EP

–0.2

–0.1

0

0.1

–20

–16

–12

–8

–4

0

4

–2 20 4 6 8 10

TIME (µs)

V

OUT

(V)

LDAC (V)

10083-019

10,000

1000

100

10

1

1k

100M10k

I

DD

(µA)

100k 1M

10M

CLOCK FREQUENCY (Hz)

ZERO SCAL E
MIDSCALE
FULL SCALE
0x5555

10083-015

0

10

20

30

40

50

60

70

80

90

100

100 1k 10k 100k 1M

10083-020

FREQUENCY (Hz)

PSRR (dB)

V

DD

= 5V

V

REF

= 10V

0

50

100

150

200

250

300

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

LOGIC INPUT (V)

SUPPLY CURRENT (µA)

10083-017

Figure 10. Small Signal Settling Time

Figure 11. Power Supply Current vs. Clock Frequency

Figure 12. Power Supply Rejection vs. Frequency

Figure 13. Power Supply Current vs. Logic Input Voltage

Rev. 0 | Page 9 of 12

AD5544-EP Enhanced Product

COMPLIANT TO JEDEC STANDARDS MO-150-AH

060106-A

28

15

14

1

10.50

10.20

9.90

8.20

7.80

7.40

5.60

5.30

5.00

SEATING
PLANE

0.05 MIN

0.65 BSC

2.00 MAX

0.38

0.22

COPLANARITY

0.10

1.85

1.75

1.65

0.25

0.09

0.95

0.75

0.55

8°
4°
0°

OUTLINE DIMENSIONS

Figure 4. 28-Lead Shrink Small Outline Package [SSOP]

(RS-28)

Dimensions shown in millimeters

ORDERING GUIDE

Model Resolution (Bits) INL LSB DNL LSB Temperature Range Package Description

AD5544SRS-EP 16 ±1.5 ±1.5 −55°C to +125°C 28-Lead Shrink Small Outline Package [SSOP] RS-28

Package
Option

Rev. 0 | Page 10 of 12

Enhanced Product AD5544-EP

NOTES

Rev. 0 | Page 11 of 12

AD5544-EP Enhanced Product

NOTES

©2012 Analog Devices, Inc. All rights reserved. Trademarks and
reg

istered trademarks are the property of their respective owners.

D10083-0-4/12(0)

Rev. 0 | Page 12 of 12