Datasheet AD5544 Datasheet (Analog Devices)

Quad, Current-Output,

FEATURES

AD5544 16-bit resolution
AD5554 14-bit resolution
2 mA full-scale current ±20%, with V
2 µs settling time

BIAS for zero-scale error reduction @ temp

V

SS

midscale or zero-scale reset
Four separate, 4-Q multiplying reference inputs

®-compatible 3-wire interface

SPI
Double buffered registers enable
Simultaneous multichannel change
Internal power ON reset
Compact SSOP-28 package

APPLICATIONS

Automatic test equipment
Instrumentation
Digitally controlled calibration

GENERAL DESCRIPTION

The AD5544/AD5554 quad, 16-/14-bit, current-output, digital
to-analog converters are designed to operate from a single
5 V supply.

The applied external reference input voltage (V
the full-scale output current. Integrated feedback resistors (R
provide temperature-tracking, full-scale voltage outputs when
combined with an external I-to-V precision amplifier.

A double-buffered serial-data interface offers high speed,
3-wire, SPI- and microcontroller-compatible inputs using serial-

CS

data-in (SDI), a chip-select (
addition, a serial-data-out pin (SDO) allows for daisy-chaining
when multiple packages are used. A common, level-sensitive,
load-DAC strobe (

LDAC
of all DAC outputs from previously loaded input registers.
Additionally, an internal power ON reset forces the output
voltage to zero at system turn ON. An MSB pin allows system
reset assertion (

RS

) to force all registers to zero code when
MSB = 0, or to half-scale code when MSB = 1.

The AD5544/AD5554 are packaged in the compact SSOP-28.

), and clock (CLK) signals. In

) input allows the simultaneous update

= ±10 V

REF

) determines

REF

FB

Serial-Input 16-/14-Bit DACs

AD5544/AD5554

FUNCTIONAL BLOCK DIAGRAM

V

ABC

D

REF

V

D0

D10
D11
D12
D13
D14
D15

EN

DAC A

2:4

DECODE

D1
D2
D3
D4
D5
D6
D7
D8

16

D9

A0
A1

B
C
D

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

POWER-

ON

RESET

MSBRSDGND

DAC A

REGISTER

R

DAC B

REGISTER

R

DAC C

REGISTER

R

DAC D

REGISTER

R

LDAC

DAC A

R

DAC B

R

DAC C

R

DAC D

R

AD5544

V

SS

SDO

CLK

SDI

CS

Figure 1.

1.0

0.5
0

–0.5
–1.0

INL (LSB)

1.0

0.5
0

–0.5
–1.0

1.0

0.5
0

–0.5
–1.0

1.0

0.5
0

–0.5
–1.0

CODE (Decimal)

)

Figure 2. AD5544 INL vs. Code Plot ( TA = 25°C)

DAC A

DAC B

DAC C

DAC D

57344491524096032768245761638481920 65536

DD

RFBA

I

OUT

A

GND

R

FB

I

OUT

A

GND

R

FB

I

OUT

A

GND

R

FB

I

OUT

A

GND

A

GND

A

A

B

B

B

C

C

C

D

D

D

F

00943-0-001

00943-0-002

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

www.analog.com

AD5554/AD5554

TABLE OF CONTENTS

Specifications..................................................................................... 3

AD5544 Electrical Characteristics ............................................. 3

AD5554 Electrical Characteristics ............................................. 4

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics........................................... 10

REVISION HISTORY

12/04—Rev. 0 to Rev. A

Updated Format...................................................................... Universal

Change to Electrical Characteristics Tables .......................................4

Change to Pin Description Table.......................................................10

Addition of Power Supply Sequence Section...................................19

Addition of Layout and Power Supply Bypassing Section.............19

Addition of Grounding Section.........................................................19

Addition of Figure 32..........................................................................19

Circuit Operation ........................................................................... 14

D/A Converter............................................................................ 14

Serial Data Interface....................................................................... 16

Power On Reset .......................................................................... 17

Applications ................................................................................ 17

Outline Dimensions....................................................................... 18

Ordering Guide .......................................................................... 18

4/00—Revision 0: Initial Version

Rev. A | Page 2 of 20

AD5544/AD5554

SPECIFICATIONS

AD5544 ELECTRICAL CHARACTERISTICS

VDD = 5 V ±10%, VSS = 0 V, I
otherwise noted.

Table 1.

Parameter Symbol Condition Min Typ Max Unit

STATIC PERFORMANCE

1

Resolution N 1 LSB = V
Relative Accuracy INL ±4 LSB
Differential Nonlinearity DNL ±1.5 LSB
Output Leakage Current I
I
Full-Scale Gain Error G
Full-Scale Tempco

2

Feedback Resistor RFBX VDD = 5 V 4 6 8 kΩ

REFERENCE INPUT

V

X Range V

REF

Input Resistance R
Input Resistance Match R
Input Capacitance2 C

ANALOG OUTPUT

Output Current I
Output Capacitance2 C

LOGIC INPUT AND OUTPUT

Logic Input Low Voltage V
Logic Input High Voltage V
Input Leakage Current I
Input Capacitance2 CIL 10 pF
Logic Output Low Voltage V
Logic Output High Voltage V

INTERFACE TIMING

2, 3

Clock Width High t
Clock Width Low t
CS

to Clock Setup

Clock to CS Hold
Clock to SDO Prop Delay t
Load DAC Pulse Width t
Data Setup t
Data Hold t
Load Setup t
Load Hold t

SUPPLY CHARACTERISTICS

Power Supply Range V
Positive Supply Current I
Negative Supply Current I
Power Dissipation P
Power Supply Sensitivity PSS ∆VDD = ±5% 0.006 %/%

X = virtual GND, A

OUT

X = 0 V, V

GND

A, B, C, D = 10 V, TA = full operating temperature range, unless

REF

/216 = 153 µV when V

REF

X Data = 0000H, TA = 25°C 10 nA

OUT

X Data = 0000H, TA = TA max 20 nA

OUT

FSE

TCV

FS

X −15 +15 V

REF

X 4 6 8 kΩ

REF

X Channel-to-channel 1 %

REF

X 5 pF

REF

X Data = FFFF

OUT

X Code-dependent 80 pF

OUT

IL

IH

IL

OL

OH

Data = FFFF

H

1 ppm/°C

H

0.8 V

2.4 V
1 µA

IOL = 1.6 mA 0.4 V
IOH = 100 µA 4 V

= 10 V 16 Bits

REF

±0.75 ±3 mV

1.25 2.5 mA

CH

CL

t

CSS

t

CSH

PD

LDAC

DS

DH

LDS

LDH

DD RANGE

DD

SS

DISS

25 ns
25 ns
0 ns

25 ns
2 20 ns

25 ns
20 ns
20 ns
5 ns
25 ns

4.5 5.5 V
Logic inputs = 0 V 50 250 µA
Logic inputs = 0 V, V

= –5 V 0.001 1 µA

SS

Logic inputs = 0 V 1.25 mW

Rev. A | Page 3 of 20

AD5554/AD5554

Parameter Symbol Condition Min Typ Max Unit

AC CHARACTERISTICS

Output Voltage Settling Time t

Output Voltage Settling Time

Reference Multiplying BW BW − 3 dB V

DAC Glitch Impulse Q V

Feedthrough Error V

Crosstalk Error V

Digital Feedthrough Q

Total Harmonic Distortion THD V

Output Spot Noise Voltage e

1

All static performance tests (except I

tied to the amplifier output. Typical values represent average readings measured at 25 °C.

2

These parameters are guaranteed by design and not subject to production testing.

3

All input control signals are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.

4

All ac characteristic tests are performed in a closed-loop system using an OP42 I-to-V converter amplifier.

AD5554 ELECTRICAL CHARACTERISTICS

VDD = 5 V ±10%, V
otherwise noted.

Table 2.

Parameter Symbol Condition Min Typ Max Unit

STATIC PERFORMANCE

Resolution N 1 LSB = V

Relative Accuracy INL ±1 LSB

Differential Nonlinearity DNL ±1 LSB

Output Leakage Current I
I

Full-Scale Gain Error G

Full-Scale Tempco

Feedback Resistor RFBX VDD = 5 V 4 6 8 kΩ
REFERENCE INPUT

V

X Range V

REF

Input Resistance R

Input Resistance Match R

Input Capacitance2 C
ANALOG OUTPUT

Output Current

Output Capacitance
LOGIC INPUT AND OUTPUT

Logic Input Low Voltage V

Logic Input High Voltage V

Input Leakage Current I

Input Capacitance2 CIL 10 pF

Logic Output Low Voltage V

Logic Output High Voltage V

4

= 0 V, I

SS

2

S

To ±0.1% of full scale, data = 0000H to FFFFH to

1 µs

0x0000

t

S

X/V

OUT

REF

A/V

OUT

REF

To ±0.0015% of full scale, data = 0000H to FFFFH to
0000

H

X = 100 mV rms, data = FFFFH, CFB = 15 pF 2 MHz

REF

X = 10 V, data 0000H to 8000H to 0000

REF

X Data = 0000H, V
B

Data = 0000

X = 100 mV rms, f = 100 kHz −65 dB

REF

, V

B = 100 mV rms, adjacent

H

REF

H

2

µs

12 nV-s

−90 dB

channel, f = 100 kHz
CS

= 1, and f

= 5 V p-p, data = FFFFH, f = 1 kHz −90 dB

REF

N

) are performed in a closed-loop system using an external precision OP177 I-to-V converter amplifier. The AD5544 RFB terminal is

OUT

X = virtual GND, A

OUT

1

2

X Data = 0000H, TA = 25°C 10 nA

OUT

X Data = 0000H, TA = TA Max 20 nA

OUT

FSE

TCV

FS

X −15 +15 V

REF

X 4 6 8 kΩ

REF

X Channel-to-channel 1 %

REF

X 5 pF

REF

X

I

OUT

C

X

OUT

IL

IH

IL

OL

OH

f = 1 kHz, BW = 1 Hz 7 nV√Hz

X = 0 V, V

GND

Data = 3FFF
1 ppm/°C

Data = 3FFF
Code-dependent

0.8 V

2.4 V
1 µA

IOL = 1.6 mA 0.4 V
IOH = 100 µA 4 V

= 1 MHz

CLK

A, B, C, D = 10 V, TA = full operating temperature range, unless

REF

/214 = 610 µV when V

REF

H

H

= 10 V 14 Bits

REF

5 nV-s

±2 ±10 mV

1.25
80

2.5

mA
pF

Rev. A | Page 4 of 20

AD5544/AD5554

Parameter Symbol Condition Min Typ Max Unit

INTERFACE TIMING

Clock Width High t
Clock Width Low t
CS

to Clock Setup

Clock to CS Hold
Clock to SDO Prop Delay t
Load DAC Pulse Width t
Data Setup t
Data Hold t
Load Setup t
Load Hold t

SUPPLY CHARACTERISTICS

Power Supply Range V
Positive Supply Current I
Negative Supply Current I
Power Dissipation P
Power Supply Sensitivity PSS ∆VDD = ±5% 0.006 %/%

AC CHARACTERISTICS

Output Voltage Settling Time t
Output Voltage Settling Time t

Reference Multiplying BW BW – 3 dB V
DAC Glitch Impulse Q V
Feedthrough Error V
Crosstalk Error V

Digital Feedthrough Q
Total Harmonic Distortion THD V

Output Spot Noise Voltage e

1

All static performance tests (except I

tied to the amplifier output. Typical values represent average readings measured at 25°C.

2

These parameters are guaranteed by design and not subject to production testing.

3

All input control signals are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.

4

All ac characteristic tests are performed in a closed-loop system using an OP42 I-to-V converter amplifier.

2, 3

4

CH

CL

t

CSS

t

CSH

PD

LDAC

DS

DH

LDS

LDH

DD RANGE

DD

SS

DISS

25 ns
25 ns
0 ns

25 ns
2 20 ns

25 ns
20 ns
20 ns
5 ns
25 ns

4.5 5.5 V
Logic inputs = 0 V 50 250 µA
Logic inputs = 0 V, VSS = –5 V 0.001 1 µA
Logic inputs = 0 V 1.25 mW

S

S

X/V

OUT

A/V

OUT

To ±0.1% of full scale, data = 0000H to 3FFFH to 0000H 1 µs
To ±0.0015% of full scale, data = 0000H to 3FFF

to 0000

H

X = 100 mV rms, data = 3FFFH, CFB = 15 pF 2 MHz

REF

X = 10 V, data 0000H to 2000H to 0000

REF

X Data = 0000H, V

REF

B

Data = 0000

REF

X = 100 mV rms, f = 100 kHz –65 dB

REF

, V

B = 100 mV rms, adjacent channel,

H

REF

H

H

2 µs

12 nV-s

–90 dB

f = 100 kHz
CS

= 1, and f

= 5 V p-p, data = 3FFFH, f = 1 kHz –90 dB

REF

N

) are performed in a closed-loop system using an external precision OP177 I-to-V converter amplifier. The AD5554 RFB terminal is

OUT

f = 1 kHz, BW = 1 Hz 7 nV√Hz

= 1 MHz

CLK

5 nV-s

Rev. A | Page 5 of 20

AD5554/AD5554

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

VDD to GND −0.3 V, +8 V
VSS to GND +0.3 V, −7 V
V

to GND −18 V, +18 V

REF

Logic Input and Output to GND −0.3 V, +8 V
V(I

) to GND −0.3 V, VDD+ 0.3 V

OUT

A

X to DGND −0.3 V, + 0.3 V

GND

Input Current to Any Pin Except Supplies ±50 mA
Package Power Dissipation (TJ Max − TA)/θ
Thermal Resistance θ

28-Lead Shrink Surface-Mount (RS-28) 100°C/W
Maximum Junction Temperature (TJ Max) 150°C
Operating Temperature Range: Model A −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Lead Temperature:

RS-28 (Vapor Phase, 60 secs) 215°C

RS-28 (Infrared, 15 secs) 220°C

JA

JA

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may
affect device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. A | Page 6 of 20

AD5544/AD5554

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

A

A

GND

2

A

I

OUT

3

V

A

REF

4

R

AR

FB

5

MSB DGND

6

RS

AD5554

7

V

DD

TOP VIEW

(Not to Scale)

8

CS

9

CLK SDO

10

SDI NC

11

B

R

FB

12

V

B

REF

13

I

B

OUT

14

A

BA

GND

NC = NO CONNECT

Figure 3. AD5544/AD5554 Pin Configuration

Table 4. Pin Function Descriptions

Pin
No. Name Function

1 A
2 I
3 V

A DAC A Analog Ground.

GND

A DAC A Current Output.

OUT

A DAC A Reference Voltage Input Terminal. Establishes DAC A full-scale output voltage. Pin can be tied to VDD pin.

REF

4 RFBA Establish voltage output for DAC A by connecting to external amplifier output.
5 MSB

6

7 V
8

RS Reset Pin, Active Low Input. Input registers and DAC registers are set to all zeros or half-scale code (8000H for AD5544

DD

CS Chip Select, Active Low Input. Disables shift register loading when high. Transfers serial register data to the input

MSB Bit. Set pin during a reset pulse (

and 2000
Register Data = 8000

for AD5554) determined by the voltage on the MSB pin. Register Data = 0000H when MSB = 0.

H

for AD5544 and 2000H.

H

Positive Power Supply Input. Specified range of operation 5 V ±10%.

register when

CS/LDAC returns high. Does not effect LDAC operation.

RS) or at system power ON if tied to ground or VDD.

9 CLK Clock Input. Positive edge clocks data into shift register.
10 SDI Serial Data Input. Input data loads directly into the shift register.
11 RFBB Establish voltage output for DAC B by connecting to external amplifier output.
12 V
13 I
14 A
15 A
16 I
17 V

B DAC B Reference Voltage Input Terminal. Establishes DAC B full-scale output voltage. Pin can be tied to VDD pin.

REF

B DAC B Current Output.

OUT

B DAC B Analog Ground.

GND

C DAC C Analog Ground.

GND

C DAC C Current Output.

OUT

C DAC C Reference Voltage Input Terminal. Establishes DAC C full-scale output voltage. Pin can be tied to VDD pin.

REF

18 RFBC Establish voltage output for DAC C by connecting to external amplifier output.
19 NC No Connect. Leave pin unconnected.
20 SDO

Serial Data Output. Input data loads directly into the shift register. Data appears at SDO, 19 clock pulses for AD5544
and 17 clock pulses for AD5554 after input at the SDI pin.

21

LDAC Load DAC Register Strobe, Level Sensitive Active Low. Transfers all input register data to DAC registers. Asynchronous

active low input. See Table 5 and Table 6 for operation.
22 AGNDF High Current Analog Force Ground.
23 VSS Negative Bias Power Supply Input. Specified range of operation: −5.5 V to +0.3 V.
24 DGND Digital Ground Pin.
25 RFBD Establish Voltage Output for DAC D by Connecting to External Amplifier Output.
26 V
27 I
28 A

D DAC D Reference Voltage Input Terminal. Establishes DAC D full-scale output voltage. Pin can be tied to VDD pin.

REF

D DAC D Current Output.

OUT

D DAC D Analog Ground.

GND

28

D

A

GND

27

D

I

OUT

26

D

V

REF

25

D

FB

24

AD5544/

23

V

SS

22

A

F

GND

21

LDAC

20
19
18

C

R

FB

17

C

V

REF

16

C

I

OUT

15

C

GND

00943-0-005

Rev. A | Page 7 of 20

AD5554/AD5554

SDI

CLK

CS

LDAC

A1 A0 D15 D14 D13 D12 D11 D10 D1 D0

t

t

t

CSS

t

DH

DS

t

CL

CH

t

LDS

t

SDO

t

PD

Figure 4. AD5544 Timing Diagram

t

CSH

LDAC

INPUT

REG

LD

t

LDH

00943-0-003

SDI

CLK

CS

LDAC

A1 A0 D13 D12 D11 D10 D09 D08 D1 D0

t

t

t

CSS

t

DH

DS

t

CL

CH

t

LDS

t

SDO

t

PD

Figure 5. AD5554 Timing Diagram

t

CSH

LDAC

INPUT

REG

LD

t

LDH

00943-0-004

1

Table 5. AD5544

CLK

CS

Control-Logic Truth Table

LDAC RS

MSB Serial Shift Register Function Input Register Function DAC Register

H X H H X No Effect Latched Latched
L L H H X No Effect Latched Latched
L

H H X

￪+

Shift-Register-Data Advanced
One Bit

Latched Latched

L H H H X No Effect Latched Latched

L H H X No Effect

￪+

Selected DAC Updated with Current
SR Contents

Latched

H X L H X No Effect Latched Transparent
H X H H X No Effect Latched Latched
H X

￪+

H X H L 0 No Effect Latched Data = 0000
H X H L H No Effect Latched Data = 8000

H X No Effect Latched Latched

H

H

Latched Data = 0000
Latched Data = 8000

1

For the AD5544, data appears at the SDO Pin 19 clock pulses after input at the SDI pin.

H

H

Rev. A | Page 8 of 20

AD5544/AD5554

Table 6. AD55541 Control-Logic Truth Table

CLK

CS

LDAC RS

H X H H X
L L H H X No Effect Latched Latched
L

2

H H X

￪+

L H H H X No Effect Latched Latched

2

L H H X No Effect

￪+

H X L H X No Effect Latched Transparent
H X H H X No Effect Latched Latched
H X

￪+

H X H L 0 No Effect Latched Data = 0000
H X H L H No Effect Latched Data = 2000

1

For the AD5554, data appears at the SDO Pin 17 clock pulses after input at the SDI pin.

2

￪+ positive logic transition.

3

X = don’t care.

4

At power on both the input register and the DAC register are loaded with all zeros.

Table 7. AD5544 Serial Input Register Data Format, Data Is Loaded in the MSB-First Format

MSB LSB

Bit Position B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
Data Word A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

1

Only the last 18 bits of data clocked into the serial register (address + data) are inspected when the CS line’s positive edge returns to logic high. At this point an inter-

nally generated load strobe transfers the serial register data contents (Bits D15 to D0) to the decoded DAC-input-register address determined by Bits A1 and A0. Any
extra bits clocked into the AD5544 shift register are ignored; only the last 18 bits clocked in are used. If double-buffered data is not needed, the
logic low to disable the DAC registers.

Table 8. AD5554 Serial Input Register Data Format, Data Is Loaded in the MSB-First Format

MSB LSB

Bit Position B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
Data Word A1 A0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

1

Only the last 16 bits of data clocked into the serial register (address + data) are inspected when the CS line’s positive edge returns to logic high. At this point an

internally generated load strobe transfers the serial register data contents (Bits D13 to D0) to the decoded DAC-input-register address determined by Bits A1 and A0.
Any extra bits clocked into the AD5554 shift register are ignored; only the last 16 bits clocked in are used. If double-buffered data is not needed, the
tied logic low to disable the DAC registers.

Table 9. Address Decode

A1 A0 DAC Decoded

0 0 DAC A
0 1 DAC B
1 0 DAC C
1 1 DAC D

MSB Serial Shift Register2 Function Input Register2 Function DAC Register

3

No Effect Latched Latched

Shift-Register-Data Advanced

Latched Latched

One Bit

Selected DAC Updated with Current
Shift-Register Contents

4

Latched

H X No Effect Latched Latched

H

H

1

1

Latched Data = 0000
Latched Data = 2000

LDAC

pin can be tied

LDAC

H

H

pin can be

Rev. A | Page 9 of 20

AD5554/AD5554

TYPICAL PERFORMANCE CHARACTERISTICS

0.50

0.25
0

DNL (LSB)

–0.25
–0.50

0.50

0.25
0

–0.25
–0.50

0.50

0.25
0

–0.25
–0.50

0.50

0.25
0

–0.25
–0.50

CODE (Decimal)

Figure 6. AD5544 DNL vs. Code, T

= 25°C

A

DAC A

DAC B

DAC C

DAC D

57344491524096032768245761638481920 65536

00943-0-006

DNL (LSB)

0.75

0.50

0.25

–0.25
–0.50
–0.75

0.75

0.50

0.25

–0.25
–0.50
–0.75

0.75

0.50

0.25

–0.25
–0.50
–0.75

0.75

0.50

0.25

–0.25
–0.50
–0.75

DAC A

0

DAC B

0

DAC C

0

DAC D

0

CODE (Decimal)

14336122881024081926144409620480 16384

00943-0-008

Figure 8. AD5554 DNL vs. Code, TA = 25°C

INL (LSB)

1.0

0.5

–0.5
–1.0

1.0

0.5

–0.5
–1.0

1.0

0.5

–0.5
–1.0

1.0

0.5

–0.5
–1.0

DAC A

0

DAC B

0

DAC C

0

DAC D

0

CODE (Decimal)

14336122881024081926144409620480 16384

00943-0-007

2.0
VDD = 5V

= 10V

V

REF

1.5
T

INTEGRAL NONLINEARITY ERROR (LSB)

–0.5

–1.0

–1.5

–2.0

1.0

0.5

0

–1500

= 25°C

A

–1000 –500

OP AMP OFFSET VOLTAGE (µV)

0

500 1000 1500

F000

8000

7FFF

0FFF

Figure 9. AD5544 Integral Nonlinearity Error vs. Op Amp Offset

H

H

H

H

00943-0-009

Figure 7. AD5554 INL vs. Code, TA = 25°C

Rev. A | Page 10 of 20

AD5544/AD5554

0.75
VDD = 5V
V

= 10V

REF

T

= 25°C

0.50

–0.25

–0.50

INTEGRAL NONLINEARITY ERROR (LSB)

–0.75

0.25

0

–2000

A

–1500 –1000 –500

OP AMP OFFSET VOLTAGE (µV)

0

500 20001000 1500

3000

2000

1FFF

0FFF

H

H

H

H

Figure 10. AD5554 Integral Nonlinearity Error vs. Op Amp Offset

00943-0-010

10.0

7.5

5.0

2.5

0

–2.5

GAIN ERROR (LSB)

–5.0

–7.5

–10.0

–1500

–1000 –500

OP AMP OFFSET VOLTAGE (µV)

0

Figure 13. AD5544 Gain Error vs. Op Amp Offset

VDD = 5V
V

= 10V

REF

T

= 25°C

A

500 1000 1500

00943-0-013

1.00

VDD = 5V
V

= 10V

REF

–0.25

–0.50

–0.75

DIFFERENTIAL NONLINEARITY ERROR (LSB)

–1.00

0.75

0.50

0.25

0

–1000

= 25°C

T

A

–750 –500 –250

OP AMP OFFSET VOLTAGE (µV)

0

250 500 750 1000

8000

F000

0FFF

H

H

H

Figure 11. AD5544 Differential Nonlinearity Error vs. Op Amp Offset

0.3

0.2

0.1

VDD = 5V
V

= 10V

REF

T

= 25°C

A

2000

3000

H

H

00943-0-011

4

3

2

1

0

–1

–2

GAIN ERROR (LSB)

–3

–4

–5
–1500

–1000 –500

OP AMP OFFSET VOLTAGE (µV)

0

Figure 14. AD5554 Gain Error vs. Op Amp Offset

30

SS = 120 UNITS

= 5V

V

DD

V

= 10V

REF

T

= –40°C TO +85°C

A

20

VDD = 5V
V

= 10V

REF

= 25°C

T

A

500 1000 1500

00943-0-014

DIFFERENTIAL NONLINEARITY ERROR (LSB)

–0.1

–0.2

–0.3

0

–1500

–1000 –500

OP AMP OFFSET VOLTAGE (µV)

ACCURACY DEGRADATION
DUE TO EXTERNAL OP AMP
INPUT OFFSET VOLTAGE
SPECIFICATION.

0

0FFF

500 15001000

H

Figure 12. AD5554 Differential Nonlinearity Error vs. Op Amp Offset

00943-0-012

Rev. A | Page 11 of 20

FREQUENCY

10

0

0

0.5 1.0 1.5

FULL-SCALE TEMPCO (ppm/°C)

Figure 15. AD5544 Full-Scale Tempco (ppm/°C)

00943-0-015

AD5554/AD5554

50

40

30

20

FREQUENCY

10

0

0.2

0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8

FULL-SCALE ERROR TEMPCO (ppm/°C)

Figure 16. AD5554 Full-Scale Tempco (ppm/°C)

SS = 180 UNITS

= 5V

V

DD

V

= 10V

REF

= –40°C TO +85°C

T

A

00943-0-016

V

VDD = 5V
V

= 10V

REF

T

= 25°C

A

A

= –343

V

1LSB = 52mV

OUT

(10V/DIV)

V

OUT

(50mV/DIV)

1µs/DIV

Figure 19. AD5544 Small Signal Settling Time

00943-0-019

7FFFH8000

0000HFFFF

H

VDD = 5V
V

= 10V

REF

T

= 25°C

A

100ns/DIV

Figure 17. AD5544 Midscale Transition

H

VDD = 5V

= 10V

V

REF

= 25°C

T

A

CS
(5V/DIV)

V

OUT

(50mV/DIV)

CS
(5V/DIV)

V

OUT

(5V/DIV)

00943-0-017

10000

VDD = 5V
V

= 10V

REF

T

= 25°C

A

1000

(µA)

DD

I

100

10

1k

10k 100k 1M 10M 100M

CLOCK FREQUENCY (Hz)

Figure 20. AD5544 Power Supply Current vs. Clock Frequency

10000

VDD = 5V

= 10V

V

REF

T

= 25°C

A

1000

(µA)

DD

I

100

5555

FFFF

8000

0000

1555

3FFF

2000

0000

H

H

H

H

00943-0-020

H

H

H

H

2µs/DIV

Figure 18. AD5544 Large Signal Settling Time

00943-0-018

Rev. A | Page 12 of 20

10

1k

10k 100k 1M 10M 100M

CLOCK FREQUENCY (Hz)

Figure 21. AD5554 Power Supply Current vs. Clock Frequency

00943-0-021

AD5544/AD5554

100

90

80

70

VDD = 5V ±10%

= 25°C

T

A

600

500

400

VDD = 5V

= 10V

V

REF

T

= 25°C

A

60

PSRR (dB)

50

40

30

20

1k

CLOCK FREQUENCY (Hz)

10k 100k 1M100

Figure 22. AD5544/AD5554 Power Supply Rejection vs. Frequency

55

VDD = 5V

54

53

52

51

50

49

SUPPLY CURRENT (µA)

48

47

46

= 10V

V

REF

LOGIC = V

DD

–25 0 25 50 75 100 125 150

–50

TEMPERATURE (°C)

Figure 23. AD5544/AD5554 Power Supply Current vs. Temperature

00943-0-022

00943-0-023

300

(µA)

DD

I

200

100

0

0

1

2345

LOGIC INPUT VOLTAGE (V)

00943-0-024

Figure 24. AD5544/AD5554 Power Supply Current vs. Logic Input Voltage

Rev. A | Page 13 of 20

AD5554/AD5554

(

)

4

CIRCUIT OPERATION

The AD5544 and AD5554 contain four, 16-bit and 14-bit, cur­rent-output, digital-to-analog converters, respectively. Each
DAC has its own independent multiplying reference input. Both
the AD5544 and the AD5554 use a 3-wire, SPI compatible, serial

RS

data interface, with a configurable asynchronous
half-scale (MSB = 1) or zero-scale (MSB = 0) preset. In addition,

LDAC

an

strobe enables four channel simultaneous updates for

hardware synchronized output voltage changes.

D/A CONVERTER

Each part contains four current-steering R-2R ladder DACs.
Figure 25 shows a typical equivalent DAC. Each DAC contains a
matching feedback resistor for use with an external I-to-V con­verter amplifier. The R
external amplifier. The I
input of the external amplifier. The A
connected to the load point requiring full 16-bit accuracy. These
DACs are designed to operate with both negative or positive
reference voltage. The V
drive the DAC switches on and off. Note that a matching switch
is used in series with the internal 5 kΩ feedback resistor. If users
attempt to measure the value of R

in order to achieve continuity. An additional VSS bias pin is

V

DD

used to guard the substrate during high temperature applica­tions, minimizing zero-scale leakage currents that double every
10°C. The DAC output voltage is determined by V
digital data (D) in the following equations:

OUT

OUT

VV

VV

Note that the output polarity is opposite to the V
dc reference voltages.

V

X

REF

DIGITAL INTERFACE CONNECTIONS OMITTED FOR CLARITY.
SWITCHES S1 AND S2 ARE CLOSED, VDD MUST BE POWERED.

RR

DGND

V

SS

Figure 25. Typical Equivalent DAC Channel

These DACs are also designed to accommodate ac reference
input signals. Both the AD5544 and the AD5554 accommodate
input reference voltages in the range of −12 V to +12 V. The
reference voltage inputs exhibit a constant nominal input

X pin connects to the output of the

FB

X terminal connects to the inverting

OUT

X pin should be Kelvin-

GND

power pin is only used by the logic to

DD

, power must be applied to

FB

D

×−=

REF

65536

D

×−= (2)

REF

FROM OTHER DACS A

(

1638

R

5544ADFor

)

5554ADFor

R2R2R2R 5kΩ

GND

pin for

and the

REF

(1)

polarity for

REF

V

DD

RFBX

S1S2

X

I

OUT

A

F

GND

A

X

GND

00943-0-025

resistance of 5 kΩ, ±30%. On the other hand, the DAC outputs
IOUTA, B, C, D are code-dependent and produce various out­put resistances and capacitances. The choice of external ampli­fier should take into account the variation in impedance
generated by the AD5544/AD5554 on the amplifiers’ inverting
input node. The feedback resistance, in parallel with the DAC
ladder resistance, dominates output voltage noise. For multi­plying mode applications, an external feedback compensation
capacitor (C

) may be needed to provide a critically damped

FB

output response for step changes in reference input voltages.
Figure 26 and Figure 27 show the gain vs. frequency perfor­mance at various attenuation settings using a 23 pF external
feedback capacitor connected across the I

X and RFBX ter-

OUT

minals for AD5544 and AD5554, respectively. In order to main­tain good analog performance, power supply bypassing of

0.01 µF, in parallel with 1 µF, is recommended. Under these
conditions, a clean power supply with low ripple voltage capa­bility should be used. Switching power supplies is usually not
suitable for this application due to the higher ripple voltage and
PSS frequency-dependent characteristics. It is best to derive the
AD5544/AD5554’s 5 V supply from the system’s analog supply
voltages. Do not use the digital 5 V supply (see Figure 28).

FFFF

H

B15
B14
B13
B12
B11
B10

B9
B8
B7
B6
B5
B4

GAIN (12dB/DIV)

B3
B2
B1

B0
ZS

1k

10k 100k 1M 10M100

FREQUENCY (Hz)

Figure 26. AD5554 Reference Multiplying Bandwidth vs. Code

3FFF

H

B13
B12
B11
B10

B9
B8
B7
B6
B5
B4
B3
B2

GAIN (12dB/DIV)

B1
B0

ZS

1k

10k 100k 1M 10M100

FREQUENCY (Hz)

Figure 27. AD5554 Reference Multiplying Bandwidth vs. Code

VDD = 5V

= 100mV rms

V

REF

= 25°C

T

A

VDD = 5V

= 100mV rms

V

REF

T

= 25°C

A

= 23pF

C

F

00943-0-026

00943-0-027

Rev. A | Page 14 of 20

AD5544/AD5554

V

15V

ANALOG

POWER

SUPPLY

5V

15V

V

CC

V

A1

OUT

+

V

EE

LOAD

00943-0-028

X

REF

DIGITAL INTERFACE CONNECTIONS OMITTED.
FOR CLARITY SWITCHES S1 AND S2 ARE CLOSED,
V

DD

RR R

FROM OTHER DACS A

V

SS

MUST BE POWERED.

Figure 28. Recommended Kelvin-Sensed Hookup

V

DD

R2R2R2R 5kΩ

GND

AD5544

DGND

2R

+

R

RFBX

S1S2

I
A

A

OUT

GND

GND

X

F
X

Rev. A | Page 15 of 20

AD5554/AD5554

SERIAL DATA INTERFACE

The AD5544/AD5554 uses a 3-wire (CS, SDI, CLK) SPI compa-

tible serial data interface. Serial data of AD5544 and AD5554 is
clocked into the serial input register in an 18-bit and 16-bit
data-word format respectively. MSB bits are loaded first. Table 6
defines the 18 data-word bits for AD5544.

Table 7 defines the 16 data-word bits for AD5554. Data is placed
on the SDI pin, and clocked into the register on the positive
clock edge of CLK subject to the data setup and data hold time
requirements specified in the interface timing specifications.
data can only be clocked in while the

low. For AD5544, only the last 18 bits clocked into the serial
register will be interrogated when the

logic high state, extra data bits are ignored. For AD5554, only
the last 16 bits clocked into the serial register will be inter­rogated when the

pin returns to the logic high state. Since

CS

most microcontrollers output serial data in 8-bit bytes, three
right justified data bytes can be written to the AD5544. Keeping

CS

CLK

EN

chip select pin is active

CS

pin returns to the

CS

line low between the first, second, and third byte trans-

the

CS

fers will result in a successful serial register update. Similarly,
two right justified data bytes can be written to the AD5554.
Keeping the

line low between the first and second byte

CS

transfer will result in a successful serial register update.

Once the data is properly aligned in the shift register, the posi­tive edge of the

CS

initiates the transfer of new data to the target
DAC register, determined by the decoding of address Bits A1
and A0. For AD5544, Table 5, Table 7, Table 9, and Figure 4
define the characteristics of the software serial interface. For
AD5554, Table 6, Table 8, Table 9, and Figure 5 define the
characteristics of the software serial interface. Figure 29 and
Figure 30 show the equivalent logic interface for the key digital
control pins for the AD5544. AD5554 has a similar configura-

RS

tion, except it has 14 data bits. Two additional pins,

and
MSB, provide hardware control over the preset function and
DAC register loading.

V

A B C D

REF

AD5544

V

DD

SDI

SDO

D10
D11
D12
D13
D14
D15

16

D0
D1
D2
D3
D4
D5
D6
D7
D8
D9

DAC A

2:4

DECODE

B
C
D

POWER-

ON

RESET

A0
A1

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

SET

MSB

R

R

R

R

DAC A

REGISTER

DACB

REGISTER

DACC

REGISTER

DAC D

REGISTER

SET

MSB

R

R

R

R

DACA

DAC B

DACC

DACD

RFBA
I

OUT

A

GND

R

FB

I

OUT

A

GND

R

FB

I

OUT

A

GND

R

FB

I

OUT

A

GND

A

GND

A

A

B

B

B

C

C

C

D

D

D

F

DGND MSB V

Figure 29. System Level Digital Interfacing

LDAC

RS

SS

00943-0-029

Rev. A | Page 16 of 20

AD5544/AD5554

Ω

If these functions are not needed, the RS pin can be tied to logic

RS

high. The asynchronous input

pin forces all input and DAC
registers to either the zero-code state (MSB = 0) or the half­scale state (MSB = 1).

TO INPUT REGISTER

A

CLOCK

B
C
D

TH

00943-0-030

CS

EN

CLK

SDI

SDO

ADDRESS
DECODER

SHIFT REGISTER

Figure 30. AD5544/AD5554 Equivalent Logic Interface

19TH/17

POWER ON RESET

When the VDD power supply is turned on, an internal reset
strobe forces all the input and DAC registers to the zero-code
state or half-scale state, depending on the MSB pin voltage. The

power supply should have a smooth positive ramp without

V

DD

drooping in order to have consistent results, especially in the
region of V
the power-on reset performance. The DAC register data will
stay at a zero or half-scale setting until a valid serial register
data load takes place.

ESD Protection Circuits

All logic-input pins contain back-biased ESD protection Zeners
connected to ground (D

Power Supply Sequence

As standard practice, it is recommended to power VDD, VSS, and
ground prior to any reference. The ideal power up sequence is

X, D

A

GND

ance power up sequence may elevate the reference current, but
the devices resume normal operation once V
powered-up.

Layout and Power Supply Bypassing

It is good practice to employ a compact, minimum-lead length
layout design. The leads to the input should be as direct as
possible with a minimum conductor length. Ground paths
should have low resistance and low inductance.

Similarly, it is good practice to bypass the power supplies with
quality capacitors for optimum stability. Supply leads to the
device should be bypassed with 0.01 µF to 0.1 µF disc or chip
ceramic capacitors. Low-ESR 1 µF to 10 µF tantalum or

= 1.5 V to 2.3 V. The VSS supply has no effect on

DD

) and VDD, as shown in Figure 31.

GND

V

DD

DIGITAL

INPUTS

Figure 31. Equivalent ESD Production Circuits

, VDD, VSS, V

GND

5kΩ

DGND

X, and digital inputs. A noncompli-

REF

00943-0-031

and VSS are

DD

electrolytic capacitors should also be applied at V
any transient disturbance and filter any low frequency ripple
(see Figure 32). Users should not apply switching regulators for

due to the power supply rejection ratio degradation over

V

DD

frequency.



AD5544/AD5554

VDD

VSS

C3

10µF

10µF

+

C1

0.1µF
C2

C4

0.1µF

VDD

A

GND

VSS

X

Figure 32. Power Supply Bypassing and Grounding Connection

Grounding

The DGND and AGNDX pins of the AD5544/AD5554 refer as
digital and analog ground references. To minimize the digital
ground bounce, the DGND terminal should be joined remotely
at a single point to the analog ground plane (see Figure 32).

APPLICATIONS

The AD5544/AD5554 are inherently 2-quadrant multiplying
D/A converters. That is, they can be easily set up for unipolar
output operation. The full-scale output polarity is the inverse of
the reference-input voltage.

In some applications it may be necessary to generate the full
4-quadrant multiplying capability or a bipolar output swing.
This is easily accomplished using an additional external ampli­fier (A2) configured as a summing amplifier (see Figure 33). In
this circuit the first and second amplifiers (A1 and A2) provide
a total gain of 2 which increases the output voltage span to 20 V.
Biasing the external amplifier with a 10 V offset from the refer­ence voltage results in a full 4-quadrant multiplying circuit. The
transfer equation of this circuit shows that both negative and
positive output voltages are created as the input data (D) is
incremented from code zero (V

= 0 V) to full-scale (V

(V

OUT

D

⎛

V

⎜

OUT

32768

⎝

D

⎛

V

⎜

OUT

8192

⎝

10V

V

REF

AD588

V

DD

DIGITAL INTERFACE CONNECTIONS
OMITTED FOR CLARITY.

Figure 33. Four-Quadrant Multiplying Application Circuit

⎞

−

⎟
⎠

⎞

−×

−

⎟
⎠

REF

ONE CHANNEL

AD5544

VSSA

GND

−×

X

F

= −10 V) to midscale

OUT

= 10 V).

OUT

(

REF

(

REF

10kΩ

5kΩ

XV

R

FB

I

A

GND

OUT

X

55441

ADForV

55541

ADForV

10k

A2

–10V < V

X

A1

to minimize

DD

DGND

00943-0-033

)

(3)

)

(4)

V

OUT

< +10V

OUT

00943-0-033

Rev. A | Page 17 of 20

AD5544/AD5554

OUTLINE DIMENSIONS

10.50

10.20

9.90

28 15

1

8.20

5.60

7.80

5.30

7.40

5.00

14

0.05
MIN

2.00 MAX

0.65

BSC

1.85

1.75

1.65

0.38

0.22

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MO-150AH

Figure 34. 28-Lead SSOP

0.10
COPLANARITY

0.25

0.09
8°
4°
0°

0.95

0.75

0.55

(RS-28)

Dimensions Shown in Inches and (Millimeters)

ORDERING GUIDE

Model RES Bit INL LSB DNL LSB Temperature Range Package Description Package Option

AD5544ARS 16 ±4 ±1.5 –40°C to +85°C SSOP-28 RS-28
AD5554BRS 14 ±1 ±1 –40°C to +85°C SSOP-28 RS-28
AD5544EVAL Evaluation Board

Rev. A | Page 18 of 20

AD5544/AD5554

NOTES

Rev. A | Page 19 of 20

AD5544/AD5554

NOTES

© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.

C00943-0-12/04(A)

Rev. A | Page 20 of 20