Datasheet AD5543-EP Datasheet (ANALOG DEVICES)

Current Output/Serial

Data Sheet

FEATURES

−1/+2 LSB DNL
±3 LSB INL
Low noise: 12 nV/√Hz
Low power: I

0.5 μs settling time
4Q multiplying reference input
2 mA full-scale current ± 20%, with V
Built-in RFB facilitates voltage conversion
3-wire interface
Ultracompact 8-lead MSOP and 8-lead SOIC packages

ENHANCED PRODUCT FEATURES

Supports defense and aerospace applications (AQEC)
Military temperature range (−55°C to +125°C)
Controlled manufacturing baseline
One assembly/test site
One fabrication site
Enhanced product change notification
Qualification data available on request

APPLICATIONS

Automatic test equipment
Instrumentation
Digitally controlled calibration
Industrial control PLCs

= 10 μA

DD

= 10 V

REF

Input, 16-Bit DAC

AD5543-EP

FUNCTIONAL BLOCK DIAGRAM

AD5543-EP

V

DD

V

CLK

REF

CS

SDI

CONTROL

LOGIC

DAC

16

DAC

REGISTER

16

16-BIT SHIFT

REGISTER

Figure 1.

R

FB

I

OUT

GND

10082-001

GENERAL DESCRIPTION

The AD5543-EP is a precision 16-bit, low power, current
output, small form factor digital-to-analog converter (DAC). It
is designed to operate from a single 5 V supply with a ±10 V
multiplying reference.

The applied external reference, V
output current. An internal feedback resistor (R
R-2R and temperature tracking for voltage conversion when
combined with an external op amp.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

, determines the full-scale

REF

) facilitates the

FB

A serial-data interface offers high speed, 3-wire microcontroller­compatible inputs using serial data in (SDI), clock (CLK), and
chip select (

CS

).

The AD5543-EP is packaged in an ultracompact (3 mm × 4.7 mm)
8-lead MSOP package.

Full details about this enhanced product are available in the

AD5543 data sheet, which should be consulted in conjunction

with this data sheet.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2012 Analog Devices, Inc. All rights reserved.

AD5543-EP Data Sheet

TABLE OF CONTENTS

Features.............................................................................................. 1

Enhanced Product Features ............................................................ 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

REVISION HISTORY

2/12—Revision 0: Initial Version

Timing Diagram............................................................................4

Absolute Maximum Ratings ............................................................5

ESD Caution...................................................................................5

Pin Configuration and Function Descriptions..............................6

Typical Performance Characteristics..............................................7

Outline Dimensions..........................................................................9

Ordering Guide .............................................................................9

Rev. 0 | Page 2 of 12

Data Sheet AD5543-EP

SPECIFICATIONS

VDD = 5 V ± 10%, VSS = 0 V, I

Table 1.

Parameter Symbol Condition 5 V ± 10% Unit

STATIC PERFORMANCE1

Resolution N 1 LSB = V
Relative Accuracy INL ±3 LSB max
Differential Nonlinearity DNL Monotonic −1/+2 LSB max
Output Leakage Current I
Data = 0x0000, TA = TA maximum 20 nA max
Full-Scale Gain Error G
Full-Scale Temperature Coefficient2 TCVFS 1 ppm/°C typ

REFERENCE INPUT

V

Range V

REF

Input Resistance R
Input Capacitance2 C

ANALOG OUTPUT

Output Current I
Output Capacitance2 C

LOGIC INPUTS AND OUTPUT

Logic Input Low Voltage VIL 0.8 V max
Logic Input High Voltage VIH 2.4 V min
Input Leakage Current IIL 10 μA max
Input Capacitance2 C

INTERFACE TIMING

2, 4

Clock Input Frequency f
Clock Width High tCH 10 ns min
Clock Width Low tCL 10 ns min
CS to Clock Setup

Clock to CS Hold
Data Setup tDS 5 ns min
Data Hold tDH 10 ns min

SUPPLY CHARACTERISTICS

Power Supply Range V
Positive Supply Current IDD Logic inputs = 0 V 10 μA max
Power Dissipation P
Power Supply Sensitivity PSS ΔVDD = ±5% 0.006 %/% max

AC CHARACTERISTICS4

Output Voltage Settling Time tS To ±0.1% of full scale, 0.5 μs typ
Data = 0x0000 to 0xFFFF to 0x0000
Reference Multiplying Bandwidth BW V
DAC Glitch Impulse Q V
Feedthrough Error V
Digital Feedthrough Q CS = 1 and f
Total Harmonic Distortion THD V
Output Spot Noise Voltage eN f = 1 kHz, BW = 1 Hz 12 nV/√Hz

1

All static performance tests (except I

the amplifier output. The +IN op amp is grounded, and the DAC I

2

These parameters are guaranteed by design and are not subject to production testing.

3

All ac characteristic tests are performed in a closed-loop system using an AD8038 I-to-V converter amplifier except for THD where an AD8065 was used.

4

All input control signals are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.

= virtual GND, GND = 0 V, V

OUT

Data = 0x0000, TA = 25°C 10 nA max

OUT

Data = 0xFFFF ±1/±4 mV typ/max

FSE

−15/+15 V min/max

REF

5 kΩ typ3

REF

5 pF typ

REF

Data = 0xFFFF 2 mA typ

OUT

Code dependent 200 pF typ

OUT

10 pF max

IL

50 MHz

CLK

t

0 ns min

CSS

t

10 ns min

CSH

4.5/5.5 V min/max

DD RANGE

Logic inputs = 0 V 0.055 mW max

DISS

REF

REF

Data = 0x0000, V

OUT/VREF

REF

) are performed in a closed-loop system using an external precision OP177 I-to-V converter amplifier. The RFB terminal is tied to

OUT

is tied to the −IN op amp. Typical values represent average readings measured at 25°C.

OUT

= 10 V, TA = full operating temperature range, unless otherwise noted.

REF

/216 = 153 μV when V

REF

= 10 V 16 Bits

REF

= 100 mV rms, data = 0xFFFF 6.6 MHz typ
= 0 V, data = 0x7FFF to 0x8000 7 nV-sec

= 100 mV rms, same channel −83 dB

REF

= 1 MHz 7 nV-sec

CLK

= 5 V p-p, data = 0xFFFF, f = 1 kHz −103 dB typ

Rev. 0 | Page 3 of 12

AD5543-EP Data Sheet

CLK

TIMING DIAGRAM

SDI

CS

D15 D14 D13 D12 D11 D10 D9 D8 D1 D0

t

t

CSS

DS

t

DH

t

CH

t

CL

t

CSH

10082-016

Figure 2. Timing Diagram

Rev. 0 | Page 4 of 12

Data Sheet AD5543-EP

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

VDD to GND −0.3 V to +8 V
V

to GND −18 V to +18 V

REF

Logic Inputs to GND −0.3 V to +8 V
V(I

) to GND −0.3 V to VDD + 0.3 V

OUT

Input Current to Any Pin Except Supplies ±50 mA
Package Power Dissipation (T
Thermal Resistance, θJA

8-Lead Surface Mount (MSOP) 150°C/W
Maximum Junction Temperature (T
Operating Temperature Range

Enhanced Plastic (EP Version) −55°C to +125°C
Storage Temperature Range −65°C to +150°C
Lead Temperature

RM-8 (Vapor Phase, 60 sec) 215°C

RM-8 (Infrared, 15 sec) 220°C

) 150°C

J Max

− TA)/θJA

J Max

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. 0 | Page 5 of 12

AD5543-EP Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

CLK

SDI

2

AD5543-EP

TOP VIEW

3

R

FB

REF

(Not to Scale)

4

V

Figure 3. Pin Configuration

Table 3. Pin Function Descriptions

Pin No. Mnemonic Description

1 CLK Clock Input. Positive-edge triggered, clocks data into shift register.
2 SDI Serial Register Input. Data loads directly into the shift register MSB first. Extra leading bits are ignored.
3 RFB Internal Matching Feedback Resistor. This pin connects to an external op amp for voltage output.
4 V
5 I

DAC Reference Input Pin. Establishes DAC full-scale voltage. Constant input resistance vs. code.

REF

OUT

DAC Current Output. This pin connects to the inverting terminal of the external precision I-to-V op amp for

voltage output.
6 GND Analog and Digital Ground.
7 VDD Positive Power Supply Input. Specified range of operation at 5 V ± 10%.
8

CS

Chip Select. Active low digital input. Transfers shift-register data to DAC register on rising edge.

8

CS
V

7

DD

6

GND
I

5

OUT

10082-004

Rev. 0 | Page 6 of 12

Data Sheet AD5543-EP

TYPICAL PERFORMANCE CHARACTERISTICS

1.0

0.8

0.6

0.4

0.2

0

INL (LSB)

–0.2

–0.4

–0.6

–0.8
–1.0

8192 16,384 57,34449,15240,96032,76824,576

065,536

CODE (Deci mal)

10082-005

Figure 4. Integral Nonlinearity Error

1.0

0.8

0.6

0.4

0.2
0

DNL (LSB)

–0.2

–0.4
–0.6

–0.8
–1.0

8192

065,536

16,384

CODE (Deci mal)

57,34449,15240,96032,76824,576

10082-006

Figure 5. Differential Nonlinearity Error

1.5
= 2.5V

V

REF

T

= 25°C

A

1.0

0.5

INL

0

–0.5

LINEARIT Y E RROR (LSB)

–1.0

–1.5

SUPPLY VOLTAGE VDD (V)

Figure 6. Linearity Error vs. Supply Voltage, V

DNL

GE

68

DD

0124

10082-009

5

VDD = 5V
T

= 25°C

A

4

(mA)

DD

3

2

SUPPLY CURRENT I

1

0

0.5 1.0 5.0

0

Figure 7. Supply Current, I

2.01.5 2.5 3.0 3.5 4.0 4.5

LOGIC INPUTVOLTAGEVIH (V)

vs. Logic Input Voltage, VIH

DD

3.0

2.5

2.0

1.5

1.0

SUPPLY CURRENT (mA)

0.5

0

CLOCK FRE QUE NCY (Hz)

0x0000

1M 10M

0x5555

0x8000

0xFFFF

Figure 8. Supply Current vs. Clock Frequency

90

80

70

60

50

40

PSRR (dB)

30

20

10

0

1k10010

FREQUENC Y (Hz)

10k

VDD = 5V ± 10%

= 10V

V

REF

100k

Figure 9. Power Supply Rejection Ratio (PSRR) vs. Frequency

10082-010

100M10k 100k

10082-011

1M

10082-012

Rev. 0 | Page 7 of 12

AD5543-EP Data Sheet

POWER SP ECTRUM (dB)

–20

–40

–60

–80

–100

–120

–140

–160

20

0

022015105

FREQUENCY ( kHz )

Figure 10. Analog Total Harmonic Distortion

5

10082-200

–3.65

–3.70

–3.75

–3.80

(V)

–3.85

OUT

V

–3.90

–3.95

–4.00

–4.05

–20 –10 0 10 20 30 40

TIME (ns)

Figure 12. Midscale Transition and Digital Feedthrough

10082-026

A2 –5V 67.72µsDLY

5V

2V

136ns

10082-014

Figure 11. Settling Time

Rev. 0 | Page 8 of 12

Data Sheet AD5543-EP

OUTLINE DIMENSIONS

3.20

3.00

2.80

8

5

3.20

3.00

2.80

PIN 1

IDENTIFIER

0.95

0.85

0.75

0.15

0.05

COPLANARITY

1

0.65 BSC

0.10

COMPLIANT TO JEDEC STANDARDS MO-187-AA

Figure 13. 8-Lead Mini Small Outline Package [MSOP]

5.15

4.90

4.65

4

15° MAX

6°
0°

0.23

0.09

0.40

0.25

1.10 MAX

(RM-8)

Dimensions shown in millimeters

0.80

0.55

0.40

10-07-2009-B

ORDERING GUIDE

1, 2

Model

INL (LSB) RES (LSB) Temperature Range Package Description

AD5543SRMZ-EP ±3 16 −55°C to +125°C 8-Lead Mini Small Outline Package [MSOP] RM-8 DHR

1

The AD5543 contains 1040 transistors. The die size measures 55 mil × 73 mil or 4,015 sq. mil.

2

Z = RoHS Compliant Part.

Package
Option Branding

Rev. 0 | Page 9 of 12

AD5543-EP Data Sheet

NOTES

Rev. 0 | Page 10 of 12

Data Sheet AD5543-EP

NOTES

Rev. 0 | Page 11 of 12

AD5543-EP Data Sheet

NOTES

©2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10082-0-2/12(0)

Rev. 0 | Page 12 of 12