Datasheet AD5543 Datasheet (Analog Devices)

Current Output/

FFFFH

START 10.000Hz

1k 100k10 100 10k 1M 10M

8000H
4000H

1000H
0800H
0400H
0200H
0100H
0080H
0040H
0020H
0010H
0008H
0004H
0002H
0001H

0000H

STOP 50 000 000.000Hz

2000H

REF LEVEL

0.000dB

/DIV

12.000dB

MARKER 4 311 677.200Hz
MAG (A/R) –2.939dB

a

FEATURES
16-Bit Resolution AD5543
14-Bit Resolution AD5553

1 LSB DNL
2 LSB INL for AD5543
1 LSB INL for AD5553

Low Noise 12 nV/√Hz
Low Power, I

0.5 s Settling Time
4Q Multiplying Reference-Input
2 mA Full-Scale Current  20%, with V
Built-in RFB Facilitates Voltage Conversion
3-Wire Interface
Ultracompact MSOP-8 and SOIC-8 Packages

APPLICATIONS
Automatic Test Equipment
Instrumentation
Digitally Controlled Calibration
Industrial Control PLCs

GENERAL DESCRIPTION

The AD5543/AD5553 are precision 16-/14-bit, low power,
current output, small form factor digital-to-analog converters.
They are designed to operate from a single 5 V supply with a
±10 V multiplying reference.

The applied external reference V
output current. An internal feedback resistor (R
R-2R and temperature tracking for voltage conversion when
combined with an external op amp.

A serial-data interface offers high speed, 3-wire microcontroller
compatible inputs using serial data in (SDI), clock (CLK), and
chip select (CS).

The AD5543/AD5553 are packaged in ultracompact
(3 mm  4.7 mm) MSOP-8 and SOIC-8 packages.

= 10 A

DD

= 10 V

REF

determines the full-scale

REF

) facilitates the

FB

Serial Input, 16-/14-Bit DAC

AD5543/AD5553

FUNCTIONAL BLOCK DIAGRAM

AD5543/AD5553

V

DD

16384

20480

CONVERTER

D/A

16 OR 14

DAC

REGISTER

16 OR 14

16-/14-BIT SHIFT

REGISTER

24575

28672

32768

36864

CODE

V

REF

CS

CLK

SDI

1.0

0.8

0.6

0.4

0.2

0

INL – LSB

–0.2

–0.4

–0.6

–0.8

–1.0

0

CONTROL

LOGIC

4096

8152

12288

Figure 1. Integral Nonlinearity Error

40960

45056

49152

53248

R

I

OUT

GND

57344

FB

61440

65536

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.

Figure 2. Reference Multiplying Bandwidth

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2003 Analog Devices, Inc. All rights reserved.

AD5543/AD5553–SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

(@ VDD = 5 V  10%, VSS = 0 V, I
TA = Full operating temperature range, unless otherwise noted.)

= Virtual GND, GND = 0 V, V

OUT

= 10 V,

REF

Parameter Symbol Condition 5 V  10% Unit

STATIC PERFORMANCE

Resolution N 1 LSB = V

1

1 LSB = V

/216 = 153 µV when V

REF

/214 = 610 µV when V

REF

= 10 V AD5543 16 Bits

REF

= 10 V AD5553 14 Bits

REF

Relative Accuracy INL Grade: AD5553C ±1LSB max

Grade: AD5543B ±2LSB max

Differential Nonlinearity DNL Monotonic ±1LSB max
Output Leakage Current I

Full-Scale Gain Error G
Full-Scale Tempco

2

OUT

FSE

TCV

FS

Data = 0000H, TA = 25°C10nA max
Data = 0000
Data = FFFF

, TA = TA max 20 nA max

H

H

±1/±4mV typ/max
1ppm/°C typ

REFERENCE INPUT

Range V

V

REF

Input Resistance R
Input Capacitance

2

REF

REF

C

REF

–15/+15 V min/max
5kΩ typ
5pF typ

ANALOG OUTPUT

Output Current I

Output Capacitance

2

OUT

C

OUT

Data = FFFFH for AD5543 2 mA typ
Data = 3FFF

for AD5553

H

Code Dependent 200 pF typ

LOGIC INPUTS AND OUTPUT

Logic Input Low Voltage V
Logic Input High Voltage V
Input Leakage Current I
Input Capacitance

INTERFACE TIMING

2

2, 4

Clock Input Frequency f
Clock Width High t
Clock Width Low t
CS to Clock Setup t
Clock to CS Hold t
Data Setup t
Data Hold t

C

IL

IH

IL

IL

CLK

CH

CL

CSS

CSH

DS

DH

0.8 V max

2.4 V min
10 µA max
10 pF max

50 MHz
10 ns min
10 ns min
0 ns min
10 ns min
5 ns min
10 ns min

SUPPLY CHARACTERISTICS

Power Supply Range VDD
Positive Supply Current I
Power Dissipation P
Power Supply Sensitivity P

AC CHARACTERISTICS

4

Output Voltage Settling Time t

Reference Multiplying BW BW V
DAC Glitch Impulse Q V

Feedthrough Error V
Digital Feedthrough Q CS = 1, and f
Total Harmonic Distortion THD V
Output Spot Noise Voltage e

NOTES

1

All static performance tests (except I
is tied to the amplifier output. The op amp +IN is grounded and the DAC I

2

These parameters are guaranteed by design and are not subject to production testing.

3

All ac characteristic tests are performed in a closed-loop system using an AD841 I-to-V converter amplifier.

4

All input control signals are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V.

) are performed in a closed-loop system using an external precision OP177 I-to-V converter amplifier. The AD5543 R

OUT

RANGE

DD

DISS

SS

S

OUT/VREF

N

Logic Inputs = 0 V 10 µA max
Logic Inputs = 0 V 0.055 mW max
∆VDD = ±5% 0.006 %/% max

To ±0.1% of Full Scale, 0.5 µs typ
Data = 0000
Data = 0000

= 5 V p-p, Data = FFFF

REF

= 0 V, Data = 7FFFH to 8000H for AD5543 7 nV-s typ

REF

Data = 1FFF
Data = 0000H, V

= 5 V p-p, Data = FFFFH, f = 1 kHz –85 dB typ

REF

to FFFFH to 0000H for AD5543

H

to 3FFFH to 0000H for AD5553

H

H

to 2000H for AD5553

H

= 100 mV rms, same channel –65 dB

REF

= 1 MHz 7 nV-s typ

CLK

f = 1 kHz, BW = 1 Hz 12 nV/√Hz

is tied to the op amp –IN. Typical values represent average readings measured at 25 °C.

OUT

4.5/5.5 V min/max

4 MHz typ

terminal

FB

3

REV. A–2–

AD5543/AD5553

ABSOLUTE MAXIMUM RATINGS*

VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +8 V

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 V, +18 V

V

REF

Logic Inputs to GND . . . . . . . . . . . . . . . . . . . . . –0.3 V, +8 V

) to GND . . . . . . . . . . . . . . . . . . . –0.3 V, VDD + 0.3 V

V(I

OUT

Input Current to Any Pin except Supplies . . . . . . . . . . ±50 mA

Package Power Dissipation . . . . . . . . . . . . . (T

Thermal Resistance 

JA

Max – TA )/

J

JA

8-Lead Surface Mount (MSOP-8) . . . . . . . . . . . . . 150°C/W

8-Lead Surface Mount (SOIC-8) . . . . . . . . . . . . . . 100°C/W

Maximum Junction Temperature (T

Max) . . . . . . . . . . 150°C

J

Operating Temperature Range

Models B, C . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C

Lead Temperature

RN-8, RM-8 (Vapor Phase, 60 sec) . . . . . . . . . . . . . . 215°C

RN-8, RM-8 (Infrared, 15 sec) . . . . . . . . . . . . . . . . . 220°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

PIN CONFIGURATION

MSOP and SOIC-8

CLK

V

SDI

R

REF

1

2

3

FB

4

AD5543/

AD5553

TOP VIEW

(Not to Scale)

8

CS

V

7

DD

6

GND

I

5

OUT

PIN FUNCTION DESCRIPTIONS

Pin
No. Mnemonic Function

1 CLK Clock Input. Positive-edge triggered, clocks

data into shift register.

2 SDI Serial Register Input. Data loads directly

into the shift register MSB first. Extra leading
bits are ignored.

3R

FB

Internal Matching Feedback Resistor. Con­nects to external op amp for voltage output.

4V

REF

DAC Reference Input Pin. Establishes DAC
full-scale voltage. Constant input resistance
versus code.

5I

OUT

DAC Current Output. Connects to inverting
terminal of external precision I-to-V op amp

for voltage output.
6GND Analog and Digital Ground
7V

DD

Positive Power Supply Input. Specified range

of operation 5 V ± 10%.
8 CS Chip Select. Active low digital input. Transfers

shift-register data to DAC register on rising

edge. See Truth Table for operation.

ORDERING GUIDE*

INL RES Temperature Package Package

Model (LSB) (LSB) Range Description Option Marking

AD5543BR ± 216–40°C to +85°C SOIC-8 RN-8 AD5543
AD5543BRM ±216–40°C to +85°CMSOP-8 RM-8 DXB
AD5553CRM ± 114–40°C to +85°CMSOP-8 RM-8 DUC

*The AD5543 contains 1040 transistors. The die size measures 55 mil  73 mil, 4,015 sq. mil.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD5543/AD5553 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

REV. A

–3–

AD5543/AD5553–Typical Performance Characteristics

1.0

0.8

0.6

0.4

0.2

0

INL – LSB

–0.2

–0.4

–0.6

–0.8

–1.0

0 655368192

16384 24576 32768 40960 49152 57344

CODE – Decimal

TPC 1. AD5543 Integral Nonlinearity Error

1.0

0.8

0.6

0.4

0.2

0

DNL – LSB

–0.2

–0.4

–0.6

–0.8

–1.0

0 655368192

16384 24576 32768 40960 49152 57344

CODE – Decimal

1.0

0.8

0.6

0.4

0.2

0

DNL – LSB

–0.2

–0.4

–0.6

–0.8

–1.0

0 2048 4096 6144 8192 10240 12288 14336 16384

CODE – Decimal

TPC 4. AD5553 Differential Nonlinearity Error

1.5
V

= 2.5V

REF

TA = 25C

1.0

0.5

INL

0

–0.5

LINEARITY ERROR – LSB

–1.0

–1.5

2104

SUPPLY VOLTAGE VDD – V

DNL

GE

68

TPC 2. AD5543 Differential Nonlinearity Error

1.0

0.8

0.6

0.4

0.2

0

INL – LSB

–0.2

–0.4

–0.6

–0.8

–1.0

0 14336

CODE – Decimal

12288102408192614440962048

16384

TPC 3. AD5553 Integral Nonlinearity Error

5

VDD = 5V

= 25C

T

A

4

– mA

DD

3

2

SUPPLY CURRENT I

1

0

0 0.5

TPC 5. Linearity Errors vs. V

1.0 2.01.5 2.5 3.0 3.5 4.0 4.5 5.0

LOGIC INPUT VOLTAGE V

DD

– V

IH

TPC 6. Supply Current vs. Logic Input Voltage

REV. A–4–

3.0

2.5

AD5543/AD5553

2.0

1.5

1.0

SUPPLY CURRENT – mA

0.5

0

10k 100M100k

CLOCK FREQUENCY – Hz

1M 10M

FFFF
0000

5555

H

8000

H

H

H

TPC 7. AD5543 Supply Current vs. Clock Frequency

90

80

70

60

50

40

PSRR – dB

30

20

10

0

1k10010

FREQUENCY – Hz

VDD = 5V  10%
V

= 10V

REF

10k 100k

1M

TPC 8. Power Supply Rejection vs. Frequency

TPC 10. Settling Time

CS (5V/DIV)

= 5V

V

DD

= 10V

V

REF

CODES 8000

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

TIME – s

↔ 7FFF

H

H

V

(50mV/DIV)

OUT

TPC 11. Midscale Transition and Digital Feedthrough

FFFFH

8000H
4000H
2000H
1000H
0800H
0400H
0200H
0100H
0080H
0040H
0020H
0010H
0008H
0004H
0002H
0001H

0000H

REV. A

REF LEVEL

0.000dB

START 10.000Hz

/DIV

12.000dB

1k 100k10 100 10k 1M 10M

MARKER 4 311 677.200Hz
MAG (A/R) –2.939dB

STOP 50 000 000.000Hz

TPC 9. Reference Multiplying Bandwidth

–5–

AD5543/AD5553

SDI

CLK

CS

SDI

CLK

D15 D14 D13 D12 D11 D10 D9 D8

t

DH

t

CSS

t

DS

Figure 3a. AD5543 Timing Diagram

D13 D12 D11 D10 D9 D8

t

DS

t

CSS

D7 D6

t

DH

D1 D0

t

CH

t

CH

t

CL

D1 D0

t

CL

t

t

CSH

CSH

CS

Figure 3b. AD5553 Timing Diagram

Table I. Control-Logic Truth Table

CLK CS Serial Shift Register Function DAC Register

XH No Effect Latched
↑+L Shift Register Data Advanced One Bit Latched
XH No Effect Latched
X ↑+ Shift Register Data Transferred to DAC Register New Data Loaded from Serial Register

↑+ positive logic transition; X Don't Care

Table II. AD5543 Serial Input Register Data Format; Data is Loaded in the MSB-First Format

MSB LSB

Bit Position B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

Data-Word D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Table III. AD5553 Serial Input Register Data Format; Data is Loaded in the MSB-First Format

MSB LSB

Bit Position B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

Data-Word*D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

*A full 16-bit data-word can be loaded into the AD5553 serial input register, but only the last 14 bits entered will be transferred to the DAC register when CS returns

to logic high.

REV. A–6–

AD5543/AD5553

V

DD

DIGITAL

INPUTS

5k

DGND

CIRCUIT OPERATION

The AD5543/AD5553 contains a 16-/14-bit, current output,
digital-to-analog converter, a serial input register, and a DAC
register. Both converters use a 3-wire serial data interface.

D/A Converter Section

The DAC architecture uses a current steering R-2R ladder
design. Figure 4 shows the typical equivalent DAC structure.
The DAC contains a matching feedback resistor for use with an
external op amp, (see Figure 5). With R

FB

and I

OUT

terminals
connected to the op amp output and inverting node respec­tively, a precision voltage output can be achieved as:

VVD AD

=×–/,()65 536 5543

OUT REF

VVD AD

=×–/,()16 384 5553

OUT REF

Note that the output voltage polarity is opposite to the V

(1)

(2)

REF

polarity for dc reference voltages.

These DACs are designed to operate with either negative or
positive reference voltages. The V

power pin is only used by

DD

the internal logic to drive the DAC switches’ ON and OFF states.

V

V

REF

RRR

2R 2R 2R R 5k

DD

R

FB

S1S2

I

OUT

GND

various resistances and capacitances. External amplifier choice
should take into account the variation in impedance generated
by the AD5543 on the amplifier’s inverting input node. The
feedback resistance, in parallel with the DAC ladder resistance,
dominates output voltage noise. To maintain good analog perfor­mance, power supply bypassing of 0.01 µF to 0.1 µF ceramic or
chip capacitors in parallel with a 1 µF tantalum capacitor is recom-
mended. Due to degradation of power supply rejection ratio in
frequency, users must avoid using switching power supplies.

SERIAL DATA INTERFACE

The AD5543/AD5553 uses a 3-wire (CS, SDI, CLK) serial
data interface. New serial data is clocked into the serial input
register in a 16-bit data-word format for AD5543. The MSB is
loaded first. Table II defines the 16 data-word bits. Data is
placed on the SDI pin and clocked into the register on the positive

edge of CLK, subject to the data setup and hold time

clock
requirements specified in the interface timing specifications

.

Only the last 16 bits clocked into the serial register are inter­rogated when the CS pin is strobed to transfer the serial register
data to the DAC register. Since most microcontrollers output
serial data in 8-bit bytes, two data bytes can be written to the
AD5543/AD5553. After loading the serial register, the rising edge
of CS transfers the serial register data to the DAC register;
during this strobe, the CLK should not be toggled. For the
AD5553, with 16-bit clock cycles, the two LSBs are ignored.

ESD Protection Circuits

All logic-input pins contain back-biased ESD protection Zener
diodes connected to ground (GND) and V

as shown in Figure 6.

DD

DIGITAL INTERFACE CONNECTIONS OMITTED FOR CLARITY;
SWITCHES S1 AND S2 ARE CLOSED, V

MUST BE POWERED

DD

Figure 4. Equivalent R-2R DAC Circuit

Note that a matching switch is used in series with the internal 5 kΩ
feedback resistor. If users attempt to measure RFB, power must be
applied to V

to achieve continuity.

DD

V

U1

V

V

REF

V

REF

GND

AD5543/AD5553

DD

R

DD

FB

I

OUT

U2

AD8628

V+

V–

–5V

V

O

Figure 5. Voltage Output Configuration

These DACs are also designed to accommodate ac reference
input signals. The AD5543 accommodates input reference
voltages in the range of –12 V to +12 V. The reference voltage
inputs exhibit a constant nominal input resistance value of 5 kΩ,
±30%. The DAC output (I

) is code-dependent, producing

OUT

Figure 6. Equivalent ESD Protection Circuits

PCB Layout and Power Supply Bypassing

It is a good practice to employ compact, minimum lead length
PCB layout design. The leads to the input should be as short as
possible to minimize IR drop and stray inductance.

It is also essential to bypass the power supplies with quality
capacitors for optimum stability. Supply leads to the device should
be bypassed with 0.01 µF to 0.1 µF disc or chip ceramic capaci-
tors. Low-ESR 1 µF to 10 µF tantalum or electrolytic capacitors
should also be applied at the supplies to minimize transient
disturbance and filter out low frequency ripple

The PCB metal traces between V

and RFB should also be

REF

matched to minimize gain error.

REV. A

–7–

AD5543/AD5553

APPLICATIONS
Stability

V

DD

U1

V

REF

V

REF

V

GND

R

FB

DD

AD5543/AD5553

I

OUT

C1

V

AD8628

U2

O

Figure 7. Optional Compensation Capacitor for Gain
Peaking Prevention

In the I-to-V configuration, the I

of the DAC and the inverting

OUT

node of the op amp must be connected as close as possible, and
proper PCB layout technique must be employed. Since every code
change corresponds to a step function, gain peaking may occur
if the op amp has limited GBP and there is excessive parasitic
capacitance at the inverting node.

An optional compensation capacitor C1 can be added for stability
as shown in Figure 7. C1 should be found empirically but 20 pF
is generally adequate for the compensation.

Positive Voltage Output

To achieve the positive voltage output, an applied negative
reference to the input of the DAC is preferred over the output
inversion through an inverting amplifier because of the resistor’s
tolerance errors. To generate a negative reference, the reference
can be level-shifted by an op amp such that the V

and GND

OUT

pins of the reference become the virtual ground and –2.5 V
respectively, (see Figure 8).

+5V

V

IN

U1

V

R

DD

V

FB

REF

GND

U3

AD5543/AD5553

I

OUT

C1

V

U2

1/2AD8628

0 < V

< +2.5

O

O

U4

+5V

V+

1/2AD8620

V–

–5V

ADR03

V

OUT

GND

–2.5V

Figure 8. Positive Voltage Output Configuration

Bipolar Output

The AD5543/AD5553 is inherently a 2-quadrant multiplying
D/A converter. That is, it can easily be set up for unipolar output
operation. The full-scale output polarity is the inverse of the
reference input voltage.

In some applications, it may be necessary to generate the full
4-quadrant multiplying capability or a bipolar output swing. This
is easily accomplished by using an additional external amplifier
U4 configured as a summing amplifier (see Figure 9). In this
circuit, the second amplifier U4 provides a gain of 2 that increases
the output span magnitude to 5 V. Biasing the external amplifier
with a 2.5 V offset from the reference voltage results in a full
4-quadrant multiplying circuit. The transfer equation of this circuit
shows that both negative and positive output voltages are created
as the input data (D) is incremented from code zero (V
–2.5 V) to midscale (V

VD VAD

=×(/ , –) ( )32 768 1 5543

OUT REF

VD VAD

=×(/, –) ( )16 384 1 5553

OUT REF

= 0 V) to full-scale (V

OUT

OUT

=

OUT

= +2.5 V).

(3)

(4)

For AD5543, the resistance tolerance becomes the dominant
error of which users should be aware.

R1 R2

10k0.01% 10k0.01%

C2

U4

1/2AD8620

–2.5 < V

V+

V–

O

+5V

–5V

< +2.5

V

O

+5V

ADR03

V

OUT

GND

+5V

U1

V

DD

V

V

IN

REF

GND

U3

AD5553 ONLY

5k0.01%

C1

R

FB

I

OUT

1/2AD8620

U2

R3

Figure 9. Four-Quadrant Multiplying Application Circuit

REV. A–8–

AD5543/AD5553

V

REF

V

DD

U2

U1

AD5543/AD5553

V

L

GND

I

OUT

R

FB

AD8628

AD8510

V+

V–

V

REF

LOAD

U3

V

DD

V

SS

R3
50

I

L

V

DD

C1

10pF

R3'
50

R2

15k

R1

150k

R2'

15k

R1'

150k

Programmable Current Source

Figure 10 shows a versatile V-I conversion circuit using an
improved Howland Current Pump. In addition to the precision
current conversion it provides, this circuit enables a bidirec­tional current flow and high voltage compliance. This circuit
can be used in 4 to 20 mA current transmitters with up to 500 Ω
of load. In Figure 10, it can be shown that if the resistor network is
matched, the load current is:

RRR

+

231

()

I

=

L REF

/

VD

3

××

R

(5)

R3 in theory can be made small to achieve the current needed
within the U3 output current driving capability. This circuit is
versatile such that AD8510 can deliver ±20 mA in both direc­tions and the voltage compliance approaches 15 V, which is
limited mainly by the supply voltages of U3. However, users
must pay attention to the compensation. Without C1, it can be
shown that the output impedance becomes:

131 2

'

Z

=

O

RR R R

12 3 1 2 3

''– '

RR R R R R

+

()

+

()

+

()

(6)

If the resistors are perfectly matched, ZO is infinite, which is
desirable, and behaves as an ideal current source. On the other
hand, if they are not matched, Z

can be either positive or nega-

O

tive. Negative can cause oscillation. As a result, C1 is needed to
prevent the oscillation. For critical applications, C1 could be
found empirically, but typically falls in the range of few pF.

REV. A

Figure 10. Programmable Current Source with Bidirec­tional Current Control and High Voltage Compliance
Capabilities

–9–

AD5543/AD5553

OUTLINE DIMENSIONS

8-Lead microSOIC Package [MSOP]

(RM-8)

Dimensions shown in millimeters

3.00
BSC

85

3.00
BSC

1

PIN 1

0.65 BSC

0.15

0.00

0.38

0.22

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-187AA

4

SEATING
PLANE

4.90
BSC

1.10 MAX

0.23

0.08



8



0

0.80

0.40

8-Lead Standard Small Outline Package [SOIC]

Narrow Body

(RN-8)

Dimensions shown in millimeters and (inches)

5.00 (0.1968)

4.80 (0.1890)

4.00 (0.1574)

3.80 (0.1497)

85

6.20 (0.2440)

5.80 (0.2284)

41

1.27 (0.0500)

0.25 (0.0098)

0.10 (0.0040)

COPLANARITY

0.10

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

BSC

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MS-012AA

1.75 (0.0688)

1.35 (0.0532)

0.51 (0.0201)

0.33 (0.0130)

0.25 (0.0098)

0.19 (0.0075)

0.50 (0.0196)

0.25 (0.0099)

8
0

1.27 (0.0500)

0.41 (0.0160)

 45

REV. A–10–

AD5543/AD5553

Revision History

Location Page

2/03—Data Sheet changed from REV. 0 to REV. A.

Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

REV. A

–11–

C02917–0–2/03(A)

–12–

PRINTED IN U.S.A.