Page 1
5 V, Serial-Input
SERIAL INPUT REGISTER
REF
CS
DIN
SCLK
AGND
V
OUT
V
DD
DGND
AD5541
16-BIT DAC
16-BIT DATA LATCH
CONTROL
LOGIC
SERIAL INPUT REGISTER
REFF
CS
DIN
SCLK
AGNDF
V
OUT
V
DD
DGND
AD5542
16-BIT DAC
16-BIT DATA LATCH
CONTROL
LOGIC
REFS
LDAC
AGNDS
RFB
INV
R
FB
R
INV
a
FEATURES
Full 16-Bit Performance
5 V Single Supply Operation
Low Power
Short Settling Time
Unbuffered Voltage Output Capable of Driving 60 k⍀
Loads Directly
SPI™/QSPI™/MICROWIRE™-Compatible Interface
Standards
Power-On Reset Clears DAC Output to 0 V (Unipolar
Mode)
Schmitt Trigger Inputs for Direct Optocoupler Interface
APPLICATIONS
Digital Gain and Offset Adjustment
Automatic Test Equipment
Data Acquisition Systems
Industrial Process Control
Voltage-Output, 16-Bit DACs
AD5541/AD5542
FUNCTIONAL BLOCK DIAGRAMS
GENERAL DESCRIPTION
The AD5541 and AD5542 are single, 16-bit, serial input,
voltage output DACs that operate from a single 5 V ± 10%
supply.
The AD5541 and AD5542 utilize a versatile 3-wire interface that
is compatible with SPI, QSPI, MICROWIRE, and DSP interface standards.
These DACs provide 16-bit performance without any adjustments. The DAC output is unbuffered, which reduces power
consumption and offset errors contributed to by an output buffer.
The AD5542 can be operated in bipolar mode generating a
±V
output swing. The AD5542 also includes Kelvin sense
REF
connections for the reference and analog ground pins to reduce
layout sensitivity.
The AD5541 and AD5542 are available in an SO package.
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corporation.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
PRODUCT HIGHLIGHTS
1. Single Supply Operation.
The AD5541 and AD5542 are fully specified and guaranteed
for a single 5 V ± 10% supply.
2. Low Power Consumption.
These parts consume typically 1.5 mW with a 5 V supply.
3. 3-Wire Serial Interface.
4. Unbuffered output capable of driving 60 kΩ loads.
This reduces power consumption as there is no internal buffer
to drive.
5. Power-On Reset circuitry.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 1999
Page 2
AD5541/AD5542–SPECIFICATIONS
(VDD = 5 V ⴞ 10%, V
TA = T
to T
MIN
MAX,
= 2.5 V, AGND = DGND = 0 V. All specifications
REF
unless otherwise noted.)
Parameter Min Typ Max Unit Test Condition
STATIC PERFORMANCE
Resolution 16 Bits
Relative Accuracy, INL ±0.5 ±1.0 LSB L, C Grades
±0.5 ±2.0 LSB B, J Grades
±0.5 ±4.0 LSB A Grade
Differential Nonlinearity ±0.5 ±1.0 LSB Guaranteed Monotonic
±1.5 LSB J Grade
Gain Error –1.5 ±5 LSB T
= 25°C
A
±7 LSB
Gain Error Temperature Coefficient ±0.1 ppm/°C
Zero Code Error 0.3 ±1 LSB T
= 25°C
A
±2 LSB
Zero Code Temperature Coefficient ±0.05 ppm/°C
AD5542
Bipolar Resistor Matching 1.000 Ω/Ω R
, Typically RFB = R
FB/RINV
= 28 kΩ
INV
±0.0015 ±0.0076 % Ratio Error
Bipolar Zero Offset Error ±1 ±5 LSB T
= 25°C
A
±7 LSB
Bipolar Zero Temperature Coefficient ±0.2 ppm/°C
OUTPUT CHARACTERISTICS
Output Voltage Range 0 V
–V
REF
Output Voltage Settling Time 1 µs to 1/2 LSB of FS, C
Slew Rate 25 V/µsC
– 1 LSB V Unipolar Operation
REF
V
– 1 LSB V AD5542 Bipolar Operation
REF
= 10 pF, Measured from 0% to 63%
L
= 10 pF
L
Digital-to-Analog Glitch Impulse 10 nV-s 1 LSB Change Around the Major Carry
Digital Feedthrough 10 nV-s All 1s Loaded to DAC, V
= 2.5 V
REF
DAC Output Impedance 6.25 kΩ Tolerance Typically 20%
Power Supply Rejection Ratio ±1.0 LSB ∆VDD ± 10%
DAC REFERENCE INPUT
Reference Input Range 2.0 V
Reference Input Resistance
2
9kΩ Unipolar Operation
DD
V
7.5 kΩ AD5542, Bipolar Operation
LOGIC INPUTS
Input Current ±1 µA
V
, Input Low Voltage 0.8 V
INL
, Input High Voltage 2.4 V
V
INH
Input Capacitance
Hysteresis Voltage
3
3
0.4 V
10 pF
REFERENCE
Reference –3 dB Bandwidth 1.3 MHz All 1s Loaded
Reference Feedthrough 1 mV p-p All 0s Loaded, V
= 1 V p-p at 100 kHz
REF
Signal-to-Noise Ratio 92 dB
Reference Input Capacitance 75 pF Code 0000 Hex
120 pF Code FFFF Hex
POWER REQUIREMENTS
V
DD
I
DD
4.50 5.50 V
0.3 1.1 mA
Power Dissipation 1.5 6.05 mW
NOTES
1
Temperature ranges are as follows: A, B, C Versions: –40°C to +85°C. J, L Versions: 0°C to 70°C.
2
Reference input resistance is code-dependent, minimum at 8555 hex.
3
Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
–2–
REV. A
Page 3
AD5541/AD5542
TIMING CHARACTERISTICS1,
Limit at T
MIN
, T
(VDD = 5 V ⴞ 5%, V
2
otherwise noted.)
MAX
= 2.5 V, AGND = DGND = 0 V. All specifications TA = T
REF
MIN
to T
MAX,
unless
Parameter All Versions Unit Description
f
SCLK
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
t
11
t
12
NOTES
1
Guaranteed by design. Not production tested.
2
Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are measured with tr = tf = 5␣ ns (10% to
90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
Specifications subject to change without notice.
25 MHz max SCLK Cycle Frequency
40 ns min SCLK Cycle Time
20 ns min SCLK High Time
20 ns min SCLK Low Time
15 ns min CS Low to SCLK High Setup
15 ns min CS High to SCLK High Setup
35 ns min SCLK High to CS Low Hold Time
20 ns min SCLK High to CS High Hold Time
15 ns min Data Setup Time
0 ns min Data Hold Time
30 ns min LDAC Pulsewidth
30 ns min CS High to LDAC Low Setup
30 ns min CS High Time Between Active Periods
t
1
SCLK
t
6
t
4
CS
DIN
LDAC*
t
12
t
8
t
9
DB15
*AD5542 ONLY. MAY BE TIED PERMANENTLY LOW IF REQUIRED.
t
2
t
3
DB0
t
5
t
7
t
11
t
10
REV. A
Figure 1. Timing Diagram
–3–
Page 4
AD5541/AD5542
WARNING!
ESD SENSITIVE DEVICE
ABSOLUTE MAXIMUM RATINGS*
(T
= 25°C unless otherwise noted)
A
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
Digital Input Voltage to DGND . . . . . –0.3 V to V
V
to AGND . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V
OUT
+ 0.3 V
DD
AGND, AGNDF, AGNDS to DGND . . . . . –0.3 V to +0.3 V
Input Current to Any Pin Except Supplies . . . . . . . . ±10 mA
Operating Temperature Range
Industrial (A, B, C Versions) . . . . . . . . . . . –40°C to +85°C
Commercial (J, L Versions) . . . . . . . . . . . . . . . 0°C to 70°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature, (T
Package Power Dissipation . . . . . . . . . . . . . (T
Thermal Impedance θ
JA
max) . . . . . . . . . 150°C
J
max – T
J
)/θ
A
JA
SOIC (SO-8) . . . . . . . . . . . . . . . . . . . . . . . . . . 149.5°C/W
SOIC (R-14) . . . . . . . . . . . . . . . . . . . . . . . . . . 104.5°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ORDERING GUIDE
Model INL DNL Temperature Range Package Description Package Option
AD5541CR ±1 LSB ±1 LSB –40°C to +85°C 8-Lead Small Outline IC SO-8
AD5541LR ±1 LSB ±1 LSB 0°C to 70°C 8-Lead Small Outline IC SO-8
AD5541BR ±2 LSB ±1 LSB –40°C to +85°C 8-Lead Small Outline IC SO-8
AD5541JR ±2 LSB ±1.5 LSB 0°C to 70°C 8-Lead Small Outline IC SO-8
AD5541AR ±4 LSB ±1 LSB –40°C to +85°C 8-Lead Small Outline IC SO-8
AD5542CR ±1 LSB ±1 LSB –40°C to +85°C 14-Lead Small Outline IC R-14
AD5542LR ±1 LSB ±1 LSB 0°C to 70°C 14-Lead Small Outline IC R-14
AD5542BR ±2 LSB ±1 LSB –40°C to +85°C 14-Lead Small Outline IC R-14
AD5542JR ±2 LSB ±1.5 LSB 0°C to 70°C 14-Lead Small Outline IC R-14
AD5542AR ±4 LSB ±1 LSB –40°C to +85°C 14-Lead Small Outline IC R-14
Die Size = 80 × 139 = 11,120 sq mil; Number of Transistors = 1,230.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD5541/AD5542 features proprietary ESD protection circuitry, permanent damage may occur
on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.
–4–
REV. A
Page 5
AD5541/AD5542
TOP VIEW
(Not to Scale)
14
13
12
11
10
9
8
1
2
3
4
5
6
7
NC = NO CONNECT
RFB
V
OUT
AGNDF
AGNDS
REFS
REFF
CS
V
DD
INV
DGND
LDAC
DIN
NC
SCLK
AD5542
AD5541 PIN FUNCTION DESCRIPTIONS
Mnemonic Pin No. Description
V
OUT
AGND 2 Ground Reference Point for Analog Circuitry.
REF 3 This is the voltage reference input for the DAC. Connect to external 2.5 V reference.
CS 4 This is a logic input signal. The chip select signal is used to frame the serial data input.
SCLK 5 Clock Input. Data is clocked into the input register on the rising edge of SCLK. Duty cycle
DIN 6 Serial Data Input. This device accepts 16-bit words. Data is clocked into the input register on
DGND 7 Digital Ground. Ground reference for digital circuitry.
V
DD
1 Analog Output Voltage from the DAC.
Reference can range from 2 V to V
DD
.
must be between 40% and 60%.
the rising edge of SCLK.
8 Analog Supply Voltage, 5 V ± 10%.
AD5541 PIN CONFIGURATION
SOIC
V
OUT
AGND
REF
1
2
AD5541
TOP VIEW
3
(Not to Scale)
4
8
7
6
5
V
DD
DGND
DIN
SCLKCS
AD5542 PIN CONFIGURATION
SOIC
AD5542 PIN FUNCTION DESCRIPTIONS
Mnemonic Pin No. Description
RFB 1 Feedback Resistor. In bipolar mode connect this pin to external op amp output.
V
OUT
2 Analog Output Voltage from the DAC.
AGNDF 3 Ground Reference Point for Analog Circuitry (Force).
AGNDS 4 Ground Reference Point for Analog Circuitry (Sense).
REFS 5 This is the voltage reference input (sense) for the DAC. Connect to external 2.5 V reference.
Reference can range from 2 V to V
DD
.
REFF 6 This is the voltage reference input (force) for the DAC. Connect to external 2.5 V reference.
Reference can range from 2 V to V
DD
.
CS 7 This is a logic input signal. The chip select signal is used to frame the serial data input.
SCLK 8 Clock input. Data is clocked into the input register on the rising edge of SCLK. Duty cycle
must be between 40% and 60%.
NC 9 No Connect.
DIN 10 Serial Data Input. This device accepts 16-bit words. Data is clocked into the input register on
the rising edge of SCLK.
LDAC 11 LDAC Input. When this input is taken low, the DAC register is simultaneously updated with
the contents of the input register.
DGND 12 Digital Ground. Ground reference for digital circuitry.
INV 13 Connected to the Internal Scaling Resistors of the DAC. Connect INV pin to external op amps
V
DD
REV. A
14 Analog Supply Voltage, 5 V ± 10%.
inverting input in bipolar mode.
–5–
Page 6
AD5541/AD5542
TERMINOLOGY
Relative Accuracy
For the DAC, relative accuracy or integral nonlinearity (INL)
is a measure of the maximum deviation, in LSBs, from a straight
line passing through the endpoints of the DAC transfer function.
A typical INL versus code plot can be seen in Figure 2.
Differential Nonlinearity
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ±1 LSB maximum
ensures monotonicity. Figure 3 illustrates a typical DNL versus
code plot.
Gain Error
Gain error is the difference between the actual and ideal analog
output range, expressed as a percent of the full-scale range.
It is the deviation in slope of the DAC transfer characteristic
from ideal.
Gain Error Temperature Coefficient
This is a measure of the change in gain error with changes in
temperature. It is expressed in ppm/°C.
Zero Code Error
Zero code error is a measure of the output error when zero code
is loaded to the DAC register.
Zero Code Temperature Coefficient
This is a measure of the change in zero code error with a change
in temperature. It is expressed in mV/°C.
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV-s
and is measured when the digital input code is changed by 1 LSB
at the major carry transition. A plot of the glitch impulse is shown
in Figure 15.
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into the
analog output of the DAC from the digital inputs of the DAC,
but is measured when the DAC output is not updated. CS is
held high, while the CLK and DIN signals are toggled. It is
specified in nV-s and is measured with a full-scale code change
on the data bus, i.e., from all 0s to all 1s and vice versa. A typical plot of digital feedthrough is shown in Figure 14.
Power Supply Rejection Ratio
This specification indicates how the output of the DAC is affected
by changes in the power supply voltage. Power-supply rejection
ratio is quoted in terms of % change in output per % change in
for full-scale output of the DAC. V
V
DD
Reference Feedthrough
This is a measure of the feedthrough from the V
is varied by ±10%.
DD
input to the
REF
DAC output when the DAC is loaded with all 0s. A 100 kHz,
1 V p-p is applied to V
. Reference feedthrough is expressed
REF
in mV p-p.
–6–
REV. A
Page 7
CODE
0
655368192 16384 24576 32768 40960 49152 57344
VDD = 5V
V
REF
= 2.5V
0.50
0.25
0
–0.25
–0.50
DIFFERENTIAL NONLINEARITY – LSB
TEMPERATURE – 8C
–60 100–40 –20 0 20 40 60 80
0
–0.25
120 140
–0.50
0.25
0.50
0.75
DIFFERENTIAL NONLINEARITY – LSB
VDD = 5V
V
REF
= 2.5V
Typical Performance Characteristics–
0.50
VDD = 5V
V
= 2.5V
REF
0.25
0
–0.25
–0.50
INTEGRAL NONLINEARITY – LSB
–0.75
0
Figure 2. Integral Nonlinearity vs. Code
0.25
VDD = 5V
= 2.5V
V
REF
0
CODE
AD5541/AD5542
655368192 16384 24576 32768 40960 49152 57344
Figure 5. Differential Nonlinearity vs. Code
–0.25
–0.50
–0.75
INTEGRAL NONLINEARITY – LSB
–1.00
–60 100–40 –20 0 20 40 60 80
TEMPERATURE – 8C
120 140
Figure 3. Integral Nonlinearity vs. Temperature
0.50
V
= 2.5V
REF
= 258C
T
A
0.25
0
–0.25
LINEARITY ERROR – LSB
–0.50
–0.75
273456
DNL
INL
SUPPLY VOLTAGE – V
Figure 4. Linearity Error vs. Supply Voltage
Figure 6. Differential Nonlinearity vs. Temperature
0.75
VDD = 5V
T
= 258C
A
0.50
0.25
0
LINEARITY ERROR – LSB
–0.25
–0.50
10
23456
REFERENCE VOLTAGE – V
DNL
INL
Figure 7. Linearity Error vs. Reference Voltage
REV. A
–7–
Page 8
AD5541/AD5542
0
VDD = 5V
V
REF
–0.25
–0.50
GAIN ERROR – LSB
–0.75
–60 140
–20–40 20 40 60 80 100 120
0
TEMPERATURE – 8C
Figure 8. Gain Error vs. Temperature
250
VDD = 5V
V
= 5V
LOGIC
= 2.5V
V
REF
A
m
200
SUPPLY CURRENT –
= 2.5V
0.75
VDD = 5V
V
= 2.5V
REF
0.50
0.25
ZERO-CODE ERROR – LSB
0
–60 140
–20–40 20 40 60 80 100 120
0
TEMPERATURE – 8C
Figure 11. Zero-Code Error vs. Temperature
450
TA = 258C
400
A
m
350
300
250
SUPPLY CURRENT –
200
REFERENCE
VOLTAGE
VDD = 5V
SUPPLY
VOLTAGE
V
= 2.5V
REF
150
0
–20–40 20 40 60 80 100 120
TEMPERATURE – 8C
Figure 9. Supply Current vs. Temperature
400
VDD = 5V
V
= 2.5V
REF
350
= 258C
T
A
A
m
300
250
SUPPLY CURRENT –
200
150
1
2045
DIGITAL INPUT VOLTAGE – V
3
Figure 10. Supply Current vs. Digital Input Voltage
150
1
20456
3
VOLTAGE – V
Figure 12. Supply Current vs Reference Voltage or Supply
Voltage
300
250
A
m
0555H
200
150
REFERENCE CURRENT –
100
50
8192
5555H
163840 32768 40960 49152 57344 65536
8555H
BIPOLAR MODE
UNIPOLAR MODE
24576
CODE
VDD = 5V
V
= 2.5V
REF
= 258C
T
A
Figure 13. Reference Current vs. Code
–8–
REV. A
Page 9
100
90
0%
10
V
REF
= 2.5V
V
DD
= 5V
T
A
= 258C
10pF
50pF
200pF
100pF
2µs/DIV
CS (5V/DIV)
V
OUT
(0.5V/DIV)
100
CLOCK (5V/DIV)
90
V
(50mV/DIV)
OUT
10
0%
2ms/DIV
V
REF
V
DD
T
A
= 2.5V
= 5V
= 258C
AD5541/AD5542
Figure 14. Digital Feedthrough
100
90
V
10
0%
CS (5V/DIV)
(0.1V/DIV)
OUT
2µs/DIV
REF
V
DD
T
A
= 5V
= 258C
100
90
10
0%
V
= 2.5V
Figure 15. Digital-to-Analog Glitch Impulse
GENERAL DESCRIPTION
The AD5541/AD5542 are single, 16-bit, serial input, voltage
output DACs. They operate from a single supply ranging from
2.7 V to 5 V and consume typically 300 mA with a supply of
5 V. Data is written to these devices in a 16-bit word format, via
With this type of DAC configuration, the output impedance
is independent of code, while the input impedance seen by
the reference is heavily code dependent. The output voltage
is dependent on the reference voltage as shown in the follow-
ing equation.
a 3- or 4-wire serial interface. To ensure a known power-up state,
these parts were designed with a power-on reset function. In unipolar mode, the output is reset to 0 V, while in bipolar mode, the
AD5542 output is set to –V
the reference and analog ground are included on the AD5542.
Digital-to-Analog Section
. Kelvin sense connections for
REF
where D is the decimal data word loaded to the DAC register
and N is the resolution of the DAC. For a reference of 2.5 V,
the equation simplifies to the following.
The DAC architecture consists of two matched DAC sections.
A simplified circuit diagram is shown in Figure 18. The DAC
architecture of the AD5541/AD5542 is segmented. The four
MSBs of the 16-bit data word are decoded to drive 15 switches,
E1 to E15. Each of these switches connects one of 15 matched
resistors to either AGND or V
. The remaining 12 bits of the
REF
data word drive switches S0 to S11 of a 12-bit voltage mode
R-2R ladder network.
R
V
REF
REV. A
2R 2R 2R
S0 S1
12-BIT R-2R LADDER FOUR MSB's DECODED INTO
Figure 18. DAC Architecture
R
2R 2R 2R 2R
S11
E1 E2 E15
15 EQUAL SEGMENTS
V
OUT
giving a V
full-scale loaded to the DAC.
The LSB size is V
Serial Interface
The AD5541 and AD5542 are controlled by a versatile 3-wire
serial interface, which operates at clock rates up to 25 MHz and
is compatible with SPI, QSPI, MICROWIRE, and DSP interface
standards. The timing diagram can be seen in Figure 1. Input
data is framed by the chip select input, CS. After a high-to-low
transition on CS, data is shifted synchronously and latched into
the input register on the rising edge of the serial clock, SCLK.
Data is loaded MSB first in 16-bit words. After 16 data bits
have been loaded into the serial input register, a low-to-high
transition on CS transfers the contents of the shift register to the
DAC. Data can only be loaded to the part while CS is low.
–9–
Figure 16. Large Signal Settling Time
V
= 2.5V
REF
V
= 5V
DD
T
A
= 258C
0.5ms/DIV
V
(1V/DIV)
OUT
V
(50mV/DIV)
OUT
GAIN = –216
1LSB = 8.2mV
Figure 17. Small Signal Settling Time
VD
×
V
OUT
V
OUT
of 1.25 V with midscale loaded, and 2.5 V with
OUT
/65,536.
REF
REF
=
N
2
D
×25
=
65 536.,
Page 10
AD5541/AD5542
The AD5542 has an LDAC function that allows the DAC latch
to be updated asynchronously by bringing LDAC low after CS
goes high. LDAC should be maintained high while data is written
to the shift register. Alternatively, LDAC may be tied permanently
low to update the DAC synchronously. With LDAC tied perma-
nently low, the rising edge of CS will load the data to the DAC.
Unipolar Output Operation
These DACs are capable of driving unbuffered loads of 60 kΩ.
Unbuffered operation results in low-supply current, typically
300 µA, and a low-offset error. The AD5541 provides a unipolar
output swing ranging from 0 V to V
configured to output both unipolar and bipolar voltages. Figure
19 shows a typical unipolar output voltage circuit. The code
table for this mode of operation is shown in Table I.
SERIAL
INTERFACE
* AD5542 ONLY
+5V +2.5V
0.1mF
V
CS
DIN
SCLK
LDAC*
REF(REFF*)
DD
AD5541/AD5542
DGND
10mF
0.1mF
REFS*
AGND
Figure 19. Unipolar Output
Table I. Unipolar Code Table
DAC Latch Contents
MSB LSB Analog Output
1111 1111 1111 1111 V
1000 0000 0000 0000 V
0000 0000 0000 0001 V
× (65,535/65,536)
REF
× (32,768/65,536) = 1/2 V
REF
× (1/65,536)
REF
0000 0000 0000 0000 0 V
Assuming a perfect reference, the worst case output voltage may
be calculated from the following equation.
Unipolar Mode Worst-Case Output
V
OUT UNI REF GE ZSE–
D
V V V INL
()=× +++
16
2
where
V
OUT–UNI
= Unipolar Mode Worst-Case Output
D = Code Loaded to DAC
V
REF
V
GE
V
ZSE
= Reference Voltage Applied to Part
= Gain Error in Volts
= Zero Scale Error in Volts
INL = Integral Nonlinearity in Volts
Bipolar Output Operation
With the aid of an external op amp, the AD5542 may be configured to provide a bipolar voltage output. A typical circuit of
such operation is shown in Figure 20. The matched bipolar offset resistors R
and R
FB
are connected to an external op amp to
INV
achieve this bipolar output swing, typically R
Table II shows the transfer function for this output operating
mode. Also provided on the AD5542 are a set of Kelvin connections to the analog ground inputs.
. The AD5542 can be
REF
AD820/
OUT
OP196
EXTERNAL
OP AMP
FB
= R
UNIPOLAR
INV
OUTPUT
REF
= 28 kΩ.
+2.5V
10mF
0.1mF
RFB
REFSREFF
R
R
INV
AD5541/AD5542
AGNDSAGNDF
+5V
FB
INV
–5V
BIPOLAR
OUTPUT
OUT
EXTERNAL
OP AMP
SERIAL
INTERFACE
0.1mF
+5V
V
CS
DIN
SCLK
LDAC
DGND
DD
Figure 20. Bipolar Output (AD5542 Only)
Table II. Bipolar Code Table
DAC Latch Contents
MSB LSB Analog Output
1111 1111 1111 1111 +V
1000 0000 0000 0001 +V
× (32,767/32,768)
REF
× (1/32,768)
REF
1000 0000 0000 0000 0 V
0111 1111 1111 1111 –V
0000 0000 0000 0000 –V
× (1/32,768)
REF
× (32,768/32,768) = –V
REF
REF
Assuming a perfect reference, the worst-case bipolar output
voltage may be calculated from the following equation.
Bipolar Mode Worst-Case Output
V
OUT BIP
VVRDVRD
()
OUT UNI OS REF
[]
=
–
–
+
21
()
12
++
()
+
RD A
–
+
()
/
where
V
= External Op Amp Input Offset Voltage
OS
RD = RFB and RIN Resistor Matching Error
A = Op Amp Open-Loop Gain
Output Amplifier Selection
For bipolar mode, a precision amplifier should be used, supplied
from a dual power supply. This will provide the ±V
REF
output.
In a single-supply application, selection of a suitable op amp
may be more difficult as the output swing of the amplifier does
not usually include the negative rail, in this case AGND. This
can result in some degradation of the specified performance
unless the application does not use codes near zero.
The selected op amp needs to have very low-offset voltage, (the
DAC LSB is 38 µV with a 2.5 V reference), to eliminate the
need for output offset trims. Input bias current should also be
very low as the bias current multiplied by the DAC output
impedance (approximately 6K) will add to the zero code error.
Rail-to-rail input and output performance is required. For fast
settling, the slew rate of the op amp should not impede the
settling time of the DAC. Output impedance of the DAC is
constant and code-independent, but in order to minimize gain
errors, the input impedance of the output amplifier should be
as high as possible. The amplifier should also have a 3 dB bandwidth of 1 MHz or greater. The amplifier adds another time
constant to the system, hence increasing the settling time of the
output. A higher 3 dB amplifier bandwidth results in a shorter
effective settling time of the combined DAC and amplifier.
Force Sense Amplifier Selection
These amplifiers will be single-supply, low-noise amplifiers. A
low-output impedance at high frequencies is preferred as they
need to be able to handle dynamic currents of up to ±20 mA.
–10–
REV. A
Page 11
AD5541/AD5542
Reference and Ground
As the input impedance is code-dependent, the reference pin
should be driven from a low-impedance source. The AD5541/
AD5542 operates with a voltage reference ranging from 2 V to
. References below 2 V will result in reduced accuracy.
V
DD
The DAC’s full-scale output voltage is determined by the
reference. Tables I and II outline the analog output voltage
or particular digital codes. For optimum performance, Kelvin
sense connections are provided on the AD5542.
If the application doesn’t require separate force and sense lines,
they should be tied together close to the package to minimize
voltage drops between the package leads and the internal die.
Power-On Reset
These parts have a power-on reset function to ensure the output
is at a known state upon power-up. On power-up, the DAC
register contains all zeros, until data is loaded from the serial
register. However, the serial register is not cleared on power-up,
so its contents are undefined. When loading data initially to the
DAC, 16 bits or more should be loaded to prevent erroneous
data appearing on the output. If more than 16 bits are loaded,
the last 16 are kept, and if less than 16 are loaded, bits will remain
from the previous word. If the AD5541/AD5542 needs to be
interfaced with data shorter than 16 bits, the data should be
padded with zeros at the LSBs.
Power Supply and Reference Bypassing
For accurate high-resolution performance, it is recommended that
the reference and supply pins be bypassed with a 10 µF tantalum
capacitor in parallel with a 0.1 µF ceramic capacitor.
MICROPROCESSOR INTERFACING
Microprocessor interfacing to the AD5541/AD5542 is via a
serial bus that uses standard protocol compatible with DSP
processors and microcontrollers. The communications channel
requires a 3-wire interface consisting of a clock signal, a data
signal and a synchronization signal. The AD5541/AD5542
requires a 16-bit data word with data valid on the rising edge of
SCLK. The DAC update may be done automatically when all
the data is clocked in or it may be done under control of LDAC
(AD5542 only).
AD5541/AD5542–ADSP-2101/ADSP-2103 Interface
Figure 21 shows a serial interface between the AD5541/AD5542
and the ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103
should be set to operate in the SPORT transmit alternate framing
mode. The ADSP-2101/ADSP-2103 is programmed through the
SPORT control register and should be configured as follows:
Internal Clock Operation, Active Low Framing, 16-Bit Word
Length. Transmission is initiated by writing a word to the Tx register after the SPORT has been enabled. As the data is clocked out
on each rising edge of the serial clock, an inverter is required
between the DSP and the DAC, because the AD5541/AD5542
clocks data in on the falling edge of the SCLK.
FO
ADSP-2101/
ADSP-2103*
*ADDITIONAL PINS OMITTED FOR CLARITY.
**AD5542 ONLY
TFS
DT
SCLK
LDAC**
CS
DIN
SCLK
AD5541/
AD5542*
Figure 21. AD5541/AD5542 to ADSP-2101/ADSP-2103
Interface
AD5541/AD5542 to 68HC11 Interface
Figure 22 shows a serial interface between the AD5541/AD5542
and the 68HC11 microcontroller. SCK of the 68HC11 drives
the SCLK of the DAC, while the MOSI output drives the
serial data lines SDIN. CS signal is driven from one of the
port lines. The 68HC11 is configured for master mode; MSTR
= 1, CPOL = 0, and CPHA = 0. Data appearing on the MOSI
output is valid on the rising edge of SCK.
PC6
68HC11/
68L11*
*ADDITIONAL PINS OMITTED FOR CLARITY.
**AD5542 ONLY
PC7
MOSI
SCK
LDAC**
CS
DIN
SCLK
AD5541/
AD5542*
Figure 22. AD5541/AD5542 to 68HC11/68L11 Interface
AD5541/AD5542 to MICROWIRE Interface
Figure 23 shows an interface between the AD5541/AD5542 and
any MICROWIRE-compatible device. Serial data is shifted out
on the falling edge of the serial clock and into the AD5541/
AD5542 on the rising edge of the serial clock. No glue logic is
required as the DAC clocks data into the input shift register on
the rising edge.
MICROWIRE*
*ADDITIONAL PINS OMITTED FOR CLARITY.
CS
SO
SCLK
CS
DIN
SCLK
AD5541/
AD5542*
Figure 23. AD5541/AD5542 to MICROWIRE Interface
AD5541/AD5542 to 80C51/80L51 Interface
A serial interface between the AD5541/AD5542 and the 80C51/
80L51 microcontroller is shown in Figure 24. TxD of the
microcontroller drives the SCLK of the AD5541/AD5542, while
RxD drives the serial data line of the DAC. P3.3 is a bit programmable pin on the serial port which is used to drive CS.
The 80C51/80L51 provides the LSB first, while the AD5541/
AD5542 expects the MSB of the 16-bit word first. Care should
be taken to ensure the transmit routine takes this into account.
When data is to be transmitted to the DAC, P3.3 is taken low.
Data on RxD is valid on the falling edge of TxD, so the clock must
be inverted as the DAC clocks data into the input shift register on the rising edge of the serial clock. The 80C51/80L51
transmits its data in 8-bit bytes with only eight falling clock
edges occurring in the transmit cycle. As the DAC requires a
16-bit word, P3.3 must be left low after the first eight bits are
transferred, and brought high after the second byte is transferred. LDAC on the AD5542 may also be controlled by
the 80C51/80L51 serial port output by using another bit
programmable pin, P3.4.
P3.4
80C51/
80L51*
*ADDITIONAL PINS OMITTED FOR CLARITY.
**AD5542 ONLY
P3.3
RxD
TxD
LDAC**
CS
DIN
SCLK
AD5541/
AD5542*
Figure 24. AD5541/AD5542 to 80C51/80L51 Interface
REV. A
–11–
Page 12
AD5541/AD5542
APPLICATIONS
Optocoupler interface
The digital inputs of the AD5541/AD5542 are Schmitttriggered, so they can accept slow transitions on the digital input
lines. This makes these parts ideal for industrial applications
where it may be necessary that the DAC is isolated from the
controller via optocouplers. Figure 25 illustrates such an interface.
5V
POWER
SCLK
10kV
REGULATOR
V
DD
V
DD
SCLK
10mF
V
DD
0.1mF
AD5541/AD5542
10kV
CS
10kV
DIN
CS
V
DD
DIN
GND
V
OUT
Figure 25. AD5541/AD5542 in an Optocoupler Interface
Decoding Multiple AD5541/AD5542s
The CS pin of the AD5541/AD5542 can be used to select one
of a number of DACs. All devices receive the same serial clock
and serial data, but only one device will receive the CS signal at
any one time. The DAC addressed will be determined by the
decoder. There will be some digital feedthrough from the digital
input lines. Using a burst clock will minimize the effects of digital feedthrough on the analog signal channels. Figure 26 shows a
typical circuit.
SCLK
DIN
ENABLE
CODED
ADDRESS
EN
V
DD
DECODER
DGND
AD5541/AD5542
CS
DIN
SCLK
AD5541/AD5542
CS
DIN
SCLK
AD5541/AD5542
CS
DIN
SCLK
AD5541/AD5542
CS
DIN
SCLK
V
OUT
V
OUT
V
OUT
V
OUT
C3713–8–10/99
0.1574 (4.00)
0.1497 (3.80)
PIN 1
0.0098 (0.25)
0.0040 (0.10)
SEATING
0.1 968 (5.00)
0.1 890 (4.80)
85
0.0500 (1.27)
PLANE
0.2440 (6.20)
0.2284 (5.80)
41
BSC
0.0192 (0.49)
0.0138 (0.35)
8-Lead SO
(SO-8)
0.0688 (1.75)
0.0532 (1.35)
0.0098 (0.25)
0.0075 (0.19)
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
0.1574 (4.00)
0.1497 (3.80)
0.0196 (0.50)
0.0099 (0.25)
88
0.0500 (1.27)
08
0.0160 (0.41)
3 458
Figure 26. Addressing Multiple AD5541/AD5542s
14-Lead SO
(R-14)
0.3444 (8.75)
0.3367 (8.55)
14
PIN 1
0.0098 (0.25)
0.0040 (0.10)
1
0.050 (1.27)
BSC
8
7
0.0688 (1.75)
0.0532 (1.35)
0.0192 (0.49)
0.0138 (0.35)
0.2440 (6.20)
0.2284 (5.80)
SEATING
PLANE
0.0099 (0.25)
0.0075 (0.19)
0.0196 (0.50)
0.0099 (0.25)
88
08
0.0500 (1.27)
0.0160 (0.41)
3 458
PRINTED IN U.S.A.
–12–
REV. A
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