Datasheet AD5533 Datasheet (Analog Devices)

32-Channel Infinite

a

FEATURES
Infinite Sample-and-Hold Capability to ⴞ0.018% Accuracy
High Integration: 32-Channel SHA in 12 ⴛ 12 mm
Per Channel Acquisition Time of 16 ␮s max
Adjustable Voltage Output Range
Output Voltage Span 10 V
Output Impedance 0.5 ⍀
Readback Capability
DSP-/Microcontroller-Compatible Serial Interface
Parallel Interface
Temperature Range –40ⴗC to +85ⴗC

APPLICATIONS
Level Setting
Instrumentation
Automatic Test Equipment
Industrial Control Systems
Data Acquisition
Low Cost I/O

2

LFBGA

Sample-and-Hold

AD5533*

GENERAL DESCRIPTION

The AD5533 combines a 32-channel voltage translation function
with an infinite output hold capability. An analog input voltage
on the common input pin, V
sentation transferred to a chosen DAC register. V
DAC is then updated to reflect the new contents of the DAC
register. Channel selection is accomplished via the parallel address
inputs A0–A4 or via the serial input port. The output voltage
range is determined by the offset voltage at the OFFS_IN pin
and the gain of the output amplifier. It is restricted to a range
from V

+ 2 V to VDD – 2 V because of the headroom of the

SS

output amplifier.

The device is operated with AV

5.25 V, V

= –4.75 V to –16.5 V and VDD = 8 V to 16.5 V and

SS

requires a stable 3 V reference on REF_IN as well as an offset
voltage on OFFS_IN.

PRODUCT HIGHLIGHTS

1. Infinite Droopless Sample-and-Hold Capability.

2. The AD5533 is available in a 74-lead LFBGA package with a

body size of 12 mm × 12 mm.

, is sampled and its digital repre-

IN

= 5 V ± 5%, DVCC = 2.7 V to

CC

OUT

for this

FUNCTIONAL BLOCK DIAGRAM

DV

AV

CC

V

IN

TRACK /RESET

BUSY

GND

DAC

AGND

DGND

SER / PAR

*Protected by U.S. Patent No. 5,969,657; other patents pending.

AD5533

SCLK

ADC

INTERFACE

CONTROL

LOGIC

DIND

REF IN REF OUT

CC

OUT

DAC

DAC

DAC

SYNC/ CS

OFFS IN

ADDRESS INPUT REGISTER

A4– A0

CAL

VDDV

OFFSET SEL

SS

V

0

OUT

V

31

OUT

OFFS OUT

WR

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 2000

(VDD = 8 V to 16.5 V, VSS = –4.75 V to –16.5 V; AVCC = 4.75 V to 5.25 V; DVCC = 2.7 V

AD5533–SPECIFICATIONS

V

+ 2 V to VDD – 2 V. All outputs unloaded. All specifications T

SS

Parameter

1

to 5.25 V; AGND = DGND = DAC_GND = 0 V; REF_IN = 3 V; Output Range from

to T

MIN

A Version

unless otherwise noted.)

MAX

2

Unit Conditions/Comments

ANALOG CHANNEL

V

IN

to V

Nonlinearity ±0.018 % max Input Range 100 mV to 2.96 V

OUT

±0.006 % typ After Gain and Offset Adjustment

Gain 3.46/3.6 min/max 3.52 typ
Offset Error ±50 mV max

ANALOG INPUT (V

)

IN

Input Voltage Range 0 to 3 V Nominal Input Range
Input Lower Deadband 70 mV max 50 mV typ. Referred to V

See Figure 5

Input Upper Deadband 40 mV max 12 mV typ. Referred to V

See Figure 5

Input Current 1 µA max 100 nA typ. V

One Channel

Input Capacitance

3

20 pF typ

Being Acquired on

IN

ANALOG INPUT (OFFS_IN)

Input Current 1 µA max 100 nA typ

VOLTAGE REFERENCE

REF_IN

Nominal Input Voltage 3.0 V
Input Voltage Range

3

2.85/3.15 V min/max

Input Current 1 µA max <1 nA typ

REF_OUT

Output Voltage 3 V typ
Output Impedance
Reference Temperature Coefficient

ANALOG OUTPUTS (V

Output Temperature Coefficient

3

3

0–31)

OUT

3, 4

280 kΩ typ
60 ppm/°C typ

20 ppm/°C typ

DC Output Impedance 0.5 Ω typ
Output Range V
Resistive Load
Capacitive Load
Short-Circuit Current
DC Power Supply Rejection Ratio

DC Crosstalk

ANALOG OUTPUT (OFFS_OUT)

Output Temperature Coefficient
DC Output Impedance

3, 5

3, 5

3

3

3

3, 4

3

+ 2 /VDD – 2 V min/max 100 µA Output Load

SS

5kΩ min
500 pF max
10 mA typ
–70 dB typ VDD = +15 V ± 5%
–70 dB typ V

= –15 V ± 5%

SS

250 µV max

20 ppm/°C typ

1.3 kΩ typ

Output Range 50 to REF_IN – 12 mV typ
Output Current 10 µA max Source Current
Capacitive Load 100 pF max

DIGITAL INPUTS

3

Input Current ±10 µA max 5 µA typ
Input Low Voltage 0.8 V max DV

0.4 V max DV

Input High Voltage 2.4 V min DV

2.0 V min DV

= 5 V ± 5%

CC

= 3 V ± 10%

CC

= 5 V ± 5%

CC

= 3 V ± 10%

CC

Input Hysteresis (SCLK and CS Only) 200 mV typ
Input Capacitance 10 pF max

DIGITAL OUTPUTS (BUSY, DOUT)

3

Output Low Voltage 0.4 V max DVCC = 5 V. Sinking 200 µA
Output High Voltage 4.0 V min DV
Output Low Voltage 0.4 V max DV
Output High Voltage 2.4 V min DV
High Impedance Leakage Current ±1 µA max D
High Impedance Output Capacitance 15 pF typ D

= 5 V. Sourcing 200 µA

CC

= 3 V. Sinking 200 µA

CC

= 3 V. Sourcing 200 µA

CC

Only

OUT

Only

OUT

.

IN

.

IN

–2–

REV. 0

AD5533

Parameter

1

A Version

2

Unit Conditions/Comments

POWER REQUIREMENTS

Power-Supply Voltages

V

DD

V

SS

AV

CC

DV

CC

Power-Supply Currents

I

DD

I

SS

AI

CC

DI

CC

Power Dissipation

NOTES

1

See Terminology.

2

A Version: Industrial temperature range –40°C to +85°C; typical at +25°C.

3

Guaranteed by design and characterization, not production tested.

4

AD780 as reference for the AD5533.

5

Ensure that you do not exceed TJ (max). See maximum ratings.

6

Outputs unloaded.

Specifications subject to change without notice.

6

6

8/16.5 V min/max
–4.75/–16.5 V min/max

4.75/5.25 V min/max

2.7/5.25 V min/max

15 mA max 10 mA typ. All Channels Full Scale
15 mA max 10 mA typ. All Channels Full Scale
33 mA max 26 mA typ

1.5 mA max 1 mA typ
280 mW typ VDD = +10 V, VSS = –5 V

(VDD = 8 V to 16.5 V, VSS = –4.75 V to –16.5 V; AVCC = 4.75 V to 5.25 V; DVCC = 2.7 V to 5.25 V; AGND =

AC CHARACTERISTICS

All specifications T

Parameter A Version

Output Settling Time
Acquisition Time 16 µs max
OFFS_IN Settling Time
Digital Feedthrough
Output Noise Spectral Density @ 1 kHz
AC Crosstalk

NOTES

1

A version: Industrial temperature range –40°C to +85°C; typical at 25°C.

2

Guaranteed by design and characterization, not production tested

Specifications subject to change without notice.

to T

MIN

2

unless otherwise noted.)

MAX

2

2

2

DGND = DAC_GND = 0 V; REF_IN = 3 V; Output Range from V

1

Unit Conditions/Comments

3 µs max

10 µs max 500 pF, 5 kΩ Load; 0 V–3 V Step

2

0.2 nV-s typ
400 nV/(√Hz) typ
5 nV-s typ

+ 2 V to VDD – 2 V. All outputs unloaded.

SS

REV. 0

–3–

AD5533

TIMING CHARACTERISTICS

PARALLEL INTERFACE

Parameter

t

1

t

2

t

3

t

4

t

5

t

6

NOTES

1

See Interface Timing Diagram.

2

Guaranteed by design and characterization, not production tested.

Specifications subject to change without notice.

1, 2

Limit at T
(A Version) Unit Conditions/Comments

0 ns min CS to WR Setup Time
0 ns min CS to WR Hold Time
50 ns min CS Pulsewidth Low
50 ns min WR Pulsewidth Low
20 ns min A4–A0, CAL, OFFS_SEL to WR Setup Time
0 ns min A4–A0, CAL, OFFS_SEL to WR Hold Time

SERIAL INTERFACE

Parameter

f

CLKIN

t

1

t

2

t

3

t

4

t

5

t

6

t

7

3

t

8

3

t

9

t

10

NOTES

1

See Serial Interface Timing Diagrams.

2

Guaranteed by design and characterization, not production tested.

3

These numbers are measured with the load circuit of Figure 2.

Specifications subject to change without notice.

1, 2

Limit at T
(A Version) Unit Conditions/Comments

20 MHz max SCLK Frequency
20 ns min SCLK High Pulsewidth
20 ns min SCLK Low Pulsewidth
10 ns min SYNC Falling Edge to SCLK Falling Edge Setup Time
50 ns min SYNC Low Time
10 ns min DIN Setup Time
5 ns min DIN Hold Time
5 ns min SYNC Falling Edge to SCLK Rising Edge Setup Time
20 ns max SCLK Rising Edge to D
60 ns max SCLK Falling Edge to D
400 ns min 10th SCLK Falling Edge to SYNC Falling Edge for Readback

MIN

MIN

, T

, T

MAX

MAX

Valid

OUT

High Impedance

OUT

PARALLEL INTERFACE TIMING DIAGRAM

CS

WR

A4– A0, CAL,

SEL

OFFS

Figure 1. Parallel Write (SHA Mode Only)

–4–

200␮A

TO

OUTPUT

PIN

C

L

50pF

200␮A

Figure 2. Load Circuit for D

I

OL

1.6V

I

OH

Timing Specifications

OUT

REV. 0

SERIAL INTERFACE TIMING DIAGRAMS

12345678910

t

1

t

2

t

3

t

4

t

5

t

6

MSB LSB

SCLK

SYNC

D

IN

Figure 3. 10-Bit Write (SHA Mode and Both Readback Modes)

t

1

SCLK

SYNC

D

OUT

10

t

7

t

10

2

13456789

t

2

t

4

MSB

t

8

AD5533

10

11

12 13 14

t

9

LSB

Figure 4. 14-Bit Read (Both Readback Modes)

REV. 0

–5–

AD5533

ABSOLUTE MAXIMUM RATINGS

(TA = 25°C unless otherwise noted)

VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +17 V

V

to AGND . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –17 V

SS

AV

to AGND, DAC_GND . . . . . . . . . . . . . –0.3 V to +7 V

CC

to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

DV

CC

Digital Inputs to DGND . . . . . . . . . . –0.3 V to DV

Digital Outputs to DGND . . . . . . . . . –0.3 V to DV

REF_IN to AGND, DAC_GND . . . . . . . . . . . –0.3 V to +7 V

to AGND, DAC_GND . . . . . . . . . . . . . . . –0.3 V to +7 V

V

IN

V

0–31 to AGND . . . . . . . . . . VSS – 0.3 V to V

OUT

0–31 toVSS . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +24 V

V

OUT

OFFS_IN to AGND . . . . . . . . . . V

OFFS_OUT to AGND . . . . AGND – 0.3 V to AV

1, 2

– 0.3 V to V

SS

+ 0.3 V

CC

+ 0.3 V

CC

+ 0.3 V

DD

+ 0.3 V

DD

+ 0.3 V

CC

AGND to DGND. . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

Operating Temperature Range

Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Junction Temperature (T
74-Lead LFBGA Package, θ

max) . . . . . . . . . . . . . . . . . . 150°C

J

Thermal Impedance . . . 41°C/W

JA

Reflow Soldering

Peak Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C

Time at Peak Temperature . . . . . . . . . . . . 10 sec to 40 sec

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

2

Transient currents of up to 100 mA will not cause SCR latch-up.

ORDERING GUIDE

Output Output Package Package

Model Function Impedance Voltage Span Description Option

AD5533ABC-1 32-Channel SHA Only 0.5 Ω typ 10 V 74-Lead LFBGA BC-74
AD5532ABC-1* 32 DACs, 32-Channel SHA 0.5 Ω typ 10 V 74-Lead LFBGA BC-74

AD5532ABC-2* 32 DACs, 32-Channel SHA 0.5 Ω typ 20 V 74-Lead LFBGA BC-74
AD5532ABC-3* 32 DACs, 32-Channel SHA 500 Ω typ 10 V 74-Lead LFBGA BC-74
AD5532ABC-5* 32 DACs, 32-Channel SHA 1 kΩ typ 10 V 74-Lead LFBGA BC-74

EVAL-AD5532EB AD5532/AD5533 Evaluation Board

*Separate Data Sheet.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD5533 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

–6–

REV. 0

PIN CONFIGURATION

1234567891011

AD5533

A

B

C

D

E

F

G

H

J

K

L

1234567891011

A

B

C

D

E

F

G

H

J

K

L

74-Lead LFBGA Ball Configuration

LFBGA Ball LFBGA Ball LFBGA Ball
Number Name Number Name Number Name

A1 N/C C10 AVCC1 J10 VO9
A2 A4 C11 REF_OUT J11 VO11
A3 A2 D1 VO20 K1 VO17
A4 A0 D2 DAC_GND2 K2 VO15
A5 CS/SYNC D10 AVCC2 K3 VO27
A6 DVCC D11 OFFS_OUT K4 VSS3
A7 SCLK E1 VO26 K5 VSS1
A8 OFFSET_SEL E2 VO14 K6 VSS4
A9 BUSY E10 AGND1 K7 VDD2
A10 TRACK/RESET E11 OFFS_IN K8 VO2
A11 N/C F1 VO25 K9 VO10
B1 VO16 F2 VO21 K10 VO13
B2 N/C F10 AGND2 K11 VO12
B3 A3 F11 VO6 L1 N/C
B4 A1 G1 VO24 L2 VO28
B5 WR G2 VO8 L3 VO29
B6 DGND G10 VO5 L4 VO30
B7 DIN G11 VO3 L5 VDD3
B8 CAL H1 VO23 L6 VDD1
B9 SER/PAR H2 VIN L7 VDD4
B10 DOUT H10 VO4 L8 VO31
B11 REF_IN H11 VO7 L9 VO0
C1 VO18 J1 VO22 L10 VO1
C2 DAC_GND1 J2 VO19 L11 N/C
C6 N/C J6 VSS2

REV. 0

–7–

AD5533

PIN FUNCTION DESCRIPTIONS

Pin Function

AGND(1–2) Analog GND Pins.
AV

(1–2) Analog Supply Pins. Voltage range from 4.75 V to 5.25 V.

CC

V

(1–4) VDD Supply Pins. Voltage range from 8 V to 16.5 V.

DD

V

(1–4) VSS Supply Pins. Voltage range from –4.75 V to –16.5 V.

SS

DGND Digital GND Pins.
DV

CC

DAC_GND(1–2) Reference GND Supply for All the DACs.
REF_IN Reference Voltage for Channels 0–31.
REF_OUT Reference Output Voltage.
V

(0–31) Analog Output Voltages from the 32 Channels.

OUT

V

IN

1

A4–A1
CAL

2

, A0

1

CS/SYNC This pin is both the active low Chip Select pin for the parallel interface and the Frame Synchronization pin

1

WR

OFFSET_SEL

2

SCLK

2

D

IN

D

OUT

SER/PAR

1

1

OFFS_IN Offset Input. The user can supply a voltage here to offset the output span. OFFS_OUT can also be tied to

OFFS_OUT Offset Output. This is the acquired/programmed offset voltage which can be tied to the OFFS_IN pin

BUSY This output tells the user when the input voltage is being acquired. It goes low during acquisition and

TRACK/RESET

NOTES

1

Internal pull-down devices on these logic inputs. Therefore, they can be left floating and will default to a logic low condition.

2

Internal pull-up devices on these logic inputs. Therefore, they can be left floating and will default to a logic high condition.

Digital Supply Pins. Voltage range from 2.7 V to 5.25 V.

Analog Input Voltage. Connect this to AGND if operating in DAC mode only.
Parallel Interface: 5-Address Pins for 32 Channels. A4 = MSB of Channel Address. A0 = LSB.
Parallel Interface: Control input that allows all 32 channels to acquire VIN simultaneously.

for the serial interface.
Parallel Interface: Write pin. Active low. This is used in conjunction with the CS pin to address the device

using the parallel interface.
Parallel Interface: Offset Select Pin. Active high. This is used to select the offset channel.
Serial Clock Input for Serial Interface. This operates at clock speeds up to 20 MHz.
Data Input for Serial Interface. Data must be valid on the falling edge of SCLK.
Output from the DAC Registers for readback. Data is clocked out on the rising edge of SCLK and is valid

on the falling edge of SCLK.
This pin allows the user to select whether the serial or parallel interface will be used. If the pin is tied low,

the parallel interface will be used. If it is tied high, the serial interface will be used.

this pin if the user wants to drive this pin with the Offset Channel.

to offset the span.

returns high when the acquisition operation is complete.

2

If this input is held high, VIN is acquired once the channel is addressed. While it is held low, the input to the
gain/offset stage is switched directly to V

. The addressed channel begins to acquire VIN on the rising edge

IN

of TRACK. See TRACK Input section for further information. This input can also be used as a means of
resetting the complete device to its power-on-reset conditions. This is achieved by applying a low-going
pulse of between 50 ns and 150 ns to this pin. See section on RESET Function for further details.

–8–

REV. 0

AD5533

TERMINOLOGY

to V

V

IN

Nonlinearity

OUT

This is a measure of the maximum deviation from a straight line
passing through the endpoints of the V

versus V

IN

OUT

transfer

function. It is expressed as a percentage of the full-scale span.

Offset Error

This is a measure of the output error when VIN = 70 mV. Ideally,
with V

Offset error is a measure of the difference between V
and V

= 70 mV:

IN

V

= (Gain × 70) – ((Gain – 1) × V

OUT

(ideal). It is expressed in mV and can be positive or

OUT

OFFS_IN

) mV

OUT

(actual)

negative. See Figure 5.

Gain Error

This is a measure of the span error of the analog channel. It is
the deviation in slope of the transfer function. See Figure 5. It
is calculated as:

Gain Error = Actual Full-Scale Output – Ideal Full-Scale Output –
Offset Error

where

Ideal Full-Scale Output = Ideal Gain × 2.96 – ((Ideal Gain-1) × V

OFFS_IN

)

Ideal Gain = 3.52

Output Temperature Coefficient

This is a measure of the change in analog output with changes
in temperature. It is expressed in ppm/°C.

DC Power-Supply Rejection Ratio

DC Power-Supply Rejection Ratio (PSRR) is a measure of the
change in analog output for a change in supply voltage (V

DD

and VSS). It is expressed in dBs. VDD and VSS are varied ±5%.

DC Crosstalk

This the dc change in the output level of one channel in response
to a full-scale change in the output of all other channels. It is
expressed in µV.

Output Settling Time

This is the time taken from when BUSY goes high to when the
output has settled to ±0.018%.

Acquisition Time

This is the time taken for the VIN input to be acquired. It is the
length of time that BUSY stays low.

OFFS_IN Settling Time

This is the time taken from a 0 V–3 V step change in input volt­age on OFFS_IN until the output has settled to within ±0.35%.

Digital Feedthrough

This is a measure of the impulse injected into the analog outputs
from the digital control inputs when the part is not being written
to, i.e., CS/SYNC is high. It is specified in nV-secs and is mea­sured with a worst-case change on the digital input pins, e.g.,
from all 0s to all 1s and vice versa.

Output Noise Spectral Density

This is a measure of internally generated random noise. Random
noise is characterized as a spectral density (voltage per root Hertz).
It is measured by loading all DACs to midscale and measuring
noise at the output. It is measured in nV/(√Hz)

1/2

.

AC Crosstalk

This is the area of the glitch that occurs on the output of one
channel while another channel is acquiring. It is expressed in
nV-secs.

V

OUT

0V

LOWER

DEADBAND

OFFSET

ERROR

IDEAL

TRANSFER

FUNCTION

ACTUAL
TRANSFER
FUNCTION

70mV

Figure 5. SHA Transfer Function

GAIN ERROR +
OFFSET ERROR

2.96

3V

UPPER

DEADBAND

V

IN

REV. 0

–9–

AD5533

–Typical Performance Characteristics

0.0024
TA = 25ⴗC

0.0020

0.0016

0.0012

0.0008

0.0004

0.0000

ERROR – V

–0.0004

OUT

–0.0008

V

–0.0012

–0.0016

–0.0020

–0.0024

Figure 6. VIN to V

= 3V

V

REFIN

= 0V

V

OFFS_IN

0.1 2.96
– V

V

IN

Accuracy after

OUT

Offset and Gain Adjustment

5V

100

90

V

OUT

10

0%

1V

BUSY

TA = 25ⴗC
V

REFIN

= 0 1.5V

V

IN

2␮s

Figure 9. Acquisition Time and
Output Settling Time

= 3V

OFFSET ERROR – mV

20

15

10

5

0

–40

GAIN

OFFSET ERROR

04080

TEMPERATURE – ⴗC

3.56

3.54

3.52

3.50

3.48

Figure 7. Offset Error and Gain vs.
Temperature

70k

60k

50k

40k

30k

FREQUENCY

20k

10k

0

5.2670

200

63791

TA = 25ⴗC
V

REFIN

= 1.5V

V

IN

V

OFFS_IN

5.2676 5.2682

V

– V

OUT

= 3V

= 0V

1545

Figure 10. SHA Mode Repeatability
(64K Acquisitions)

GAIN

3.535

TA = 25ⴗC
V

REFIN

V

IN

3.530

– V

OUT

V

3.525

3.520
6

Figure 8. V
Capability

= 3V

= 1V

42 –2 –4 –6

SINK/SOURCE CURRENT – mA

OUT

0

Source and Sink

–10–

REV. 0

AD5533

FUNCTIONAL DESCRIPTION

The AD5533 can be thought of as consisting of an ADC and 32
DACs in a single package. The input voltage V

is sampled

IN

and converted into a digital word. The digital result is loaded
into one of the DAC registers and is converted (with gain and
offset) into an analog output voltage (V

OUT

0–V

31). Since

OUT

the channel output voltage is effectively the output of a DAC
there is no droop associated with it. As long as power to the
device is maintained, the output voltage will remain constant
until this channel is addressed again.

To update a single channel’s output voltage, the required new
voltage level is set up on the common input pin, V

. The desired

IN

channel is then addressed via the parallel port or the serial port.
When the channel address has been loaded, provided TRACK is
high, the circuit begins to acquire the correct code to load to the
DAC in order that the DAC output matches the voltage on V

.

IN

The BUSY pin goes low and remains so until the acquisition is
complete. The noninverting input to the output buffer is tied to

during the acquisition period to avoid spurious outputs while

V

IN

the DAC acquires the correct code. The acquisition is completed
in 16 µs max. The BUSY pin goes high and the updated DAC
output assumes control of the output voltage. The output voltage
of the DAC is connected to the noninverting input of the output
buffer. The held voltage will remain on the output pin indefinitely,
without drooping, as long as power to the device is maintained.

On power-on, all the DACs, including the offset channel, are
loaded with zeros. The outputs of the DACs are at 50 mV typical
(negative full-scale). If the OFFS_IN pin is driven by the on-board
offset channel, the outputs V
power-on since OFFS_IN = 50 mV (V
× V

= 176 mV – 126 mV = 50 mV).

OFFS_IN

OUT

0 to V

31 are also at 50 mV on

OUT

= 3.52 × V

OUT

DAC

– 3.52

Analog Input

The equivalent analog input circuit is shown in Figure 11. The
Capacitor C1 is typically 20 pF and can be attributed to pin
capacitance and 32 off-channels. When a channel is selected, an
extra 7.5 pF (typ) is switched in. This Capacitor C2 is charged to
the previously acquired voltage on that particular channel so
it must charge/discharge to the new level. It is essential that the
external source can charge/discharge this additional capaci­tance within 1 µs–2 µs of channel selection so that V

can be

IN

acquired accurately. For this reason a low impedance source is
recommended.

ADDRESSED CHANNEL

V

IN

C1
20pF

C2

7.5pF

Figure 11. Analog Input Circuit

Large source impedances will significantly affect the performance
of the ADC. This may necessitate the use of an input buffer
amplifier.

Output Buffer Stage—Gain and Offset

The function of the output buffer stage is to translate the 0 V–3 V
output of the DAC to a wider range. This is done by gaining up
the DAC output by 3.52 and offsetting the voltage by the volt­age on OFFS_IN pin.

V

= 3.52 × V

OUT

V

is the output of the DAC.

DAC

V

is the voltage at the OFFS_IN pin.

OFFS_IN

Table I shows how the output range on V

– 2.52 × V

DAC

OFFS_IN

relates to the offset

OUT

voltage supplied by the user.

Table I. Sample Output Voltage Ranges

V

(V) V

OFFS_IN

(V) V

DAC

OUT

(V)

0.5 0 to 3 –1.26 to +9.3
1 0 to 3 –2.52 to +8.04

is limited only by the headroom of the output amplifiers.

V

OUT

must be within maximum ratings.

V

OUT

Offset Voltage Channel

The offset voltage can be externally supplied by the user at
OFFS_IN or it can be supplied by an additional offset voltage
channel on the device itself. The required offset voltage is set up

and acquired by the offset DAC. This offset channel’s

on V

IN

DAC output is directly connected to OFFS_OUT. By connect­ing OFFS_OUT to OFFS_IN this offset voltage can be used as
the offset voltage for the 32-output amplifiers. It is important to
choose the offset so that V

is within maximum ratings.

OUT

REV. 0

CONTROLLER

DAC

V

IN

BUSY

TRACK

ACQUISITION

CIRCUIT

ONLY ONE CHANNEL SHOWN FOR SIMPLICITY

Figure 12. Typical ATE Circuit Using

–11–

OUTPUT

STAGE

AD5533

V

TRACK

1

OUT

Input

PIN

DRIVER

THRESHOLD

VOLTAGE

DEVICE
UNDER
TEST

AD5533

Reset Function

The reset function on the AD5533 can be used to reset all nodes
on this device to their power-on-reset condition. This is imple­mented by applying a low-going pulse of between 50 ns and 150 ns
to the TRACK/RESET pin on the device. If the applied pulse
is less than 50 ns it is assumed to be a glitch and no operation
takes place. If the applied pulse is wider than 150 ns this pin adopts
its track function on the selected channel, V

is switched to the

IN

output buffer and an acquisition on the channel will not occur
until a rising edge of TRACK.

TRACK Function

Normally in SHA mode of operation, TRACK is held high and
the channel begins to acquire when it is addressed. However, if
TRACK is low when the channel is addressed, V

is switched

IN

to the output buffer and an acquisition on the channel will not
occur until a rising edge of TRACK. At this stage the BUSY pin
will go low until the acquisition is complete, at which point the
DAC assumes control of the voltage to the output buffer and
V

is free to change again without affecting this output value.

IN

This is useful in an application where the user wants to ramp up
V

until V

IN

reaches a particular level (Figure 12). VIN does

OUT

not need to be acquired continuously while it is ramping up.
TRACK can be kept low and only when V

has reached its

OUT

desired voltage is TRACK brought high. At this stage, the
acquisition of V

begins.

IN

In the example shown, a desired voltage is required on the out­put of the pin driver. This voltage is represented by one input to
a comparator. The microcontroller/microprocessor ramps up
the input voltage on V
while the voltage on V

through a DAC. TRACK is kept low

IN

ramps up so that VIN is not continu-

IN

ally acquired. When the desired voltage is reached on the output of
the pin driver, the comparator output switches. The µC/µP then
knows what code is required to be input in order to obtain the
desired voltage at the DUT. The TRACK input is now brought
high and the part begins to acquire V

. BUSY goes low until V

IN

IN

has been acquired. When BUSY goes high, the output buffer
is switched from V

MODES OF OPERATION

to the output of the DAC.

IN

The AD5533 can be used in three different modes. These modes
are set by two mode bits, the first two bits in the serial word.
The 01 option (DAC Mode) is not available for the AD5533.
To avail of this mode refer to the AD5532 data sheet. If you
attempt to set up DAC mode, the AD5533 will enter a test-mode
and a 24-clock write will be necessary to clear this.

Table II. Modes of Operation

Mode Bit 1 Mode Bit 2 Operating Mode

0 0 SHA Mode
0 1 DAC Mode (Not Available)
1 0 Acquire and Readback
1 1 Readback

1. SHA Mode

In this standard mode a channel is addressed and that channel
acquires the voltage on V
to address the relevant channel (V

. This mode requires a 10-bit write

IN

OUT

0–V

31, offset channel

OUT

or all channels). MSB is written first.

2. Acquire and Readback Mode

This mode allows the user to acquire VIN and read back the data
in a particular DAC register. The relevant channel is addressed
(10-bit write, MSB first) and V

is acquired in 16 µs (max).

IN

Following the acquisition, after the next falling edge of SYNC
the data in the relevant DAC register is clocked out onto the

line in a 14-bit serial format. During readback DIN is

D

OUT

ignored. The full acquisition time must elapse before the DAC
register data can be clocked out.

3. Readback Mode

Again, this is a readback mode but no acquisition is performed.
The relevant channel is addressed (10-bit write, MSB first) and
on the next falling edge of SYNC, the data in the relevant DAC
register is clocked out onto the D

line in a 14-bit serial format.

OUT

The user must allow 400 ns (min) between the last SCLK fall­ing edge in the 10-bit write and the falling edge of SYNC in
the 14-bit readback. The serial write and read words can be seen in
Figure 13.

This feature allows the user to read back the DAC register code
of any of the channels. Readback is useful if the system has been
calibrated and the user wants to know what code in the DAC
corresponds to a desired voltage on V

INTERFACES
SERIAL INTERFACE

OUT

.

The SER/PAR pin is tied high to enable the serial interface and
to disable the parallel interface. The serial interface is controlled
by four pins as follows:

SYNC, DIN, SCLK

Standard 3-wire interface pins. The SYNC pin is shared
with the CS function of the parallel interface.

D

OUT

Data Out pin for reading back the contents of the DAC regis­ters. The data is clocked out on the rising edge of SCLK and
is valid on the falling edge of SCLK.

Cal Bit

When this is high all 32 channels acquire VIN simultaneously.
The acquisition time is then 45 µs (typ) and accuracy may be
reduced.

Offset_Sel Bit

If this bit is set high, the offset channel is selected and Bits
A4–A0 are ignored.

Test Bit

This must be set low for correct operation of the part.

A4–A0

Used to address any one of the 32 channels (A4 = MSB of
address, A0 = LSB).

–12–

REV. 0

OFFSET SEL A4 –A0

CAL00

MSB LSB

MODE BIT 1 MODE BIT 2

MODE BITS

0

TEST BIT

a. 10-Bit Input Serial Write Word (SHA Mode)

AD5533

MSB LSB

OFFSET SEL A4–A0CAL01

MODE BITS

10-BIT

SERIAL WORD

WRITTEN TO PART

TEST BIT

b. Input Serial Interface (Acquire and Readback Mode)

MSB LSB

011

OFFSET SEL A4 –A0

MODE BITS

10-BIT

SERIAL WORD

WRITTEN TO PART

TEST BIT

c. Input Serial Interface (Readback Mode)

Figure 13. Serial Interface Formats

DB13–DB0

These are used in both readback modes to read a 14-bit word
from the addressed DAC register.

The serial interface is designed to allow easy interfacing to most
microcontrollers and DSPs, e.g., PIC16C, PIC17C, QSPI, SPI,
DSP56000, TMS320, and ADSP-21xx, without the need for
any glue logic. When interfacing to the 8051, the SCLK must
be inverted. The Microprocessor/Microcontroller Interface
section explains how to interface to some popular DSPs and
microcontrollers.

Figures 3 and 4 show the timing diagram for a serial read and
write to the AD5533. The serial interface works with both a
continuous and a noncontinuous serial clock. The first falling
edge of SYNC resets a counter that counts the number of serial
clocks to ensure the correct number of bits are shifted in and
out of the serial shift registers. Any further edges on SYNC are
ignored until the correct number of bits are shifted in or out.
Once the correct number of bits have been shifted in or out, the
SCLK is ignored. In order for another serial transfer to take
place the counter must be reset by the falling edge of SYNC.
In readback, the first rising SCLK edge after the falling edge
of SYNC causes D
data is clocked out onto the D
SCLK rising edges. The D

to leave its high impedance state and

OUT

line and also on subsequent

OUT

pin goes back into a high imped-

OUT

ance state on the falling edge of the 14th SCLK. Data on the

line is latched in on the first SCLK falling edge after the

D

IN

MSBLSB

DB13 –DB00

14-BIT DATA

READ FROM PART AFTER

NEXT FALLING EDGE OF SYNC

(DB13 = MSB OF DAC WORD)

MSBLSB

0

DB13 –DB0

14-BIT DATA

READ FROM PART AFTER

NEXT FALLING EDGE OF SYNC

(DB13 = MSB OF DAC WORD)

falling edge of the SYNC signal and on subsequent SCLK falling
edges. The serial interface will not shift data in or out until it
receives the falling edge of the SYNC signal.

Parallel Interface

The SER/PAR bit must be tied low to enable the parallel inter­face and disable the serial interface. The parallel interface is
controlled by nine pins.

CS

Active low package select pin. This pin is shared with the SYNC
function for the serial interface.

WR

Active low write pin. The values on the address pins are latched
on a rising edge of WR.

A4–A0

Five address pins (A4 = MSB of address, A0 = LSB). These are
used to address the relevant channel (out of a possible 32).

Offset_Sel

Offset select pin. This has the same function as the Offset_Sel
bit in the serial interface. When it is high, the offset channel is
addressed and the address on A4–A0 is ignored.

Cal

Same functionality as the Cal bit in the serial interface. When this
pin is high, all 32 channels acquire V

simultaneously.

IN

REV. 0

–13–

AD5533

MICROPROCESSOR INTERFACING
AD5533 to ADSP-21xx Interface

The ADSP-21xx family of DSPs are easily interfaced to the
AD5533 without the need for extra logic.

A data transfer is initiated by writing a word to the TX register
after the SPORT has been enabled. In a write sequence data is
clocked out on each rising edge of the DSP’s serial clock and
clocked into the AD5533 on the falling edge of its SCLK. In
readback 16 bits of data are clocked out of the AD5533 on each
rising edge of SCLK and clocked into the DSP on the rising edge
of SCLK. DIN is ignored. The valid 14 bits of data will be cen­tered in the 16-bit RX register when using this configuration.
The SPORT control register should be set up as follows:

TFSW = RFSW = 1, Alternate Framing
INVRFS = INVTFS = 1, Active Low Frame Signal
DTYPE = 00, Right Justify Data
ISCLK = 1, Internal Serial Clock
TFSR = RFSR = 1, Frame Every Word
IRFS = 0, External Framing Signal
ITFS = 1, Internal Framing Signal
SLEN = 1001, 10-Bit Data Words (SHA Mode Write)
SLEN = 1111, 16-Bit Data Words (Readback Mode)

Figure 14 shows the connection diagram.

AD5533*

*ADDITIONAL PINS OMITTED FOR CLARITY

D

OUT

SYNC

D

SCLK

IN

DR

TFS

RFS

DT

SCLK

ADSP-2101/
ADSP-2103*

Figure 14. AD5533 to ADSP-2101/ADSP-2103 Interface

AD5533 to MC68HC11

The Serial Peripheral Interface (SPI) on the MC68HC11 is
configured for Master Mode (MSTR = 1), Clock Polarity Bit
(CPOL) = 0 and the Clock Phase Bit (CPHA) = 1. The SPI is
configured by writing to the SPI Control Register (SPCR)—see
68HC11 User Manual. SCK of the 68HC11 drives the SCLK of
the AD5533, the MOSI output drives the serial data line (D
of the AD5533 and the MISO input is driven from D

OUT

IN

. The

)

SYNC signal is derived from a port line (PC7). When data is
being transmitted to the AD5533, the SYNC line is taken low
(PC7). Data appearing on the MOSI output is valid on the fall­ing edge of SCK. Serial data from the 68HC11 is transmitted in
8-bit bytes with only eight falling clock edges occurring in the
transmit cycle. Data is transmitted MSB first. In order to trans­mit 10-data bits in SHA mode it is important to left-justify the

data in the SPDR register. PC7 must be pulled low to start a
transfer. It is taken high and pulled low again before any further
read/write cycles can take place. A connection diagram is shown in
Figure 15.

AD5533*

*ADDITIONAL PINS OMITTED FOR CLARITY

D

OUT

SYNC

SCLK

D

IN

MC68HC11*

MISO

PC7

SCK

MOSI

Figure 15. AD5533 to MC68HC11 Interface

AD5533 to PIC16C6x/7x

The PIC16C6x Synchronous Serial Port (SSP) is configured
as an SPI Master with the Clock Polarity bit = 0. This is done
by writing to the Synchronous Serial Port Control Register
(SSPCON). See user PIC16/17 Microcontroller User Manual.
In this example I/O port RA1 is being used to pulse SYNC and
enable the serial port of the AD5533. This microcontroller trans­fers only eight bits of data during each serial transfer operation;
therefore, two consecutive read/write operations are needed for
a 10-bit write and a 14-bit readback. Figure 16 shows the con­nection diagram.

AD5533*

SCLK

D

OUT

D

IN

SYNC

*ADDITIONAL PINS OMITTED FOR CLARITY

PIC16C6x/7x*

SCK/RC3

SDO/RC5

SDI/RC4

RA1

Figure 16. AD5533 to PIC16C6x/7x Interface

AD5533 TO 8051

The AD5533 requires a clock synchronized to the serial data.
The 8051 serial interface must therefore be operated in Mode

0. In this mode serial data enters and exits through RxD and a
shift clock is output on TxD. Figure 17 shows how the 8051 is
connected to the AD5533. Because the AD5533 shifts data
out on the rising edge of the shift clock and latches data in on
the falling edge, the shift clock must be inverted. The AD5533
requires its data with the MSB first. Since the 8051 outputs
the LSB first, the transmit routine must take this into account.

AD5533*

SCLK

D

OUT

D

SYNC

IN

8051*

TxD

RxD

P1.1

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 17. AD5533 to 8051 Interface

–14–

REV. 0

AD5533

APPLICATION CIRCUITS
AD5533 in a Typical ATE System

The AD5533 Infinite Sample-and-Hold is ideally suited for use
in Automatic Test Equipment. Several SHAs are required to
control pin drivers, comparators, active loads, and signal timing.
Traditionally, sample-and-hold devices with droop were used in
this application. These required refreshing to prevent the volt­age from drifting.

The AD5533 has several advantages: no refreshing is required,
there is no droop, pedestal error is eliminated, and there is no
need for extra filtering to remove glitches. Overall, a higher level
of integration is achieved in a smaller area, see Figure 18.

STORED

DATA

AND INHIBIT

PATTERN

PERIOD

GENERATION

AND
DELAY
TIMING

SHAs

SHA

SHA

SHA

FORMATTER

COMPARE
REGISTER

SYSTEM BUS

ACTIVE

LOAD

DRIVER

COMPARATOR

PARAMETRIC

MEASUREMENT

SHA

SHA

UNIT

SYSTEM BUS

DUT

SHA

SHA

Figure 18. AD5533 in an ATE System

Typical Application Circuit

The AD5533 can be used to set up voltage levels on 32 channels
as shown in the circuit below. An AD780 provides the 3 V refer­ence for the AD5533, and for the AD5541 16-bit DAC. A simple
3-wire interface is used to write to the AD5541. The DAC out­put is buffered by an AD820. It is essential to minimize noise on

and REFIN when laying out this circuit.

V

IN

POWER SUPPLY DECOUPLING

In any circuit where accuracy is important, careful consideration
of the power supply and ground return layout helps to ensure
the rated performance. The printed circuit board on which the
AD5533 is mounted should be designed so that the analog and
digital sections are separated, and confined to certain areas of
the board. If the AD5533 is in a system where multiple devices
require an AGND-to-DGND connection, the connection should
be made at one point only. The star ground point should be
established as close as possible to the device. For supplies with
multiple pins (V

, VDD, AVCC) it is recommended to tie those pins

SS

together. The AD5533 should have ample supply bypassing of
10 µF in parallel with 0.1 µF on each supply located as close to
the package as possible, ideally right up against the device. The
10 µF capacitors are the tantalum bead type. The 0.1 µF capacitor
should have low Effective Series Resistance (ESR) and Effective
Series Inductance (ESI), like the common ceramic types that
provide a low impedance path to ground at high frequencies, to
handle transient currents due to internal logic switching.

The power supply lines of the AD5533 should use as large a trace
as possible to provide low impedance paths and reduce the effects
of glitches on the power supply line. Fast switching signals such
as clocks should be shielded with digital ground to avoid radiat­ing noise to other parts of the board, and should never be run
near the reference inputs. A ground line routed between the

and SCLK lines will help reduce crosstalk between them (not

D

IN

required on a multilayer board as there will be a separate ground
plane, but separating the lines will help). It is essential to mini­mize noise on V

and REFIN lines.

IN

Avoid crossover of digital and analog signals. Traces on opposite
sides of the board should run at right angles to each other. This
reduces the effects of feedthrough through the board. A microstrip
technique is by far the best, but not always possible with a double­sided board. In this technique, the component side of the board
is dedicated to ground plane while signal traces are placed on
the solder side.

CS

DIN

SCLK

REV. 0

AV

CC

REF

V

AD820

OUT

AD5541*

AD780*

*ADDITIONAL PINS OMITTED FOR CLARITY

V

DD

AV

V

IN

OFFS_IN

OFFS_OUT

REFIN

SCLK DIN

Figure 19. Typical Application Circuit

DV

CC

CC

AD5533*

V

SS

SYNC

V

0–31

OUT

–15–

AD5533

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

74-Lead LFBGA

(BC-74)

0.472 (12.00) BSC

A1

0.067

(1.70)

MAX

CONTROLLING DIMENSIONS
ARE IN MILLIMETERS

TOP VIEW

0.472

(12.00)

BSC

DETAIL A

0.039

(1.00)

BSC

0.010

(0.25)

0.394 (10.00) BSC

11 10 9 8 7 6 5 4 3 2 1

BOTTOM

0.039 (1.00) BSC

DETAIL A

MIN

0.024 (0.60)
BSC

BALL DIAMETER

VIEW

SEATING
PLANE

A
B
C
D
E
F
G
H
J
K
L

0.033
(0.85)

MIN

0.394

(10.00)

BSC

C3745–2.5–4/00 (rev. 0) 00940

–16–

PRINTED IN U.S.A.

REV. 0