32-Channel 14-Bit DAC with
a
FEATURES
High Integration: 32-Channel DAC in 12 ⴛ 12 mm
Guaranteed Monotonic
DSP-/Microcontroller-Compatible Serial Interface
Channel Update Rate 1.1 MHz
Output Impedance 0.5 ⍀
Selectable Output Voltage 0 V to 5 V or –2.5 V to +2.5 V
Asynchronous RESET Facility
Temperature Range –40ⴗC to +85ⴗC
APPLICATIONS
Optical Networks
Level Setting
Instrumentation
Automatic Test Equipment
Industrial Control Systems
Data Acquisition
Low Cost I/O
FUNCTIONAL BLOCK DIAGRAM
DV
AV
CC
CC
High-Speed 3-Wire Serial Interface
AD5532HS*
2
LFBGA
REF_IN OFFS_IN
GENERAL DESCRIPTION
The AD5532HS is a 32-channel voltage-output 14-bit DAC
with a high-speed serial interface. The selected DAC register is
written to via the 3-wire interface. The serial interface operates
at clock rates up to 30 MHz and is compatible with DSP and
microcontroller interface standards. The output voltage range is
0 V to 5 V or –2.5 V to +2.5 V and is determined by the offset
voltage at the OFFS_IN pin. It is restricted to a range from
+ 2 V to VDD – 2 V because of the headroom of the out-
V
SS
put amplifier.
The device is operated with AV
to 5.25 V, V
= –4.75 V to –12 V and VDD = +4.75 V to +12 V
SS
= 5 V ± 5%, DVCC = 2.7 V
CC
and requires a stable 2.5 V reference on REF_IN.
PRODUCT HIGHLIGHTS
1. 32 14-bit DACs in one package, guaranteed monotonic.
2. The AD5532HS is available in a 74-ball LFBGA package
with a body size of 12 mm by 12 mm.
VDDV
SS
AD5532HS
RESET
DAC_GND
AGND
DGND
INTERFACE
CONTROL
LOGIC
D
SCLK
IN
*Protected by U.S. Patent No. 5,969,657; other patents pending.
14-BIT BUS
SYNC
DAC
DAC
DAC
DAC
R
R
R
R
R
R
R
R
V
0
OUT
V
1
OUT
30
V
OUT
31
V
OUT
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 2001
AD5532HS–SPECIFICATIONS
(VDD = +4.75 V to +12 V, VSS = –4.75 V to –12 V; AVCC = 4.75 V to 5.25 V; DVCC = 2.7 V to 5.25 V; AGND = DGND = DAC_GND = 0 V; REF_IN =
2.5 V; OFFS_IN = 0 V; All outputs unloaded. All specifications T
Parameter
D
AC DC PERFORMANCE
1
A Version
Min Typ Max Unit Conditions/Comments
Resolution 14 Bits
Integral Nonlinearity (INL) –0.39 ±0.1 +0.39 % of FSR See TPC 7
Differential Nonlinearity (DNL) –1 ±0.5 +1 LSB Monotonic
Offset Error –10 +15 +50 mV See TPC 8
Full-Scale Error –1 –0.3 +0.5 % of FSR See TPC 9
VOLTAGE REFERENCE REF_IN
Input Voltage Range
3
2.375 2.5 2.625 V
Input Current ±0.001 ±1 µA
ANALOG INPUT OFFS_IN
Input Voltage Range
3, 4
0V
Input Current ±0.1 ±1 µA
ANALOG OUTPUTS (V
Output Temperature Coefficient
DC Output Impedance
Output Range
4
OUT
3
0–V
OUT
3, 5
31)
OFFS_IN = 0 0 – 2REF_IN V
OFFS_IN = REF_IN –REF_IN to +REF_IN V
Resistive Load
Capacitive Load
Short-Circuit Current
DC Power-Supply Rejection Ratio
DC Crosstalk
DIGITAL INPUTS
3
3
3
3
3
3
5kΩ
Input Current ±5 ±10 µA
Input Low Voltage 0.8 V DV
Input High Voltage 2.4 V DV
2.0 V DV
Input Hysteresis (SCLK and SYNC Only) 200 mV
Input Capacitance 10 pF
POWER SUPPLY VOLTAGES
V
DD
V
SS
AV
CC
DV
CC
POWER SUPPLY CURRENTS
I
DD
I
SS
AI
CC
DI
CC
POWER DISSIPATION
NOTES
1
See Terminology
2
A Version: Industrial temperature range –40°C to +85°C; typical at 25°C.
3
Guaranteed by design and characterization, not production tested.
4
Output range is restricted from VSS + 2 V to VDD – 2 V.
5
AD780 as reference for the AD5532HS.
6
Outputs unloaded.
Specifications subject to change without notice.
6
6
+4.75 +12 V
–4.75 –12 V
4.75 5.25 V
2.7 5.25 V
to T
MIN
unless otherwise noted.)
MAX
2
– 1.5 V
DD
20 ppm/°C
0.5 Ω
100 pF
7mA
–70 dB VDD = +10 V ± 5%
–70 dB V
= –10 V ± 5%
SS
120 µV
= 5 V ± 5%
0.4 V DV
CC
= 3 V ± 10%
CC
= 5 V ± 5%
CC
= 3 V ± 10%
CC
9 12 mA All Channels Full Scale
9 12 mA All Channels Full Scale
6.5 10 mA
0.1 0.5 mA VIH = DVCC and VIL = DGND
123 mW VDD = +5 V, VSS = –5 V
–2–
REV. 0
AD5532HS
AC CHARACTERISTICS
DGND = DAC_GND = 0 V; REF_IN = 2.5 V; All outputs unloaded. All specifications T
Parameter1,
Output Voltage Settling Time
2
(VDD = +4.75 V to +12 V, VSS = –4.75 V to –12 V; AVCC = 4.75 V to 5.25 V; DVCC = 2.7 V to 5.25 V; AGND =
to T
MIN
A Version
4
10 µs max 100 pF, 5 kΩ Load; Full-Scale Change
3
Unit Conditions/Comments
unless otherwise noted.)
MAX
Slew Rate 0.85 V/µs typ
Digital-to-Analog Glitch Impulse 1 nV-s typ 1 LSB Change around Major Carry
Digital Crosstalk 5 nV-s typ
Analog Crosstalk 1 nV-s typ
Digital Feedthrough 0.2 nV-s typ
Output Noise Spectral Density @ 1 kHz 170 nV/√Hz typ
NOTES
1
See Terminology
2
Guaranteed by design and characterization, not production tested
3
B Version: Industrial temperature range –40°C to +85°C.
4
Timed from the end of a write sequence.
Specifications subject to change without notice.
TIMING CHARACTERISTICS
AGND = DGND = DAC_GND = 0 V; All specifications T
Limit at T
Parameter1, 2,
f
UPDATE
f
CLKIN
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
NOTES
1
See Timing Diagrams in Figure 1.
2
Guaranteed by design and characterization, not production tested.
3
All input signals are specified with tR = tF = 5 ns (10% to 90% of DVCC) and timed from a voltage level of (VIL + VIH)/2.
Specifications subject to change without notice.
3
(A Version) Unit Conditions/Comments
1.1 MHz max Channel Update Rate
30 MHz max SCLK Frequency
13 ns min SCLK High Pulsewidth
13 ns min SCLK Low Pulsewidth
15 ns min SYNC Falling Edge to SCLK Falling Edge Setup Time
50 ns min SYNC Low Time
10 ns min SYNC High Time
10 ns min DIN Setup Time
5 ns min DIN Hold Time
280 ns min 19th SCLK Falling Edge to SYNC Falling Edge for Next Write
20 ns min RESET Pulsewidth
MIN
(VDD = +4.75 V to +12 V, VSS = –4.75 V to –12 V; AVCC = 4.75 V to 5.25 V; DVCC = 2.7 V to 5.25 V;
to T
unless otherwise noted.)
MAX
, T
MIN
MAX
SCLK
SYNC
D
IN
RESET
REV. 0
t
1
1
t
3
t
5
MSB
t
9
2345
t
2
t
4
t
6
t
7
16 17 18 19
LSB
1
t
8
Figure 1. Serial Interface Timing Diagram
–3–
AD5532HS
WARNING!
ESD SENSITIVE DEVICE
ABSOLUTE MAXIMUM RATINGS1,
(TA = 25°C unless otherwise noted)
2
VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +17 V
to AGND . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –17 V
V
SS
AV
to AGND, DAC_GND . . . . . . . . . . . . . –0.3 V to +7 V
CC
DV
to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
CC
Digital Inputs to DGND . . . . . . . . . . –0.3 V to DV
+ 0.3 V
CC
REF_IN to AGND, DAC_GND . . . . . . . . . . . –0.3 V to +7 V
V
0–V
OUT
0–V
V
OUT
OFFS_IN to AGND . . . . . . . . . . . V
31 to AGND . . . . . . . VSS – 0.3 V to VDD + 0.3 V
OUT
31 to VSS . . . . . . . . . . . . . . . . . . –0.3 V to +24 V
OUT
– 0.3 V to VDD + 0.3 V
SS
AGND to DGND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V
Operating Temperature Range
Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature (T
74-Lead LFBGA Package, θ
max) . . . . . . . . . . . . . . . . . . 150°C
J
Thermal Impedance . . . 41°C/W
JA
Reflow Soldering
Peak Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C
Time at Peak Temperature . . . . . . . . . . . . 10 sec to 40 sec
Max Power Dissipation at T
= 70°C,
A
Outputs Loaded . . . . . . . . . . . . . . . . . . . . . . . . . . 550 mW
(for TA > 70°C, derate at 26 mW for each °C over 70°C)
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
Transient currents of up to 100 mA will not cause SCR latch-up.
3
This limit includes load power and applies only when there is a resistive load on
V
outputs.
OUT
ORDERING GUIDE
Output Package Package
Model Function Voltage Span Description Option
AD5532HSABC 32 DACs 5 V 74-Ball LFBGA BC-74
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD5532HS features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
3
ACT UAL
IDEAL
OUTPUT VOLTAGE
OFFSET
ERROR
0
DAC CODE
16k
Figure 2. DAC Transfer Function (OFFS_IN = 0)
–4–
FULL-SCALE
ERROR
REV. 0
PIN CONFIGURATION
1234567891011
AD5532HS
A
B
C
D
E
F
G
H
J
K
L
1234567891011
TOP VIEW
A
B
C
D
E
F
G
H
J
K
L
AD5532HS 74-Ball (LFBGA) Configuration
LFBGA Ball LFBGA Ball LFBGA Ball
Number Name Number Name Number Name
A1 N/C C10 AVCC1 J10 VO9
A2 N/C C11 N/C J11 VO11
A3 N/C D1 VO20 K1 VO17
A4 N/C D2 DAC_GND2 K2 VO15
A5 SYNC D10 AVCC2 K3 VO27
A6 DVCC D11 N/C K4 VSS3
A7 SCLK E1 VO26 K5 VSS1
A8 N/C E2 VO14 K6 VSS4
A9 N/C E10 AGND1 K7 VDD2
A10 RESET E11 OFFS_IN K8 VO2
A11 N/C F1 VO25 K9 VO10
B1 VO16 F2 VO21 K10 VO13
B2 N/C F10 AGND2 K11 VO12
B3 N/C F11 VO6 L1 N/C
B4 N/C G1 VO24 L2 VO28
B5 N/C G2 VO8 L3 VO29
B6 DGND G10 VO5 L4 VO30
B7 DIN G11 VO3 L5 VDD3
B8 DGND H1 VO23 L6 VDD1
B9 N/C H2 N/C L7 VDD4
B10 N/C H10 VO4 L8 VO31
B11 REF_IN H11 VO7 L9 VO0
C1 VO18 J1 VO22 L10 VO1
C2 DAC_GND1 J2 VO19 L11 N/C
C6 N/C J6 VSS2
REV. 0
–5–
AD5532HS
PIN FUNCTION DESCRIPTIONS
Pin Function
AGND (1–2) Analog GND Pins.
AV
(1–2) Analog Supply Pins. Voltage range from 4.75 V to 5.25 V.
CC
V
(1–4) VDD Supply Pins. Voltage range from 8 V to 12 V.
DD
V
(1–4) VSS Supply Pins. Voltage range from –4.75 V to –12 V.
SS
DGND Digital GND Pins.
DV
CC
DAC_GND (1–2) Reference GND Supply for All the DACs.
REF_IN Reference Voltage for Channels 0–31.
V
OUT
0–V
31 Analog Output Voltages from the 32 Channels.
OUT
SYNC Active Low Input. This is the Frame Synchronization signal for the serial interface. While SYNC is low,
SCLK* Serial Clock Input. Data is clocked into the shift register on the falling edge of SCLK. This
D
* Serial Data Input. Data must be valid on the falling edge of SCLK.
IN
OFFS_IN Offset Input. The user can connect this to GND or REF_IN to determine the output span.
RESET* Active Low Input. This pin can also be used to reset the complete device to its power-on-reset conditions.
*Internal pull-up device on this logic input. Therefore, it can be left floating and will default to a logic high condition.
Digital Supply Pins. Voltage range from 2.7 V to 5.25 V.
data is transferred in on the falling edge of SCLK.
operates at clock speeds up to 30 MHz.
TERMINOLOGY
Integral Nonlinearity (INL)
A measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is
expressed as a percentage of full-scale range.
Differential Nonlinearity (DNL)
The difference between the measured change and the ideal 1 LSB
change between any two adjacent codes. A specified DNL of
±1 LSB maximum ensures monotonicity.
Offset Error
A measure of the error present at the device output with all 0s
loaded to the DAC. It includes the offset of the DAC and the
output amplifier. It is expressed in mV.
Full-Scale Error
A measure of the output error with all 1s loaded to the DAC.
Ideally the output should be 2 REF_IN if OFFS_IN = 0. It is
expressed as a percentage of full-scale range.
DC Power-Supply Rejection Ratio (PSRR)
A measure of the change in analog output for a change in supply
voltage (V
and VSS). It is expressed in dB. VDD and VSS are
DD
varied ± 5%.
DC Crosstalk
The dc change in the output level of one DAC at midscale in
response to a full-scale code change (all 0s to all 1s and vice
versa) and output change of all other DACs. It is expressed in µV.
Output Temperature Coefficient
A measure of the change in analog output with changes in temperature. It is expressed in ppm/°C.
Output Voltage Settling Time
The time taken from when the last data bit is clocked into the
DAC until the output has settled to within ±0.5 LSB of its
final value.
Digital-to-Analog Glitch Impulse
The area of the glitch injected into the analog output when
the code in the DAC register changes state. It is specified as
the area of the glitch in nV-secs when the digital code is changed
by 1 LSB at the major carry transition (011 . . . 11 to 100 . . . 00
or 100 . . . 00 to 011 . . . 11).
Digital Crosstalk
The glitch impulse transferred to the output of one DAC at
midscale while a full-scale code change (all 1s to all 0s and vice
versa) is being written to another DAC. It is expressed in nV-secs.
Analog Crosstalk
The area of the glitch transferred to the output (V
DAC due to a full-scale change in the output (V
OUT
) of one
OUT
) of another
DAC. The area of the glitch is expressed in nV-secs.
Digital Feedthrough
A measure of the impulse injected into the analog outputs from the
digital control inputs when the part is not being written to, i.e.,
SYNC is high. It is specified in nV-secs and measured with a
worst-case change on the digital input pins, e.g., from all 0s
to all 1s and vice versa.
Output Noise Spectral Density
A measure of internally generated random noise. Random noise is
characterized as a spectral density (voltage per root Hertz). It is
measured by loading all DACs to midscale and measuring
noise at the output. It is measured in nV/√Hz.
–6–
REV. 0
Typical Performance Characteristics–
AD5532HS
1.0
V
= 2.5V
REF_IN
0.8
0.6
0.4
0.2
0.0
–0.2
–0.4
DAC ERROR –LSBs
–0.6
–0.8
–1.0
0
= 0V
V
OFFS_IN
T
= 25ⴗC
A
2K 4K 6K 8K 10K 12K 14K 16K
DAC CODE
TPC 1. Typical DNL Plot
– V
V
OUT
2.535
2.530
2.525
2.520
= 25ⴗC
T
A
V
= 2.5V
REFIN
= 0V
V
OFFS_IN
DAC LOADED TO MIDSCALE
64
20
SINK/SOURCE CURRENT – mA
–2 –4 –6
1.0
0.5
0.0
DNL ERROR – LSBs
–0.5
–1.0
–40
DNL MAX
INL MIN
DNL MIN
04080
TEMPERATURE – ⴗC
INL MAX
TPC 2. INL Error and DNL Error vs.
Temperature
6
5
4
3
– V
OUT
2
V
1
0
–1
TIME BASE – 1.25
TA = 25ⴗC
V
REFIN
V
OFFS_IN
s/DIV
= 2.5V
= 0V
0.2
0.1
0.0
–0.1
–0.2
INL ERROR – % FSR
5.000
4.995
– V
OUT
V
4.990
4.985
TPC 3. V
2.520
2.518
2.516
2.514
2.512
2.510
– V
2.508
2.506
OUT
V
2.504
2.502
2.500
2.498
2.496
2.494
V
= 2.5V
REFIN
= 0V
V
OFFS_IN
DAC LOADED TO FULL SCALE
–40 0
TEMPERATURE – ⴗC
vs. Temperature
OUT
TA = 25ⴗC
= 2.5V
V
REFIN
= 0V
V
OFFS_IN
TIME BASE – 200ns/DIV
40 80
TPC 4. V
Source and Sink
OUT
Capability
15
10
5
FREQUENCY – %
0
0
0.1
% FSR
0.2
0.3
TPC 7. INL Error Distribution at 25°C
TPC 5. Full-Scale Settling Time
15
10
5
FREQUENCY – %
0
0
10 30
mV
20
TPC 8. Offset Error Distribution
°
C
at 25
TPC 6. Major Code Transition Glitch
Impulse
20
10
FREQUENCY – %
0
–1.0
–0.5 0.0
% FSR
TPC 9. Full-Scale Error Distribution
°
C
at 25
REV. 0
–7–
AD5532HS
FUNCTIONAL DESCRIPTION
The AD5532HS consists of 32 DACs in a single package. A
14-bit digital word is loaded into one of the 32 DAC registers
via the serial interface. This is then converted (with gain and
offset) into an analog output voltage (V
OUT
0–V
OUT
31).
To update a DAC’s output voltage, the required DAC is
addressed via the serial port. When the 5-bit DAC address
and 14-bit DAC data have been loaded the selected DAC
converts the code.
On power-on, all the DACs are loaded with zeros.
Digital-to-Analog Section
The architecture of each DAC channel consists of a resistorstring DAC followed by an output buffer amplifier. The voltage
at the REF_IN pin provides the reference voltage for the corresponding DAC. Since the input coding to the DAC is straight
binary, the ideal DAC output voltage is given by:
V
VD
=
DAC
REF IN
_
2
×
14
where D = decimal equivalent of the binary code that is loaded
to the DAC register i.e., 0–16,383.
Output Buffer Stage—Gain and Offset
The function of the output buffer stage is to translate the
0 V–2.5 V output of the DAC to a wider range. This is done by
gaining up the DAC output by two and offsetting the voltage
by the voltage on OFFS_IN pin.
VVV
=×()–
2
OUT DAC OFFS IN
V
is the output of the DAC.
DAC
V
is the voltage at the OFFS_IN pin.
OFFS_IN
Table I shows how the output range of V
_
relates to the offset
OUT
voltage supplied by the user.
Table I. Sample Output Voltage Ranges
V
OFFS_IN
V
DAC
V
OUT
(V) (V) (V)
0 0 to 2.5 0 to 5
2.5 0 to 2.5 –2.5 to +2.5
V
is limited only by the headroom of the output amplifiers.
OUT
V
must be within maximum ratings.
OUT
Reset Function
The reset function on the AD5532HS can be used to reset all
nodes on the device to their power-on-reset condition. All the
DACs are loaded with 0s and all registers are cleared. The reset
function is implemented by taking the RESET pin low.
SERIAL INTERFACE
The serial interface is controlled by three pins as follows:
SYNC: This pin is the Frame Synchronization pin for the serial
interface.
SCLK: This pin is the Serial Clock Input. It operates at clock
speeds up to 30 MHz.
D
: This pin is the Serial Data Input. Data must be valid on
IN
the falling edge of SCLK.
To update a single DAC channel a 19-bit data-word is written
into the AD5532HS. See Table II.
Table II. Serial Data Format
MSB LSB
A4 A3 A2 A1 A0 DB13–DB0
A4–A0 Bits
Used to address any one of the 32 channels (A4 = MSB of
address, A0 = LSB).
DB13–DB0 Bits
These are used to write a 14-bit word into the addressed
DAC register.
Figure 1 shows the timing diagram for a serial write to the
AD5532HS. The serial interface works with both a continuous and
a noncontinuous serial clock. The first falling edge of SYNC resets
a counter that counts the number of serial clocks to ensure
the correct number of bits are shifted in and out of the serial
shift registers. Any further edges on SYNC are ignored until the
correct number of bits are shifted in or out. Once 19 bits have
been shifted in or out, the SCLK is ignored. In order for another
serial transfer to take place, the counter must be reset by the
falling edge of SYNC. The user must allow 280 ns (min)
between successive writes (refer to Timing Specifications).
–8–
REV. 0
AD5532HS
SCLK
PIC16C6x/7x*
SYNC
D
IN
SCK/RC3
AD5532HS*
*ADDITIONAL PINS OMITTED FOR CLARITY
SDI/RC4
RA1
AD5532HS*
SCLK
D
IN
SYNC
TxD
RxD
P1.1
8051*
*ADDITIONAL PINS OMITTED FOR CLARITY
MICROPROCESSOR INTERFACING
AD5532HS-to-ADSP-21xx Interface
The ADSP-21xx family of DSPs are easily interfaced to the
AD5532HS without the need for extra logic.
A data transfer is initiated by writing a word to the Tx register
after the SPORT has been enabled. In a write sequence, data is
clocked out on each rising edge of the DSP’s serial clock and
clocked into the AD5532HS on the falling edge of its SCLK.
The easiest way to provide the 19-bit data-word required by
the AD5532HS, is to transmit two 10-bit data-words from the
ADSP-21xx. Ensure that the data is positioned correctly in the
TX register so that the first 19 bits transmitted contain valid
data. The SPORT control register should be set up as follows:
TFSW = 1, Alternate Framing
INVTFS = 1, Active Low Frame Signal
DTYPE = 00, Right Justify Data
ISCLK = 1, Internal Serial Clock
TFSR = 1, Frame Every Word
ITFS = 1, Internal Framing Signal
SLEN = 1001, 10-Bit Data Word
Figure 3 shows the connection diagram.
SCLK
DT
TFS
ADSP-2101/
ADSP-2103*
AD5532HS*
SCLK
D
IN
SYNC
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 3. AD5532HS-to-ADSP-2101/ADSP-2103 Interface
AD5532HS-to-MC68HC11 Interface
The Serial Peripheral Interface (SPI) on the MC68HC11 is
configured for Master Mode (MSTR = 1), Clock Polarity Bit
(CPOL) = 0 and the Clock Phase Bit (CPHA) = 1. The SPI is
configured by writing to the SPI Control Register (SPCR)—see
68HC11 User Manual. SCK of the 68HC11 drives the SCLK of
the AD5532HS and the MOSI output drives the serial data line
) of the AD5532HS. The SYNC signal is derived from a port
(D
IN
line (PC7). When data is being transmitted to the AD5532HS, the
SYNC line is taken low (PC7). Data appearing on the MOSI
output is valid on the falling edge of SCK. The 68HC11 transfers
only eight bits of data during each serial transfer operation;
therefore, three consecutive write operations are necessary to
transmit 19 bits of data. Data is transmitted MSB first. It is
important to left-justify the data in the SPDR register so that
the first 19 bits transmitted contain valid data. PC7 must be
pulled low to start a transfer. It is taken high and pulled low
again before any further write cycles can take place. See Figure 4.
AD5532HS-to-PIC16C6x/7x Interface
The PIC16C6x/7x Synchronous Serial Port (SSP) is configured
as an SPI Master with the Clock Polarity bit = 0. This is done
by writing to the Synchronous Serial Port Control Register
(SSPCON). See user PIC16/17 Microcontroller User Manual.
In this example I/O port RA1 is being used to pulse SYNC
and enable the serial port of the AD5532HS. This microcontroller
transfers only eight bits of data during each serial transfer
operation; therefore, three consecutive write operations are
necessary to transmit 19 bits of data. Data is transmitted MSB
first. It is important to left-justify the data in the SPDR register
so that the first 19 bits transmitted contain valid data. RA1
must be pulled low to start a transfer. It is taken high and pulled
low again before any further write cycles can take place. Figure 5
shows the connection diagram.
Figure 5. AD5532HS-to-PIC16C6x/7x Interface
AD5532HS-to-8051 Interface
The AD5532HS requires a clock synchronized to the serial
data. The 8051 serial interface must therefore be operated in
Mode 0. In this mode serial data exits the 8051 through RxD
and a shift clock is output on TxD. The SYNC signal is derived
from a port line (P1.1). Figure 6 shows how the 8051 is connected
to the AD5532HS. Because the AD5532HS shifts data out on
the rising edge of the shift clock and latches data in on the
falling edge, the shift clock must be inverted. Note also that
the AD5532HS requires its data with the MSB first. Since the
8051 outputs the LSB first, the transmit routine must take this
into account.
Figure 6. AD5532HS-to-8051 Interface
AD5532HS*
SCLK
SYNC
ADDITIONAL PINS OMITTED FOR CLARITY
*
REV. 0
Figure 4. AD5532HS-to-MC68HC11 Interface
MC68HC11*
SCK
D
IN
MOSI
PC7
–9–
AD5532HS
APPLICATION CIRCUITS
AD5532HS in an Optical Network Control Loop
The AD5532HS can be used in optical network applications
that require a large number of DACs to perform a control and
measurement function. In the circuit shown in Figure 7, the
0 V–5 V outputs of the AD5532HS are amplified to a range of
0 V–180 V and then used to control actuators that determine
the position of MEMS mirrors in an optical switch. The exact
position of each mirror is measured using sensors. The sensor
readings are muxed using four dual 4-channel matrix switches
(ADG739) and fed back to an 8-channel 14-bit ADC (AD7856).
The control loop is driven by an ADSP-21065L, a 32-bit SHARC
®
DSP with an SPI-compatible SPORT interface. It writes data
to the DAC, controls the multiplexor, and reads data from
the ADC via a 3-wire serial interface.
S
AD5532HS
1
0V–180V
AMPS
32
ACTUATORS
FOR MEMS
MIRROR
ARRAY
E
1
N
S
O
32
R
S
ADSP-21065L
ADG739
ⴛ 4
1
AD7856
8
Figure 7. AD5532HS and DSP Control an Optical Switch
Alternatively, the AD5532HS can be driven by an ADMC401
Motor-Controller as shown in the control-loop in Figure 8. The
DAC outputs are fed into eight AD8534 quad transconductance
amps to generate currents for voice-coil actuators that determine
the position of the mirrors. The exact position of each mirror
is measured and the readings are muxed into the on-chip
8-channel ADC of the ADMC401.
AD5532HS
1
32
AD8534
ⴛ 8
3
VOICE-COIL
ACTUATORS
FOR
MEMS
MIRROR
ARRAY
S
P
O
ADMC401
R
T
S
1
E
N
ADG704
S
O
32
R
S
8-CH
12-BIT
ⴛ 8
ADC
1
8
AD8544
ⴛ 2
3
1
8
Figure 8. AD5532HS and ADMC401 Control an Optical
Switch
AD5532HS in a Typical ATE System
The AD5532HS is ideally suited for use in Automatic Test
Equipment. Several DACs are required to control pin drivers,
comparators, active loads, and signal timing. Traditionally,
sample-and-hold devices were used in this application.
The AD5532HS has several advantages: no refreshing is required,
there is no droop, pedestal error is eliminated, and there is no
need for extra filtering to remove glitches. A higher level of
integration is achieved in a smaller area (see Figure 9).
SHARC is a registered trademark of Analog Devices, Inc.
PARAMETRIC
STORED
DATA
AND INHIBIT
PATTERN
PERIOD
GENERATION
AND
DELAY
TIMING
DACs
DAC
DAC
DAC
FORMATTER
COMPARE
REGISTER
SYSTEM BUS
ACTIVE
LOAD
DRIVER
COMPARATOR
MEASUREMENT
DAC
DAC
UNIT
SYSTEM BUS
DUT
DAC
DAC
Figure 9. AD5532HS in an ATE System
POWER SUPPLY DECOUPLING
In any circuit where accuracy is important, careful consideration
of the power supply and ground return layout helps to ensure
the rated performance. The printed circuit board on which the
AD5532HS is mounted should be designed so that the analog
and digital sections are separated, and confined to certain areas
of the board. If the AD5532HS is in a system where multiple
devices require an AGND-to-DGND connection, the connection
should be made at one point only. The star ground point should
be established as close as possible to the device. For supplies
with multiple pins (V
, VDD, AVCC), it is recommended to
SS
tie those pins together. The AD5532HS should have ample
supply bypassing of 10 µF in parallel with 0.1 µF on each supply
located as close to the package as possible, ideally right up against
the device. The 10 µF capacitors are the tantalum bead type. The
0.1 µF capacitor should have low Effective Series Resistance
(ESR) and Effective Series Inductance (ESI), like the common
ceramic types that provide a low impedance path to ground at
high frequencies, to handle transient currents due to internal
logic switching.
The power supply lines of the AD5532HS should use as large a
trace as possible to provide low impedance paths and reduce
the effects of glitches on the power supply line. Fast switching
signals such as clocks should be shielded with digital ground to
avoid radiating noise to other parts of the board, and should
never be run near the reference inputs. A ground line routed
between the D
and SCLK lines will help reduce crosstalk
IN
between them (not required on a multilayer board as there will
be a separate ground plane, but separating the lines will help). It
is essential to minimize noise on REF_IN.
Avoid crossover of digital and analog signals. Traces on opposite
sides of the board should run at right angles to each other. This
reduces the effects of feedthrough through the board. A microstrip
technique is by far the best, but not always possible with a doublesided board. In this technique, the component side of the board
is dedicated to ground plane while signal traces are placed on
the solder side.
As is the case for all thin packages, care must be taken to avoid
flexing the package and to avoid a point load on the surface of
the package during the assembly process.
–10–
REV. 0
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
74-Ball LFBGA
(BC-74)
AD5532HS
0.472 (12.00) BSC
A1
0.067
(1.70)
MAX
CONTROLLING DIMENSIONS
ARE IN MILLIMETERS
TOP VIEW
0.472
(12.00)
BSC
DETAIL A
0.039
(1.00)
BSC
0.020
(0.50)
0.394 (10.00) BSC
11 10 9 8 7 6 5 4 3 2 1
0.039 (1.00) BSC
DETAIL A
MIN
0.024 (0.60)
BALL DIAMETER
BOTTOM
VIEW
BSC
A
B
C
D
E
F
G
H
J
K
L
SEATING
PLANE
0.394
(10.00)
BSC
0.033
(0.85)
MIN
REV. 0
–11–
C02548–1.5–6/01(0)
–12–
PRINTED IN U.S.A.
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