Datasheet AD5532B Datasheet (ANALOG DEVICES)

32-Channel, 14-Bit

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FEATURES

High integration:

32-channel DAC in 12 mm × 12 mm CSPBGA
Adjustable voltage output range
Guaranteed monotonic
Readback capability
DSP/microcontroller compatible serial interface
Output impedance:

0.5 Ω (AD5532-1, AD5532-2)

500 Ω (AD5532-3)

1 kΩ (AD5532-5)
Output voltage span:

10 V (AD5532-1, AD5532-3, AD5532-5)

20 V (AD5532-2)
Infinite sample-and-hold capability to ±0.018% accuracy
Temperature range −40°C to +85°C

APPLICATIONS

Automatic test equipment
Optical networks
Level setting
Instrumentation
Industrial control systems
Data acquisition
Low cost I/O

AV

DV

CC

CC

GENERAL DESCRIPTION

The AD55321 is a 32-channel, 14-bit voltage-output DAC with
an additional infinite sample-and-hold mode. The selected DAC
register is written to via the 3-wire serial interface; V
DAC is then updated to reflect the new contents of the DAC
register. DAC selection is accomplished via Address Bits A0–A4.
The output voltage range is determined by the offset voltage at
the OFFS_IN pin and the gain of the output amplifier. It is
restricted to a range from V
headroom of the output amplifier.

The device is operated with AV

5.25 V; V

= −4.75 V to −16.5 V; and VDD = 8 V to 16.5 V. The

SS

AD5532 requires a stable 3 V reference on REF_IN as well as an
offset voltage on OFFS_IN.

PRODUCT HIGHLIGHTS

1. 32-channel, 14-bit DAC in one package, guaranteed

monotonic.

2. Available in a 74-lead CSPBGA package with a body size of

12 mm ×12 mm.

3. Droopless/infinite sample-and-hold mode.

1

Protected by U.S. Patent No. 5,969,657; other patents pending.

REF_IN REF_OUT OFFS_IN VDDV

Voltage-Output DAC

AD5532

for this

OUT

+ 2 V to VDD – 2 V because of the

SS

= 5 V ± 5%; DVCC = 2.7 V to

CC

SS

AD5532

V

TRACK/RESET

BUSY

DAC_GND

AGND

DGND

SER/PAR

IN

ADC

MUX DAC

MODE

INTERFACE

CONTROL

LOGIC

SCLK DIND

OUT

Figure 1. Functional Block Diagram

14-BIT BUS

Rev. C

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

DAC

DAC

SYNC/CS

V

0

OUT

V

31

OUT

OFFS_OUT

ADDRESS INPUT REGISTER

A4–A0 CAL OFFSET_SEL

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

WR

00939-C-001

AD5532

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TABLE OF CONTENTS

Specifications..................................................................................... 3

Offset Voltage Channel.............................................................. 14

ISHA Mode.................................................................................... 5

Timing Characteristics..................................................................... 6

Parallel Interface ........................................................................... 6

Parallel Interface Timing Diagrams........................................... 6

Serial Interface.............................................................................. 7

Absolute Maximum Ratings............................................................ 8

Pin Configuration and Function Descriptions............................. 9

Te r m in o l o g y .................................................................................... 11

Dac Mode ....................................................................................11

ISHA Mode.................................................................................. 11

Typical Performance Characteristics........................................... 12

Functional Description ..................................................................14

Output Buffer Stage—Gain and Offset.................................... 14

REVISION HISTORY

Reset Function............................................................................ 14

ISHA Mode ................................................................................. 14

Analog Input (ISHA Mode) ......................................................14

TRACK

Modes of Operation ...................................................................15

Serial Interface............................................................................ 16

Parallel Interface (ISHA Mode Only) ...................................... 17

Microprocessor Interfacing....................................................... 17

Application Circuits................................................................... 18

Power Supply Decoupling .........................................................19

Outline Dimensions....................................................................... 20

Ordering Guide .......................................................................... 20

Function (ISHA Mode) .............................................. 15

6/04—Data Sheet Changed from Rev. B to Rev. C

pdated Format........................................................... Universal

U

Changed LFBGA to CSPBGA.................................... Universal

Changes to Outline Dimensions.............................................24

Changes to Ordering Guide....................................................24

6/02—Data Sheet Changed from Rev. A to Rev. B

Term SHA changed to ISHA........................................... Global

C

hanges to Absolute Maximum Ratings .................................6

Changes to Ordering Guide......................................................6

Changes to Functional Description .......................................11

Changes to Table 8....................................................................11

Changes to ISHA Mode ...........................................................11

Added Figure 27 and accompanying text..............................15

Changes to Power Supply Decoupling Section.....................15

Rev. C | Page 2 of 20

AD5532

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SPECIFICATIONS

VDD = 8 V to 16.5 V, VSS = –4.75 V to –16.5 V; AVCC = 4.75 V to 5.25 V; DVCC = 2.7 V to 5.25 V; AGND = DGND = DAC_GND = 0 V;
REF_IN = 3 V; output range from V

+ 2 V to VDD − 2 V. All outputs unloaded. All specifications T

SS

MIN

to T

, unless otherwise noted.

MAX

Table 1.

A Version
Parameter2 AD5532-1/-3/-5 AD5532-2 Only Unit Conditions/Comments

DAC DC PERFORMANCE

Resolution 14 14 Bits
Integral Nonlinearity (INL) ±0.39 ±0.39 % of FSR max ±0.15% typ
Differential Nonlinearity (DNL) ±1 ±1 LSB max ±0.5 LSB typ, monotonic
Offset 90/170/250 180/350/500 mV min/typ/max See Figure 8

Gain 3.52 7 typ
Full Scale Error ±2 ±2 % of FSR max
VOLTAGE REFERENCE

REF_IN

Nominal Input Voltage 3.0 3.0 V typ
Input Voltage Range3 2.85/3.15 2.85/3.15 V min/max
Input Current 1 1 µA max < 1 nA typ

REF_OUT

Output Voltage 3 3 V typ
Output Impedance3 280 280 kΩ typ

Reference Temperature Coefficient3 60 60 ppm/°C typ
ANALOG OUTPUTS (V
Output Temperature Coefficient3, 4 10 10 ppm/°C typ

DC Output Impedance3

AD5532-1 0.5 0.5 Ω typ

AD5532-3 500 Ω typ

AD5532-5 1 kΩ typ

Output Range
Resistive Load3, 5 5 5 kΩ min
Capacitive Load3, 5

AD5532-1 500 500 pF max

AD5532-3 15 nF max

AD5532-5 40 nF max

Short-Circuit Current3 7 7 mA typ
DC Power-Supply Rejection Ratio3

DC Crosstalk3 250 1800 µV max

ANALOG OUTPUT (OFFS_OUT)

Output Temperature Coefficient3, 4 10 10 ppm/°C typ
DC Output Impedance3 1.3 1.3 kΩ typ
Output Range
Output Current 10 10 µA max Source current
Capacitive Load 100 100 pF max

DIGITAL INPUTS3

Input Current ±10 ±10 µA max ±5 µA typ
Input Low Voltage 0.8 0.8 V max DVCC = 5 V ±5%

0.4 0.4 V max DVCC = 3 V ±10%

Input High Voltage 2.4 2.4 V min DVCC = 5 V ±5%

2.0 2.0 V min DVCC = 3 V ±10%

Input Hysteresis (SCLK and CS Only)

0–31)

OUT

V

+ 2/VDD − 2 VSS + 2 /VDD − 2

SS

−70 −70

−70 −70

50 to REF_IN−1

200 200 mV typ

2 50 to REF_IN−12

1

V min/max

dB typ VDD = +15 V ±5%
dB typ

mV typ

V

= −15 V ±5%

SS

Rev. C | Page 3 of 20

AD5532

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A Version

1

Parameter2 AD5532-1/-3/-5 AD5532-2 Only Unit Conditions/Comments

Input Capacitance 10 10 pF max

DIGITAL OUTPUTS (BUSY, D

OUT

)3
Output Low Voltage, DVCC = 5 V 0.4 0.4 V max Sinking 200 µA.
Output High Voltage, DVCC = 5 V 4.0 4.0 V min Sourcing 200 µA.
Output Low Voltage, DVCC = 3 V 0.4 0.4 V max Sinking 200 µA.
Output High Voltage, DVCC = 3 V 2.4 2.4 V min Sourcing 200 µA.
High Impedance Leakage Current ±1 ±1 µA max D
High Impedance Output Capacitance 15 15 pF typ D

OUT

OUT

only.

only.

POWER REQUIREMENTS

Power-Supply Voltages
VDD 8/16.5 8/16.5 V min/max
VSS

−4.75/−16.5 −4.75/−16.5

V min/max
AVCC 4.75/5.25 4.75/5.25 V min/max
DVCC 2.7/5.25 2.7/5.25 V min/max
Power-Supply Currents

IDD 15 15 mA max

6

10 mA typ. All channels
full scale.

ISS 15 15 mA max

10 mA typ. All channels

full scale.
AICC 33 33 mA max 26 mA typ.
DICC 1.5 1.5 mA max 1 mA typ.

Power Dissipation6 280 280 mW typ

V

= 10 V, VSS = −5 V.

DD

AC CHARACTERISTICS3

Output Voltage Settling Time 22 30 µs max

OFFS_IN Settling Time 10 25

µs max

Digital-to-Analog Glitch Impulse 1 1 nV-s typ

500 pF, 5 kΩ load. Full-scale

change.

500 pF, 5 kΩ load; 0 V to 3 V

step.

1 LSB change around. Major

carry.

Digital Crosstalk 5 5 nV-s typ
Analog Crosstalk 1 1 nV-s typ
Digital Feedthrough 0.2 0.2 nV-s typ
Output Noise Spectral Density @ 1 kHz 400 400 nV/(√Hz) typ

1

A version: Industrial temperature range -40°C to +85°C; typical at +25°C.

2

See section. Terminology

3

Guaranteed by design and characterization, not production tested.

4

AD780 as reference for the AD5532.

5

Ensure that you do not exceed TJ (max). See Ab section. solute Maximum Ratings

6

Output unloaded.

Rev. C | Page 4 of 20

AD5532

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ISHA MODE

Table 2.

A Version
Parameter

2

AD5532-1/-3/-5 AD5532-2 Only Unit Conditions/Comments

1

ANALOG CHANNEL

VIN to V

Nonlinearity

OUT

3

±0.018 ±0.018 % max ±0.006% typ after offset and gain adjustment.
Offset Error ±50 ±75 mV max ±10 mV typ. See Figure 9.
Gain 3.46/3.52/3.6 6.96/7/7.02 min/typ/max See Figure 9

ANALOG INPUT (VIN)

Input Voltage Range 0 to 3 0 to 3 V Nominal input range.
Input Lower Dead Band 70 70 mV max 50 mV typ. Referred to VIN. See Figure 9.
Input Upper Dead Band 40 40 mV max 12 mV typ. Referred to VIN. See Figure 9.
Input Current 1 1 µA max 100 nA typ.
V

acquired on 1 channel.

IN

Input Capacitance4 20 20 pF typ

ANALOG INPUT (OFFS_IN)

Input Current 1 1 µA max 100 nA typ.
Input Voltage Range 0/4 0/4 Vmin/max

Output range restricted from V

+ 2 V to VDD − 2 V.

SS

AC CHARACTERISTICS

Output Settling Time4 3 3 µs max Output unloaded.
Acquisition Time 16 16 µs max
AC Crosstalk4 5 5 nV-s typ

1

A version: Industrial temperature range -40°C to +85°C; typical at +25°C.

2

See section. Terminology

3

Input range 100 mV to 2.96 V.

4

Guaranteed by design and characterization, not production tested.

Rev. C | Page 5 of 20

AD5532

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TIMING CHARACTERISTICS

PARALLEL INTERFACE

Table 3.

Parameter1,

2

Limit at T

MIN

, T

(A Version) Unit Conditions/Comments

MAX

t1 0 ns min
t2 0 ns min
t3 50 ns min
t4 50 ns min
t5 20 ns min
t6 7 ns min

1

See and , the parallel interface timing diagrams. Figure 2 Figure 3

2

Guaranteed by design and characterization, not production tested.

PARALLEL INTERFACE TIMING DIAGRAMS

t

2

t

6

00939-C-002

CS

WR

A4–A0, CAL,

OFFS_SEL

t

1

t

3

t

4

t

5

Figure 2. Parallel Write (ISHA Mode Only)

CS

to WR setup time

CS

to WR hold time

CS

pulse width low

WR

pulse width low
A4–A0, CAL, OFFS_SEL to WR
A4–A0, CAL, OFFS_SEL to WR

200µAI

TO OUTPUT

PIN

C

L

50pF

200µAI

Figure 3. Load Circuit for D

Timing Specifications

OUT

setup time
hold time

OL

1.6V

OH

00939-C-003

Rev. C | Page 6 of 20

AD5532

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SERIAL INTERFACE

Table 4.

Parameter1, 2 Limit at T

3

f

14 MHz max SCLK frequency

CLKIN

t1 28 ns min SCLK high pulse width
t2 28 ns min SCLK low pulse width
t3 15 ns min

t4 50 ns min
t5 10 ns min DIN setup time

t6 5 ns min DIN hold time
t7 5 ns min

4

t

8

4

t

60 ns max SCLK falling edge to D

9

20 ns max SCLK rising edge to D

t10 400 ns min
t11 400 ns min

5

t

12

7 ns min

, T

(A Version) Unit Conditions/Comments

MIN

MAX

SYNC

falling edge to SCLK falling edge setup time

SYNC

low time

SYNC

falling edge to SCLK rising edge setup time for read back

10th SCLK falling edge to
24th SCLK falling edge to
SCLK falling edge to

t

1

valid

OUT

high impedance

OUT

SYNC

falling edge for read back

SYNC

falling edge for DAC mode write

SYNC

falling edge setup time for read back

SCLK

SYNC

D

IN

12345678910

t

3

MSB LSB

t

2

t

4

t

5

t

6

Figure 4. 10-Bit Write (ISHA Mode and Both Readback Modes)

t

1

SCLK

SYNC

D

IN

12345 21222324 1

t

3

t

2

t

4

t

5

t

6

LSBMSB

Figure 5. 24-Bit Write (DAC Mode)

t

7

SCLK 10 1 2 34567891011121314

t

12

SYNC

t

10

D

OUT

t

1

t

2

t

4

MSB LSB

t

8

Figure 6. 14-Bit Read (Both Readback Modes)

1

See Figur , and . Figure 4, e 5 Figure 6

2

Guaranteed by design and characterization, not production tested.

3

In ISHA mode the maximum SCLK frequency is 20 MHz and the minimum pulse width is 20 ns.

4

These numbers are measured with the load circuit of . Figure 3

5

SYNC

should be taken low while SCLK is low for read back.

00939-C-004

t

11

00939-C-005

t

9

00939-C-006

Rev. C | Page 7 of 20

AD5532

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ABSOLUTE MAXIMUM RATINGS

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

T

= 25°C unless otherwise noted.

A

Table 5.

Parameter1 Rating

VDD to AGND
VSS to AGND
AVCC to AGND, DAC_GND
DVCC to DGND
Digital Inputs to DGND
Digital Outputs to DGND
REF_IN to AGND, DAC_ GND
V

to AGND, DAC_GND

IN

V

0–31 to AGND

OUT

OFFS_IN to AGND
OFFS_OUT to AGND AGND - 0.3 V to AVCC + 0.3 V
AGND to DGND
Operating Temperature Range

Industrial
Storage Temperature Range
Junction Temperature (TJ max) 150°C
74-Lead CSPBGA Package,

Thermal Impedance

θ

JA

Reflow Soldering
Peak Temperature 220°C
Time at Peak Temperature 10 sec to 40 sec
Max Power Dissipation
Max Continuous Load Current at

= 70°C, per Channel Group

T

J

1

Transient currents of up to 100 mA do not cause SCR latch-up.

2

This limit includes load power.

3

This maximum allowed continuous load current is spread over 8 channels

and channels are grouped as follows:

Group 1: Channels 3, 4, 5, 6, 7, 8, 9, 10

Group 2: Channels 14, 16, 18, 20. 21, 24, 25, 26

Group 3: Channels 15, 17, 19, 22, 23, 27, 28, 29

Group 4: Channels 0, 1, 2, 11, 12, 13, 30, 31

−0.3 V to +17 V
+0.3 V to −17 V

−0.3 V to +7 V

−0.3 V to +7 V

−0.3 V to DV

−0.3 V to DV

−0.3 V to AV

−0.3 V to AV

V

− 0.3 V to VDD + 0.3 V

SS

V

− 0.3 V to VDD + 0.3 V

SS

+ 0.3 V

CC

+ 0.3 V

CC

+ 0.3 V

CC

+ 0.3 V

CC

−0.3 V to +0.3 V

−40°C to +85°C

−65°C to +150°C

41°C/W

(150°C − T
15 mA

3

)/θJA mW2

A

For higher junction temperatures derate as follows:

TJ (°C) Max Continuous Load Current per Group (mA)

70 15.5
90 9.025
100 6.925
110 5.175
125 3.425
135 2.55
150 1.5

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. C | Page 8 of 20

AD5532

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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1234567891011

A
B
C
D

E

F
G
H

J
K

L

1234567891011

Figure 7. 74-Lead CSPBGA Ball Configuration

TOP VIEW

A
B
C
D
E
F
G
H
J
K
L

00939-C-028

Table 6. 74-Lead CSPBGA Ball Configuration

CSPBGA Number Ball Name CSPBGA Number Ball Name CSPBGA Number Ball Name

A1 Not connected C10 AVCC1 J10 VO9
A2 A4 C11 REF_OUT J11 VO11
A3 A2 D1 VO20 K1 VO17
A4 A0 D2 DAC_GND2 K2 VO15

CS

A5

/SYNC

D10 AV

2 K3 VO27

CC

A6 DVCC D11 OFFS_OUT K4 VSS3
A7 SCLK E1 VO26 K5 VSS1
A8 OFFSET_SEL E2 VO14 K6 VSS4

BUSY
TRACK

/RESET

E10 AGND1 K7 V

DD

E11 OFFS_IN K8 VO2

2

A9
A10
A11 Not connected F1 VO25 K9 VO10

B1 VO16 F2 VO21 K10 VO13
B2 Not connected F10 AGND2 K11 VO12
B3 A3 F11 VO6 L1 Not connected
B4 A1 G1 VO24 L2 VO28

WR

B5

G2 VO8 L3 VO29
B6 DGND G10 VO5 L4 VO30
B7 DIN G11 VO3 L5 VDD3
B8 CAL H1 VO23 L6 VDD1
B9

SER/PAR

H2 VIN L7 V

4

DD

B10 DOUT H10 VO4 L8 VO31
B11 REF_IN H11 VO7 L9 VO0
C1 VO18 J1 VO22 L10 VO1
C2 DAC_GND1 J2 VO19 L11 Not connected
C6 Not connected J6 VSS2

Rev. C | Page 9 of 20

AD5532

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Table 7. Pin Function Descriptions

Pin Function

AGND (1–2) Analog GND pins.
AVCC (1–2) Analog Supply pins. Voltage range from 4.75 V to 5.25 V.
VDD (1–4) VDD Supply pins. Voltage range from 8 V to 16.5 V.
VSS (1–4) VSS Supply pins. Voltage range from –4.75 V to –16.5 V.
DGND Digital GND pins.
DV

CC

DAC_GND (1–2) Reference GND supply for all DACs.
REF_IN Reference voltage for Channels 0–31.
REF_OUT Reference Output Voltage.
V

(0–31) Analog Output Voltages from the 32 channels.

OUT

V

IN

A4–A1, A0

CAL

CS/SYNC
WR Parallel interface: Write pin; active low. This is used in conjunction with the CS pin to address the device using the parallel

OFFSET_SEL

SCLK Serial Clock Input for Serial Interface. This operates at clock speeds up to 14 MHz (20 MHz in ISHA mode).
DIN

D

OUT

SER/PAR This pin allows the user to select whether the serial or parallel interface is used. If the pin is tied low, the parallel interface

OFFS_IN

OFFS_OUT Offset Output. This is the acquired/programmed offset voltage which can be tied to OFFS_IN to offset the span.
BUSY This output tells the user when the input voltage is being acquired. It goes low during acquisition and returns high when

TRACK/RESET If this input is held high, VIN is acquired once the channel is addressed. While it is held low, the input to the gain/offset

FULL-SCALE

ERROR RANGE

Digital Supply pins. Voltage range from 2.7 V to 5.25 V.

Analog Input Voltage. Connect this to AGND if operating in DAC mode only.
Parallel Interface: 5 address pins for 32 channels. A4 = MSB of channel address. A0 = LSB. Internal pull-up devices on these

logic inputs. Therefore, they can be left floating and default to a logic high condition.
Parallel Interface: Control input that allows all 32 channels to acquire V

simultaneously. Internal pull-down devices on

IN

these logic inputs. Therefore, they can be left floating and default to a logic low condition
This is the active low Chip Select pin for the parallel interface and the Frame Synchronization pin for the serial interface.

interface. Internal pull-down devices on these logic inputs. Therefore, they can be left floating and default to a logic low
condition.

Parallel interface: Offset Select pin; active high. This is used to select the offset channel. Internal pull-down devices on
these logic inputs. Therefore, they can be left floating and default to a logic low condition

Data Input for Serial Interface. Data must be valid on the falling edge of SCLK. Internal pull-up devices on these logic
inputs. Therefore, they can be left floating and default to a logic high condition.

Output from the DAC registers for read back. Data is clocked out on the rising edge of SCLK and is valid on the falling
edge of SCLK.

is used. If it is tied high, the serial interface is used. Internal pull-down devices on these logic inputs. Therefore, they can
be left floating and default to a logic low condition.

Offset Input. The user can supply a voltage here to offset the output span. OFFS_OUT can also be tied to this pin if the
user wants to drive this pin with the offset channel.

the acquisition operation is complete.

stage is switched directly to V

. The addressed channel begins to acquire VIN on the rising edge of TRACK. See TRACK

IN

Input section for further information. This input can also be used as a means of resetting the complete device to its
power-on-reset conditions. This is achieved by applying a low-going pulse of between 90 ns and 200 ns to this pin. See
section on RESET

Function for further details. Internal pull-up devices on these logic inputs. Therefore, they can be left

floating and default to a logic high condition.

OUTPUT

VOLTAGE

IDEAL GAIN

IDEAL TRANSFER
FUNCTION

OFFSET

RANGE

Figure 8. DAC Transfer Function (OFFS_IN=0)

IDEAL GAIN

0 16k

×

50mV

DAC CODE

×

REFIN

00939-C-007

OUT

0V

DEAD BAND

OFFSET

ERROR

LOWER

IDEAL

TRANSFER

FUNCTION

ACTUAL
TRANSFER
FUNCTION

70mV

Figure 9. ISHA Transfer Function

GAIN ERROR +
OFFSET ERROR

3V

2.96
UPPER

DEAD BAND

V

IN

00939-C-008

Rev. C | Page 10 of 20

AD5532

(

)

()(

(

)

−×=

(

(

)

×

−

−

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TERMINOLOGY

DAC MODE

Integral Nonlinearity (INL)

This is a measure of the maximum deviation from a straight
line passing through the endpoints of the DAC transfer
function. It is expressed as a percentage of full-scale span.

Differential Nonlinearity (DNL)

This is the difference between the measured change and the
ideal 1 LSB change between any two adjacent codes. A specified
DNL of ±1 LSB maximum ensures monotonicity.

Offset

Offset is a measure of the output with all zeros loaded to the
DAC and OFFS_IN = 0. Because the DAC is lifted off the
ground by approximately 50 mV, this output is typically

mV50×= GainV

CS

ScaleFullOUT

− )(

5/3/15532ADfor52.3

−−−=

25532ADfor7

−=

/

is high. It is specified in nV-secs

SYNC

REFINGainIdealVErrorScaleFull

×−=−

OUT

OUT

) of

) of

OUT

Full-Scale Error

This is a measure of the output error with all 1s loaded to the
DAC. It is expressed as a percentage of full-scale range. See
Figure 8. It is calculated as

where

GainIdeal

GainIdeal

Output Settling Time

This is the time taken from when the last data bit is clocked into
the DAC until the output has settled to within ±0.39%.

OFFS_IN Settling Time

The time taken from a 0 V to 3 V step change in input voltage
on OFFS_IN until the output has settled to within ±0.39%.

Digital-to-Analog Glitch Impulse

This is the area of the glitch injected into the analog output
when the code in the DAC register changes state. It is specified
as the area of the glitch in nV-secs when the digital code is
changed by 1 LSB at the major carry transition (011 . . . 11 to
100 . . . 00 or 100 . . . 00 to 011 . . . 11).

Digital Crosstalk

This is the glitch impulse transferred to the output of one DAC
at midscale while a full-scale code change (all 1s to all 0s and
vice versa) is written to another DAC. It is expressed in nV-secs.

Analog Crosstalk

This is the area of the glitch transferred to the output (V
one DAC due to a full-scale change in the output (V
another DAC. The area of the glitch is expressed in nV-secs.

Digital Feedthrough

This is a measure of the impulse injected into the analog
outputs from the digital control inputs when the part is not
being written to, i.e.,

and is measured with a worst-case change on the digital input
pins, for example, from all 0s to all 1s and vice versa.

Output Noise Spectral Density

This is a measure of internally generated random noise.
Random noise is characterized as a spectral density (voltage per
root Hertz). It is measured by loading all DACs to midscale and
measuring noise at the output. It is measured in nV/(√

Hz

).

Output Temperature Coefficient

This is a measure of the change in analog output with changes
in temperature. It is expressed in ppm/°C.

DC Power-Supply Rejection Ratio (PSRR)

DC power-supply rejection ratio is a measure of the change in
analog output for a change in supply voltage (V
expressed in dBs. V

and VSS are varied ±5%.

DD

and VSS). It is

DD

DC Crosstalk

This is the DC change in the output level of one DAC at
midscale in response to a full-scale code change (all 0s to all 1s
and vice versa) and an output change of all other DACs. It is
expressed in µV.

ISHA MODE

VIN to V

The measure of the maximum deviation from a straight line
passing through the endpoints of the V
function. It is expressed as a percentage of the full-scale span.

Offset Error

This is a measure of the output error when VIN = 70 mV. Ideally,
with V

Offset error is a measure of the difference between V
and V
negative. See Figure 9.

Gain Error

This is a measure of the span error of the analog channel. It is
the deviation in slope of the transfer function expressed in mV.
See Figure 9. It is calculated as

Gain Error =
Actual Full-Scale Output − Ideal Full-Scale Output − Offset Error

where:

AC Crosstalk

This is the area of the glitch that occurs on the output of one
channel while another channel is acquiring. It is expressed in
nV-secs.

Output Settling Time

This is the time taken from when
output has settled to ±0.018%.

Acquisition Time

This is the time taken for the VIN input to be acquired. It is the
length of time that

Nonlinearity

OUT

versus V

IN

= 70 mV:

IN

)

VGainGainV ×−

OUT

(ideal). It is expressed in mV and can be positive or

OUT

stays low.

BUSY

_ INOFFS

−×=

goes high to when the

BUSY

OUT

mV170

transfer

OUT

)

VGainGainOutputScaleFullIdeal

196.2

(actual)

INOFFS

_

Rev. C | Page 11 of 20

AD5532

www.BDTIC.com/ADI

TYPICAL PERFORMANCE CHARACTERISTICS

1.0
V

= 3V

REFIN

V

= 0V

OFFS_IN

T

= 25°C

A

0 12k10k8k6k4k2k 14k 16k

DAC CODE

Figure 10. Typical DNL Plot

DNL MAX

INL MAX

INL MIN

DNL MIN

0.2

0.1

0

–0.1

00939-C-009

INL ERROR (% FSR)

DNL ERROR (LSB)

DNL ERROR (LSB)

1.0

0.5

–0.5

0.8

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

0

3.535
TA = 25°C

V

= 3V

REFIN

3.530

(V)

OUT

V

3.525

3.520

6420–2–4–

10

TA = 25°C
V

REFIN

V

OFFS_IN

8

6

(V)

4

OUT

V

2

0

SINK/SOURCE CURRENT (mA)

Figure 13. V

= 3V

= 0.5V

Source and Sink Capability

OUT

00939-C-012

6

00939-C-010

–1.0

–40 40080

TEMPERATURE (°C)

–0.2

Figure 11. INL Error an DNL Error vs. Temperature

5.325
DAC LOADED TO MIDSCALE
V

= 3V

REFIN

V

= 0V

OFFS_IN

5.315

5.305

(V)

OUT

V

5.295

5.285

5.275

–40 4008

TEMPERATURE (°C)

Figure 12. V

vs. Temperature

OUT

0

00939-C-011

–2

TIME BASE (2µs/DIV)

Figure 14. Full-Scale Settling Time

5.309

5.308

5.307

5.306

(V)

5.305

OUT

V

5.304

5.303
TA = 25°C

V

REFIN

V

OFFS_IN

= 3V

= 0V

TIME BASE (50ns/DIV)

5.302

5.301

Figure 15. Major Code Transition Glitch Impulse

00939-C-013

00939-C-014

Rev. C | Page 12 of 20

AD5532

www.BDTIC.com/ADI

0.024
TA = 25°C

0.020

V

= 3V

REFIN

V

= 0V

OFFS_IN

0.016

0.012

0.008

0.004

0

ERROR (%)

–0.004

OUT

V

–0.008
–0.012
–0.016
–0.020
–0.024

0.10 2.96

to V

Figure 16. V

Accuracy after Offset and Gain Adjustment (ISHA

IN

OUT

VIN (V)

Mode)

5V

00939-C-015

FREQUENCY

70k

60k

50k

40k

30k

20k

10k

63791

200

0

5.2670 5.2676 5.2682
V

(V)

OUT

TA = 25°C
V
V
V

Figure 18. ISHA-Mode Repeatability (64 k Acquisitions)

REFIN

= 1.5V

IN
OFFS_IN

= 3V

1545

= 0V

00939-C-017

100

90

V

OUT

10

0%

BUSY

TA = 25°C
V

REFIN

= 0→1.5V

V

IN

2µs1V

= 3V

00939-C-016

Figure 17. Acquisition Time and Output Settling Time (ISHA Mode)

Rev. C | Page 13 of 20

AD5532

www.BDTIC.com/ADI

FUNCTIONAL DESCRIPTION

The AD5532 consists of 32 DACs and an ADC (for ISHA
mode) in a single package. In DAC mode, a 14-bit digital word
is loaded into one of the 32 DAC Registers via the serial
interface. This is then converted (with gain and offset) into an

0–V

analog output voltage (V

OUT

To update a DAC’s output voltage, the required DAC is
addressed via the serial port. When the DAC address and code
have been loaded, the selected DAC converts the code.

At power-on, all the DACs, including the offset channel, are
loaded with zeros. Each of the 33 DACs is offset internally by
50 mV (typ) from GND, so the outputs V
50 mV (typ) at power-on if the OFFS_IN pin is driven directly
by the on-board offset channel (OFFS_OUT), i.e. if OFFS_IN is
50 mV, V

= (Gain × V

OUT

DAC

OUTPUT BUFFER STAGE—GAIN AND OFFSET

The function of the output buffer stage is to translate the 50
mV–3 V output of the DAC to a wider range. This is done by
gaining up the DAC output by 3.52/7 and offsetting the voltage
by the voltage on OFFS_IN pin.

AD5532-1/AD5532-3/AD5532-5:

OUT

AD5532-2:

OUT

V

is the output of the DAC.

DAC

V

is the voltage at the OFFS_IN pin.

OFFS_IN

67 ×−×=

The following table shows how the output range on V
to the offset voltage supplied by the user.

Table 8. Sample Output Voltage Ranges

V

OFFS_IN VDAC

V

OUT

(V) (V) (AD5532-1/-3/-5) (AD5532-2)

0.5 0.05 to 3
1 0.05 to 3

−1.26 to +9.3

−2.52 to +8.04 −6 to +15

is limited only by the headroom of the output amplifiers.

V

OUT

V

must be within maximum ratings.

OUT

OFFSET VOLTAGE CHANNEL

The offset voltage can be externally supplied by the user at
OFFS_IN or it can be supplied by an additional offset voltage
channel on the device itself. The offset can be set up in two
ways. In ISHA mode, the required offset voltage is set up on V
and acquired by the offset channel. In DAC mode, the code
corresponding to the offset value is loaded directly into the
offset DAC. This offset channel’s DAC output is directly
connected to OFFS_OUT. By connecting OFFS_OUT to

31).

OUT

OUT

) – (Gain – 1) ×V

VVV

52.252.3 ×−×=

VVV

_

INOFFSDAC

_

INOFFSDAC

V

0 to V

OFFS_IN

OUT

OUT

= 50 mV.

31 are

relates

OUT

Headroom limited

IN

OFFS_IN this offset voltage can be used as the offset voltage for
the 32 output amplifiers. It is important to choose the offset so
that V

is within maximum ratings.

OUT

RESET FUNCTION

The reset function on the AD5532 can be used to reset all
nodes on this device to their power-on reset condition. This is
implemented by applying a low-going pulse of between 90 ns
and 200 ns to the

TRACK

/

pin on the device. If the

RESET

applied pulse is less than 90 ns, it is assumed to be a glitch
and no operation takes place. If the applied pulse is wider
than 200 ns, this pin adopts its track function on the selected
channel, V
on the channel does not occur until a rising edge of

is switched to the output buffer, and an acquisition

IN

TRACK

.

ISHA MODE

In ISHA mode, the input voltage VIN is sampled and converted
into a digital word. The noninverting input to the output buffer
(gain and offset stage) is tied to V

during the acquisition

IN

period to avoid spurious outputs, while the DAC acquires the
correct code. This is completed in 16 µs max. The updated DAC
output then assumes control of the output voltage. The output
voltage of the DAC is connected to the noninverting input of
the output buffer. Because the channel output voltage is
effectively the output of a DAC, there is no droop associated
with it. As long as power is maintained to the device, the output
voltage is constant until this channel is addressed again. Because
the internal DACs are offset by 70 mV (max) from GND, the
minimum V

in ISHA mode is 70 mV. The maximum VIN is

IN

2.96 V due to the upper dead band of 40 mV (max).

ANALOG INPUT (ISHA MODE)

Figure 19 shows the equivalent analog input circuit. The
Capacitor C1 is typically 20 pF and can be attributed to pin
capacitance and 32 off-channels. When a channel is selected, an
extra 7.5 pF (typ) is switched in. This Capacitor C2 is charged to
the previously acquired voltage on that particular channel so it
must charge/discharge to the new level. The external source
must be able to charge/discharge this additional capacitance

C2

7.5pF

can be

IN

00939-C-018

within 1 µs–2 µs of channel selection so that V
acquired accurately. Thus, a low impedance source is suggested.

ADDRESSED CHANNEL

V

IN

C1
20pF

Figure 19. Analog Input Circuit

Large source impedances significantly affect the performance
of the ADC. An input buffer amplifier may be required.

Rev. C | Page 14 of 20

AD5532

www.BDTIC.com/ADI

TRACK

Typically in ISHA mode of operation

FUNCTION (ISHA MODE)

TRACK

is held high and

the channel begins to acquire when it is addressed. However, if
TRACK

is low when the channel is addressed, VIN is switched to

the output buffer and an acquisition on the channel does not
occur until a rising edge of

TRACK

. At this stage, the

BUSY

pin

goes low until the acquisition is complete, at which point the
DAC assumes control of the voltage to the output buffer and V

IN

is free to change again without affecting this output value.

This is useful in an application where the user wants to ramp up
V

IN

until V

reaches a particular level (see Figure 20). VIN does

OUT

not need to be acquired continuously while it is ramping up.
TRACK

can be kept low and only when V
desired voltage is
acquisition of V

TRACK

begins.

IN

brought high. At this stage, the

has reached its

OUT

In the example shown, a desired voltage is required on the
output of the pin driver. This voltage is represented by one input
to a comparator. The microcontroller/microprocessor ramps up
the input voltage on V

while the voltage on V

through a DAC.

IN

ramps up so that VIN is not continually

IN

TRACK

is kept low

acquired. When the desired voltage is reached on the output of
the pin driver, the comparator output switches. The µC/µP then
knows what code is required to be input to obtain the desired
voltage at the DUT. The

TRACK
the part begins to acquire V
V

has been acquired. The output buffer is then switched from

IN

to the output of the DAC.

V

IN

input is now brought high and

. At this stage

IN

goes low until

BUSY

MODES OF OPERATION

The AD5532 can be used in four different modes of operation.
These modes are set by two mode bits, the first two bits in the
serial word.

Table 9. Modes of Operation

Mode Bit 1 Mode Bit 2 Operating Mode

0 0 ISHA mode
0 1 DAC mode
1 0 Acquire and Read Back
1 1 Read Back

V

CONTROLLER

DAC

IN

BUSY

TRACK

ACQUISITION

CIRCUIT

ONLY ONE CHANNEL SHOWN FOR SIMPLICITY

Figure 20. Typical ATE Circuit Using

1. ISHA Mode

In this mode, a channel is addressed and that channel acquires
the voltage on V
21a) to address the relevant channel (V

. This mode requires a 10-bit write (see Figure

IN

0–V

OUT

31, offset

OUT

channel or all channels). MSB is written first.

2. DAC Mode

In this standard mode, a selected DAC register is loaded serially.
This requires a 24-bit write (10 bits to address the relevant DAC
plus an extra 14 bits of DAC data). MSB is written first. The user
must allow 400 ns (min) between successive writes in DAC
mode.

3. Acquire and Readback Mode

This mode allows the user to acquire VIN and read back the data
in a particular DAC register. The relevant channel is addressed
(10-bit write, MSB first) and V
Following the acquisition, after the next falling edge of

is acquired in 16 µs (max).

IN

SYNC

,

the data in the relevant DAC register is clocked out onto the
D

line in a 14-bit serial format. The full acquisition time

OUT

must elapse before the DAC register data can be clocked out.

4. Readback Mode

Again, this is a Readback mode but no acquisition is performed.
The relevant channel is addressed (10-bit write, MSB first) and
on the next falling edge of

register is clocked out onto the D

, the data in the relevant DAC

SYNC

line in a 14-bit serial

OUT

format. The user must allow 400 ns (min) between the last
SCLK falling edge in the 10-bit write and the falling edge of

in the 14-bit read back. The serial write and read words

SYNC
can be seen in Figure 21.

This feature allows the user to read back the DAC register code
of any of the channels. In DAC mode, this is useful in
verification of write cycles. In ISHA mode, readback is useful if
the system has been calibrated and the user wants to know what
code in the DAC corresponds to a desired voltage on V

OUT

. If
this voltage is required again, the user can input the code
directly to the DAC register without going through the
acquisition sequence.

PIN

DRIVER

V

1

OUTPUT

STAGE

AD5532

TRACK

OUT

Input

THRESHOLD

VOLTAGE

DEVICE
UNDER
TEST

00939-C-019

Rev. C | Page 15 of 20

AD5532

www.BDTIC.com/ADI

SERIAL INTERFACE

The serial interface allows easy interfacing to most micro­controllers and DSPs, such as the PIC16C, PIC17C, QSPI, SPI,
DSP56000, TMS320, and ADSP-21xx, without the need for any
glue logic. When interfacing to the 8051, the SCLK must be
inverted. The Microprocessor Interfacing section explains how
to interface to some popular DSPs and microcontrollers. Figure
4, Figure 5, and Figure 6 show the timing diagram for a serial
read and write to the AD5532. The serial interface works with
both a continuous and a noncontinuous serial clock. The first
falling edge of

serial clocks to ensure the correct number of bits are shifted in
and out of the serial shift registers. Any further edges on

are ignored until the correct number of bits are shifted in or out.
Once the correct number of bits for the selected mode has been
shifted in or out, the SCLK is ignored. In order for another
serial transfer to take place the counter must be reset by the
falling edge of

In readback, the first rising SCLK edge after the falling edge of

causes D

SYNC
clocked out onto the D

rising edges. The D
state on the falling edge of the 14th SCLK. Data on the D
is latched in on the first SCLK falling edge after the falling edge
of the

signal and on subsequent SCLK falling edges.

SYNC

During read-back D

resets a counter that counts the number of

SYNC

.

SYNC

to leave its high impedance state and data is

OUT

line and also on subsequent SCLK

OUT

pin goes back into a high impedance

OUT

is ignored. The serial interface does

IN

MSB LSB

MODE BIT 1 MODE BIT 2

MODE BITS

a. 10-BIT SERIAL WRITE WORD (ISHA MODE)

MSB LSB

CAL10

MODE BITS

b. 24-BIT INPUT SERIAL WRITE WORD (DAC MODE)

SYNC

line

IN

CAL00

OFFSET_SEL

not shift data in or out until it receives the falling edge of the
SYNC

Table 10

Pin Description

SER/PAR This pin is tied high to enable the serial interface

SYNC,
DIN, SCLK

D

OUT

Mode
Bits

Cal Bit

Offset Sel
Bit

Test Bit Must be set low for correct operation of the part.
A4–A0

DB13–
DB0

OFFSET_SEL A4–A0

0

TEST BIT

signal.

and to disable the parallel interface. The serial
interface is controlled by the four pins that follow.

Standard 3-wire interface pins. The SYNC pin is
shared with the CS function of the parallel interface.

Data Out pin for reading back the contents of the
DAC registers. The data is clocked out on the rising
edge of SCLK and is valid on the falling edge of
SCLK.

The four different modes of operation are described
in the Modes of Operation section.

In DAC mode, this is a test bit. When high, it loads all
0s or all 1s to the 32 DACs simultaneously. In ISHA
mode, all 32 channels acquire V

at the same time

IN

when this bit is high. In ISHA mode, the acquisition
time is then 45 µs (typ) and accuracy may be
reduced. This bit is set low for normal use.

If this is set high, the offset channel is selected and
Bits A4–A0 are ignored.

Used to address any one of the 32 channels
(A4 = MSB of address, A0 = LSB).

Used to write a 14-bit word into the addressed DAC
register. Only valid when in DAC mode.

0

TEST BIT

A4–A0

DB13–DB0

MSB LSB

OFFSET_SEL A4–A0CAL01

MODE BITS

c. INPUT SERIAL INTERFACE (ACQUIRE AND READ-BACK MODE)

MSB LSB

MODE BITS

10-BIT

SERIAL WORD

WRITTEN TO PART

OFFSET_SEL

10-BIT

SERIAL WORD

WRITTEN TO PART

d. INPUT SERIAL INTERFACE (READ-BACK MODE)

Figure 21. Serial Interface Formats

TEST BIT

A4–A0CAL11

TEST BIT

Rev. C | Page 16 of 20

MSBLSB

DB13–DB00

14-BIT DATA

READ FROM PART AFTER

NEXT FALLING EDGE OF SYNC

(DB13 = MSB OF DAC WORD)

MSBLSB

DB13–DB00

14-BIT DATA

READ FROM PART AFTER

NEXT FALLING EDGE OF SYNC

(DB13 = MSB OF DAC WORD)

00939-C-020

AD5532

www.BDTIC.com/ADI

PARALLEL INTERFACE (ISHA MODE ONLY)

The SER/
interface and disable the serial interface. The parallel interface is

controlled by nine pins, as described in Table 11.

Table 11.

Pin Description

CS Active low package select pin. This pin is shared

WR Active low write pin. The values on the address

A4–A0

OFFSET_SEL

CAL

MICROPROCESSOR INTERFACING

AD5532 to ADSP-21xx Interface

ADSP-21xx DSPs are easily interfaced to the AD5532 without
the need for extra logic.

A data transfer is initiated by writing a word to the TX register
after the SPORT has been enabled. In a write sequence, data is
clocked out on each rising edge of the DSP serial clock and
clocked into the AD5532 on the falling edge of its SCLK. In
readback, 16 bits of data are clocked out of the AD5532 on each
rising edge of SCLK and clocked into the DSP on the rising
edge of SCLK. D
centered in the 16-bit RX register in this configuration. The
SPORT Control register should be set up as in Table 12.

Table 12.

TFSW = RFSW = 1 Alternate framing
INVRFS = INVTFS = 1 Active low frame signal
DTYPE = 00 Right justify data
ISCLK = 1 Internal serial clock
TFSR = RFSR = 1 Frame every word
IRFS = 0 External framing signal
ITFS = 1 Internal framing signal
SLEN = 1001 10-bit data-words (ISHA mode write)
SLEN = 0111 3 × 8-bit data-words (DAC mode write)
SLEN = 1111 16-bit data-words (Readback mode)

bit must be tied low to enable the parallel

PA R

with the SYNC

function for the serial interface.

pins are latched on a rising edge of WR
Five address pins (A4 = MSB of address,

A0 = LSB). These are used to address the
relevant channel (out of a possible 32).

Offset select pin. This has the same function as
the Offset_Sel bit in the serial interface. When it
is high, the offset channel is addressed. The
address on A4–A0 is ignored in this case.

When this pin is high, all 32 channels acquire
VIN simultaneously. The acquisition time is then
45 µs (typ) and accuracy may be reduced.

is ignored. The valid 14 bits of data is

IN

Figure 22 shows the connection diagram.

AD5532*

D

OUT

SYNC

D

IN

SCLK

.

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 22. AD5532 to ADSP-2101/ADSP-2103 Interface

ADSP-2101/

ADSP-2103*

DR
TFS
RFS
DT
SCLK

00939-C-021

AD5532 to MC68HC11

The serial peripheral interface (SPI) on the MC68HC11 is
configured for master mode (MSTR) = 1, clock polarity bit
(CPOL) = 0, and the clock phase bit (CPHA) = 1. The SPI is
configured by writing to the SPI control register (SPCR)—see

68HC11 User Manual. SCK of the 68HC11 drives the SCLK

the
of the AD5532, the MOSI output drives the serial data line (D
of the AD5532, and the MISO input is driven from D

signal is derived from a port line (PC7). When data is

SYNC
being transmitted to the AD5532, the

line is taken low

SYNC

OUT

IN

. The

(PC7). Data appearing on the MOSI output is valid on the
falling edge of SCK. Serial data from the 68HC11 is transmitted
in 8-bit bytes with only eight falling clock edges occurring in
the transmit cycle. Data is transmitted MSB first. To transmit
10 data bits in ISHA mode, it is important to left-justify the data
in the SPDR register. PC7 must be pulled low to start a transfer.
It is taken high and pulled low again before other read/write
cycles can take place. Figure 23 shows a connection diagram.

AD5532*

D

OUT

SCLK SCK

D

IN

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 23. AD5532 to MC68HC11 Interface

MC68HC11*

MISO

PC7SYNC

MOSI

00939-C-022

)

Rev. C | Page 17 of 20

AD5532

www.BDTIC.com/ADI

AD5532 to PIC16C6x/7x

The PIC16C6x/7x synchronous serial port (SSP) is configured
as an SPI master with the Clock Polarity Bit = 0. This is done by
writing to the synchronous serial port control register
(SSPCON). See the
this example, the I/O port RA1 is being used to pulse

and enable the serial port of the AD5532. This microcontroller
transfers only eight bits of data during each serial transfer
operation; therefore, two or three consecutive read/write
operations are needed depending on the mode. Figure 24
shows the connection diagram.

PIC16/17 Microcontroller User Manual. In

SYNC

The AD5532 has several advantages: no refreshing is required,
there is no droop, pedestal error is eliminated, and there is no
need for extra filtering to remove glitches. Overall a higher level
of integration is achieved in a smaller area (see Figure 26).

DAC

DAC

DAC

ACTIVE

LOAD

PARAMETRIC

MEASUREMENT

UNIT

SYSTEM BUS

AD5532*

SCLK SCK/RC3

D

OUT

D

IN

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 24. AD5532 to PIC16C6x/7x Interface

PIC16C6x/7x*

SDO/RC5

SDI/RC4

RA1SYNC

00939-C-023

AD5532 to 8051

The AD5532 requires a clock synchronized to the serial data.
The 8051 serial interface must therefore be operated in Mode 0.
In this mode, serial data enters and exits through RxD and a
shift clock is output on TxD. Figure 25 shows how the 8051 is
connected to the AD5532. Because the AD5532 shifts data out
on the rising edge of the shift clock and latches data in on the
falling edge, the shift clock must be inverted. The AD5532
requires its data with the MSB first. Because the 8051 outputs
the LSB first, the transmit routine must take this into account.

AD5532*

SCLK TxD

D

OUT

D

IN

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 25. AD5532 to 8051 Interface

8051*

RxD

P1.1SYNC

00939-C-024

APPLICATION CIRCUITS

AD5532 in a Typical ATE System

The AD5532 is ideally suited for use in automatic test
equipment. Several DACs are required to control pin drivers,
comparators, active loads, and signal timing. Traditionally,
sample-and-hold devices were used in this application.

STORED

DATA

AND INHIBIT

PATTERN

PERIOD

GENERATION

AND
DELAY
TIMING

DACs

FORMATTER

COMPARE
REGISTER

SYSTEM BUS

DRIVER

COMPARATOR

DAC

DAC

DUT

DAC

DAC

Figure 26. AD5532 in an ATE System

Typical Application Circuit (DAC Mode)

The AD5532 can be used in many optical networking
applications that require a large number of DACs to perform
control and measurement functions. In the example shown in
Figure 27, the outputs of the AD5532 are amplified and used to
control actuators that determine the position of MEMS mirrors
in an optical switch. The exact position of each mirror is
measured using sensors. The sensor readings are muxed using
four dual, 4-channel matrix switches (ADG739) and fed back to
an 8-channel, 14-bit ADC (AD7856).

The control loop is driven by an ADSP-2191M, a 16-bit fixed­point DSP with 3 SPORT interfaces and 2 SPI ports. The DSP
uses some of these serial ports to write data to the DAC, control
the multiplexer, and read back data from the ADC.

S

1

E
N
S
O

32

R

ADSP-2191M

ADG739

×4

1

8

AD8544

×2

AD7856

AD5532

1

MEMS

MIRROR

ARRAY

32

Figure 27. Typical Optical Control and Measurement Application Circuit

00939-C-025

00939-C-026

Rev. C | Page 18 of 20

AD5532

www.BDTIC.com/ADI

Typical Application Circuit (ISHA Mode)

The AD5532 can be used to set up voltage levels on 32 channels
as shown in the circuit that follows. An AD780 provides the 3 V
reference for the AD5532 and for the AD5541 16-bit DAC. A
simple 3-wire interface is used to write to the AD5541. Because
the AD5541 has an output resistance of 6.25 k
taken to charge/discharge the capacitance at the V

Ω(typ), the time

pin is

IN

significant. Hence an AD820 is used to buffer the DAC output.
Note that it is important to minimize noise on V

and REFIN

IN

when laying out the circuit.

DIN

SCLK

AV

CC

V

DD

REF

V

AD820

OUT

CS

AD5541*

AD780*

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 28. Typical Application Circuit (ISHA Mode)

AVCCDV

V

IN

AD5532*

OFFS_IN
OFFS_OUT
REFIN

SCLK DIN SYNC

V

CC

SS

V

0–V

OUT

OUT

POWER SUPPLY DECOUPLING

In any circuit where accuracy is important, careful
consideration of the power supply and ground return layout
helps to ensure the rated performance. The printed circuit
board on which the AD5532 is mounted should be designed so
that the analog and digital sections are separated and confined
to certain areas of the board. If the AD5532 is in a system where
multiple devices require an AGND-to-DGND connection, the
connection should be made at one point only. The star ground
point should be established as close as possible to the device.
For supplies with multiple pins (V
mended to tie those pins together. The AD5532 should have
ample supply bypassing of 10 µF in parallel with 0.1 µF on each
supply located as close to the package as possible, ideally right
up against the device. The 10 µF capacitors are the tantalum
bead type. The 0.1 µF capacitor should have low effective series
resistance (ESR) and effective series inductance (ESI), such as
the common ceramic types that provide a low impedance path
to ground at high frequencies, to handle transient currents due
to internal logic switching.

, VDD, AVCC) it is recom-

SS

31

00939-C-027

The power supply lines of the AD5532 should use as large a
trace as possible to provide low impedance paths and reduce the
effects of glitches on the power supply line. Fast switching
signals, such as clocks, should be shielded with digital ground to
avoid radiating noise to other parts of the board and should
never be run near the reference inputs. A ground line routed
between the D

and SCLK lines helps reduce crosstalk between

IN

them (not required on a multilayer board as there is a separate
ground plane, but separating the lines helps).

Note it is essential to minimize noise on V

and REFIN lines.

IN

Particularly for optimum ISHA performance, the V
be kept noise free. Depending on the noise performance of the
board, a noise filtering capacitor may be required on the V
line. If this capacitor is necessary, then for optimum throughput
it may be necessary to buffer the source which is driving V
Avoid crossover of digital and analog signals. Traces on opposite
sides of the board should run at right angles to each other. This
reduces the effects of feedthrough through the board. A micro­strip technique is by far the best, but not always possible with a
double-sided board. In this technique, the component side of
the board is dedicated to ground plane while signal traces are
placed on the solder side.

As is the case for all thin packages, care must be taken to avoid
flexing the package and to avoid a point load on the surface of
the package during the assembly process.

line must

IN

IN

.

IN

Rev. C | Page 19 of 20

AD5532

www.BDTIC.com/ADI

OUTLINE DIMENSIONS

A1 CORNER

12.00

1.70

MAX

BSC SQ

A1

TOP VIEW

DETAIL A

COMPLIANT TO JEDEC STANDARDS MO-192ABD-11

Figure 29. 74-Lead Chip Scale Ball Grid Array [CSPBGA]

Dimensions shown in millimeters

1110987654321

1.00

BSC

0.30 MIN

(BC-74)

ORDERING GUIDE

Model

AD5532ABC-1
AD5532ABC-1REEL
AD5532ABC-2
AD5532ABC-3
AD5532ABC-3REEL
AD5532ABC-5
AD5532ABC-5REEL

Range Function

−40°C to + 85°C

−40°C to + 85°C

−40°C to + 85°C

−40°C to + 85°C

−40°C to + 85°C

−40°C to + 85°C

−40°C to + 85°C

32 DACs, 32-channel ISHA 0.5 Ω typ 10 V 74-lead CSPBGA BC-74
32 DACs, 32-channel ISHA 0.5 Ω typ 10 V 74-lead CSPBGA BC-74
32 DACs, 32-channel ISHA 0.5 Ω typ 20 V 74-lead CSPBGA BC-74
32 DACs, 32-channel ISHA 500 Ω typ 10 V 74-lead CSPBGA BC-74
32 DACs, 32-channel ISHA 500 Ω typ 10 V 74-lead CSPBGA BC-74
32 DACs, 32-channel ISHA 1 kΩ typ 10 V 74-lead CSPBGA BC-74
32 DACs, 32-channel ISHA 1 kΩ typ 10 V 74-lead CSPBGA BC-74

EVAL-AD5532EB Evaluation Board

Temperature

Output
Impedance

INDEX AREA

BOTTOM

VIEW

1.00 BSC

DETAIL A

0.70

0.60

0.50

BALL DIAMETER

Output Voltage
Span

SEATING
PLANE

A
B
C
D

10.00

E

BSC SQ

F
G
H
J
K
L

0.20 MAX
COPLANARITY

Package
Description

Package
Option

© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.

C00939-0-6/04(C)

Rev. C | Page 20 of 20