Datasheet AD5532 Datasheet (Analog Devices)

32-Channel, 14-Bit

a

FEATURES
High Integration: 32-Channel DAC in 12 ⴛ 12 mm
Adjustable Voltage Output Range
Guaranteed Monotonic
Readback Capability
DSP-/Microcontroller-Compatible Serial Interface
Output Impedance

0.5 ⍀ (AD5532-1, AD5532-2)
500 ⍀ (AD5532-3)
1 k⍀ (AD5532-5)

Output Voltage Span

10 V (AD5532-1, AD5532-3, AD5532-5)

20 V (AD5532-2)
Infinite Sample-and-Hold Capability to ⴞ0.018% Accuracy
Temperature Range –40ⴗC to +85ⴗC

APPLICATIONS
Level Setting
Instrumentation
Automatic Test Equipment
Industrial Control Systems
Data Acquisition
Low Cost I/O

2

LFBGA

Voltage-Output DAC

AD5532*

GENERAL DESCRIPTION

The AD5532 is a 32-channel voltage-output 14-bit DAC with
an additional infinite sample-and-hold mode. The selected DAC
register is written to via the 3-wire serial interface and V
for this DAC is then updated to reflect the new contents of the
DAC register. DAC selection is accomplished via address bits
A0–A4. The output voltage range is determined by the offset
voltage at the OFFS_IN pin and the gain of the output amplifier.
It is restricted to a range from V

SS

+ 2 V to V

– 2 V because

DD

of the headroom of the output amplifier.

The device is operated with AV
to 5.25 V, V

= –4.75 V to –16.5 V and VDD = 8 V to 16.5 V

SS

= 5 V ± 5%, DVCC = 2.7 V

CC

and requires a stable +3 V reference on REF_IN as well as an
offset voltage on OFFS_IN.

PRODUCT HIGHLIGHTS

1. 32-channel, 14-bit DAC in one package, guaranteed
monotonic.

2. The AD5532 is available in a 74-lead LFBGA package with
a body size of 12 mm × 12 mm.

3. Droopless/Infinite Sample-and-Hold Mode.

OUT

FUNCTIONAL BLOCK DIAGRAM

DV

AV

CC

AD5532

V

IN

TRACK /RESET

BUSY

GND

DAC

AGND

DGND

SER / PAR

*Protected by U.S. Patent No. 5,969,657; other patents pending.

ADC

MUX DAC

MODE

INTERFACE

CONTROL

LOGIC

SCLK

DIND

REF IN REF OUT

CC

14-BIT BUS

OUT

DAC

DAC

SYNC / CS

OFFS IN

ADDRESS INPUT REGISTER

CALA4– A0

VDDV

OFFSET SEL

SS

V

0

OUT

V

31

OUT

OFFS OUT

WR

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 2000

AD5532–SPECIFICATIONS

5.25 V; AGND = DGND = DAC_GND = 0 V; REF_IN = 3 V; Output Range from V
to T

unless otherwise noted.)

MAX

Parameter

1

(VDD = 8 V to 16.5 V, VSS = –4.75 V to –16.5 V; AVCC = 4.75 V to 5.25 V; DVCC = 2.7 V to

+ 2 V to VDD – 2 V. All outputs unloaded. All specifications T

SS

A Version
AD5532-1/-3/-5 AD5532-2 Only Unit Comments

2

Conditions/

DAC DC PERFORMANCE

Resolution 14 14 Bits
Integral Nonlinearity (INL) ±0.39 ±0.39 % of FSR max ±0.15% typ
Differential Nonlinearity (DNL) ±1 ±1 LSB max ±0.5% typ, Monotonic
Offset 90/170/250 180/350/500 mV min/typ/max See Figure 6
Gain 3.52 7 typ
Full-Scale Error ±2 ±2 % of FSR max

VOLTAGE REFERENCE

REF_IN

Nominal Input Voltage 3.0 3.0 V
Input Voltage Range

3

2.85/3.15 2.85/3.15 V min/max

Input Current 1 1 µA max < 1 nA typ

REF_OUT

Output Voltage 3 3 V typ
Output Impedance
Reference Temperature Coefficient

ANALOG OUTPUTS (V

Output Temperature Coefficient
DC Output Impedance

3

3

0–31)

OUT

3

3, 4

280 280 kΩ typ
60 60 ppm/°C typ

20 20 ppm/°C typ

AD5532-1 0.5 0.5 Ω typ
AD5532-3 500 Ω typ
AD5532-5 1 kΩ typ

Output Range V
Resistive Load
Capacitive Load

3, 5

3, 5

+ 2/VDD – 2 VSS + 2 /VDD – 2 V min/max 100 µA Output Load

SS

55 kΩ min

AD5532-1 500 500 pF max
AD5532-3 15 nF max

AD5532-5 40 nF max
Short-Circuit Current
DC Power-Supply Rejection Ratio

DC Crosstalk

3

ANALOG OUTPUT (OFFS_OUT)

Output Temperature Coefficient
DC Output Impedance

3

3

10 10 mA typ
–70 –70 dB typ VDD = +15 V ± 5%
–70 –70 dB typ V

= –15 V ± 5%

SS

250 250 µV max

3, 4

3

20 20 ppm/°C typ

1.3 1.3 kΩ typ

Output Range 50 to REF_IN–12 50 to REF_IN–12 mV typ
Output Current 10 10 µA max Source Current
Capacitive Load 100 100 pF max

DIGITAL INPUTS

3

Input Current ± 10 ±10 µA max ± 5 µA typ
Input Low Voltage 0.8 0.8 V max DVCC = 5 V ± 5%

0.4 0.4 V max DV

= 3 V ± 10%

CC

Input High Voltage 2.4 2.4 V min DVCC = 5 V ± 5%

2.0 2.0 V min DV

= 3 V ± 10%

CC

Input Hysteresis (SCLK and CS Only) 200 200 mV typ
Input Capacitance 10 10 pF max

DIGITAL OUTPUTS (BUSY, D

OUT

3

)
Output Low Voltage, DVCC = 5 V 0.4 0.4 V max Sinking 200 µA
Output High Voltage, DVCC = 5 V 4.0 4.0 V min Sourcing 200 µA
Output Low Voltage, DV

= 3 V 0.4 0.4 V max Sinking 200 µA

CC

Output High Voltage, DVCC = 3 V 2.4 2.4 V min Sourcing 200 µA
High Impedance Leakage Current ±1 ±1 µA max D
High Impedance Output Capacitance 15 15 pF typ D

OUT

OUT

Only
Only

MIN

–2–

REV. 0

AD5532

A Version
AD5532-1/-3/-5 AD5532-2 Only Unit Comments

Parameter

1

POWER REQUIREMENTS

Power-Supply Voltages

V

DD

V

SS

AV

CC

DV

CC

Power-Supply Currents

I

DD

I

SS

6

8/16.5 8/16.5 V min/max
–4.75/–16.5 –4.75/–16.5 V min/max

4.75/5.25 4.75/5.25 V min/max

2.7/5.25 2.7/5.25 V min/max

15 15 mA max 10 mA typ.

15 15 mA max 10 mA typ.

AICC 33 33 mA max 26 mA typ
DICC 1.5 1.5 mA max 1 mA typ

Power Dissipation

AC CHARACTERISTICS

6

3

280 280 mW typ VDD = 10 V, VSS = –5 V

Output Voltage Settling Time 22 30 µs max 500 pF, 5 kΩ Load

OFFS_IN Settling Time 10 20 µs max 500 pF, 5 kΩ Load;

Digital-to-Analog Glitch Impulse 1 1 nV-s typ 1 LSB Change Around

Digital Crosstalk 5 5 nV-s typ
Analog Crosstalk 1 1 nV-s typ
Digital Feedthrough 0.2 0.2 nV-s typ
Output Noise Spectral Density @ 1 kHz 400 400 nV/(√Hz) typ

NOTES

1

See Terminology.

2

A Version: Industrial temperature range –40°C to +85°C; typical at +25° C.

3

Guaranteed by design and characterization, not production tested.

4

AD780 as reference for the AD5532.

2

Conditions/

All Channels Full-Scale

All Channels Full-Scale

Full-Scale Change

0 V–3 V Step

Major Carry

5

Ensure that you do not exceed TJ (max). See Maximum Ratings.

6

Output unloaded.

Specifications subject to change without noti

ce.

SHA MODE

Parameter

1

ANALOG CHANNEL

to V

V

IN

Nonlinearity

OUT

3

A Version
AD5532-1/-3/-5 AD5532-2 Only Unit Comments

±0.018 ± 0.018 % max ±0.006% typ after Offset and

Offset Error ± 50 ±100 mV max ±10 mV typ. See Figure 7
Gain 3.46/3.52/3.6 6.88/7/7.12 min/typ/max See Figure 7

ANALOG INPUT (V

)

IN

Input Voltage Range 0 to 3 0 to 3 V Nominal Input Range
Input Lower Deadband 70 70 mV max 50 mV typ. Referred to V

Input Upper Deadband 40 40 mV max 12 mV typ. Referred to V

Input Current 1 1 µA max 100 nA typ.

Input Capacitance

4

20 20 pF typ

ANALOG INPUT (OFFS_IN)

Input Current 1 1 µA max 100 nA typ

AC CHARACTERISTICS

Output Settling Time
Acquisition Time 16 16 µs max
AC Crosstalk

NOTES

1

S

ee Terminology.

2

A version: Industrial temperature range –40°C to +85°C; typical at +25°C.

3

Input range 100 mV to 2.96 V.

4

Guaranteed by design and characterization, not production tested.

Specifications subject to change

4

4

without notice.

33 µs max Output Unloaded

5 5 nV-s typ

2

Conditions/

Gain Adjustment

See Figure 7

See Figure 7

V

Acquired on 1 Channel

IN

.

IN

.

IN

REV. 0

–3–

AD5532

TIMING CHARACTERISTICS

PARALLEL INTERFACE

Parameter

t

1

t

2

t

3

t

4

t

5

t

6

NOTES

1

See Interface Timing Diagram.

2

Guaranteed by design and characterization, not production tested.

Specifications subject to change without notice.

1, 2

Limit at T
(A Version) Unit Conditions/Comments

0 ns min CS to WR Setup Time
0 ns min CS to WR Hold Time
50 ns min CS Pulsewidth Low
50 ns min WR Pulsewidth Low
20 ns min A4–A0, CAL, OFFS_SEL to WR Setup Time
0 ns min A4–A0, CAL, OFFS_SEL to WR Hold Time

SERIAL INTERFACE

Parameter

f

CLKIN

t

1

t

2

t

3

t

4

t

5

t

6

t

7

4

t

8

4

t

9

t

10

t

11

NOTES

1

See Serial Interface Timing Diagrams.

2

Guaranteed by design and characterization, not production tested.

3

In SHA mode the maximum SCLK frequency is 20 MHz and the minimum pulsewidth is 20 ns.

4

These numbers are measured with the load circuit of Figure 2.

Specifications subject to change without notice.

1, 2

3

Limit at T
(A Version) Unit Conditions/Comments

14 MHz max SCLK Frequency
28 ns min SCLK High Pulsewidth
28 ns min SCLK Low Pulsewidth
10 ns min SYNC Falling Edge to SCLK Falling Edge Setup Time
50 ns min SYNC Low Time
10 ns min DIN Setup Time
5 ns min DIN Hold Time
5 ns min SYNC Falling Edge to SCLK Rising Edge Setup Time
20 ns max SCLK Rising Edge to D
60 ns max SCLK Falling Edge to D
400 ns min 10th SCLK Falling Edge to SYNC Falling Edge for Readback
400 ns min 24th SCLK Falling Edge to SYNC Falling Edge for DAC Mode Write

MIN

MIN

, T

, T

MAX

MAX

Valid

OUT

High Impedance

OUT

PARALLEL INTERFACE TIMING DIAGRAMS

CS

WR

A4– A0, CAL,

SEL

OFFS

Figure 1. Parallel Write (SHA Mode Only)

OUTPUT

Figure 2. Load Circuit for D

–4–

TO

PIN

C

L

50pF

200␮A

200␮A

I

OL

1.6V

I

OH

Timing Specifications

OUT

REV. 0

SERIAL INTERFACE TIMING DIAGRAMS

t

1

SCLK

SYNC

D

IN

12345678910

t

3

MSB LSB

t

2

t

4

Figure 3. 10-Bit Write (SHA Mode and Both Readback Modes)

t

1

SCLK

SYNC

D

IN

1

t

MSB

2345

t

3

2

t

4

Figure 4. 24-Bit Write (DAC Mode)

AD5532

t

5

t

6

21 22 23 24

t

5

t

6

LSB

t

11

1

SCLK

SYNC

D

OUT

t

1

2

10

t

10

1 34567

t

7

MSB

t

2

t

4

t

8

8

9

10

11

12 13 14

t

9

LSB

Figure 5. 14-Bit Read (Both Readback Modes)

REV. 0

–5–

AD5532

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS

(TA = 25°C unless otherwise noted)

VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +17 V

V

to AGND . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –17 V

SS

to AGND, DAC_GND . . . . . . . . . . . . . –0.3 V to +7 V

AV

CC

to DGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

DV

CC

Digital Inputs to DGND . . . . . . . . . . –0.3 V to DV

Digital Outputs to DGND . . . . . . . . . –0.3 V to DV

REF_IN to AGND, DAC_ GND . . . . . . . . . . –0.3 V to +7 V

to AGND, DAC_GND . . . . . . . . . . . . . . . –0.3 V to +7 V

V

IN

0–31 to AGND . . . . . . . . . . VSS – 0.3 V to V

V

OUT

0–31 to VSS . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +24 V

V

OUT

OFFS_IN to AGND . . . . . . . . . . V

OFFS_OUT to AGND . . . . AGND – 0.3 V to AV

1, 2

– 0.3 V to V

SS

+ 0.3 V

CC

+ 0.3 V

CC

+ 0.3 V

DD

+ 0.3 V

DD

+ 0.3 V

CC

Operating Temperature Range

Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Junction Temperature (T
74-Lead LFBGA Package, θ

max) . . . . . . . . . . . . . . . . . . 150°C

J

Thermal Impedance . . . 41°C/W

JA

Reflow Soldering

Peak Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C

Time at Peak Temperature . . . . . . . . . . . . 10 sec to 40 sec

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

2

Transient currents of up to 100 mA will not cause SCR latch-up.

AGND to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

ORDERING GUIDE

Output Output Package Package

Model Function Impedance Voltage Span Description Option

AD5532ABC-1 32 DACs, 32-Channel SHA 0.5 Ω typ 10 V 74-Lead LFBGA BC-74
AD5532ABC-2 32 DACs, 32-Channel SHA 0.5 Ω typ 20 V 74-Lead LFBGA BC-74
AD5532ABC-3 32 DACs, 32-Channel SHA 500 Ω typ 10 V 74-Lead LFBGA BC-74
AD5532ABC-5 32 DACs, 32-Channel SHA 1 kΩ typ 10 V 74-Lead LFBGA BC-74

AD5533ABC-1* 32-Channel SHA Only 0.5 Ω typ 10 V 74-Lead LFBGA BC-74
EVAL-AD5532EB Evaluation Board

*Separate Data Sheet.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD5532 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

–6–

REV. 0

PIN CONFIGURATION

1234567891011

AD5532

A

B

C

D

E

F

G

H

J

K

L

1234567891011

A

B

C

D

E

F

G

H

J

K

L

74-Lead LFBGA Ball Configuration

LFBGA Ball LFBGA Ball LFBGA Ball
Number Name Number Name Number Name

A1 N/C C10 AVCC1 J10 VO9
A2 A4 C11 REF_OUT J11 VO11
A3 A2 D1 VO20 K1 VO17
A4 A0 D2 DAC_GND2 K2 VO15
A5 CS/SYNC D10 AVCC2 K3 VO27
A6 DVCC D11 OFFS_OUT K4 VSS3
A7 SCLK E1 VO26 K5 VSS1
A8 OFFSET_SEL E2 VO14 K6 VSS4
A9 BUSY E10 AGND1 K7 VDD2
A10 TRACK/RESET E11 OFFS_IN K8 VO2
A11 N/C F1 VO25 K9 VO10
B1 VO16 F2 VO21 K10 VO13
B2 N/C F10 AGND2 K11 VO12
B3 A3 F11 VO6 L1 N/C
B4 A1 G1 VO24 L2 VO28
B5 WR G2 VO8 L3 VO29
B6 DGND G10 VO5 L4 VO30
B7 D

IN

G11 VO3 L5 VDD3

B8 CAL H1 VO23 L6 VDD1
B9 SER/PAR H2 VIN L7 VDD4
B10 DOUT H10 VO4 L8 VO31
B11 REF_IN H11 VO7 L9 VO0
C1 VO18 J1 VO22 L10 VO1
C2 DAC_GND1 J2 VO19 L11 N/C
C6 N/C J6 VSS2

REV. 0

–7–

AD5532

PIN FUNCTION DESCRIPTION

Pin Function

AGND (1–2) Analog GND Pins.
AV

(1–2) Analog Supply Pins. Voltage range from 4.75 V to 5.25 V.

CC

V

(1–4) VDD Supply Pins. Voltage range from 8 V to 16.5 V.

DD

V

(1–4) VSS Supply Pins. Voltage range from –4.75 V to –16.5 V.

SS

DGND Digital GND Pins.
DV

CC

DAC_GND(1–2) Reference GND Supply for All the DACs.
REF_IN Reference Voltage for Channels 0–31.
REF_OUT Reference Output Voltage.
V

(0–31) Analog Output Voltages from the 32 Channels.

OUT

V

IN

1

A4–A1
CAL

2

, A0

1

CS/SYNC This pin is both the active low Chip Select pin for the parallel interface and the Frame Synchronization pin

1

WR

OFFSET_SEL

2

SCLK

2

D

IN

D

OUT

SER/PAR

1

1

OFFS_IN Offset Input. The user can supply a voltage here to offset the output span. OFFS_OUT can also be tied to

OFFS_OUT Offset Output. This is the acquired/programmed offset voltage which can be tied to OFFS_IN to offset the

BUSY This output tells the user when the input voltage is being acquired. It goes low during acquisition and

TRACK/RESET

NOTES

1

Internal pull-down devices on these logic inputs. Therefore, they can be left floating and will default to a logic low condition.

2

Internal pull-up devices on these logic inputs. Therefore, they can be left floating and will default to a logic high condition.

Digital Supply Pins. Voltage range from 2.7 V to 5.25 V.

Analog Input Voltage. Connect this to AGND if operating in DAC mode only.
Parallel Interface: 5-Address Pins for 32 Channels. A4 = MSB of Channel Address. A0 = LSB.
Parallel Interface: Control input that allows all 32 channels to acquire VIN simultaneously.

for the serial interface.
Parallel Interface: Write pin. Active low. This is used in conjunction with the CS pin to address the device

using the parallel interface.
Parallel Interface: Offset Select Pin. Active high. This is used to select the offset channel.
Serial Clock Input for Serial Interface. This operates at clock speeds up to 14 MHz (20 MHz in SHA mode).
Data Input for Serial Interface. Data must be valid on the falling edge of SCLK.
Output from the DAC Registers for readback. Data is clocked out on the rising edge of SCLK and is

valid on the falling edge of SCLK.
This pin allows the user to select whether the serial or parallel interface will be used. If the pin is tied low,

the parallel interface will be used. If it is tied high, the serial interface will be used.

this pin if the user wants to drive this pin with the Offset Channel.

span.

returns high when the acquisition operation is complete.

2

If this input is held high, VIN is acquired once the channel is addressed. While it is held low, the input to the
gain/offset stage is switched directly to V

. The addressed channel begins to acquire VIN on the rising edge

IN

of TRACK. See TRACK Input section for further information. This input can also be used as a means of
resetting the complete device to its power-on-reset conditions. This is achieved by applying a low-going
pulse of between 50 ns and 150 ns to this pin. See section on RESET Function for further details.

OUTPUT

VOLTAGE

FULL-SCALE

ERROR RANGE

IDEAL GAIN ⴛ REFIN

IDEAL TRANSFER
FUNCTION

OFFSET

RANGE

IDEAL GAIN ⴛ 50mV

0 16k

DAC CODE

Figure 6. DAC Transfer Function (OFFS_IN = 0)

–8–

V

OUT

IDEAL

TRANSFER

FUNCTION

OFFSET

ERROR

0V

LOWER

DEADBAND

70mV

ACTUAL
TRANSFER
FUNCTION

Figure 7. SHA Transfer Function

GAIN ERROR +
OFFSET ERROR

3V

2.96

UPPER

DEADBAND

V

IN

REV. 0

AD5532

TERMINOLOGY

DAC MODE
Integral Nonlinearity (INL)

This is a measure of the maximum deviation from a straight line
passing through the endpoints of the DAC transfer function. It
is expressed as a percentage of full-scale span.

Differential Nonlinearity (DNL)

Differential Nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A specified DNL of ±1 LSB maximum ensures
monotonicity.

Offset

Offset is a measure of the output with all zeros loaded to the
DAC and OFFS_IN = 0. Since the DAC is lifted off the ground
by approximately 50 mV, this output will typically be:

V

= Gain × 50 mV

OUT

Full-Scale Error

This is a measure of the output error with all 1s loaded to the
DAC. It is expressed as a percentage of full-scale range. See Fig­ure 6. It is calculated as:

Full-Scale Error = V

OUT(Full-Scale)

– (Ideal Gain × REFIN)

where

Ideal Gain = 3.52 for AD5532-1/-3/-5
Ideal Gain = 7 for AD5532-2

Output Settling Time

This is the time taken from when the last data bit is clocked into
the DAC until the output has settled to within ±0.39%.

OFFS_IN Settling Time

This is the time taken from a 0 V–3 V step change in input volt­age on OFFS_IN until the output has settled to within ±0.39%.

Digital-to-Analog Glitch Impulse

This is the area of the glitch injected into the analog output when
the code in the DAC register changes state. It is specified as the
area of the glitch in nV-secs when the digital code is changed by
1 LSB at the major carry transition (011 . . . 11 to 100 . . . 00 or
100 . . . 00 to 011 . . . 11).

Digital Crosstalk

This is the glitch impulse transferred to the output of one DAC
at midscale while a full-scale code change (all 1s to all 0s and vice
versa) is being written to another DAC. It is expressed in nV-secs.

Analog Crosstalk

This the area of the glitch transferred to the output (V
one DAC due to a full-scale change in the output (V

OUT

OUT

) of

) of

another DAC. The area of the glitch is expressed in nV-secs.

Digital Feedthrough

This is a measure of the impulse injected into the analog outputs
from the digital control inputs when the part is not being written
to, i.e., CS/SYNC is high. It is specified in nV-secs and is mea­sured with a worst-case change on the digital input pins, e.g.,
from all 0s to all 1s and vice versa.

Output Noise Spectral Density

This is a measure of internally generated random noise. Random
noise is characterized as a spectral density (voltage per root Hertz).
It is measured by loading all DACs to midscale and measur­ing noise at the output. It is measured in nV/(√Hz)

Output Temperature Coefficient

1/2

.

This is a measure of the change in analog output with changes
in temperature. It is expressed in ppm/°C.

DC Power-Supply Rejection Ratio

DC Power-Supply Rejection Ratio (PSRR) is a measure of the
change in analog output for a change in supply voltage (V

). It is expressed in dBs. VDD and VSS are varied ±5%.

V

SS

DC Crosstalk

DD

and

This the DC change in the output level of one DAC at midscale
in response to a full-scale code change (all 0s to all 1s and vice
versa) and output change of all other DACs. It is expressed in µV.

SHA MODE
V

IN

to V

Nonlinearity

OUT

This is a measure of the maximum deviation from a straight line
passing through the endpoints of the V

versus V

IN

OUT

transfer

function. It is expressed as a percentage of the full-scale span.

Offset Error

This is a measure of the output error when VIN = 70 mV. Ideally,
with V

Offset error is a measure of the difference between V
and V

= 70 mV:

IN

V

= (Gain × 70) – ((Gain – 1) × V

OUT

(ideal). It is expressed in mV and can be positive or

OUT

OFFS_IN

) mV

OUT

(actual)

negative. See Figure 7.

Gain Error

This is a measure of the span error of the analog channel. It is
the deviation in slope of the transfer function expressed in mV.
See Figure 7. It is calculated as:

Gain Error = Actual Full-Scale Output – Ideal Full-Scale Output –
Offset Error

where

Ideal Full-Scale Output = Gain × 2.96 – ((Gain – 1) × V

AC Crosstalk

OFFS_IN

)

This is the area of the glitch that occurs on the output of one
channel while another channel is acquiring. It is expressed in
nV-secs.

Output Settling Time

This is the time taken from when BUSY goes high to when the
output has settled to ±0.018%.

Acquisition Time

This is the time taken for the VIN input to be acquired. It is the
length of time that BUSY stays low.

REV. 0

–9–

AD5532

–Typical Performance Characteristics

1.0
V

= 3V

REFIN

0.8

0.6

0.4

0.2

0.0

–0.2

–0.4

DNL ERROR – LSBs

–0.6

–0.8

–1.0

0

= 0V

V

OFFS_IN

T

= 25ⴗC

A

2k 4k 6k 8k 10k 12k 16k14k

DAC CODE

Figure 8. Typical DNL Plot

3.535

TA = 25ⴗC
V

= 3V

REFIN

3.530

– V

OUT

V

3.525

3.520

Figure 11. V

420–2 –4 –6

6

SINK/SOURCE CURRENT – mA

Source and Sink

OUT

Capability

1.0

0.5

0.0

DNL ERROR – LSBs

–0.5

–1.0

–40

DNL MAX

INL MAX

INL MIN

DNL MIN

04080

TEMPERATURE – ⴗC

0.2

0.1

0.0

–0.1

–0.2

Figure 9. INL Error and DNL Error
vs. Temperature

10.0
TA = 25ⴗC

= 3V

V

REFIN

– V

V

OUT

–2.0

8.0

6.0

4.0

2.0

0.0

= 0.5V

V

OFFS_IN

TIME BASE – 2␮s/DIV

Figure 12. Full-Scale Settling Time

INL ERROR – % FSR

5.325
DAC LOADED TO MIDSCALE

= 3V

V

REFIN

= 0V

V

OFFS_IN

5.315

5.305

– V

OUT

V

5.295

5.285

5.275

–40

Figure 10. V

5.309

5.308

5.307

5.306

– V

5.305

OUT

V

5.304

TA = 25ⴗC

5.303
V

5.302

V

5.301

04080
TEMPERATURE – ⴗC

vs. Temperature

OUT

= 3V

REFIN

= 0V

OFFS_IN

TIME BASE – 50ns/DIV

Figure 13. Major Code Transition
Glitch Impulse

0.0024
TA = 25ⴗC

0.0020
V

= 3V

REFIN

0.0016

0.0012

0.0008

0.0004

0.0000

ERROR – V

–0.0004

OUT

–0.0008

V

–0.0012

–0.0016

–0.0020

–0.0024

0.1 2.96

Figure 14. VIN to V

V

OFFS_IN

= 0V

V

– V

IN

Accuracy

OUT

After Offset and Gain Adjustment
(SHA Mode)

5V

100

90

V

OUT

BUSY

TA = 25ⴗC
V

= 3V

REFIN

= 0 1.5V

10

0%

V

IN

2␮s1V

Figure 15. Acquisition Time and
Output Settling Time (SHA Mode)

–10–

70k

60k

50k

40k

30k

FREQUENCY

20k

10k

0

5.2670

200

63791

TA = 25ⴗC
V

REFIN

= 1.5V

V

IN

V

OFFS_IN

1545

5.2676 5.2682

V

– V

OUT

= 3V

= 0V

Figure 16. SHA-Mode Repeatability
(64K Acquisitions)

REV. 0

AD5532

FUNCTIONAL DESCRIPTION

The AD5532 can be thought of as consisting of 32 DACs and
an ADC (for SHA mode) in a single package. In DAC mode a
14-bit digital word is loaded into one of the 32 DAC registers
via the serial interface. This is then converted (with gain and
offset) into an analog output voltage (V

OUT

0–V

OUT

31).

To update a DAC’s output voltage the required DAC is addressed
via the serial port. When the DAC address and code have been
loaded the selected DAC converts the code.

On power-on, all the DACs, including the offset channel, are
loaded with zeros. The internal DAC outputs are at 50 mV
typical (negative full-scale). If the OFFS_IN pin is driven by
the on-board offset channel, the outputs V
also at 50 mV on power-on since OFFS_IN = 50 mV, V
(Gain × V

–(Gain –1) × V

DAC)

OFFS_IN

= 50 mV.

OUT

0 to V

OUT

31 are

=

OUT

Output Buffer Stage—Gain and Offset

The function of the output buffer stage is to translate the 0 V–3 V
output of the DAC to a wider range. This is done by gaining up
the DAC output by 3.52/7 and offsetting the voltage by the
voltage on OFFS_IN pin.

AD5532-1/AD5532-3/AD5532-5:

V

= 3.52 × V

OUT

– 2.52 × V

DAC

OFFS_IN

AD5532-2:

V

= 7 × V

OUT

V

is the output of the DAC.

DAC

V

is the voltage at the OFFS_IN pin.

OFFS_IN

The following table shows how the output range on V

DAC

– 6 × V

OFFS_IN

OUT

relates

to the offset voltage supplied by the user:

Table I. Sample Output Voltage Ranges

Reset Function

The reset function on the AD5532 can be used to reset all nodes
on this device to their power-on-reset condition. This is imple­mented by applying a low-going pulse of between 50 ns and 150 ns
to the TRACK/RESET pin on the device. If the applied pulse is
less than 50 ns it is assumed to be a glitch and no operation
takes place. If the applied pulse is wider than 150 ns this pin
adopts its track function on the selected channel, V

is switched

IN

to the output buffer and an acquisition on the channel will not
occur until a rising edge of TRACK.

SHA Mode

In SHA mode the input voltage VIN is sampled and converted
into a digital word. The noninverting input to the output buffer
(gain and offset stage) is tied to V

during the acquisition period

IN

to avoid spurious outputs while the DAC acquires the correct
code. This is completed in 16 µs max. At this time the updated
DAC output assumes control of the output voltage. The output
voltage of the DAC is connected to the noninverting input of
the output buffer. Since the channel output voltage is effectively
the output of a DAC there is no droop associated with it. As
long as power is maintained to the device the output voltage will
remain constant until this channel is addressed again.

Analog Input (SHA Mode)

The equivalent analog input circuit is shown in Figure 17. The
Capacitor C1 is typically 20 pF and can be attributed to pin
capacitance and 32 off-channels. When a channel is selected, an
extra 7.5 pF (typ) is switched in. This Capacitor C2 is charged
to the previously acquired voltage on that particular channel
so it must charge/discharge to the new level. It is essential that the
external source can charge/discharge this additional capaci­tance within 1 µs–2 µs of channel selection so that V

can be

IN

acquired accurately. For this reason a low impedance source
is recommended.

V

OFFS_INVDAC

V

OUT

V

OUT

(V) (V) (AD5532-1/-3/-5) (AD5532-2)

0.5 0 to 3 –1.26 to +9.3 Headroom Limited
1 0 to 3 –2.52 to +8.04 –6 to +15

V

is limited only by the headroom of the output amplifiers.

OUT

V

must be within maximum ratings.

OUT

Offset Voltage Channel

The offset voltage can be externally supplied by the user at
OFFS_IN or it can be supplied by an additional offset volt­age channel on the device itself. The offset can be set up in
two ways. In SHA mode the required offset voltage is set up

and acquired by the offset channel. In DAC mode the

on V

IN

code corresponding to the offset value is loaded directly into
the offset DAC. This offset channel’s DAC output is directly
connected to OFFS_OUT. By connecting OFFS_OUT to OFFS_IN
this offset voltage can be used as the offset voltage for the 32
output amplifiers. It is important to choose the offset so that

is within maximum ratings.

V

OUT

ADDRESSED CHANNEL

V

IN

C1
20pF

C2

7.5pF

Figure 17. Analog Input Circuit

Large source impedances will significantly affect the performance
of the ADC. This may necessitate the use of an input buffer
amplifier.

TRACK Function (SHA Mode)

Normally in SHA mode of operation, TRACK is held high and
the channel begins to acquire when it is addressed. However, if
TRACK is low when the channel is addressed, V

is switched to

IN

the output buffer and an acquisition on the channel will not
occur until a rising edge of TRACK. At this stage the BUSY pin
will go low until the acquisition is complete, at which point the
DAC assumes control of the voltage to the output buffer and

is free to change again without affecting this output value.

V

IN

REV. 0

–11–

AD5532

CONTROLLER

DAC

BUSY

TRACK

V

IN

ACQUISITION

CIRCUIT

ONLY ONE CHANNEL SHOWN FOR SIMPLICITY

OUTPUT

STAGE

AD5532

V

OUT

PIN

DRIVER

1

THRESHOLD

VOLTAGE

DEVICE
UNDER
TEST

Figure 18. Typical ATE Circuit Using

This is useful in an application where the user wants to ramp up
V

until V

IN

reaches a particular level (Figure 18). VIN does

OUT

not need to be acquired continuously while it is ramping up.
TRACK can be kept low and only when V

has reached its

OUT

desired voltage is TRACK brought high. At this stage, the
acquisition of VIN begins.

In the example shown, a desired voltage is required on the out­put of the pin driver. This voltage is represented by one input to
a comparator. The microcontroller/microprocessor ramps up
the input voltage on V
while the voltage on V

through a DAC. TRACK is kept low

IN

ramps up so that VIN is not continu-

IN

ally acquired. When the desired voltage is reached on the output
of the pin driver, the comparator output switches. The µC/µP
then knows what code is required to be input in order to obtain
the desired voltage at the DUT. The TRACK input is now
brought high and the part begins to acquire V
BUSY goes low until V
is then switched from V

has been acquired. The output buffer

IN

to the output of the DAC.

IN

. At this stage

IN

MODES OF OPERATION

The AD5532 can be used in four different modes of opera­tion. These modes are set by two mode bits, the first two bits in
the serial word.

Table II. Modes of Operation

Mode Bit 1 Mode Bit 2 Operating Mode

0 0 SHA Mode
0 1 DAC Mode
1 0 Acquire and Readback
1 1 Readback

1. DAC Mode

In this standard mode a selected DAC register is loaded serially.
This requires a 24-bit write (10 bits to address the relevant DAC
plus an extra 14 bits of DAC data). MSB is written first. The
user must allow 400 ns (min) between successive writes in DAC
mode.

2. SHA Mode

In this mode a channel is addressed and that channel acquires
the voltage on V
ure 21) to address the relevant channel (V

. This mode requires a 10-bit write (see Fig-

IN

OUT

0–V

31, offset

OUT

channel or all channels) MSB is written first.

3. Acquire and Readback Mode

This mode allows the user to acquire VIN and read back the data
in a particular DAC register. The relevant channel is addressed
(10-bit write, MSB first) and V

is acquired in 16 µs (max).

IN

Following the acquisition, after the next falling edge of SYNC,
the data in the relevant DAC register is clocked out onto the

TRACK

D

line in a 14-bit serial format. The full acquisition time

OUT

Input

must elapse before the DAC register data can be clocked out.

4. Readback Mode

Again, this is a readback mode but no acquisition is performed.
The relevant channel is addressed (10-bit write, MSB first) and
on the next falling edge of SYNC, the data in the relevant DAC
register is clocked out onto the D

line in a 14-bit serial format.

OUT

The user must allow 400 ns (min) between the last SCLK fall­ing edge in the 10-bit write and the falling edge of SYNC in
the 14-bit readback. The serial write and read words can be
seen in Figure 19.

This feature allows the user to read back the DAC register code
of any of the channels. In DAC mode this is useful in verification
of write cycles. In SHA mode readback is useful if the system
has been calibrated and the user wants to know what code in
the DAC corresponds to a desired voltage on V

. If the user

OUT

requires this voltage again, he can input the code directly to the
DAC register without going through the acquisition sequence.

INTERFACES
Serial Interface

The SER/PAR pin is tied high to enable the serial interface and
to disable the parallel interface. The serial interface is controlled
by four pins as follows:

SYNC, DIN, SCLK

Standard 3-wire interface pins. The SYNC pin is shared
with the CS function of the parallel interface.

D

OUT

Data Out pin for reading back the contents of the DAC
registers. The data is clocked out on the rising edge of SCLK
and is valid on the falling edge of SCLK.

Mode Bits

There are four different modes of operation as described above.

Cal Bit

In DAC mode this is a test bit. When it is high it is used to load
all zeros or all ones to the 32 DACs simultaneously. In SHA mode
all 32 channels acquire V

simultaneously when this bit is high.

IN

In SHA mode the acquisition time is then 45 µs (typ) and accu-
racy may be reduced. This bit is set low for normal operation.

Offset_Sel Bit

If this is set high, the offset channel is selected and Bits A4–
A0 are ignored.

Test Bit

This must be set low for correct operation of the part.

A4–A0

Used to address any one of the 32 channels (A4 = MSB of
address, A0 = LSB).

–12–

REV. 0

OFFSET SEL A4 –A0

CAL00

MSB LSB

MODE BIT 1 MODE BIT 2

MODE BITS

0

TEST BIT

a. 10-Bit Input Serial Write Word (SHA Mode)

MSB LSB

MODE BITS

CAL10

OFFSET SEL A4 –A0

0

TEST BIT

DB13 –DB0

b. 24-Bit Input Serial Write Word (DAC Mode)

AD5532

MSB LSB

MODE BITS

10-BIT

SERIAL WORD

WRITTEN TO PART

c. Input Serial Interface (Acquire and Readback Mode)

MSB LSB

MODE BITS

10-BIT

SERIAL WORD

WRITTEN TO PART

d. Input Serial Interface (Readback Mode)

Figure 19. Serial Interface Formats

DB13–DB0

These are used to write a 14-bit word into the addressed DAC
register. Clearly, this is only valid when in DAC mode.

The serial interface is designed to allow easy interfacing to
most microcontrollers and DSPs, e.g., PIC16C, PIC17C, QSPI,
SPI, DSP56000, TMS320, and ADSP-21xx, without the need
for any glue logic. When interfacing to the 8051, the SCLK
must be inverted. The Microprocessor/Microcontroller Interface
section explains how to interface to some popular DSPs and
microcontrollers.

Figures 3, 4, and 5 show the timing diagram for a serial read and
write to the AD5532. The serial interface works with both a con­tinuous and a noncontinuous serial clock. The first falling edge of
SYNC resets a counter that counts the number of serial clocks to
ensure the correct number of bits are shifted in and out of the
serial shift registers. Any further edges on SYNC are ignored until
the correct number of bits are shifted in or out. Once the correct
number of bits for the selected mode have been shifted in or out,
the SCLK is ignored. In order for another serial transfer to take
place the counter must be reset by the falling edge of SYNC.

In readback, the first rising SCLK edge after the falling edge of
SYNC causes D
is clocked out onto the D
rising edges. The D
state on the falling edge of the fourteenth SCLK. Data on the

line is latched in on the first SCLK falling edge after the

D

IN

REV. 0

to leave its high impedance state and data

OUT

OUT

line and also on subsequent SCLK

OUT

pin goes back into a high impedance

MSBLSB

OFFSET SEL A4–A0CAL01

TEST BIT

OFFSET SEL A4– A0CAL11

TEST BIT

DB13 –DB00

14-BIT DATA

READ FROM PART AFTER

NEXT FALLING EDGE OF SYNC

(DB13 = MSB OF DAC WORD)

MSBLSB

DB13 –DB00

14-BIT DATA

READ FROM PART AFTER

NEXT FALLING EDGE OF SYNC

(DB13 = MSB OF DAC WORD)

falling edge of the SYNC signal and on subsequent SCLK fall­ing edges. During readback D

is ignored. The serial interface

IN

will not shift data in or out until it receives the falling edge of
the SYNC signal.

Parallel Interface (SHA Mode Only)

The SER/PAR bit must be tied low to enable the parallel inter­face and disable the serial interface. The parallel interface is
controlled by 9 pins.

CS

Active low package select pin. This pin is shared with the SYNC
function for the serial interface.

WR

Active low write pin. The values on the address pins are latched
on a rising edge of WR.

A4–A0

Five address pins (A4 = MSB of address, A0 = LSB). These are
used to address the relevant channel (out of a possible 32).

Offset_Sel

Offset select pin. This has the same function as the Offset_Sel
bit in the serial interface. When it is high, the offset channel is
addressed. The address on A4–A0 is ignored in this case.

Cal

When this pin is high, all 32 channels acquire VIN simultaneously.
The acquisition time is then 45 µs (typ) and accuracy may be
reduced.

–13–

AD5532

MICROPROCESSOR INTERFACING
AD5532 to ADSP-21xx Interface

The ADSP-21xx family of DSPs are easily interfaced to the
AD5532 without the need for extra logic.

A data transfer is initiated by writing a word to the TX register
after the SPORT has been enabled. In a write sequence data is
clocked out on each rising edge of the DSP’s serial clock and
clocked into the AD5532 on the falling edge of its SCLK. In
readback 16 bits of data are clocked out of the AD5532 on each
rising edge of SCLK and clocked into the DSP on the rising
edge of SCLK. D

is ignored. The valid 14 bits of data will be

IN

centered in the 16-bit RX register when using this configuration.
The SPORT control register should be set up as follows:

TFSW = RFSW = 1, Alternate Framing
INVRFS = INVTFS = 1, Active Low Frame Signal
DTYPE = 00, Right Justify Data
ISCLK = 1, Internal Serial Clock
TFSR = RFSR = 1, Frame Every Word
IRFS = 0, External Framing Signal
ITFS = 1, Internal Framing Signal
SLEN = 1001, 10-Bit Data Words (SHA Mode Write)
SLEN = 0111, 3× 8-Bit Data Words (DAC Mode Write)
SLEN = 1111, 16-Bit Data Words (Readback Mode)

Figure 20 shows the connection diagram.

AD5532*

*ADDITIONAL PINS OMITTED FOR CLARITY

D

OUT

SYNC

D

SCLK

IN

ADSP-2101/
ADSP-2103*

DR

TFS

RFS

DT

SCLK

Figure 20. AD5532 to ADSP-2101/ADSP-2103 Interface

AD5532 to MC68HC11

The Serial Peripheral Interface (SPI) on the MC68HC11 is
configured for Master Mode (MSTR = 1), Clock Polarity Bit
(CPOL) = 0 and the Clock Phase Bit (CPHA) = 1. The SPI is
configured by writing to the SPI Control Register (SPCR)—see
68HC11 User Manual. SCK of the 68HC11 drives the SCLK of
the AD5532, the MOSI output drives the serial data line (D
of the AD5532 and the MISO input is driven from D

OUT

IN

. The

)

SYNC signal is derived from a port line (PC7). When data is
being transmitted to the AD5532, the SYNC line is taken low
(PC7). Data appearing on the MOSI output is valid on the fall­ing edge of SCK. Serial data from the 68HC11 is transmitted in
8-bit bytes with only eight falling clock edges occurring in the
transmit cycle. Data is transmitted MSB first. In order to trans­mit 10-data bits in SHA mode it is important to left-justify the
data in the SPDR register. PC7 must be pulled low to start a
transfer. It is taken high and pulled low again before any further
read/write cycles can take place. A connection diagram is shown in
Figure 21.

AD5532*

*ADDITIONAL PINS OMITTED FOR CLARITY

D

OUT

SYNC

SCLK

D

IN

MC68HC11*

MISO

PC7

SCK

MOSI

Figure 21. AD5532 to MC68HC11 Interface

AD5532 to PIC16C6x/7x

The PIC16C6x/7x Synchronous Serial Port (SSP) is config­ured as an SPI Master with the Clock Polarity bit = 0. This is
done by writing to the Synchronous Serial Port Control Register
(SSPCON). See user PIC16/17 Microcontroller User Manual. In
this example I/O port RA1 is being used to pulse SYNC and
enable the serial port of the AD5532. This microcontroller
transfers only eight bits of data during each serial transfer opera­tion; therefore, two or three consecutive read/write operations
are needed depending on the mode. Figure 22 shows the connec­tion diagram.

AD5532*

SCLK

D

OUT

D

IN

SYNC

*ADDITIONAL PINS OMITTED FOR CLARITY

PIC16C6x/7x*

SCK/RC3

SDO/RC5

SDI/RC4

RA1

Figure 22. AD5532 to PIC16C6x/7x Interface

AD5532 to 8051

The AD5532 requires a clock synchronized to the serial data.
The 8051 serial interface must therefore be operated in Mode

0. In this mode serial data enters and exits through RxD and a
shift clock is output on TxD. Figure 23 shows how the 8051 is
connected to the AD5532. Because the AD5532 shifts data out
on the rising edge of the shift clock and latches data in on the
falling edge, the shift clock must be inverted. The AD5532
requires its data with the MSB first. Since the 8051 outputs the
LSB first, the transmit routine must take this into account.

AD5532*

SCLK

D

OUT

D

IN

SYNC

*ADDITIONAL PINS OMITTED FOR CLARITY

8051*

TxD

RxD

P1.1

Figure 23. AD5532 to 8051 Interface

–14–

REV. 0

AD5532

APPLICATION CIRCUITS
AD5532 in a Typical ATE System

The AD5532 is ideally suited for use in Automatic Test Equipment.
Several DACs are required to control pin drivers, comparators,
active loads and signal timing. Traditionally, sample-and-hold
devices were used in this application.

The AD5532 has several advantages: no refreshing is required,
there is no droop, pedestal error is eliminated and there is no
need for extra filtering to remove glitches. Overall a higher level
of integration is achieved in a smaller area (see Figure 24).

STORED

DATA

AND INHIBIT

PATTERN

PERIOD

GENERATION

AND

DELAY

TIMING

DACs

DAC

DAC

DAC

FORMATTER

COMPARE
REGISTER

SYSTEM BUS

ACTIVE

LOAD

DRIVER

COMPARATOR

PARAMETRIC

MEASUREMENT

DAC

DAC

UNIT

SYSTEM BUS

DUT

DAC

DAC

Figure 24. AD5532 in an ATE System

Typical Application Circuit (SHA Mode)

The AD5532 can be used to set up voltage levels on 32 channels
as shown in the circuit below. An AD780 provides the 3 V refer­ence for the AD5532, and for the AD5541 16-bit DAC. A simple
3-wire interface is used to write to the AD5541. The DAC output
is buffered by an AD820. It is essential to minimize noise on V

IN

and REFIN when laying out this circuit.

POWER SUPPLY DECOUPLING

In any circuit where accuracy is important, careful consideration
of the power supply and ground return layout helps to ensure
the rated performance. The printed circuit board on which the
AD5532 is mounted should be designed so that the analog and
digital sections are separated, and confined to certain areas of
the board. If the AD5532 is in a system where multiple devices
require an AGND-to-DGND connection, the connection should
be made at one point only. The star ground point should be
established as close as possible to the device. For supplies with
multiple pins (V

, VDD, AVCC) it is recommended to tie those pins

SS

together. The AD5532 should have ample supply bypassing of
10 µF in parallel with 0.1 µF on each supply located as close to
the package as possible, ideally right up against the device. The
10 µF capacitors are the tantalum bead type. The 0.1 µF capacitor
should have low Effective Series Resistance (ESR) and Effective
Series Inductance (ESI), like the common ceramic types that
provide a low impedance path to ground at high frequencies, to
handle transient currents due to internal logic switching.

The power supply lines of the AD5532 should use as large a trace
as possible to provide low impedance paths and reduce the
effects of glitches on the power supply line. Fast switching signals
such as clocks should be shielded with digital ground to avoid
radiating noise to other parts of the board, and should never be
run near the reference inputs. A ground line routed between

and SCLK lines will help reduce crosstalk between them

the D

IN

(not required on a multilayer board as there will be a separate
ground plane, but separating the lines will help). It is essential
to minimize noise on V

and REFIN lines.

IN

Avoid crossover of digital and analog signals. Traces on opposite
sides of the board should run at right angles to each other. This
reduces the effects of feedthrough through the board. A microstrip
technique is by far the best, but not always possible with a double­sided board. In this technique, the component side of the board
is dedicated to ground plane while signal traces are placed on
the solder side.

CS

DIN

SCLK

REV. 0

AV

CC

REF

V

AD820

OUT

AD5541*

AD780*

*ADDITIONAL PINS OMITTED FOR CLARITY

V

DD

AVCCDVCCV

V

IN

OFFS_IN

OFFS_OUT

REFIN

SCLK DIN

Figure 25. Typical Application Circuit

AD5532*

SYNC

SS

V

0–31

OUT

–15–

AD5532

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

74-Lead LFBGA

(BC-74)

0.472 (12.00) BSC

A1

TOP VIEW

0.067
(1.70)

MAX

CONTROLLING DIMENSIONS
ARE IN MILLIMETERS

0.472

(12.00)

BSC

DETAIL A

0.039
(1.00)

BSC

0.010
(0.25)

0.394 (10.00) BSC

11 10 9 8 7 6 5 4 3 2 1

0.039 (1.00) BSC

DETAIL A

MIN

0.024 (0.60)
BSC

BALL DIAMETER

BOTTOM

VIEW

SEATING
PLANE

A
B
C
D
E
F
G
H
J
K
L

0.033
(0.85)

MIN

0.394

(10.00)

BSC

C3744–2.5–4/00 (rev. 0) 00939

–16–

PRINTED IN U.S.A.

REV. 0