Datasheet AD5530, AD5531 Datasheet (ANALOG DEVICES)

Serial Input, Voltage Output

VDDV

12-/14-Bit Digital-to-Analog Converters

FEATURES

Pin-compatible 12-, 14-bit digital-to-analog converters
Serial input, voltage output
Maximum output voltage range of ±10 V
Data readback
3-wire serial interface
Clear function to a user-defined voltage
Power-down function
Serial data output for daisy-chaining
16-lead TSSOP

APPLICATIONS

Industrial automation
Automatic test equipment
Process control
General-purpose instrumentation

GENERAL DESCRIPTION

The AD5530/AD5531 are single 12- and 14-bit (respectively)
serial input, voltage output digital-to-analog converters (DAC).

They utilize a versatile 3-wire interface that is compatible with
SPI®, QSPI™, MICROWIRE™, and DSP interface standards. Data
is presented to the part in a 16-bit serial word format. Serial
data is available on the SDO pin for daisy-chaining purposes.
Data readback allows the user to read the contents of the DAC
register via the SDO pin.

AD5530/AD5531

FUNCTIONAL BLOCK DIAGRAM

SS

DAC

CONTROL LOGIC

AD5530/AD5531

POWER-DOWN

LDAC

can be used to

V

OUT

R

R

DUTGND

CLR

PD

REFIN

REFAGND

LDAC

RBEN

SDIN

R

DAC REGIS TER

SHIFT REGISTER

GND

SCLK SYNC SDO

R

12-/14-BIT

Figure 1.

The DAC output is buffered by a gain of two amplifier and
referenced to the potential at DUTGND.
update the output of the DAC asynchronously. A power-down

PD

pin (
a

) allows the DAC to be put into a low power state, and

CLR

pin allows the output to be cleared to a user-defined

voltage, the potential at DUTGND.

The AD5530/AD5531 are available in 16-lead TSSOP.

0938-001

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2007 Analog Devices, Inc. All rights reserved.

AD5530/AD5531

TABLE OF CONTENTS

Features.............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

AC Performance Characteristics ................................................ 5

Standalone Timing Characteristics............................................ 5

Daisy-Chaining and Readback Timing Characteristics.......... 6

Absolute Maximum Ratings............................................................ 7

ESD Caution.................................................................................. 7

Pin Configuration and Function Descriptions............................. 8

Typical Performance Characteristics ............................................. 9

Terminology .................................................................................... 12

Theory of Operation ...................................................................... 13

DAC Architecture....................................................................... 13

Serial Interface ............................................................................ 13

PD

Function................................................................................ 13

Readback Function .................................................................... 13

CLR

Function.............................................................................. 13

Output Voltage............................................................................ 14

Bipolar Configuration................................................................ 14

Microprocessor Interfacing........................................................... 15

AD5530/AD5531 to ADSP-21xx.............................................. 15

AD5530/AD5531 to 8051 Interface......................................... 15

AD5530/AD5531 to MC68HC11 Interface............................ 15

Applications Information.............................................................. 17

Optocoupler Interface................................................................ 17

Serial Interface to Multiple AD5530s or AD5531s ................ 17

Daisy-Chaining Interface with Multiple AD5530s or

AD5531s ...................................................................................... 17

Outline Dimensions....................................................................... 18

Ordering Guide .......................................................................... 18

REVISION HISTORY

1/07—Rev. A to Rev. B

Updated Format..................................................................Universal

Changes to Figure 28...................................................................... 17

3/06—Rev. 0 to Rev. A

Change to Table 3 ............................................................................. 5

Change to Figure 4 ........................................................................... 8

Change to Output Voltage Section ............................................... 14

Change to Ordering Guide............................................................ 18

5/02—Revision 0: Initial Version

Rev. B | Page 2 of 20

AD5530/AD5531

SPECIFICATIONS

VDD = 15 V ± 10%; VSS = −15 V ± 10%; GND = 0 V; RL = 5 kΩ and CL = 220 pF to GND. All specifications T

MIN

to T

, unless otherwise noted.

MAX

Table 1.

Parameter

1

AD5530 AD5531 Unit Test Conditions/Comments

ACCURACY

Resolution 12 14 Bits
Relative Accuracy ±1 ±2 LSB max
Differential Nonlinearity ±1 ±1 LSB max Guaranteed monotonic over temperature
Zero-Scale Error ±2 ±8 LSB max Typically within ±1 LSB
Full-Scale Error ±2 ±8 LSB max Typically within ±1 LSB
Gain Error ±1 ±4 LSB typ
Gain Temperature Coefficient2 0.5 0.5 ppm FSR/°C typ

10 10 ppm FSR/°C max

REFERENCE INPUTS2

Reference Input Range 0 to 5 0 to 5 V min to V max Max output range ±10 V
DC Input Resistance 100 100 MΩ typ
Input Current ±1 ±1 μA max Per input, typically ±20 nA

DUTGND INPUT2

DC Input Impedance 60 60 kΩ typ
Max Input Current ±0.3 ±0.3 mA typ
Input Range −4 to +4 −4 to +4 V min to V max Max output range ±10 V

O/P CHARACTERISTICS2

Output Voltage Swing ±10 ±10 V max
Short-Circuit Current 15 15 mA max
Resistive Load 5 5 kΩ min To 0 V
Capacitive Load 1200 1200 pF max To 0 V
DC Output Impedance 0.5 0.5 Ω max

DIGITAL I/O

V

, Input High Voltage 2.4 2.4 V min

INH

V

, Input Low Voltage 0.8 0.8 V max

INL

I

, Input Current ±10 ±10 μA max Total for all pins

INH

CIN, Input Capacitance
SDO VOL, Output Low Voltage 0.4 0.4 V max I

2

10 10 pF max 3 pF typical

= 1 mA

SINK

POWER REQUIREMENTS

VDD/VSS +15/−15 +15/−15 V nom ±10% for specified performance
Power Supply Sensitivity

ΔFull Scale/ΔVDD 110 110 dB typ

ΔFull Scale/ΔVSS 100 100 dB typ
IDD 2 2 mA max Outputs unloaded
ISS 2 2 mA max Outputs unloaded
IDD in Power-Down 150 150 μA max Typically 50 μA

1

Temperature range for B Version: −40°C to +85°C.

2

Guaranteed by design, not subject to production test.

Rev. B | Page 3 of 20

AD5530/AD5531

VDD = 12 V ± 10%; VSS = −12 V ± 10%; GND = 0 V; RL = 5 kΩ and CL = 220 pF to GND; TA = T

MIN

to T

, unless otherwise noted.

MAX

Table 2.

Parameter

1

AD5530 AD5531 Unit Test Conditions/Comments

ACCURACY

Resolution 12 14 Bits
Relative Accuracy ±1 ±2 LSB max
Differential Nonlinearity ±1 ±1 LSB max Guaranteed monotonic over temperature
Zero-Scale Error ±2 ±8 LSB max Typically within ±1 LSB
Full-Scale Error ±2 ±8 LSB max Typically within ±1 LSB
Gain Error ±1 ±4 LSB typ
Gain Temperature Coefficient2 0.5 0.5 ppm FSR/°C typ
10 10 ppm FSR/°C max

REFERENCE INPUTS2

Reference Input Range 0 to 4.096 0 to 4.096 V min to V max Max output range ±8.192 V
DC Input Resistance 100 100 MΩ typ
Input Current ±1 ±1 μA max Per input, typically ±20 nA

DUTGND INPUT2

DC Input Impedance 60 60 kΩ typ
Max Input Current ±0.3 ±0.3 mA typ
Input Range −3 to +3 −3 to +3 V min to V max Max output range ±8.192 V

O/P CHARACTERISTICS2

Output Voltage Swing ±8.192 ±8.192 V max
Short-Circuit Current 15 15 mA max
Resistive Load 5 5 kΩ min To 0 V
Capacitive Load 1200 1200 pF max To 0 V
DC Output Impedance 0.5 0.5 Ω max

DIGITAL I/O

V

, Input High Voltage 2.4 2.4 V min

INH

V

, Input Low Voltage 0.8 0.8 V max

INL

I

, Input Current ±10 ±10 μA max Total for all pins

INH

CIN, Input Capacitance2 10 10 pF max 3 pF typical
SDO VOL, Output Low Voltage 0.4 0.4 V max I

= 1 mA

SINK

POWER REQUIREMENTS

VDD/VSS +12/−12 +12/−12 V nom ±10% for specified performance
Power Supply Sensitivity

ΔFull Scale/ΔVDD 110 110 dB typ

ΔFull Scale/ΔVSS 100 100 dB typ
IDD 2 2 mA max Outputs unloaded
ISS 2 2 mA max Outputs unloaded
IDD in Power-Down 150 150 μA max Typically 50 μA

1

Temperature range for B Version: −40°C to +85°C.

2

Guaranteed by design, not subject to production test.

Rev. B | Page 4 of 20

AD5530/AD5531

AC PERFORMANCE CHARACTERISTICS

VDD = 10.8 V to 16.5 V, VSS = −10.8 V to −16.5 V; GND = 0 V; RL = 5 kΩ and CL = 220 pF to GND. All specifications T
otherwise noted.

Table 3.

Parameter B Version Unit Test Conditions/Comments

DYNAMIC PERFORMANCE

Output Voltage Settling Time 20 μs typ

Full-scale change to ±½ LSB. DAC latch contents alternately

loaded with all 0s and all 1s.
Slew Rate 1.3 V/μs typ
Digital-to-Analog Glitch Impulse 120 nV-s typ

DAC latch alternately loaded with 0x0FFF and 0x1000. Not

dependent on load conditions.
Digital Feedthrough 0.5 nV-s typ Effect of input bus activity on DAC output under test.
Output Noise Spectral Density @ 1 kHz 100 nV/√Hz typ All 1s loaded to DAC.

STANDALONE TIMING CHARACTERISTICS

VDD = 10.8 V to 16.5 V, VSS = −10.8 V to −16.5 V; GND = 0 V; RL = 5 kΩ and CL = 220 pF to GND. All specifications T
otherwise noted.

MIN

MIN

to T

to T

MAX

MAX

, unless

, unless

Table 4.

Parameter Limit at T

f

MAX

1, 2

MIN

, T

Unit Description

MAX

7 MHz max SCLK frequency
t1 140 ns min SCLK cycle time
t2 60 ns min SCLK low time
t3 60 ns min SCLK high time
t4 50 ns min
t5 40 ns min
t6 50 ns min

SYNC to SCLK falling edge setup time
SCLK falling edge to

SYNC high time

Min

SYNC rising edge

t7 40 ns min Data setup time
t8 15 ns min Data hold time
t9 5 ns min

t10 50 ns min
t11 5 ns min
t12 50 ns min

1

Guaranteed by design, not subject to production test.

2

Sample tested during initial release and after any redesign or process change that can affect this parameter. All input signals are measured with tR = tF = 5 ns (10% to

90% of VDD) and timed from a voltage level of (VIL + VIH)/2.

SYNC high to LDAC low
LDAC pulse width
LDAC high to SYNC low
CLR

pulse width

SCLK

t

4

SYNC

SDIN

1

LDAC

CLR

1

LDAC CAN BE TIED PERMANENTLY LO W, IF REQUIRED.

t

6

MSB

DB15 DB14 DB11 DB0

t

1

t7t

8

Figure 2. Timing Diagram for Standalone Mode

LSB

t

3

t

t

5

2

t

9

t

11

t

10

t

12

0938-002

Rev. B | Page 5 of 20

AD5530/AD5531

DAISY-CHAINING AND READBACK TIMING CHARACTERISTICS

VDD = 10.8 V to 16.5 V, VSS = −10.8 V to −16.5 V; GND = 0 V; RL = 5 kΩ and CL = 220 pF to GND. All specifications T
otherwise noted.

MIN

to T

MAX

, unless

Table 5.

Parameter Limit at T

f

MAX

1, 2, 3

MIN

, T

Unit Description

MAX

2 MHz max SCLK frequency
t1 500 ns min SCLK cycle time
t2 200 ns min SCLK low time
t3 200 ns min SCLK high time
t4 50 ns min
t5 40 ns min
t6 50 ns min

SYNC to SCLK falling edge setup time
SCLK falling edge to

SYNC high time

Min

SYNC rising edge

t7 40 ns min Data setup time
t8 15 ns min Data hold time
t12 50 ns min

CLR pulse width
t13 130 ns min SCLK falling edge to SDO valid
t14 50 ns max SCLK falling edge to SDO invalid
t15 50 ns min
t16 50 ns min
t17 100 ns min

1

Guaranteed by design, not subject to production test.

2

Sample tested during initial release and after any redesign or process change that can affect this parameter. All input signals are measured with tR = tF = 5 ns (10% to

90% of VDD) and timed from a voltage level of (VIL + VIH)/2.

3

SDO; R

= 5 kΩ, CL = 15 pF

PULLUP

RBEN to SCLK falling edge setup time

RBEN hold time

RBEN falling edge to SDO valid

SCLK

SYNC

SDIN

SDO

(DAISY-

CHAINING)

RBEN

t

1

t

4

t

6

MSB

DB15 DB14 DB11 DB0

t7t

8

t

3

t

2

t

MSB LSB

DB15 DB11 DB0

14

t

15

LSB

t

5

t

13

t

16

SDO

(READBACK)

t

17

Figure 3. Timing Diagram for Daisy-Chaining and Readback Mode

Rev. B | Page 6 of 20

t

13

MSB LSB

t

14

RB0RB1300

00938-003

AD5530/AD5531

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 6.

Parameter Rating

VDD to GND −0.3 V to +17 V
VSS to GND +0.3 V to −17 V
Digital Inputs to GND −0.3 V to VDD + 0.3 V
SDO to GND −0.3 V to +6.5 V
REFIN to REFAGND −0.3 V to +17 V
REFIN to GND VSS − 0.3 V to VDD + 0.3 V
REFAGND to GND VSS − 0.3 V to VDD + 0.3 V
DUTGND to GND VSS − 0.3 V to VDD + 0.3 V
Operating Temperature Range

Industrial (B Version) −40°C to +85°C
Storage Temperature Range −65°C to +150°C
Maximum Junction Temperature (T
Package Power Dissipation ( T
Thermal Impedance θJA

TSSOP (RU-16) 150.4°C/W
Lead Temperature (Soldering 10 sec) 300°C
IR Reflow, Peak Temperature (<20 sec) 235°C

) 150°C

J MAX

J MAX

– TA)/θJA

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. B | Page 7 of 20

AD5530/AD5531

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

REFAGND

REFIN

LDAC

SDIN

SYNC

RBEN

SCLK

SDO

1

2

3

AD5530/

AD5531

4

TOP VIEW

(Not to Scale)

5

6

7

8

NC = NO CONNECT

16

15

14

13

12

11

10

9

V

DD

V

OUT

DUTGND

V

SS

NC

GND

PD

CLR

0938-004

Figure 4. Pin Configuration

Table 7. Pin Function Descriptions

Pin No. Mnemonic Description

1 REFAGND For bipolar ±10 V output range, this pin should be tied to 0 V.
2 REFIN This is the voltage reference input for the DAC. Connect to external 5 V reference for specified bipolar ±10 V output.
3

LDAC Load DAC Logic Input (Active Low). When taken low, the contents of the shift register are transferred to the DAC

register.

LDAC can be tied permanently low, enabling the outputs to be updated on the rising edge of SYNC.
4 SDIN Serial Data Input. This device accepts 16-bit words. Data is clocked into the input register on the falling edge of SCLK.
5
6

SYNC
RBEN Active Low Readback Enable Function. This function allows the contents of the DAC register to be read. Data

Active Low Control Input. Data is clocked into the shift register on the falling edges of SCLK.

from the DAC register is shifted out on the SDO pin on each rising edge of SCLK.
7 SCLK Clock Input. Data is clocked into the input register on the falling edge of SCLK.
8 SDO

Serial Data Out. This pin is used to clock out the serial data previously written to the input shift register or can be

used in conjunction with

RBEN to read back the data from the DAC register. This is an open drain output; it

should be pulled high with an external pull-up resistor. In standalone mode, SDO should be tied to GND or left

high impedance.
9

CLR Level Sensitive, Active Low Input. A falling edge of CLR resets V

to DUTGND. The contents of the registers

OUT

are untouched.
10

PD

This allows the DAC to be put into a power-down state.
11 GND Ground Reference.

12 NC Do not connect anything to this pin.
13 VSS Negative Analog Supply Voltage. −12 V ± 10% or −15 V ± 10%, for specified performance.
14 DUTGND V
15 V

DAC Output.

OUT

is referenced to the voltage applied to this pin.

OUT

16 VDD Positive Analog Supply Voltage. 12 V ± 10% or 15 V ± 10%, for specified performance.

Rev. B | Page 8 of 20

AD5530/AD5531

TYPICAL PERFORMANCE CHARACTERISTICS

1.0
VDD = +15V
V

= –15V

0.8

SS

REFIN = +5V
REFAGND = 0V

0.6
T

= 25°C

A

0.4

0.2

0

LSB

–0.2

–0.4

–0.6

–0.8

–1.0

0 500 1000 1500 2000 2500 3000 3500 4000

CODE

Figure 5. AD5530 Typical INL Plot Figure 8. AD5531 Typical DNL Plot

0.5
VDD = +15V
V

= –15V

0.4

SS

REFIN = +5V
REFAGND = 0V

0.3
T

= 25°C

A

0.2

0.1

0

LSB

–0.1

–0.2

–0.3

–0.4

–0.5

0 500 1000 1500 2000 2500 3000 3500 4000

CODE

Figure 6. AD5530 Typical DNL Plot Figure 9. AD5531 Typical INL Error vs. Temperature

2.0
VDD = +15V
V

= –15V

SS

1.5
REFIN = +5V

REFAGND = 0V
T

= 25°C

A

1.0

0.5

0

LSB

–0.5

–1.0

–1.5

–2.0

0 2000 4000 6000 8000 10000 12000 14000 16000

CODE

Figure 7. AD5531 Typical INL Plot

1.00
VDD = +15V
V

= –15V

SS

0.75
REFIN = +5V

REFAGND = 0V
T

= 25°C

A

0.50

0.25

0

LSB

–0.25

–0.50

–0.75

00938-005

00938-006

00938-007

–1.00

0 2000 4000 6000 8000 10000 12000 14000 16000

2.0
VDD = +15V
V

= –15V

SS

1.5
REFIN = +5V

REFAGND = 0V

1.0

0.5

0

–0.5

ERROR (LSB)

–1.0

–1.5

–2.0

–40 806040200–20

1.0
VDD = +15V
V

= –15V

0.8

SS

REFIN = +5V
REFAGND = 0V

0.6

0.4

0.2

0

–0.2

ERROR (LSB)

–0.4

–0.6

–0.8

–1.0

–40 806040200–20

CODE

TEMPERATURE (°C)

TEMPERATURE (°C)

Figure 10. AD5531 Typical DNL Error vs. Temperature

00938-008

00938-009

00938-010

Rev. B | Page 9 of 20

AD5530/AD5531

3

2

1

0

ERROR (LSB)

–1

–2

POSITIVE INL

NEGATIVE INL

VDD = +15V
V

= –15V

SS

REFIN = 0V
T

= 25°C

A

0.03

–40°C

0.02

+25°C

(mA)

DD

I

0.01

+85°C

–3

2.0 6.05.55.04.54.03.53.02.5

REFIN VOL TAGE (V)

00938-011

0

10 17161514131211

Figure 11. AD5531 Typical INL Error vs. Reference Voltage Figure 14. I

0

–0.5

–1.0

–1.5

ERROR (LSB)

–2.0

–2.5

–40 –20 0 20 40 60 80

TEMPERATURE (°C)

VDD = +15V
V

= –15V

SS

REFIN = +5V
REFAGND = 0V

00938-012

12

8

4

(V)

0

OUT

V

–4

–8

–12

0 5 10 15 20 25

Figure 12. Typical Full-Scale and Offset Error vs. Temperature

CURRENT (mA)

1.50

1.45

1.40

1.35

1.30

1.25

1.20
10 17161514131211

+85°C

+25°C

–40°C

Figure 13. I

VDD/VSS (V)

vs. VDD/VSS

DD

00938-013

0

–0.02

–0.04

–0.06

(V)

–0.08

OUT

V

–0.10

–0.12

–0.14

–0.16

Figure 16. Typical Digital-to-Analog Glitch Impulse

SUPPLY VOLTAGE (V)

in Power-Down vs. Supply

DD

TIME (µs)

Figure 15. Settling Time

TIME (750ns/DIV)

VDD = +15V

= –15V

V

SS

REFIN = +5V
REFAGND = 0V

= 25°C

T

A

VDD = +15V

= –15V

V

SS

REFIN = +5V
REFAGND = 0V

= 25°C

T

A

00938-014

00938-015

00938-016

Rev. B | Page 10 of 20

AD5530/AD5531

V

OUT

PD

VDD = +15V
V

= –15V

SS

REFIN = +5V
REFAGND = 0V
T

= 25°C

A

2V/DIV

2V/DIV

0938-017

Figure 17. Typical Power-Down Time

Rev. B | Page 11 of 20

AD5530/AD5531

TERMINOLOGY

Relative Accuracy

Relative accuracy or endpoint linearity is a measure of the
maximum deviation, in LSBs, from a straight line passing
through the endpoints of the DAC transfer function.

Differential Nonlinearity

Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ±1 LSB maximum
ensures monotonicity.

Zero-Scale Error

Zero-scale error is a measure of the output error when all 0s are
loaded to the DAC latch.

Full-Scale Error

This is the error in DAC output voltage when all 1s are loaded
into the DAC latch. Ideally the output voltage, with all 1s loaded
into the DAC latch, should be 2 V

− 1 LSB.

REF

Gain Error

Gain error is the difference between the actual and ideal analog
output range, expressed as a percent of the full-scale range. It is
the deviation in slope of the DAC transfer characteristic from ideal.

Output Voltage Settling Time

This is the amount of time it takes for the output to settle to a
specified level for a full-scale input change.

Digital-to-Analog Glitch Impulse

Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is specified as the area of the glitch in nV-s and is
measured when the digital input code is changed by 1 LSB at
the major carry transition.

Digital Feedthrough

Digital feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital inputs of the
DAC, but is measured when the DAC output is not updated. It
is specified in nV-s and is measured with a full-scale code
change on the data bus, that is, from all 0s to all 1s and vice versa.

Rev. B | Page 12 of 20

AD5530/AD5531

THEORY OF OPERATION

DAC ARCHITECTURE

The AD5530/AD5531 are pin-compatible 12- and 14-bit DACs.
The AD5530 consists of a straight 12-bit R-2R voltage mode
DAC, and the AD5531 consists of a 14-bit R-2R section. Using a
5 V reference connected to the REFIN pin and REFAGND tied
to 0 V, a bipolar ±10 V voltage output results. The DAC coding
is straight binary.

SERIAL INTERFACE

Serial data on the SDIN input is loaded to the input register

SYNC LDAC

under the control of SCLK,
operation transfers a 16-bit word to the AD5530/AD5531.
Figure 2 and Figure 3 show the timing diagrams. Figure 18 and
Figure 19 show the contents of the input shift register. Twelve or
14 bits of the serial word are data bits; the rest are don’t cares.

DB15 (MSB)

XX D9D10D11 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X

Figure 18. AD5530 Input Shift Register Contents

DB15 (MSB) DB0 (LSB)

XX D11D12D13 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Figure 19. AD5531 Input Shift Register Contents

The serial word is framed by the signal, . After a high-to­low transition on

SYNC

, data is latched into the input shift
register on the falling edges of SCLK. There are two ways the
DAC register and output can be updated. The
examined on the falling edge of
either a synchronous or asynchronous update is selected. If
LDAC

is low, then the DAC register and output are updated on
the low-to-high transition of
high upon sampling, the DAC register is not loaded with the
new data on a rising edge of
register and the output voltage are updated by bringing
low any time after the 16-bit data transfer is complete.
can be tied permanently low if required. A simplified diagram

of the input loading circuitry is illustrated in

, and . A write

DATA BITS

DATA BIT S

SYNC

LDAC

SYNC

; depending on its status,

SYNC

. Alternatively, if

SYNC

. The contents of the DAC

Figure 20.

DB0 (LSB)

signal is

LDAC

00938-018

00938-019

LDAC

LDAC

is

REFIN

LDAC

SYNC

SDIN

Figure 20. Simplified Serial Interface

12-/14-BIT DAC

14

DAC REGISTER

14

SYNC REGISTER

14

16-BIT SHIFT

REGISTER

Data written to the part via SDIN is available on the SDO pin 16
clocks later if the readback function is not used. SDO data is
clocked out on the falling edge of the serial clock with some delay.

PD FUNCTION

PD

The pin allows the user to place the device into power-down
mode. While in this mode, power consumption is at a minimum;
the device draws only 50 μA of current. The
not affect the contents of the DAC register.

READBACK FUNCTION

The AD5530/AD5531 allows the data contained in the DAC
register to be read back if required. The pins involved are the
RBEN RBEN

and SDO (serial data out). When is taken low, on
the next falling edge of SCLK, the contents of the DAC register
are transferred to the shift register.

RBEN

the readback data by leaving it low for 16 clock cycles, or it can
be asserted high after the required hold time. The shift register
contains the DAC register data and this is shifted out on the
SDO line on each falling edge of SCLK with some delay. This
ensures the data on the serial data output pin is valid for the
falling edge of the receiving part. The two MSBs of the 16-bit
word are 0s.

CLR FUNCTION

The falling edge of
potential as DUTGND. The contents of the registers remain
unchanged, so the user can reload the previous data with

CLR

after

is asserted high. Alternatively, if
output is loaded with the contents of the DAC register auto­matically after

CLR

causes V

CLR

is brought high.

to be reset to the same

OUT

OUTPUT

SDO

00938-020

PD

function does

can be used to frame

LDAC

LDAC

is tied low, the

Rev. B | Page 13 of 20

AD5530/AD5531

V

OUTPUT VOLTAGE

The DAC transfer function is as follows:

= 2 × [2 × ((REFIN − REFAGND) × ) + 2 ×

V

OUT

D

N

2

REFAGND − REFIN] − DUTGND

where:

D is the decimal data-word loaded to the DAC register.
N is the resolution of the DAC.

BIPOLAR CONFIGURATION

Figure 21 shows the AD5530/AD5531 in a bipolar circuit
configuration. REFIN is driven by the AD586, 5 V reference,
and the REFAGND and DUTGND pins are tied to GND. This
results in a bipolar output voltage ranging from −10 V to +10 V.
Resistor R1 is provided (if required) for gain adjust.
shows the transfer function of the DAC when REFAGND is tied
to 0 V.

Figure 22

2

AD586

4

SIGNAL

GND

6

5

9

C1

1µF

1

ADDITIONAL PINS OMITTED FOR CLARITY.

R1
10kΩ

REFIN

AD5530/

AD5531

REFAGND

Figure 21. Bipolar ±10 V Operation

2 REFIN

0V

DAC OUTPUT VO LTAGE

–2 REFIN

+15

V

OUT

DUTGND

V

SS

–15V

V

1

GND

OUT

V

OUT

(–10V TO +10V)

SIGNAL

GND

0938-021

DAC INPUT CODE 000 001 (3)FFF

Figure 22. Output Voltage vs. DAC Input Codes (Hex)

00938-022

Rev. B | Page 14 of 20

AD5530/AD5531

MICROPROCESSOR INTERFACING

Microprocessor interfacing to the AD5530/AD5531 is via a
serial bus that uses standard protocol compatible with micro­controllers and DSP processors. The communications channel
is a 3-wire (minimum) interface consisting of a clock signal, a
data signal, and a synchronization signal. The AD5530/AD5531
requires a 16-bit data-word with data valid on the falling edge
of SCLK.

For all the interfaces, the DAC output update can be done
automatically when all the data is clocked in or asynchronously
under the control of

LDAC

.

The contents of the DAC register can be read using the
readback function.

RBEN

is used to frame the readback data,
which is clocked out on SDO. Figure 23, Figure 24, and Figure 25
show these DACs interfacing with a simple 4-wire interface.
The serial interface of the AD5530/AD5531 can be operated
from a minimum of three wires.

AD5530/AD5531 TO ADSP-21xx

An interface between the AD5530/AD5531 and the ADSP-21xx
is shown in

Figure 23. In the interface example shown, SPORT0
is used to transfer data to the DAC. The SPORT control register
should be configured as follows: internal clock operation,
alternate framing mode; active low framing signal.

Transmission is initiated by writing a word to the Tx register
after the SPORT has been enabled. As the data is clocked out of
the DSP on the rising edge of SCLK, no glue logic is required to
interface the DSP to the DAC. In the interface shown, the DAC
output is updated using the

LDAC

the

input could be tied permanently low and then the

LDAC

pin via the DSP. Alternatively,

update takes place automatically when TFS is taken high.

ADSP-2101/
ADSP-2103

1

ADDITIONAL PINS OMI TTED FO R CLARITY.

Figure 23. AD5530/AD5531 to ADSP-21xx Interface

1

FO

AD5530/

AD5531

LDAC

SYNCTFS

SDINDT

SCLKSCLK

1

00938-023

AD5530/AD5531 TO 8051 INTERFACE

A serial interface between the AD5530/AD5531 and the 8051 is
shown in
AD5530/AD5531, while RxD drives the serial data line, SDIN.
P3.3 and P3.4 are bit-programmable pins on the serial port and
are used to drive

Figure 24. TxD of the 8051 drives SCLK of the

SYNC

and

LDAC

, respectively.

The 8051 provides the LSB of its SBUF register as the first bit in
the data stream. The user has to ensure that the data in the SBUF
register is arranged correctly because the DAC expects MSB first.

80C51/80L51

1

ADDITIONAL PINS OMI TTED FO R CLARITY.

Figure 24. AD5530/AD5531 to 8051 Interface

1

P3.4

AD5530/

AD5531

LDAC

SYNCP3.3

SDINRxD

SCLKTxD

1

00938-024

When data is to be transmitted to the DAC, P3.3 is taken low.
Data on RxD is clocked out of the microcontroller on the rising
edge of TxD and is valid on the falling edge. As a result no glue
logic is required between this DAC and microcontroller interface.

The 8051 transmits data in 8-bit bytes with only eight falling
clock edges occurring in the transmit cycle. As the DAC expects
a 16-bit word, P3.3 must be left low after the first 8 bits are
transferred. After the second byte has been transferred, the P3.3
line is taken high. The DAC can be updated using

LDAC

via

P3.4 of the 8051.

AD5530/AD5531 TO MC68HC11 INTERFACE

Figure 25 shows an example of a serial interface between the
AD5530/AD5531 and the MC68HC11 microcontroller. SCK of
the MC68HC11 drives the SCLK of the DAC, and the MOSI
output drives the serial data lines, SDIN.
one of the port lines, in this case PC7.

MC68HC11

1

ADDITIONAL PINS OMI TTED FO R CLARITY.

Figure 25. AD5530/AD5531 to MC68HC11 Interface

1

PC6

The MC68HC11 is configured for master mode, MSTR = 1,
CPOL = 0, and CPHA = 1. When data is transferred to the part,
PC7 is taken low and data is transmitted MSB first. Data
appearing on the MOSI output is valid on the falling edge of SCK.
Eight falling clock edges occur in the transmit cycle, so to load the
required 16-bit word, PC7 is not brought high until the second
8-bit word has been transferred to the DAC input shift register.

SYNC

AD5530/
AD5531

LDAC

SYNCPC7

SDINMOSI

SCLKSCK

is driven from

1

00938-025

Rev. B | Page 15 of 20

AD5530/AD5531

LDAC

is controlled by the PC6 port output. The DAC can be
updated after each 2-byte transfer by bringing
example does not show other serial lines for the DAC. If
were used, it could be controlled by port output PC5. To read

LDAC

low. This

CLR

data back from the DAC register, the SDO line can be
connected to MISO of the MC68HC11, with
another port output controlling and framing the readback
data transfer.

RBEN

tied to

Rev. B | Page 16 of 20

AD5530/AD5531

V

S

V

APPLICATIONS INFORMATION

OPTOCOUPLER INTERFACE

In many process control applications, it is necessary to provide
an isolation barrier between the controller and the unit being
controlled. Opto-isolators can provide voltage isolation in
excess of 3 kV. The serial loading structure of the AD5530/
AD5531 makes it ideal for opto-isolated interfaces because the
number of interface lines is kept to a minimum.
shows a 4-channel isolated interface to the AD5530/AD5531.
To reduce the number of opto-isolators, if simultaneous
updating is not required, then the

LDAC

permanently low.

CC

µCONTROLLER

CONTROL O UT TO LDAC

SYNC OUT TO SYNC

SERIAL CLO CK OUT TO SCLK

SERIAL DATA O UT TO SDIN

Figure 26

pin can be tied

SERIAL INTERFACE TO MULTIPLE AD5530s OR AD5531s

Figure 27 shows how the pin is used to address multiple
AD5530/AD5531s. All devices receive the same serial clock and
serial data, but only one device receives the
one time. The DAC addressed is determined by the decoder.
There is some feedthrough from the digital input lines, the
effects of which can be minimized by using a burst clock.

ENABLE

CODED

ADDRESS

1

EN

DECODER

DGND

ADDITIONAL PINS
OMITT ED FOR CLARITY.

SYNC

SYNC

signal at any

SCLK

SDIN

V

CC

AD5530/AD5531

SYNC

SDIN

SCLK

AD5530/AD5531

1

SYNC

SDIN

SCLK

AD5530/AD5531

SYNC

SDIN

SCLK

1

V

OUT

1

V

OUT

1

V

OUT

OPTO COUPL ER

Figure 26. Opto-Isolated Interface

00938-026

AD5530/AD5531

SYNC

SDIN

SCLK

Figure 27. Addressing Multiple AD5530/AD5531s

DAISY-CHAINING INTERFACE WITH MULTIPLE AD5530s OR AD5531s

A number of these DAC parts can be daisy-chained together using the SDO pin. Figure 28 illustrates such a configuration.

DD

AD5530/AD5531

SCLK

SDIN

YNC

1

ADDITIONAL PINS OMI TTED FO R CLARITY.

SCLK

SDIN

SYNC

1

SDO

Figure 28. Daisy-Chaining Multiple AD5530/AD5531s

R R

AD5530/AD5531

SCLK

SDIN

SYNC

1

SDO

AD5530/AD5531

SCLK

SDIN

SYNC

SDO

R

1

TO OTHER
SERIAL DEVICES

0938-028

1

V

OUT

00938-027

Rev. B | Page 17 of 20

AD5530/AD5531

OUTLINE DIMENSIONS

5.10

5.00

4.90

0.15

0.05

4.50

4.40

4.30

PIN 1

16

0.65

BSC

COPLANARITY

COMPLIANT TO JEDEC STANDARDS MO-153-AB

0.10

0.30

0.19

9

81

1.20
MAX

SEATING
PLANE

6.40
BSC

0.20

0.09
8°

0°

0.75

0.60

0.45

Figure 29. 16-Lead Thin Shrink Small Outline Package (TSSOP)

(RU-16)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Resolution INL (LSBs) DNL (LSBs) Package Description Package Option

AD5530BRU −40°C to +85°C 12 ±1 ±1 16-Lead TSSOP RU-16
AD5530BRU-REEL −40°C to +85°C 12 ±1 ±1 16-Lead TSSOP RU-16
AD5530BRU-REEL7 −40°C to +85°C 12 ±1 ±1 16-Lead TSSOP RU-16
AD5530BRUZ −40°C to +85°C 12 ±1 ±1 16-Lead TSSOP RU-16
AD5530BRUZ-REEL −40°C to +85°C 12 ±1 ±1 16-Lead TSSOP RU-16
AD5530BRUZ-REEL7 −40°C to +85°C 12 ±1 ±1 16-Lead TSSOP RU-16
AD5531BRU −40°C to +85°C 14 ±2 ±1 16-Lead TSSOP RU-16
AD5531BRU-REEL −40°C to +85°C 14 ±2 ±1 16-Lead TSSOP RU-16
AD5531BRU-REEL7 −40°C to +85°C 14 ±2 ±1 16-Lead TSSOP RU-16
AD5531BRUZ −40°C to +85°C 14 ±2 ±1 16-Lead TSSOP RU-16
AD5531BRUZ-REEL −40°C to +85°C 14 ±2 ±1 16-Lead TSSOP RU-16
AD5531BRUZ-REEL7 −40°C to +85°C 14 ±2 ±1 16-Lead TSSOP RU-16

1

Z = Pb-free part.

1

1

1

1

1

1

Rev. B | Page 18 of 20

AD5530/AD5531

NOTES

Rev. B | Page 19 of 20

AD5530/AD5531

NOTES

©2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C00938-0-1/07(B)

Rev. B | Page 20 of 20