Datasheet AD5530 Datasheet (Analog Devices)

Serial Input, Voltage Output

a

FEATURES
Pin-Compatible 12- and 14-Bit DACs
Serial Input, Voltage Output
Maximum Output Voltage Range of ⴞ10 V
Data Readback
3-Wire Serial Interface
Clear Function to a User-Defined Voltage
Power-Down Function
Serial Data Output for Daisy-Chaining
16-Lead TSSOP Packages

APPLICATIONS
Industrial Automation
Automatic Test Equipment
Process Control
General-Purpose Instrumentation

12-/14-Bit DACs

AD5530/AD5531

GENERAL DESCRIPTION

The AD5530 and AD5531 are single 12-/14-bit serial input,
voltage output DACs, respectively.

They utilize a versatile 3-wire interface that is compatible with

™

SPI

, QSPI™, MICROWIRE™, and DSP interface standards.
Data is presented to the part in the format of a 16-bit serial word.
Serial data is available on the SDO pin for daisy-chaining pur­poses. Data readback allows the user to read the contents of the
DAC register via the SDO pin.

The DAC output is buffered by a gain of 2 amplifier and refer­enced to the potential at DUTGND. LDAC may be used to update
the output of the DAC asynchronously. A power-down (PD) pin
allows the DAC to be put into a low power state, and a CLR pin
allows the output to be cleared to a user-defined voltage, the
potential at DUTGND.

The AD5530 and AD5531 are available in 16-lead TSSOP
packages.

REFIN

REFAGND

LDAC

RBEN

SDIN

FUNCTIONAL BLOCK DIAGRAM

VSSV

DD

AD5530/AD5531

GND

R

–

+

DAC REGISTER

SHIFT REGISTER

SCLK

R

SYNC

12-/14-BIT DAC

SDO

POWER-DOWN

CONTROL LOGIC

+

–

R

R

V

OUT

DUTGND

CLR

PD

SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corporation.

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]www.analog.com
Fax: [phone] © Analog Devices, Inc., 2002

(VDD = +15 V ±10%; VSS = –15 V ±10%; GND = 0 V; RL = 5 kΩ and

1

AD5530/AD5531–SPECIFICATIONS

CL = 220 pF to GND. All specifications T

MIN

to T

, unless otherwise noted.)

MAX

Parameter AD5530 AD5531 Unit Test Conditions/Comments

ACCURACY

Resolution 12 14 Bits
Relative Accuracy ±1 ±2LSB max
Differential Nonlinearity ±1 ±1 LSB max Guaranteed Monotonic Over Temperature
Zero-Scale Error ±2 ± 8 LSB max Typically within ±1 LSB
Full-Scale Error ±2 ± 8 LSB max Typically within ±1 LSB
Gain Error ±1 ± 4 LSB typ
Gain Temperature Coefficient

2

0.5 0.5 ppm FSR/°C typ
10 10 ppm FSR/°C max

REFERENCE INPUTS

2

Reference Input Range 0/5 0/5 V min/V max Max Output Range ±10 V
DC Input Resistance 100 100 MΩ typ
Input Current ±1 ± 1 µA max Per Input. Typically ±20 nA.

DUTGND INPUT

2

DC Input Impedance 60 60 kΩ typ
Max Input Current ±0.3 ±0.3 mA typ
Input Range –4/+4 –4/+4 V min/V max Max Output Range ±10 V

O/P CHARACTERISTICS

2

Output Voltage Swing ±10 ±10 V max
Short Circuit Current 15 15 mA max
Resistive Load 5 5 kΩ min To 0 V
Capacitive Load 1200 1200 pF max To 0 V
DC Output Impedance 0.5 0.5 Ω max

DIGITAL I/O

V

, Input High Voltage 2.4 2.4 V min

INH

V

, Input Low Voltage 0.8 0.8 V max

INL

I

, Input Current ±10 ± 10 µA max Total for All Pins

INH

, Input Capacitance

C

IN

SDO VOL Output Low Voltage 0.4 0.4 V max I

2

10 10 pF max 3 pF Typ

= 1 mA

SINK

POWER REQUIREMENTS

VDD/V

SS

+15/–15 +15/–15 V nom ±10% For Specified Performance

Power Supply Sensitivity

∆Full Scale/∆V
∆Full Scale/∆V

I

DD

I

SS

DD

SS

110 110 dB typ
100 100 dB typ
2 2 mA max Outputs Unloaded
2 2 mA max Outputs Unloaded

IDD in Power-Down 150 150 µA max Typically 50 µA

NOTES

1

Temperature range for B Version: –40°C to +85°C.

2

Guaranteed by design, not subject to production test.

Specifications subject to change without notice.

REV. 0–2–

SPECIFICATIONS

1

(VDD = +12 V ±10%; VSS = –12 V ±10%; GND = 0 V;

RL = 5 kΩ and CL = 220 pF to GND; TA = T

MIN

to T

, unless otherwise noted.)

MAX

AD5530/AD5531

Parameter AD5530 AD5531 Unit Test Conditions/Comments

ACCURACY

Resolution 12 14 Bits
Relative Accuracy ±1 ± 2LSB max
Differential Nonlinearity ±1 ± 1 LSB max Guaranteed Monotonic Over Temperature
Zero-Scale Error ±2 ± 8 LSB max Typically within ±1 LSB
Full-Scale Error ±2 ± 8 LSB max Typically within ±1 LSB
Gain Error ±1 ± 4 LSB typ
Gain Temperature Coefficient

2

0.5 0.5 ppm FSR/°C typ
10 10 ppm FSR/°C max

REFERENCE INPUTS

2

Reference Input Range 0/4.096 0/4.096 V min/V max Max Output Range ±8.192 V
DC Input Resistance 100 100 MΩ typ
Input Current ±1 ± 1 µA max Per Input. Typically ±20 nA.

DUTGND INPUT

2

DC Input Impedance 60 60 kΩ typ
Max Input Current ±0.3 ±0.3 mA typ
Input Range –3/+3 –3/+3 V min/V max Max Output Range ±8.192 V

O/P CHARACTERISTICS

2

Output Voltage Swing ±8.192 ±8.192 V max
Short Circuit Current 15 15 mA max
Resistive Load 5 5 kΩ min To 0 V
Capacitive Load 1200 1200 pF max To 0 V
DC Output Impedance 0.5 0.5 Ω max

DIGITAL I/O

V

, Input High Voltage 2.4 2.4 V min

INH

, Input Low Voltage 0.8 0.8 V max

V

INL

I

, Input Current ±10 ± 10 µA max Total for All Pins

INH

C

, Input Capacitance

IN

SDO VOL Output Low Voltage 0.4 0.4 V max I

2

10 10 pF max 3 pF Typ

= 1 mA

SINK

POWER REQUIREMENTS

VDD/V

SS

+12/–12 +12/–12 V nom ±10% For Specified Performance

Power Supply Sensitivity

∆Full Scale/∆V
∆Full Scale/∆V

I

DD

I

SS

DD

SS

110 110 dB typ
100 100 dB typ
2 2 mA max Outputs Unloaded
2 2 mA max Outputs Unloaded

IDD in Power-Down 150 150 µA max Typically 50 µA

NOTES

1

Temperature range for B Version: –40°C to +85°C.

2

Guaranteed by design, not subject to production test.

Specifications subject to change without notice.

(VDD = 10.8 V to 16.5 V, VSS = –10.8 V to –16.5 V; GND = 0 V; RL = 5 kΩ and

AC PERFORMANCE CHARACTERISTICS

CL = 220 pF to GND. All specifications T

MIN

to T

, unless otherwise noted.)

MAX

Parameter A Unit Test Conditions/Comments

DYNAMIC PERFORMANCE

Output Voltage Settling Time 20 µs typ Full-Scale Change to ±1/2 LSB. DAC Latch Contents

alternately loaded with all 0s and all 1s.

Slew Rate 1.3 V/µs typ
Digital-to-Analog Glitch Impulse 120 nV-s typ DAC Latch alternately loaded with 0FFF Hex and

1000 Hex. Not dependent on load conditions.
Digital Feedthrough 0.5 nV-s typ Effect of Input Bus Activity on DAC Output Under Test
Output Noise Spectral Density

@ 1 kHz 100 nV/(Hz)

Specifications subject to change without notice. Guaranteed by design, not subject to production test.

REV. 0

1/2

typ All 1s Loaded to DAC

–3–

AD5530/AD5531

L

STANDALONE TIMING CHARACTERISTICS

RL = 5 kΩ and CL = 220 pF to GND. All specifications T

Parameter Limit at T

f

MAX

t

1

t

2

t

3

t

4

t

5

t

6

t

7

t

8

t

9

t

10

t

11

t

12

1

Guaranteed by design. Not production tested.

2

Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are measured with tr = tf = 5 ns

(10% to 90% of VDD) and timed from a voltage level of (VIL +VIH)/2.

Specifications subject to change without notice.

SCLK

SYNC

SDIN

DAC*

CLR

*LDAC MAY BE TIED PERMANENTLY LOW IF REQUIRED

7 MHz max SCLK Frequency
140 ns min SCLK Cycle Time
60 ns min SCLK Low Time
60 ns min SCLK High Time
50 ns min SYNC to SCLK Falling Edge Setup Time
40 ns min SCLK Falling Edge to SYNC Rising Edge
50 ns min Min SYNC High Time
40 ns min Data Setup Time
15 ns min Data Hold Time
5 ns min SYNC High to LDAC Low
50 ns min LDAC Pulsewidth
5 ns min LDAC High to SYNC Low
50 ns min CLR Pulsewidth

t

4

t

6

MSB LSB

DB15 DB14 DB11 DB0

MIN

, T

MAX

t7t

MIN

t

1

8

1, 2

(VDD = 10.8 V to 16.5 V, VSS = –10.8 V to –16.5 V; GND = 0 V;

to T

, unless otherwise noted.)

MAX

Unit Description

t

5

t

3

t

2

t

9

t

11

t

10

t

12

Figure 1. Timing Diagram for Standalone Mode

REV. 0–4–

AD5530/AD5531

DAISY-CHAINING AND READBACK TIMING CHARACTERISTICS

to –16.5 V; VSS = –15 V ±10%; GND = 0 V; RL = 5 kΩ and CL = 220 pF to GND. All specifications T

Parameter Limit at T

f

MAX

t

1

t

2

t

3

t

4

t

5

t

6

t

7

t

8

t

12

t

13

t

14

t

15

t

16

t

17

1

Guaranteed by design. Not production tested.

2

Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are measured with tr = tf = 5 ns

(10% to 90% of VDD) and timed from a voltage level of (VIL +VIH)/2.

3

SDO; R

Specifications subject to change without notice.

= 5 kΩ, CL = 15 pF.

PULLUP

2 MHz max SCLK Frequency
500 ns min SCLK Cycle Time
200 ns min SCLK Low Time
200 ns min SCLK High Time
50 ns min SYNC to SCLK Falling Edge Setup Time
40 ns min SCLK Falling Edge to SYNC Rising Edge
50 ns min Min SYNC High Time
40 ns min Data Setup Time
15 ns min Data Hold Time
50 ns min CLR Pulsewidth
130 ns min SCLK Falling Edge to SDO Valid
50 ns max SCLK Falling Edge to SDO Invalid
50 ns min RBEN to SCLK Falling Edge Setup Time
50 ns min RBEN Hold Time
100 ns min RBEN Falling Edge to SDO Valid

MIN

, T

MAX

Unit Description

1, 2, 3

to T

MIN

(VDD = 10.8 V to 16.5 V, VSS = –10.8 V

, unless otherwise noted.)

MAX

SCLK

SYNC

SDIN

SDO

(DAISY

CHAINING)

RBEN

SDO

(READBACK)

t

1

t

4

t

6

MSB

DB15 DB14 DB11

t7t

8

t

3

t

2

t

MSB LSB

DB15

14

DB11 DB0

t

15

t

17

MSB LSB

LSB

DB0

t

5

t

13

t

16

t

13

0

RB13 RB0

0

t

14

Figure 2. Timing Diagram for Daisy-Chaining and READBACK Mode

REV. 0

–5–

AD5530/AD5531

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS*

(TA = 25°C unless otherwise noted)

VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +17 V

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V, –17 V

V

SS

Digital Inputs to GND . . . . . . . . . . . . . –0.3 V to V

+0.3 V

DD

SDO to GND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6.5 V

REFIN to REFAGND . . . . . . . . . . . . . . . . . . . . –0.3 V, +17 V

REFIN to GND . . . . . . . . . . . . . . . . V

REFAGND to GND . . . . . . . . . . . . . V

DUTGND to GND . . . . . . . . . . . . . . V

– 0.3 V, V

SS

– 0.3 V, V

SS

– 0.3 V, V

SS

DD

DD

DD

+0.3 V
+0.3 V
+0.3 V

Operating Temperature Range

Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +85°C

ORDERING GUIDE

Model Temperature Range Resolution INL (LSBs) DNL(LSBs) Package Option*

AD5530BRU –40°C to +85 °C12 ±1 ±1 RU-16
AD5531BRU –40°C to +85 °C14 ±2 ±1 RU-16

*RU = Thin Shrink Small Outline Package.

PIN CONFIGURATION

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Maximum Junction Temperature (T

Package Power Dissipation . . . . . . . . . . . . . . (T

Thermal Impedance θ

JA

) . . . . . . . . . . 150°C

J MAX

J MAX

– TA)/θ

JA

TSSOP (RU-16) . . . . . . . . . . . . . . . . . . . . . . . . 150.4°C/W

Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . 300°C

IR Reflow, Peak Temperature (< 20 sec) . . . . . . . . . . . . 235°C

*

Stresses above those listed under Absolute Maximum Ratings may cause permanent

damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

REFAGND V

2

REFIN V

LDAC

SDIN V

SYNC

RBEN

SCLK

AD5530/

3

4

5

(Not to Scale)

6

7

8

SDO

NC = NO CONNECT

AD5531

TOP VIEW

161

15

14

13

12

11

10

9

DD

OUT

DUTGND

SS

NC

GND

PD

CLR

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD5530/AD5531 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.

REV. 0–6–

AD5530/AD5531

PIN FUNCTION DESCRIPTIONS

Pin Mnemonic Function

1 REFAGND For bipolar ±10 V output range, this pin should be tied to 0 V.

2 REFIN This is the voltage reference input for the DAC. Connect to external +5 V reference for specified bipolar

±10 V output.

3 LDAC Load DAC logic input (active low). When taken low, the contents of the shift register are transferred to

the DAC register. LDAC may be tied permanently low enabling the outputs to be updated on the rising
edge of SYNC.

4 SDIN Serial data input. This device accepts 16-bit words. Data is clocked into the input register on the falling

edge of SCLK.

5 SYNC Active low control input. Data is clocked into the shift requester on the falling edges of SCLK.
6 RBEN Active low readback enable function. This function allows the contents of the DAC register to be read.

Data from the DAC register will be shifted out on SDO pin on each rising edge of SCLK.

7 SCLK Clock input. Data is clocked into the input register on the falling edge of SCLK.

8 SDO Serial data out. This pin is used to clock out the serial data previously written to the input shift register or

may be used in conjunction with RBEN to read back the data from the DAC register. This is an open
drain output; it should be pulled high with an external pull-up resistor. In standalone mode, SDO should
be tied to GND or left high impedance.

9 CLR Level sensitive, active low input. A falling edge of CLR resets V

registers are untouched.

10 PD This allows the DAC to be put into a power-down state.

11 GND Ground reference

12 NC Do not connect anything to this pin.

13 V

SS

14 DUTGND V

15 V

16 V

OUT

DD

Negative analog supply voltage, –12 V ±10% or –15 V ±10% for specified performance.

is referenced to the voltage applied to this pin.

OUT

DAC output
Positive analog supply voltage, +12 V ±10% or +15 V ±10% for specified performance.

to DUTGND. The contents of the

OUT

TERMINOLOGY

Relative Accuracy

Relative accuracy or endpoint linearity is a measure of the maximum
deviation, in LSBs, from a straight line passing through the end­points of the DAC transfer function.

Differential Nonlinearity

Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ±1 LSB maximum
ensures monotonicity.

Zero-Scale Error

Zero-scale error is a measure of the output error when all 0s are
loaded to the DAC latch.

Full-Scale Error

This is the error in DAC output voltage when all 1s are loaded
into the DAC latch. Ideally the output voltage, with all 1s loaded
into the DAC latch, should be 2 V

– 1 LSB.

REF

Gain Error

Gain error is the difference between the actual and ideal analog
output range, expressed as a percent of the full-scale range. It is the
deviation in slope of the DAC transfer characteristic from ideal.

Output Voltage Settling Time

This is the amount of time it takes for the output to settle to a
specified level for a full-scale input change.

Digital-to-Analog Glitch Impulse

Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is specified as the area of the glitch in nV-s and is mea­sured when the digital input code is changed by 1 LSB at the
major carry transition.

Digital Feedthrough

Digital feedthrough is a measure of the impulse injected into the
analog output of the DAC from the digital inputs of the DAC, but
is measured when the DAC output is not updated. It is specified
in nV-s and is measured with a full-scale code change on the data
bus, i.e., from all 0s to all 1s and vice versa.

REV. 0

–7–

AD5530/AD5531–Typical Performance Characteristics

LSB

LSB

1

0.8

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1

0

500 1000 1500 2000 2500 3000

code

TPC 1. AD5530 Typical INL Plot

0.5

0.4

0.3

0.2

0.1

0

–0.1

–0.2

–0.3

–0.4

–0.5

500 1000 1500 2000 2500 3000

0

code

VDD = +15V

= –15V

V

SS

REFIN = +5V
REFAGND = 0V

= +25ⴗC

T

A

3500 4000

VDD = +15V

= –15V

V

SS

REFIN = +5V
REFAGND = 0V

= +25ⴗC

T

A

3500 4000

1

0.75

0.5

0.25

0

LSB

–0.25

–0.5

–0.75

–1

2000 4000 6000 8000 10000 12000 14000 16000

0

code

TPC 4. AD5531 Typical DNL Plot

2.0
VDD = +15V

= –15V

V

SS

1.5

REFIN = +5V
REFAGND = 0V

1.0

0.5

0

–0.5

ERROR – LSBs

–1.0

–1.5

–2.0

–200 20406080

–40

TEMPERATURE – ⴗC

= +15V

V

DD

= –15V

V

SS

REFIN = +5V
REFAGND = 0V
T

= +25ⴗC

A

TPC 2. AD5530 Typical DNL Plot

2

1.5

1

0.5

0

LSB

–1

–0.3

–1.5

–2

2000 4000 6000 8000 10000 12000

0

code

TPC 3. AD5531 Typical INL Plot

VDD = +15V

= –15V

V

SS

REFIN = +5V
REFAGND = 0V

= +25ⴗC

T

A

14000 16000

TPC 5. AD5531 Typical INL Error vs. Temperature

1.0
VDD = +15V

= –15V

V

SS

0.8

REFIN = +5V
REFAGND = 0V

0.6

0.4

0.2

0

–0.2

ERROR – LSBs

–0.4

–0.6

–0.8

–1.0

–200 20406080

–40

TEMPERATURE – ⴗC

TPC 6. AD5531 Typical DNL Error vs. Temperature

REV. 0–8–

AD5530/AD5531

12

0

V

OUT

– V

–12

0

8

4

–4

–8

VDD = +15V
V

SS

= –15V

REFIN = +5V
REFAGND = 0V
T

A

= +25ⴗC

5 ␮s/div

TIME – ␮s

TIME – 750ns/DIV

0

V

OUT

– V

–0.14

–0.16

–0.08

–0.02

–0.04

–0.06

–0.10

–0.12

VDD = +15V
V

SS

= –15V

REFIN = +5V
REFAGND = 0V
T

A

= +25ⴗC

ERROR – LSBs

–1

–2

–3

3

2

1

0

2.5 3.0 3.5 4.0 4.5 5.0 5.5

2.0

POSITIVE INL

NEGATIVE INL

REFIN VOLTAGE – V

VDD = +15V

= –15V

V

SS

REFAGND = 0V

= +25ⴗC

T

A

6.0

TPC 7. AD5531 Typical INL Error vs. Reference Voltage

0

–0.5

–1.0

VDD = +15V

= –15V

V

SS

REFIN = +5V
REFAGND = 0V

0.03

–40ⴗC

0.02

– mA

DD

I

0.01

0

10

SUPPLY VOLTAGE – V

TPC 10. IDD in Power-Down vs. Supply

+25ⴗC

+85ⴗC

1711 12 13 14 15 16

–1.5

ERROR – LSBs

–2.0

–2.5

TPC 8. Typical Full-Scale and Offset Error

–200 20406080

–40

TEMPERATURE – ⴗC

TPC 11. Settling Time

vs. Temperature

1.50

1.45

+85ⴗC

1.40

1.35

CURRENT – mA

1.30

1.25

1.20
10

REV. 0

+25ⴗC

–40ⴗC

VDD/VSS – V

TPC 9. IDD vs. VDD/V

SS

1711 12 13 14 15 16

TPC 12. Typical Digital-to-Analog Glitch Impulse

–9–

AD5530/AD5531

VDD = +15V

= –15V

V

SS

REFIN = +5V
REFAGND = 0V

= +25ⴗC

T

V

OUT

PD

A

2V/DIV

2V/DIV

TPC 13. Typical Power-Down Time

GENERAL DESCRIPTION
DAC Architecture

The AD5530/AD5531 are pin-compatible 12-/14-bit DACs.
The AD5530 consists of a straight 12-bit R-2R voltage mode DAC,
while the AD5531 consists of a 14-bit R-2R section. Using a +5 V
reference connected to the REFIN pin and REFAGND tied to
0 V, a bipolar ±10 V voltage output results. The DAC coding is
straight binary.

Serial Interface

Serial data on the SDIN input is loaded to the input register under
the control of SCLK, SYNC, and LDAC. A write operation
transfers a 16-bit word to the AD5530/AD5531. Figures 1 and 2
show the timing diagrams. Figure 3 shows the contents of the
input shift register. Twelve or 14 bits of the serial word are data
bits; the rest are don’t cares.

DB15 (MSB) DB0 (LSB)

X X D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X

DATA BITS

Figure 3a. AD5530 Input Shift Register Contents

DB15 (MSB) DB0 (LSB)

X X D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

DATA BITS

Figure 3b. AD5531 Input Shift Register Contents

The serial word is framed by the signal, SYNC. After a high to low
transition on SYNC, data is latched into the input shift register
on the falling edges of SCLK. There are two ways in which the
DAC register and output may be updated. The LDAC signal is
examined on the falling edge of SYNC; depending on its status,
either a synchronous or asynchronous update is selected. If
LDAC is low, then the DAC register and output are updated on
the low to high transition of SYNC. Alternatively, if LDAC is
high upon sampling, the DAC register is not loaded with the
new data on a rising edge of SYNC. The contents of the DAC
register and the output voltage will be updated by bringing

LDAC low any time after the 16-bit data transfer is complete.
LDAC may be tied permanently low if required. A simplified

diagram of the input loading circuitry is illustrated in Figure 4.

REFIN

LDAC

SYNC

SDIN

12-/14-BIT DAC

14

DAC REGISTER

14

SYNC REGISTER

14

16-BIT SHIFT

REGISTER

OUTPUT

SDO

Figure 4. Simplified Serial Interface

Data written to the part via SDIN is available on the SDO pin
16 clocks later if the readback function is not used. SDO data is
clocked out on the falling edge of the serial clock with some delay.

PD Function

The PD pin allows the user to place the device into power-down
mode. While in this mode, power consumption is at a minimum;
the device draws only 50µA of current. The PD function does
not affect the contents of the DAC register.

READBACK Function

The AD5530/AD5531 allows the data contained in the DAC
register to be read back if required. The pins involved are the
RBEN and SDO (serial data out). When RBEN is taken low, on
the next falling edge of SCLK, the contents of the DAC register
are transferred to the shift register. RBEN may be used to frame
the readback data by leaving it low for 16 clock cycles, or it may
be asserted high after the required hold time. The shift register
contains the DAC register data and this is shifted out on the
SDO line on each falling edge of SCLK with some delay. This
ensures the data on the serial data output pin is valid for the
falling edge of the receiving part. The two MSBs of the 16-bit
word will be ‘0’s.

CLR Function

The falling edge of CLR causes V

to be reset to the same

OUT

potential as DUTGND. The contents of the registers remain
unchanged, so the user can reload the previous data with LDAC
after CLR is asserted high. Alternatively, if LDAC is tied low,
the output will be loaded with the contents of the DAC register
automatically after CLR is brought high.

Output Voltage

The DAC transfer function is as follows:

V REFIN REFAGND

OUT



=× × +× −

22






D

N

2

E AGND REFIN DUTGND

2[ – ] –RF




where:

D is the decimal data word loaded to the DAC register,
N is the resolution of the DAC.

Bipolar Configuration

Figure 5 shows the AD5530/AD5531 in a bipolar circuit configu­ration. REFIN is driven by the AD586, 5 V reference, while the
REFAGND and DUTGND pins are tied to GND. This results
in a bipolar output voltage ranging from –10 V to +10 V. Resistor
R1 is provided (if required) for gain adjust. Figure 6 shows the
transfer function of the DAC when REFAGND is tied to 0 V.

REV. 0–10–

+15V

V

OUT

GND

SIGNAL

GND

C1

1␮F

2

8

6

AD586

5

R1
10k⍀

4

SIGNAL

GND

*ADDITIONAL PINS OMITTED FOR CLARITY

V

REFIN

AD5530/

AD5531*

REFAGND

V

–15V

OUT

DUTGND

SS

Figure 5. Bipolar ±10 V Operation

2 REFIN

0V

DAC OUTPUT VOLTAGE

–2 REFIN

DAC INPUT CODE 000 001 (3)FFF

V

OUT

(–10V TO +10V)

AD5530/AD5531

ADSP-2101/

ADSP-2103*

FO

TFS

DT

SCLK

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 7. AD5530/AD5531 to ADSP-21xx Interface

AD5530/AD5531 to 8051 Interface

A serial interface between the AD5530/AD5531 and the 8051 is
shown in Figure 8. TXD of the 8051 drives SCLK of the AD5530/
AD5531, while RXD drives the serial data line, SDIN. P3.3 and
P3.4 are bit-programmable pins on the serial port and are used
to drive SYNC and LDAC respectively.

The 8051 provides the LSB of its SBUF register as the first bit in
the data stream. The user will have to ensure that the data in the
SBUF register is arranged correctly as the DAC expects MSB first.

80C51/80L51*

P3.4

P3.3

RXD

TXD

AD5530/

AD5531*

LDAC

SYNC

SDIN

SCLK

AD5530/

AD5531*

LDAC

SYNC

SDIN

SCLK

Figure 6. Output Voltage vs. DAC Input Codes (Hex)

MICROPROCESSOR INTERFACING

Microprocessor interfacing to the AD5530/AD5531 is via a serial
bus that uses standard protocol compatible with microcontrollers
and DSP processors. The communications channel is a 3-wire
(minimum) interface consisting of a clock signal, a data signal,
and a synchronization signal. The AD5530/AD5531 requires a
16-bit data word with data valid on the falling edge of SCLK.

For all the interfaces, the DAC output update may be done
automatically when all the data is clocked in or asynchronously
under the control of LDAC.

The contents of the DAC register may be read using the readback
function. RBEN is used to frame the readback data, which is
clocked out on SDO. The following figures illustrate these DACs
interfacing with a simple 4-wire interface. The serial interface of
the AD5530/AD5531 may be operated from a minimum of
three wires.

AD5530/AD5531 to ADSP-21xx

An interface between the AD5530/AD5531 and the ADSP-21xx
is shown in Figure 7. In the interface example shown, SPORT0
is used to transfer data to the DAC. The SPORT control regis­ter should be configured as follows: internal clock operation,
alternate framing mode; active low framing signal.

Transmission is initiated by writing a word to the Tx register
after the SPORT has been enabled. As the data is clocked out of
the DSP on the rising edge of SCLK, no glue logic is required to
interface the DSP to the DAC. In the interface shown, the DAC
output is updated using the LDAC pin via the DSP. Alternatively,
the LDAC input could be tied permanently low and then the
update takes place automatically when TFS is taken high.

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 8. AD5530/AD5531 to 8051 Interface

When data is to be transmitted to the DAC, P3.3 is taken low.
Data on RXD is clocked out of the microcontroller on the rising
edge of TXD and is valid on the falling edge. As a result no glue
logic is required between this DAC and microcontroller interface.

The 8051 transmits data in 8-bit bytes with only eight falling clock
edges occurring in the transmit cycle. As the DAC expects a
16-bit word, P3.3 must be left low after the first 8 bits are transferred.
After the second byte has been transferred, the P3.3 line is taken
high. The DAC may be updated using LDAC via P3.4 of the 8051.

AD5530/AD5531 to MC68HC11 Interface

Figure 9 shows an example of a serial interface between the
AD5530/AD5531 and the MC68HC11 microcontroller. SCK
of the 68HC11 drives the SCLK of the DAC, while the MOSI
output drives the serial data lines, SDIN. SYNC is driven from
one of the port lines, in this case PC7.

MC68HC11*

PC6

PC7

MOSI

SCK

*ADDITIONAL PINS OMITTED FOR CLARITY

AD5530/

AD5531*

LDAC

SYNC

SDIN

SCLK

Figure 9. AD5530/AD5531 to MC68HC11 Interface

REV. 0

–11–

AD5530/AD5531

The 68HC11 is configured for master mode, MSTR= 1,
CPOL = 0, and CPHA = 1. When data is transferred to the part,
PC7 is taken low and data is transmitted MSB first. Data appear­ing on the MOSI output is valid on the falling edge of SCK. Eight
falling clock edges occur in the transmit cycle, so in order to load
the required 16-bit word, PC7 is not brought high until the second
8-bit word has been transferred to the DAC’s input shift register.

LDAC is controlled by the PC6 port output. The DAC can be
updated after each 2-byte transfer by bringing LDAC low. This
example does not show other serial lines for the DAC. If CLR
were used, it could be controlled by port output PC5. In order to
read data back from the DAC register, the SDO line could be
connected to MISO of the MC68HC11, with RBEN tied to another
port output controlling and framing the readback data transfer.

APPLICATIONS
Optocoupler Interface

In many process control applications, it is necessary to provide
an isolation barrier between the controller and the unit being
controlled. Opto-isolators can provide voltage isolation in excess
of 3 kV. The serial loading structure of the AD5530/AD5531
makes it ideal for opto-isolated interfaces as the number of
interface lines is kept to a minimum. Figure 10 shows a 4- channel
isolated interface to the AD5530/AD5531. To reduce the
number of opto-isolators, if simultaneous updating is not re­quired, then the LDAC pin may be tied permanently low.

Serial Interface to Multiple AD5530s or AD5531s

Figure 11 shows how the SYNC pin is used to address multiple
AD5530/AD5531s. All devices receive the same serial clock and
serial data, but only one device will receive the SYNC signal at any
one time. The DAC addressed will be determined by the decoder.
There will be some feedthrough from the digital input lines, the
effects of which can be minimized by using a burst clock.

AD5530/AD5531*

ENABLE

CODED

ADDRESS

*ADDITIONAL PINS
OMITTED FOR CLARITY

SCLK

SDIN

V

CC

EN

DECODER*

DGND

SYNC

SDIN

SCLK

AD5530/AD5531*

SYNC

SDIN

SCLK

AD5530/AD5531*

SYNC

SDIN

SCLK

V

OUT

V

OUT

V

OUT

V

CC

␮CONTROLLER

CONTROL OUT

SYNC OUT

SERIAL CLOCK OUT

SERIAL DATA OUT

OPTOCOUPLER

Figure 10. Opto-Isolated Interface

V

AD5530/AD5531*

SCLK

SDIN

SYNC

SCLK

SDIN

SYNC

DD

SDO

TO LDAC

Figure 11. Addressing Multiple AD5530/AD5531s

TO SYNC

Daisy-Chaining Interface with Multiple AD5530s or AD5531s

A number of these DAC parts may be daisy-chained together

TO SCLK

TO SDIN

R R R

AD5530/AD5531*

SCLK

SDIN

SYNC

using the SDO pin. Figure 12 illustrates such a configuration.

AD5530/AD5531*

SCLK

SDO

SDIN

SYNC

SDO

AD5530/AD5531*

SYNC

SDIN

SCLK

TO OTHER
SERIAL DEVICES

V

OUT

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 12. Daisy-Chaining Multiple AD5530/AD5531s

REV. 0–12–

OUTLINE DIMENSIONS

Dimensions shown in millimeters

16-Lead Thin Shrink SO Package (TSSOP)

(RU-16)

5.10

5.00

4.90

AD5530/AD5531

4.50

4.40

4.30

PIN 1

COPLANARITY

0.15

0.05

16

0.65

BSC

COMPLIANT TO JEDEC STANDARDS MO-153AB

0.30

0.19

9

6.40
BSC

81

1.20
MAX

SEATING

PLANE

0.20

0.09

8ⴗ
0ⴗ

0.75

0.60

0.45

REV. 0

–13–

–14–

–15–

C00938–0–5/02(0)

–16–

PRINTED IN U.S.A.