Page 1
Per Pin Parametric
Measurement Unit/Source Measure Unit
AD5520
FEATURES
Force/Measure Functions
Force Voltage/Current, Measure Current/Voltage
Force Current/Voltage, Measure Current/Voltage
Force/Measure Voltage Range 11 V
4 Programmable Force/Measure Current Ranges
4 A, 40 A, 400 A, 4 mA
Extended Current Ranges
40 mA and 160 mA with External Driver
Clamp Circuitry and Window Comparators On Board
Guard Amplifier
64-Lead LQFP Package
APPLICATIONS
Automatic Test Equipment
Per Pin PMU, Shared Pin PMU, Device Power Supply
Instrumentation
Source Measure, Parametric Measurement, Precision
Measurement
FUNCTIONAL BLOCK DIAGRAM
AD5520
FIN
CLH
CLL
REFGND
MEASIOUT
MEASOUT
MEASVOUT
COMPARATOR
CPH
CPOH
CPOH
CPL
CPCK
REV. A
COMPIN1
COMPIN0
STB
STANDBY
GENERAL DESCRIPTION
The AD5520 is a single channel per pin parametric measurement unit (PPMU) for use in semiconductor automatic test
equipment. The part is also suited for use as a source
measurement unit for instrumentation applications. It
contains programmable modes to force a pin voltage and
measure the corresponding current or force a current and
measure the voltage. The AD5520 can force/measure over a
± 11 V range or currents up to ± 4 mA with its on-board
force amplifier. An external amplifier is required for wider
current ranges. The device provides a force sense capability to
ensure accuracy at the tester pin. A guard output is also
available to drive the shield of a force/sense pair. The AD5520
is available in a 64-lead LQFP package.
AVEEAV
CC
COMPIN2
BW SELECT
CLAMP
DETECT
LOGICS
FSEL
CPSEL
COMPOUT1
COMPOUT0
G = 16
I
SENSE
INST AMP
V
SENSE
INST AMP
G = 1
AM1
AM2
MSEL
COMPOUT2
MOE
CLHDETECT
AM0
MEASI5H
MEASI4H
MEASI3H
MEASI2H
MEASI1H
MEASI0H
GUARDIN
G = 1
MEASVH
MEASVL
CLLDETECT
AC0
AC1
FOH
FOH3
FOH2
FOH1
FOH0
MEASIL
GUARD
AGND
QM5
QM4
DVDDCS
DGND
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 www.analog.com
Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.
Page 2
(AVCC = +15 V 5%, AVEE = –15 V 5%, DVDD = 5 V 10%, AGND = 0 V, REFGND = 0 V,
AD5520–SPECIFICATIONS
DGND = 0 V. All specifications 0C to 70C, unless otherwise noted.)
Parameter Min Typ1Max Unit Test Conditions/Comments
VOLTAGE FORCE MODE
Force Control Output Voltage Range ⫾11 V R
= 10 kΩ, C
LOAD
LOAD
= 50 pF
FOH Output Impedance 70 Ω
FOH0 2.5 kΩ
FOH1 3 kΩ
FOH2 500 Ω
FOH3 60 Ω
Input Offset Error ⫾1 ⫾5mV
Gain Error 1 %
Clamp Voltage Error
2
⫾1% FSof FIN
CURRENT MEASURE/FORCE Set with external sense resistors
FOH0 ± 4 µA MODE0, RS = 125 kΩ
FOH1 ± 40 µA MODE1, R
FOH2 ± 400 µA MODE2, R
= 12.5 kΩ
S
= 12.5 kΩ
S
FOH3 ± 4mAMODE3, RS = 125 Ω
CURRENT MEASURE MODE
High Sense Input Range, V
Linearity
3
Input Bias Current ⫾1 ⫾3nA
Input Bias Current Drift
1
MEASIxH
50 pA/°C
⫾11 V
⫾0.01 % FSR +11 V > V
> –11 V
FOL
Output Offset Error ⫾100 mV MODE0
⫾100 mV MODE1
⫾100 mV MODE2
⫾100 mV MODE3
Gain Error ⫾0.1 ⫾0.35 % Gain of 16
Gain Error Temperature Coefficient
4
30 µV/°C
MEASIOUT Output Load Current ⫾4mA
CMRR 95 dB @ DC
CURRENT FORCE MODE
Input Offset Error ⫾10 mV With MODE0, MODE1, MODE2, MODE3
Gain Error 1 %
Clamp Current Error
2
⫾1% FSof FIN
VOLTAGE MEASURE MODE
Differential Input Range ⫾11 V
Low Sense Input Voltage Range ⫾100 mV MEASVL
Linearity
3
+0.005 % FSR +11 V > V
MEASVH
to V
MEASVL
> –11 V
Input Offset Error ⫾5 ⫾10 mV FIN = 0 V, Measured @ MEASVOUT
Input Offset Error Temperature
Coefficient
Gain Error ⫾0.03 ⫾0.15 % Gain of 1
Gain Error Temperature Coefficient
Input Bias Current ⫾1 ⫾3nA
Input Bias Current Drift
MEASVOUT Output Load Current ⫾4mA
CMRR
AMPLIFIER SETTLING TIME
V
SENSE
I
SENSE
LOOP SETTLING
1
4
4
4
4, 5
⫾15 mV/°C
2 mV/°C
50 pA/°C
73 dB @ DC
Amp 20 µsTo 0.2%
Amp 12 µsTo 0.2%
4, 5
Settling to within 0.024% of 8 V step
COMPIN2 = 100 pF 450 600 µs MODE0
285 390 µs MODE1
170 240 µs MODE2, MODE3
COMPIN1 = 1000 pF 2 2.5 ms MODE0
1.8 2.4 ms MODE1, MODE2, MODE3
COMPIN0 = 3000 pF 5.75 8.7 ms MODE0, MODE1, MODE2, MODE3
REV. A–2–
Page 3
Parameter Min Typ1Max Unit Test Conditions/Comments
SLEW RATE
4, 5
50 mV/µs COMPIN2 = 100 pF
4.3 mV/µs COMPIN1 = 1000 pF
1.28 mV/µs COMPIN0 = 3000 pF
COMPARATOR
CPH, CPL Input Range ⫾11 V V
CPH
> V
CPL
Input Offset ⫾7mV
GUARD DRIVER
Output Voltage ⫾11 V
Output Impedance 130 Ω Capacitive Load Only
Output Offset Voltage 400 mV
Load Current
Output Settling Time
4
4
⫾4mA
0.5 2 µs 100 pF Capacitive Load
ANALOG REFERENCE INPUTS
Force Control Input Range ⫾11 V
Force Control Input Impedance 1 MΩ
Clamp Control Input Range ⫾11 V V
CLH
> V
CLL
Clamp Control Input Impedance 1 MΩ
Comparator Threshold Input Range ⫾11 V
Comparator Threshold Input Impedance 1 MΩ
Input Capacitance
4
3pF
ANALOG MEASUREMENT OUTPUTS
Voltage Measure Output Impedance 2 Ω
Current Measure Output Impedance 3 Ω
Multiplexed Sense Output Impedance 1 kΩ
Input Capacitance
MEASIxH, MEASVH, FOHx 8 pF
LOGIC INPUTS
Input Current ⫾1 µAAll digital inputs together
Input Low Voltage, V
Input High Voltage, V
Input Capacitance
LOGIC OUTPUTS
Output Low Voltage, V
Output High Voltage, V
INL
IHL
4
4
OL
4
OH
POWER REQUIREMENTS
AV
CC
AV
EE
Power Supply Rejection Ratio, PSRR
2.0 V
2.4 V I
+14.25 +15 +15.75 V For specific performance
–14.25 –15 +15.75 V
1
0.8 V
3pF
0.4 V I
= 2 mA
SINK
SOURCE
= 2 mA
6
FOH –25 dB 100 kHz
–16 dB 500 kHz
–15 dB 1 MHz
MEASOUT –55 dB 100 kHz
–10 dB 500 kHz
DC PSR 90 dB
DV
DD
I
AVCC
I
AVEE
I
DVDD
NOTES
1
Typical values are at 25°C and nominal supply, unless otherwise noted.
2
Full-scale = 11 V.
3
Full-scale range = 22 V.
4
Guaranteed by design and characterization but not subject to production test.
5
Force control amplifier dominates slew rate and settling time.
6
Operational with ± 12 V supplies, force/measure range is reduced to ± 8.5 V.
Specifications subject to change without notice.
5V
12 mA
12 mA
0.5 mA Digital inputs at supply rails
AD5520
REV. A
–3–
Page 4
AD5520
(AVCC = +15 V 5%, AVEE = –15 V 5%, AGND = 0 V, REFGND = 0 V, DGND = 0 V. All
1, 2
TIMING CHARACTERISTICS
DV
Parameter 5 V 10% 3.3 V Unit Conditions/Comments
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
t
11
t
12
t
13
NOTES
1
See Figure 1.
2
All input signals are specified with tr = tf = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
Specifications subject to change without notice.
00ns min CS Falling Edge to STB Falling Edge Setup Time
30 200 ns min STB Pulse Width
40 70 ns min STB Rising Edge to CS Rising Edge Setup Time
040ns min Data Setup Time
550 560 ns min CS Falling Edge to CPCK Rising Edge Setup Time
320 320 ns min CPCK Pulse Width
450 500 ns min CPCK to STB Falling Edge Setup Time
150 800 ns min STB Rising Edge to QMx, CLxDETECT Valid
100 440 ns min STB Rising Edge to CPOH, CPOL Valid
240 240 µs min Comparator Setup Time, MODE2, MODE3 settling
150 500 ns min Comparator Hold Time
100 440 ns min Comparator Output Delay Time
320 320 ns min Comparator Strobe Pulse Width
DD
specifications 0C to 70C, unless otherwise noted.)
STB
AMx, ACx, FSEL,
MSEL, CPSEL
CPCK
QM4, QM5,
CLHDETECT,
CLLDETECT
CPOL, CPOH
CS
t
1
t
4
MEASVOUT
OR MEASIOUT
CPOH, CPOL
t
2
CPCK
t
3
t
5
t
8
Figure 1. Timing Diagram
t
11
t
10
t
12
t
13
t
t
6
7
t
9
Figure 2. Comparator Timing
REV. A–4–
Page 5
AD5520
ABSOLUTE MAXIMUM RATINGS*
(TA = 25°C, unless otherwise noted.)
AVCC to AVEE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 V
to AGND . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +17 V
AV
CC
AV
to AGND . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V, –17 V
EE
DV
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V
DD
Digital Inputs to DGND . . . . . . . . . . –0.3 V to DV
Analog Inputs to AGND . . . . . AV
C
to CLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +34 V
LH
to CPL . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +34 V
C
PH
REFGND, DGND . . . . . . . . . AV
+ 0.3 V to AVEE – 0.3 V
CC
+ 0.3 V to AVEE – 0.3 V
CC
+ 0.3 V
DD
Operating Temperature Range
Commercial (J Version) . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Maximum Junction Temperature, (T
Package Power Dissipation . . . . . . . . . . . . . (T
Thermal Impedance JA . . . . . . . . . . . . . . . . . . . . . . 47.8°C/W
Lead Temperature (Soldering 10 sec) . . . . . . . . . . . . . . 300°C
IR Reflow, Peak Temperature . . . . . . . . . . . . . . . . . . . . 220°C
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
ORDERING GUIDE
Model Temperature Range Package Description Package Option
AD5520JST 0°C to 70°C 64-Lead LQFP ST-64-2
AD5520JST-REEL 0°C to 70°C 64-Lead LQFP ST-64-2
EVAL-AD5520EB Evaluation Board and Software
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD5520 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
max) . . . . . . . . . 150°C
J
max – TA)/
J
JA
REV. A
–5–
Page 6
AD5520
CPH
CPL
DV
CPOH
CPOL
CPCK
DGND
CLHDETECT
CLLDETECT
QM4
QM5
MOE
CS
STB
AC0
AC1
PIN CONFIGURATION
64-Lead LQFP
COMPIN0
COMPIN1
COMPIN2
REFGND
MEASOUT
REFGND
MEASIOUT
MEASVOUT
FIN
CLH
CLL
1
2
3
DD
4
5
6
7
8
9
10
11
12
13
14
15
16
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
AD5520
(Not to Scale)
COMPOUT1
COMPOUT2
CC_B
COMPOUT0
AV
49505152535455565758596061626364
FOH
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
AV
EE_B
MEASI5H
MEASI4H
FOH3
MEASI3H
FOH2
MEASI2H
FOH1
MEASI1H
FOH0
MEASI0H
MEASIL
MEASVH
GUARD(NC)
MEASVL
AV
CC_G
DGND
DV
DD
AM2
AM1
AM0
FSEL
STANDBY
NC = NO CONNECT
MSEL
CPSEL
AV
EE
AV
CC
AGND
EE_G
AV
NC
GUARD
GUARDIN
PIN FUNCTION DESCRIPTIONS
Pin No. Mnemonic Description
1 CPH Upper Comparator Threshold Voltage Input, CPH > CPL.
2 CPL Lower Comparator Threshold Voltage Input, CPL < CPH.
3, 18 DV
DD
Digital Supply Voltage.
4 CPOH Logic Output. When high, indicates MEASVOUT or MEASIOUT > CPH.
5 CPOL Logic Output. When high, indicates MEASVOUT or MEASIOUT < CPL.
6CPCK Logic Input. Used to initiate comparator sampling and update CPOH and CPOL.
7, 17 DGND Digital Ground.
8 CLHDETECT Logic Output. When high, indicates upper clamp active. For details, see the Clamp Function section.
9 CLLDETECT Logic Output. When high, indicates lower clamp active. For details, see the Clamp Function section.
10 QM4 Logic Output. When high, indicates current range Mode 4 is enabled. May be used to drive external
relay or switch. For details, see the High Current Ranges section.
11 QM5 Logic Output. When high, indicates current range Mode 5 is enabled. May be used to drive external
relay or switch. For details, see the High Current Ranges section.
12 MOE Active Low MEASOUT Enable.
13 CS Active Low Logic Input. The device is selected when this pin is low. For details, see the Interface
section.
14 STB Active Low Logic Input. Used in conjunction with CPCK and CS to configure the device for differ-
ent configurations. Rising edge of STB triggers sequence inputs. For details, see the Interface section.
15 AC0 Logic Input. Used in conjunction with AC1 to select one of three external compensation capacitors.
For details, see the Force Control Amplifier section.
16 AC1 Logic Input. Used in conjunction with AC0 to select one of three external compensation capacitors.
For details, see the Force Control Amplifier section.
REV. A–6–
Page 7
AD5520
PIN FUNCTION DESCRIPTIONS (continued)
Pin No. Mnemonic Description
19 AM2 Logic Input. Used in conjunction with AM1 and AM0 to select one of six current ranges or to enable
standby mode. For details, see the Current Ranges section.
20 AM1 Logic Input. Used in conjunction with AM2 and AM0 to select one of six current ranges or to enable
standby mode. For details, see the Current Ranges section.
21 AM0 Logic Input. Used in conjunction with AM2 and AM1 to select one of six current ranges or to enable
standby mode. For details, see the Current Ranges section.
22 STANDBY Logic Input. When high, device is in standby mode of operation. For details, see the Standby
Mode section.
23 FSEL Logic Input. Force mode select. Used to select between current or voltage force operation. For details,
see the Force Voltage or Force Current section.
24 MSEL Logic Input. Measure mode select. Used to connect MEASOUT to either MEASIOUT when high or
MEASVOUT when low.
25 CPSEL Logic Input. Comparator select. Used to compare CPL, CPH to MEASVOUT when low, or to
MEASIOUT when high. For details, see the Comparator Function and Strobing section.
26 AV
27 AV
EE
CC
28 AGND MEASx Input Ground.
29 AV
EE_G
30 GUARD Guard Output.
31 NC No Connect.
32 GUARDIN Guard Input.
33 AV
CC_G
34 MEASVL DUT Voltage Sense Inputs (Low Sense).
35 GUARD(NC) No Connect.
36 MEASVH DUT Voltage Sense Inputs (High Sense).
37 MEASIL DUT Current Sense Inputs (Low Sense).
38 MEASI0H DUT Current Sense Inputs (High Sense).
39 FOH0 Force Control Voltage Output.
40 MEASI1H DUT Current Sense Inputs (High Sense).
41 FOH1 Force Control Voltage Output.
42 MEASI2H DUT Current Sense Inputs (High Sense).
43 FOH2 Force Control Voltage Output.
44 MEASI3H DUT Current Sense Inputs (High Sense).
45 FOH3 Force Control Voltage Output.
46 MEASI4H DUT Current Sense Inputs (High Sense).
47 MEASI5H DUT Current Sense Inputs (High Sense).
48 AV
EE_B
49 FOH External Force Driver Control Voltage Output.
50 AV
CC_B
51 COMPOUT0 Compensation Capacitor 0 Output.
52 COMPOUT1 Compensation Capacitor 1 Output.
53 COMPOUT2 Compensation Capacitor 2 Output.
54 COMPIN0 Compensation Capacitor 0 Input.
55 COMPIN1 Compensation Capacitor 1 Input.
56 COMPIN2 Compensation Capacitor 2 Input.
57, 59 REFGND Analog Input/Output Reference Ground.
58 MEASOUT Multiplexed DUT Voltage/Current Sense Output. For details, see the Measured Parameter section.
60 MEASIOUT DUT Current Sense Output.
61 MEASVOUT DUT Voltage Sense Output.
62 FIN Force Control Voltage Input.
63 CLH Upper Clamp Voltage Input CLH > CLL.
64 CLL Lower Clamp Voltage CLL < CLH.
Most Negative Supply Voltage.
Most Positive Supply Voltage.
Most Negative Supply Voltage.
Most Positive Supply Voltage.
Most Negative Supply Voltage.
Most Positive Supply Voltage.
REV. A
–7–
Page 8
AD5520–Typical Performance Characteristics
0.0030
0.0025
0.0020
0.0015
0.0010
VM LINEARITY (%)
0.0005
0
010203040506070
TEMPERATURE (C)
VDD = +15V
= –15V
V
SS
MODE 3
TPC 1. Voltage Sense Amplifier Linearity vs. Temperature
80
70
60
50
40
30
AMPLITUDE (dB)
20
10
VDD = +15V
= –15V
V
SS
= 25C
T
A
0.0030
VDD = +15V
= –15V
V
SS
MODE 3
0.0025
0.0020
0.0015
0.0010
IM LINEARITY (%)
0.0005
0
010203040506070
TEMPERATURE (C)
TPC 4. Current Sense Linearity vs. Temperature
140
VDD = +15V
V
T
120
100
80
60
CMRR (dB)
40
20
= –15V
SS
= 25C
A
I
SENSE
CMRR
0
110100 1k 10k 100k 1M
FREQUENCY (Hz)
TPC 2. Voltage Sense Amplifier CMRR vs. Frequency
10
C
0
–10
–20
–30
AMPLITUDE (dB)
–40
VDD = +15V
–50
= –15V
V
SS
= 25C
T
A
–60
100 1k 10k 100k
C
= 1.0nF
COMP
C
COMP
FREQUENCY (Hz)
= 3.3nF
COMP
= 0.1nF
TPC 3. Force Amplifier Bandwidth–MODE 0 (4 A)
0
110100 1k 10k 100k 1M
FREQUENCY (Hz)
TPC 5. Current Sense Amplifier CMRR vs. Frequency
5
0
–5
C
–10
–15
C
= 1.0nF
–20
AMPLITUDE (dB)
–25
–30
VDD = +15V
–35
= –15V
V
SS
= 25C
T
A
–40
100 1k 10k 100k
COMP
C
COMP
FREQUENCY (Hz)
= 3.3nF
COMP
= 0.1nF
TPC 6. Force Amplifier Bandwidth–MODE 1 (40 A)
REV. A–8–
Page 9
AD5520
0
VDD = +15V
–5
= –15V
V
SS
= 25C
T
A
–10
–15
–20
C
–25
AMPLITUDE (dB)
–30
–35
–40
–45
100 1k 10k 100k
FREQUENCY (Hz)
COMP
= 1.0nF
C
COMP
C
COMP
= 3.3nF
= 0.1nF
TPC 7. Force Amplifier Bandwidth–MODE 2 (400 A)
5
VDD = +15V
= –15V
V
SS
= 25C
T
A
0
–5
–10
0
VDD = +15V
= –15V
V
–5
SS
= 25C
T
A
–10
–15
–20
–25
AMPLITUDE (dB)
–30
–35
–40
–45
100 1k 10k 100k
C
= 1.0nF
COMP
FREQUENCY (Hz)
C
COMP
C
COMP
= 3.3nF
= 0.1nF
TPC 10. Force Amplifier Bandwidth–MODE 3 (4 mA)
30
20
10
0
I
SENSE
AMPLITUDE (dB)
–15
–20
–25
1101k10k 100k 1M 10M100 100M
FREQUENCY (Hz)
TPC 8. Guard Amplifier Bandwidth
20
VDD = +15V
= –15V
V
SS
10
= 25C
T
A
0
–10
–20
–30
AMPLITUDE (dB)
–40
–50
–60
100k 1M 10M
FREQUENCY (Hz)
TPC 9. Current Sense Amplifier AC PSRR
V
AMPLITUDE (dB)
–10
–20
VDD = +15V
= –15V
V
SS
= 25C
T
A
–30
100 1k 100k 1M10k 10M
SENSE
FREQUENCY (Hz)
TPC 11. Voltage Sense and Current Sense
Amplifier Bandwidths
0
VDD = +15V
= –15V
V
SS
= 25C
T
A
–5
–10
–15
AMPLITUDE (dB)
–20
–25
–30
100k 1M 10M
FREQUENCY (Hz)
TPC 12. Force Amplifier AC PSRR–MODE 3,
= 100 pF
C
COMP
REV. A
–9–
Page 10
AD5520
20
VDD = +15V
= –15V
V
SS
10
= 25C
T
A
0
–10
–20
–30
AMPLITUDE (dB)
–40
–50
–60
100k 1M 10M
FREQUENCY (Hz)
TPC 13. Voltage Sense Amplifier AC PSRR
700
600
500
400
nV/ Hz
300
200
100
0
10 100 1k 10k 100k
FOH
I
SENSE
GUARD
V
SENSE
FREQUENCY (Hz)
TPC 14. Noise Spectral Density
16
14
V
12
10
8
6
VOLTAGE (V)
4
2
0
–2
051015 20 25 30 35 40 45
CC
V
TIME (ms)
TPC 15. Power Up
9
COMPIN2 = 100pF
8
7
6
5
4
3
VOLTAGE (V)
2
1
0
–1
0 0.001 0.002 0.003 0.004 0.005 0.006 0.007
COMPIN1 = 1000pF
COMPIN2 = 3000pF
TIME (s)
TPC 16. Settling Time, Mode 2
DUT
0.008
REV. A–10–
Page 11
THEORY OF OPERATION
The AD5520 is a single channel per pin parametric measurement
unit (PPMU) for use in semiconductor automatic test equipment. It contains programmable modes to force a pin voltage and
measure the corresponding current (FVMI), force current measure voltage (FIMV), force current measure current (FIMI), and
force voltage measure voltage (FVMV). The PPMU can force or
measure a voltage from –11 V to +11 V. It can force or measure a
current over four ranges: 4 µA, 40 µA, 400 µA, and 4 mA. The
addition of an external driver allows two extended ranges.
The device provides a force sense capability to ensure accuracy
at the tester pin. A guard output is also available to drive the
shield of a force/sense pair.
The AD5520 has an on-board window comparator that provides two bits of useful information, DUT too low or too high.
Also provided on the chip is clamp circuitry that will flag via
CLHDETECT and CLLDETECT if the voltage applied to
FIN or across the DUT has exceeded the voltage applied to
CLL and CLH.
On chip is clamp circuitry that clamps the output of the force
amplifier if the voltage at MEASIOUT and MEASVOUT
exceeds CLL and CLH.
INTERFACE
The AD5520 PPMU is controlled via a number of digital inputs,
which are discussed in detail in the following sections. All inputs
are TTL compatible. CS is used to select the device while STB
(active low input) latches data available on the other digital inputs
and updates any required digital outputs. The rising edge of STB
triggers sequence inputs. The remaining digital inputs control the
function of the PMU—which measure mode it is in, which compensation capacitor is used, and the selected current range.
Standby Mode
The AD5520 may be placed into standby mode via the standby
logic input. In this mode, the force amplifier is disconnected from
the force input (FIN), the switch in series with the force output
pins, FOHx, is opened, and the current measure amplifier is disconnected from the sense resistors. The voltage measure amplifier
is still connected across the DUT, so DUT voltage measurements may still be made while in standby mode. Figure 3 shows
the configuration of the PMU while in standby mode.
Table I. Standby Mode
AD5520
DAC
FIN
MEASIOUT
MEASVOUT
G = 16
G = 1
Figure 3. PMU in Standby Mode
Force Voltage or Force Current
FSEL is an input that determines whether the PPMU forces a
voltage or current.
Table II. FSEL Function
FSEL Function
Low Voltage Force and Current Clamp with
MEASIOUT Voltage
High Current Force and Voltage Clamp with
MEASVOUT Voltage
Measured Parameter
MEASOUT is a muxed output that tracks the sensed parameter,
MSEL connects it to the output of either the current sense
amplifier or the voltage sense amplifier, depending on which is
the measured parameter of interest.
The MEASOUT pin will be connected back to an ADC to
allow the measured value to be converted to a digital code.
Table III. MEASOUT Connected to
Voltage or Current
MSEL Function
Low MEASOUT = DUT Voltage
High MEASOUT = DUT Current
The MEASOUT pin may also be made high impedance through
the MOEB logic input.
FOHx
MEASIHx
MEASIL
MEASVH
MEASVL
R
DUT
S
REV. A
STANDBY Function
Low Normal Force Mode
High Standby Mode
Table IV. MOEB Allows MEASOUT
to Go High Impedance
MOEB Function
Low Enable MEASOUT Output
High Hi-Z MEASOUT Output
–11–
Page 12
AD5520
Current Ranges
A number of current ranges are possible with the AD5520. The
AM0, AM1, and AM2 pins are digital inputs used to establish
full-scale current range of the PMU.
Table V. Selection of Current Range
AM0 AM1 AM2 Function
Low Low Low Current Range MODE0 (up to 4 µA)
High Low Low Current Range MODE1 (up to 40 µA)
Low High Low Current Range MODE2 (up to 400 µA)
High High Low Current Range MODE3 (up to 4 mA)
Low Low High Current Range MODE4 (External
Buffer Mode)
High Low High Current Range MODE5 (External
Buffer Mode)
Low High High Standby (same as STANDBY = High)
High High High Standby (same as STANDBY = High)
RS Selection
The AD5520 is designed so that the voltage drop across each of
the R
resistors will be less than ±500 mV when maximum current
S
is flowing through them. To support other current ranges, these
sense resistor values may be changed. A force amplifier can
drive a maximum of 6 mA. It is not recommended to increase
the maximum current above the nominal range.
The two external current ranges use an external buffer to drive the
required current. Our example uses 40 mA and 160 mA ranges.
These ranges can be changed to suit user requirements for a high
current range.
Force Control Amplifier
The force control amplifier requires external capacitors connected
between the COMPOUTx and COMPINx pins. For stability
with large capacitance at the DUT, the largest capacitance value
(3000 pF) should be selected. The force control amplifier should
always contribute the dominant pole in the control loop. Settling times will increase with larger capacitances. ACx inputs
select which external compensation capacitor is used.
Table VI. AC0, AC1 Compensation Capacitor Selection
AC0 AC1 Function
Low Low Select External Compensation Capacitor 0
High Low Select External Compensation Capacitor 1
Low High Select External Compensation Capacitor 2
Comparator Function and Strobing
The AD5520 has an on-board window comparator that provides two bits of useful information, DUT too low or too high.
CPSEL is the digital input that controls this function, selecting
whether it should compare to the voltage sense or the current
sense amplifier.
Table VII. Comparator Function Select
CPSEL Function
Low Compare CPL, CPH to MEASVOUT
High Compare CPL, CPH to MEASIOUT
After CPSEL has selected which amplifier output is of interest,
logic input CPCK is used to initiate comparator sampling and
update the logic outputs CPOH and CPOL, indicating if the
voltages at MEASIOUT or MEASVOUT have exceeded voltages set at CPL or CPH (thus providing DUT too high or DUT
too low information). A rising edge on STB is required to clock
the CPOH and CPOL data out.
Table VIII. CPCK Synchronous Logic Outputs
CPOH Function
Low MEASVOUT or MEASIOUT < CPH
High MEASVOUT or MEASIOUT > CPH
CPOL Function
Low MEASVOUT or MEASIOUT > CPL
High MEASVOUT or MEASIOUT < CPL
Clamp Function
Clamp circuitry is also included on chip, allowing the output of
the force amplifier to be clamped in the event of the voltage at
MEASIOUT and MEASVOUT exceeding CLL and CLH. The
clamp circuitry play their role in the event of a short or open
circuit. When in force current range, the voltage clamps protect
the DUT in the event of an open circuit. Likewise, when forcing
a voltage and a short circuit occurs, the current clamps will
protect the DUT in this case. The clamps also function to protect the DUT in the event of a transient voltage or current spike
that may occur when changing to a different operating mode or
when programming the device to a different current range.
The digital output flags, which indicate a clamp limit has been
hit, are CLHDETECT for the upper clamp and CLLDETECT
output for the lower clamp.
Table IX. Clamp Detect Outputs
CLHDETECT Function
Low Upper Clamp Inactive
High Upper Clamp Active
CLLDETECT Function
Low Lower Clamp Inactive
High Lower Clamp Active
High Current Ranges
With the use of an external high current amplifier, two high
current ranges are possible. The current range values can be
selected as required in the application through appropriate
selection of the sense resistors connected between MEASI5H,
MEASI4H, and MEASIL. When one of these high current
ranges (MODE 4 or MODE 5) is selected via the AMx control
lines, the appropriate QM4 or QM5 output will be enabled.
These outputs can thus be used to control relays connected in
series with the high current amplifier as shown in Figure 8.
Table X. High Current Range Logic Outputs
QM4 QM5 Function
High Low Current Range MODE 4 Enable Output
Low High Current Range MODE 5 Enable Output
REV. A–12–
Page 13
AD5520
CIRCUIT OPERATION
Force Voltage
Most PMU measurements are performed while in force voltage
and measure current modes, for example, when the device is
used as a device power supply, or in continuity or leakage
testing. In the force voltage mode, the voltage at analog input
FIN is mapped directly to the voltage forced at the DUT.
When in force voltage and measure current modes, the maximum voltage applied to the input corresponds to the maximum
current outputs. Figure 4 shows the transfer function when forcing
a voltage.
V
DUT
R
DUT
V
CLH
R
16
S
V
FIN
R
CLL
V
CLL
RS 16
DUT
R
16
S
V
V
CLH
FIN
V
CLH
RS 16
V
CLH
I
V
DUT
the CLL and CLH levels to ensure the clamp voltages have not
been exceeded. Strobing CPCK and STB will provide information
about the voltage level with respect to the comparator levels,
CPH and CPL.
FIN
FOHx
MEASIHx
MEASIOUT
MEASVOUT
< I
RS 16
DUT
< I
RS 16
DUT
V
= V
DUT
G = 16
G = 1
CLH
V
CLH
V
CLL
MEASIL
MEASVH
MEASVL
> I
DUT
> I
DUT
V
DUT
RS 16
RS 16
= V
CLL
R
S
R
DUT
VFIN
CONDITION
OUTPUT
VCLH
CLH
CLL
VCLL
REFGNDI/V
V
VMEASVOUT
V
VMEASIOUT
V
> I
RS 16
CLH
DUT
< I
CLL
V
DUT
RS 16
DUT
= V
FIN
V
V
CLH
V
CLL
Figure 5. Voltage Force, Measure Current Mode
Force Current
In the force current mode, the voltage at FIN is now converted
to a current through the following relationship:
Force Current V R
= /
FIN SENSE
Figure 6 shows a simplified diagram of the PMU when in
force current mode. The control loop consists of the force
amplifier with the current sense amplifier making up the feedback path. In this case, voltage at the DUT is sensed across
the voltage measure amplifier (Gain = 1) and presented at
the MEASVOUT output.
FIN
FOHx
MEASIHx
Figure 4. Voltage Force Transfer Function
Measure Current
Figure 5 shows a simplified diagram of the PMU when in force
voltage mode. The control loop consists of the force amplifier
with the voltage sense amplifier making up the feedback path.
Current flowing through the DUT is measured by sensing the
current flowing through a selectable sense resistor, which is in
series with the DUT. The current sense amplifier (Gain = 16)
generates a voltage at its output, which is proportional to the
current flowing through the DUT. This voltage is compared to
REV. A
–13–
MEASIOUT
MEASVOUT
V
< V
CLH
DUT
V
< V
CLL
DUT
V
CLH
I
=
DUT
R
G = 16
G = 1
S
V
CLH
V
CLL
I
DUT
VFIN
VCLH
CONDITION
OUTPUT
VCLL
CLH
CLL
REFGNDI/V
V
VMEASVOUT
V
VMEASIOUT
V
CLH
V
CLL
I
DUT
=
> V
< V
DUT
DUT
V
FIN
R
S
Figure 6. Current Force, Voltage Measure Mode
> V
> V
=
MEASIL
MEASVH
MEASVL
DUT
DUT
V
CLL
R
S
R
S
R
DUT
Page 14
AD5520
Figure 7 illustrates the transfer function of the current force mode.
I
DUT
V
CLH
R
DUT
V
FIN
V
CLL
R
DUT
V
DUT
V
CLH
V
CLH
V
CLH
V
CLH
V
FIN
Figure 7. Current Force Transfer Function
Measure Voltage
A DUT voltage is tested via the voltage measure amplifier by a
window comparator to ensure that CPH and CPL levels are not
exceeded. In addition, the DUT voltage is automatically tested
against the voltage levels at the clamp, and clamp flags are
enabled if the DUT voltage exceeds either of the levels.
Short Circuit Protection
The AD5520 is designed to withstand a direct short circuit on
any of the amplifier outputs.
SETTLING TIME CONSIDERATIONS
Fast throughput is a key requirement in automatic test equipment
because it relates directly to the cost of manufacturing the DUT,
thus reducing the time required to make a DAC measurement is of
upmost importance. When taking measurements using a PMU, the
limiting factor is usually the time it takes the output to settle to the
required accuracy so a measurement can be taken. DUT capacitance, measurement accuracy, and the design of the PMU are the
major contributors to this time. Figure 8 shows a simplified block
diagram of the AD5520 PMU. In brief, the device consists of a
force control amplifier, access to a number of selectable sense
resistors, a voltage measure instrumentation amplifier, and a
current measure instrumentation amplifier. To optimize the
performance of the device, there are also nodes provided where
external compensation capacitors are added. As mentioned, making an accurate measurement in the fastest time while avoiding
overshoots and ringing is the key requirement in any ATE system.
This in itself provides challenges. The external compensation
capacitors set up different settling times or bandwidths on the force
control amplifier, and, while one compensation capacitor value
may suit one range, it may not suit other ranges. To optimize
measurement performance and speed, differences in signal behavior on each range and frequency of use of each range need to be
taken into account.
When selecting a faster settling time, there is a trade-off between
the faster settling, overshoots, and ringing. A small compensation value will result in faster settling but may incur penalties in
overshoots or ringing at the DUT. Compensation capacitor
selection should be optimized to ensure minimum overshoots
while still giving good settling time performance.
While careful selection of the compensation capacitor is required
to minimize the settling time, another factor can greatly contribute
to the overall settling of the loop if the feedback loop is broken
in some manner and the force control amplifier goes to either
the positive or negative rails. There is a finite amount of time
required for the amplifier to recover from this condition, typically 85 µs, which adds to the settling of the loop. Ensuring that
the force control amplifier never goes into saturation is the best
solution. This solution can be helped by putting the device into
standby mode at any time the operating mode or range selection
is changed. In addition, ensure that the selected output range
can supply the required current needed by the DUT.
PCB LAYOUT AND POWER SUPPLY DECOUPLING
In any circuit where accuracy is important, careful consideration
to the power supply and the ground return layout helps to ensure
the rated performance. The printed circuit board on which
the AD5520 is mounted should be designed so that the analog
and digital sections are separated and confined to certain areas
of the board. If the PMU is in a system where multiple devices
require an AGND-to-DGND connection, the connection should
be made at one point only. The star ground point should be
established as close as possible to the device.
This PMU should have ample supply bypassing of 10 µF in
parallel with 0.1 µF on the supply located as close to the pack-
age as possible, ideally right up against the device. The 0.1 µF
capacitor should have low effective series resistance (ESR) and
effective series inductance (ESI), such as the common ceramic
types that provide a low impedance path to ground at high
frequencies, to handle transient currents due to internal logic
switching. Low ESR, 1 µF to 10 µF, tantalum or electrolytic
capacitors should also be applied at the supplies to minimize
transient disturbance and filter out low frequency ripple.
Fast switching signals, such as clocks, should be shielded with
digital ground to avoid radiating noise to other parts of the
board and should never be run near the reference inputs.
Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other.
This reduces the effects of feedthrough through the board. A
microstrip technique is by far the best but not always possible
with a double-sided board. In this technique, the component
side of the board is dedicated to the ground plane while signal
traces are placed on the solder side.
REV. A–14–
Page 15
AD5520
It is good practice to employ compact, minimum lead length
PCB layout design. Leads to the input should be as short as
possible to minimize IR drops and stray inductance.
TYPICAL CONNECTION CIRCUIT FOR THE AD5520
Figure 8 shows the AD5520 connected as it would be in a typical
application. The external components required are three compensation capacitors and six sense resistors, depending on how
many ranges are required. If high current ranges > 6 mA are
3000pF
1000pF
100pF
+15V –15V
AVEEAV
CC
AD5520
FIN
CLH
CLL
REFGND
MEASIOUT
MEASOUT
MEASVOUT
COMPARATOR
CPH
CPOH
CPOH
CPL
COMPIN0
COMPIN2
COMPIN1
BW SELECT
COMPOUT1
COMPOUT0
FORCE
AMPLIFIER
CLAMP
DETECT
G = 16
I
SENSE
INST AMP
V
SENSE
INST AMP
G = 1
LOGICS
COMPOUT2
G = 1
MEASI5H
MEASI4H
MEASI3H
MEASI2H
MEASI1H
MEASI0H
GUARDIN
required, an external amplifier must be used with relays to switch
in the different current ranges to the DUT. Other components
are also required to make the PMU function. The PMU requires
a number of discrete voltage levels: five DAC levels for each
PMU used in the system, two levels each for the comparator
and clamps, and one voltage level for the AD5520 force input
voltage. To utilize the information gathered from the DUT, an
ADC (such as the AD7665 16-Bit ADC) must be connected to
the MEASOUT pin to convert the measured current or voltage
to the digital world for analysis.
FOH
FOH3
FOH2
FOH1
FOH0
12.5k⍀
125k⍀
MEASIL
GUARD
MEASVH
MEASVL
AGND
QM5
QM4
AD815
RELAY
<ⴞ11.5V
3.126⍀
12.5⍀
125⍀
1.25k⍀
ⱕⴞ11V
DUT
<ⴞ100mV
REV. A
CPCK
STB
STANDBY
FSEL
CPSEL
MSEL
AM2
AM1
AM0
MOE
CLHDETECT
CLLDETECT
AC0
AC1
DVDDCS
DGND
Figure 8. Typical Configuration of the AD5520 as Used in an ATE Circuit
–15–
Page 16
AD5520
TYPICAL APPLICATION CIRCUIT
Figure 9 shows the AD5520 as it would be used in an ATE
system. This device could be used as a per pin parametric unit
in order to speed up the rate at which testing could be done. It
could also be used as a DUT power supply, as shown in the
application circuit. The central PMU shown in the block
diagram is usually a highly accurate PMU and is shared among a
number of pins in the tester. In general, many discrete levels are
required in an ATE system for the pin drivers, comparators,
clamps, and active loads. DAC devices, such as the AD5379, offer
a highly integrated solution for a number of these levels. The
AD5379 is a dense 40-channel DAC designed with high channel
requirements, like ATE in mind.
The flexible function of the AD5520 also makes it suited for use in
instrumentation applications such as source measure units. Source
measure units are programmable instruments capable of sourcing
and measuring voltage or current simultaneously. The AD5520
provides a more integrated solution in such equipment.
EVALUATION BOARD FOR THE AD5520 PMU
A full featured evaluation kit is available for the AD5520. It
consists of an evaluation board with direct hookup via a 36-way
CENTRAL PMU
TIMING DATA
MEMORY
TIMING
GENERATOR
DLL, LOGIC
DAC
ADC
FORMATTER
DE-SKEW
DAC
DAC
GUARD AMP
DAC
VTERM
VH
DRIVER
VCH
RELAYS
centronics connector to a PC. PC-based software to control the
AD5520 is provided as part of the evaluation kit. The evaluation board schematic is shown in Figure 10. Note that V
must provide sufficient headroom for the force and measure
V
SS
DD
and
voltage range. In addition to the supply voltages for the evaluation board, it is also necessary to provide the following voltage
levels for the clamp, comparator, and the force input pin—CLL,
CLH, CPL, CPH, and FIN. SMB connections are provided
for these voltage inputs. To use the evaluation board, it will also
be necessary to provide a DUT connected via the gold pins.
Both AGND and DGND inputs are provided on the board.
The AGND and DGND planes are connected at one location
close to the AD5520. It is recommended not to connect AGND
and DGND elsewhere in the system to avoid ground loop problems. REFGND is routed back to AGND at the power block to
maintain a clean ground reference for accurate measurements.
Each supply is decoupled to the relevant ground plane with
10 F and 0.1 F capacitors. The device supply pin is again
decoupled with a 10 F and 0.1 F capacitor pair to the relevant
ground plane.
Care should be taken when replacing devices to ensure that
the pins line up correctly with the PCB pads.
PPMU
DAC
ADC
DEVICE UNDER
TEST (DUT)
50 COAX
COMPARE
MEMORY
FORMATTER
DE-SKEW
DAC
DAC
DAC
DAC
DAC
DAC
VCL
VL
DAC
COMP
VTH
VTL
ACT IVE LOAD
IOL
VCOM
IOH
Figure 9. Typical Application ATE Circuit
GND SENSE
DEVICE POWER
SUPPLIES
DAC
ADC
GUARD
AMP
REV. A–16–
Page 17
AD5520
QM5
R9
D2
RL2
10k
B
C
Q1
C16
10pF
E
T1
T3
U5–B
14
15
16
AD815ARB–24
T2
D1
RL1
AD815ARB
59
57
REFGND
REFGND
974210
RELAY–G6H
974210
RELAY–G6H
R11
52
E
R5, 12.4
R4, 124
R3, 1.24k
R2, 12.4k
R1, 124k
54
C9, 3.3nF
QM4
C15
10pF
35
36
NC
MEASVH
COMPIN0
COMPOUT0
51
323130
34
MEASVL
GAURDIN
EE
AV
26
29
C5
LK1
NC
AV
0.1F
C10
–15V
GUARD
EE_G
48
10F
C17
EE_B
AV
C19
R10
C6
20V
DGND AGND
7 17 28
DGND
10F
C11
C18
0.1F
20V
C12
0.1F
AD815ARB–24
12
13
+VS
–VS
U5–C
+15V
20V
C23
10F
C22
0.1F
J11–1
20V
+5VD
C21
10F
C20
0.1F
C13
C25
C24
J11–2
10F
20V
20V
+15V
–15V
10F
0.1F
J11–3
R8
10k
B
C
Q1
R7
R6
5k
C14
49
4746454443424140393837
FOH
16
FOH3
FOH2
MEASI5H
MEASI4H
MEASI3H
MEASI2H
CPOH4CPOL5CHL-DET8CLL-DET9QM410QM5
FOH1
11
FOH0
MEASIL
MEASI1H
MEASIOH
COMPIN256COMPOUT2
53
C8, 1nF
C7, 100pF
COMPIN155COMPOUT1
831
+5VD +5VD
J9
J8
J7
J6
T4
27
C4
T5
CC
CC_G
AV
AV
33
10F
T7
T6
6061626364
58
MEASOUT
MEASIOUT
CC_B
AV
50
20V
J5
J4
J3
J2
C2
C1
20V
10F
0.1F
DD
3
DV
+15V
DD
DV
18
C3
0.1F
+5VD
T11
T10
T9
T8
FIN
CLL
CLH
MEASVOUT
STANDBY22STB14CPCK6MOEB12CSB13AM021AM120AM219FSEL23CPSEL25MSEL24AC015AC1
1
2
CPH
CPL
U5–A
R12
831
5k
T12
U2, U3, U4 BYPASS CAPACITORS
REV. A
18
19
Q0
74HCT573
D0D1D2D3D4D5D6
2
D0D1D2D3D4D5D6
D[0:7]
+5VD
C28
0.1F
C27
0.1F
C26
0.1F
15
16
17
141312
Q1Q2Q3Q4Q5Q6Q7
D7
6
543
789
D7
U2
C
11
J1–14
J10–1
J10–2
1
141312
11
C
D7
OE
U4
74HCT573
J1–19
D7
J1–31
J1–36
J1–23
J1–22
J1–21
J1–20
D0D1D2D3D4D5D6
J1–2
J1–24
J1–3
J1–25
J1–4
J1–26
J1–5
J1–27
J1–28
J1–7
J1–6
J1–29
J1–30
D7
J1–9
J1–8
543
11
U3
C
1
J1–1
OE
2
D0D1D2D3D4D5D6
Q0
19
D0D1D2D3D4D5D6
19
Q0
74HCT573
OE
1
D0D1D2D3D4D5D6
2
D0D1D2D3D4D5D6
141312
Q1Q2Q3Q4Q5Q6Q7
D7
6
543
789
D7
15
16
17
18
789
6
Q1Q2Q3Q4Q5Q6Q7
15
16
17
18
Figure 10. Evaluation Board Schematic
–17–
Page 18
AD5520
OUTLINE DIMENSIONS
64-Lead Low Profile Quad Flat Package [LQFP]
(ST-64-2)
Dimensions shown in millimeters
1.45
1.40
1.35
0.15
0.05
10ⴗ
6ⴗ
2ⴗ
SEATING
PLANE
ROTATED 90ⴗ CCW
VIEW A
0.08 MAX
COPLANARITY
0.75
0.60
0.45
SEATING
PLANE
0.20
0.09
7ⴗ
3.5ⴗ
0ⴗ
COMPLIANT TO JEDEC STANDARDS MS-026BCD
1.60
MAX
1
VIEW A
16
17
PIN 1
0.50
BSC
12.00 BSC
SQ
TOP VIEW
(PINS DOWN)
0.27
0.22
0.17
4964
48
10.00
BSC SQ
33
32
REV. A–18–
Page 19
AD5520
Revision History
Location Page
10/03—Data Sheet changed from REV. 0 to REV. A.
Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Updated ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
REV. A
–19–
Page 20
C03701–0–10/03(A)
–20–
Loading...