Datasheet AD5516 Datasheet (Analog Devices)

16-Channel, 12-Bit Voltage-Output DAC

with 14-Bit Increment Mode

FEATURES
High Integration:

16-Channel DAC in 12 mm ⴛ 12 mm

CSPBGA
14-Bit Resolution via Increment/Decrement Mode
Guaranteed Monotonic

®

Low Power, SPI

, QSPI™, MICROWIRE™, and
DSP Compatible
3-Wire Serial Interface

Output Impedance 0.5 ⍀
Output Voltage Range

ⴞ2.5 V (AD5516-1)
ⴞ5 V (AD5516-2)
ⴞ10 V (AD5516-3)

Asynchronous Reset Facility (via RESET Pin)
Asynchronous Power-Down Facility (via PD Pin)
Daisy-Chain Mode
Temperature Range: –40ⴗC to +85ⴗC

APPLICATIONS
Level Setting
Instrumentation
Automatic Test Equipment
Optical Networks
Industrial Control Systems
Data Acquisition
Low Cost I/O

FUNCTIONAL BLOCK DIAGRAM

AD5516

*

GENERAL DESCRIPTION

The AD5516 is a 16-channel, 12-bit voltage-output DAC. The
selected DAC register is written to via the 3-wire serial inter­face. DAC selection is accomplished via address bits A3–A0.
14-bit resolution can be achieved by fine adjustment in Incre­ment/Decrement Mode (Mode 2). The serial interface operates
at clock rates up to 20 MHz and is compatible with standard
SPI, MICROWIRE, and DSP interface standards. The output
voltage range is fixed at ±2.5 V (AD5516-1), ±5 V (AD5516-2),
and ± 10 V (AD5516-3). Access to the feedback resistor in each
channel is provided via the R

The device is operated with AV
to 5.25 V, V

= –4.75 V to –12 V, and V

SS

0 to RFB15 pins.

FB

= 5 V ± 5%, DVCC = 2.7 V

CC

= +4.75 V to +12 V,

DD

and requires a stable 3 V reference on REF_IN.

PRODUCT HIGHLIGHTS

1. Sixteen 12-bit DACs in one package, guaranteed monotonic.

2. Available in a 74-lead CSPBGA package with a body size of
12 mm ⫻ 12 mm.

DV

AV

CC

CC

AD5516

RESET

BUSY

DACGND

AGND

DGND

DCEN

*Protected by U.S. Patent No. 5,969,657; other patents pending.

ANALOG

CALIBRATION

LOOP

MODE1

INTERFACE

CONTROL

LOGIC

SCLK DIND

12-BIT BUS

SYNC

OUT

MODE2

7-BIT BUS

REV. B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.

LOGIC

PD

V

DDVSS

R

OFFS

R

OFFS

R

OFFS

R

OFFS

R

FB

RFB0

V

0

OUT

R

FB

RFB1

1

V

OUT

R

FB

R

FB

14

R

FB

14

V

OUT

15

R

FB

V

15

OUT

REF_IN

V

BIAS

DAC

DAC

DAC

DAC

POWER-DOWN

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2003 Analog Devices, Inc. All rights reserved.

(VDD = +4.75 V to +13.2 V, VSS = –4.75 V to –13.2 V; AVCC = 4.75 V to 5.25 V; DVCC =

AD5516–SPECIFICATIONS

Parameter

DAC DC PERFORMANCE

VOLTAGE REFERENCE

ANALOG OUTPUTS (V

DIGITAL INPUTS

DIGITAL OUTPUTS (BUSY, D

POWER REQUIREMENTS

NOTES

1

See Terminology section.

2

A Version: Industrial temperature range –40∞C to +85∞C; typical at +25∞C.

3

Guaranteed by design and characterization; not production tested.

4

AD780 as reference for the AD5516.

5

Output range is restricted from V

6

Ensure that you do not exceed T

7

With 5 kW resistive load, footroom required is as follows: AD5516–1, 2 V; AD5516–2, 2.5 V; AD5516–3, 3 V.

8

Outputs unloaded.

Specifications subject to change without notice.

1

Resolution 12 Bits
Integral Nonlinearity (INL) ± 2 LSB max Mode 1
Differential Nonlinearity (DNL) –1/+1.3 LSB max ± 0.5 LSB typ, Monotonic; Mode 1
Increment/Decrement Step-Size ± 0.25 LSB typ Monotonic; Mode 2 Only
Bipolar Zero Error ± 7 LSB max
Positive Full-Scale Error ± 10 LSB max
Negative Full-Scale Error ± 10 LSB max

REF_IN

Nominal Input Voltage 3 V
Input Voltage Range

3

Input Current ± 1 mA max < 1 nA typ

0–15)
Output Temperature Coefficient
DC Output Impedance
Output Range

5

OUT

3

3, 4

AD5516-1 ± 2.5 V typ 100 mA Output Load
AD5516-2 ± 5V typ 100 mA Output Load

AD5516-3 ± 10 V typ 100 mA Output Load
Resistive Load
Capacitive Load
Short Circuit Current
DC Power Supply Rejection Ratio
DC Crosstalk

3, 6, 7

3, 6

3

3

3

3

Input Current ± 10 mA max ± 5 mA typ
Input Low Voltage 0.8 V max DV

Input High Voltage 2.4 V min DV

Input Hysteresis (SCLK and SYNC) 150 mV typ
Input Capacitance 10 pF max 5 pF typ

3

)
Output Low Voltage, DVCC = 5 V 0.4 V max Sinking 200 mA
Output High Voltage, DV
Output Low Voltage, DV
Output High Voltage, DV
High Impedance Leakage Current (D
High Impedance Output Capacitance (D

OUT

= 5 V 4 V min Sourcing 200 mA

CC

= 3 V 0.4 V max Sinking 200 mA

CC

= 3 V 2.4 V min Sourcing 200 mA

CC

only) ± 1 mA max DCEN = 0

OUT

only) 5 pF typ DCEN = 0

OUT

Power Supply Voltages

V

DD

V

SS

AV

CC

DV

CC

Power Supply Currents

I

DD

I

SS

AI

CC

DI

CC

Power-Down Currents

I

DD

I

SS

AI

CC

DI

CC

Power Dissipation

8

8

8

+ 2 V to V

SS

. See Absolute Maximum Ratings section.

J (MAX)

– 2 V. Output span varies with reference voltage and is functional down to 2 V.

DD

2.7 V to 5.25 V; AGND = DGND = DACGND = 0 V; REF_IN = 3 V; All outputs unloaded.
All specifications T

A Version

2.875/3.125 V min/max

10 ppm/∞C typ of FSR

0.5 W typ

5kW min
200 pF
7 mA typ
–85 dB typ VDD = +12 V ± 5%, VSS = –12 V ± 5%

0.1 LSB max

0.4 V max DV

2V min DV

4.75/15.75 V min/max
–4.75/–15.75 V min/max

4.75/5.25 V min/max

2.7/5.25 V min/max

5 mA max 3.5 mA typ. All Channels Full-Scale.
5 mA max 3.5 mA typ. All Channels Full-Scale.
17 mA max 13 mA typ

1.5 mA max 1 mA typ

1 mA typ
1 mA typ
2 mA max 200 nA typ
2 mA max 200 nA typ

105 mW typ VDD= +5 V, VSS= –5 V

2

MIN

to T

, unless otherwise noted.)

MAX

Unit Conditions/Comments

= 5 V ± 5%

CC

= 3 V ± 10%

CC

= 5 V ± 5%

CC

= 3 V ± 10%

CC

REV. B–2–

(VDD = +4.75 V to +13.2 V, VSS = –4.75 V to –13.2 V; AVCC = 4.75 V to 5.25 V; DVCC = 2.7 V to 5.25 V;

AC CHARACTERISTICS

Parameter

Output Voltage Settling Time (Mode 1)

1, 2

AGND = DGND = DACGND = 0 V; REF IN = 3 V. All outputs unloaded.
All specifications T

4

to T

MIN

MAX

A Version

, unless otherwise noted.)

3

Unit Conditions/Comments

100 pF, 5 kW Load Full-Scale Change
AD5516–1 32 ␮s max
AD5516–2 32 ␮s max
AD5516–3 36 ␮s max

Output Voltage Settling Time (Mode 2)

4

100 pF, 5 kW Load, 127 Code Increment
AD5516–1 2.5 ␮s max
AD5516–2 3.35 ␮s max
AD5516–3 7 ␮s max

Slew Rate 0.85 V/␮s typ
Digital-to-Analog Glitch Impulse 1 nV-s typ 1 LSB Change around Major Carry
Digital Crosstalk 5 nV-s typ
Analog Crosstalk

AD5516–1 1 nV-s typ
AD5516–2 5 nV-s typ
AD5516–3 20 nV-s typ

Digital Feedthrough 1 nV-s typ
Output Noise Spectral Density @ 10 kHz

AD5516–1 150 nV/(Hz)
AD5516–2 350 nV/(Hz)
AD5516–3 700 nV/(Hz)

NOTES

1

See Terminology section.

2

Guaranteed by design and characterization; not production tested.

3

A version: Industrial temperature range –40∞C to +85∞C.

4

Timed from the end of a write sequence and includes BUSY low time.

Specifications subject to change without notice.

1/2

1/2

1/2

typ
typ
typ

AD5516

(VDD = +4.75 V to +13.2 V, VSS = – 4.75 V to –13.2 V; AVCC = 4.75 V to 5.25 V; DVCC = 2.7 V to 5.25 V;

TIMING CHARACTERISTICS

Parameter

f

UPDATE1

f

UPDATE2

f

CLKIN

t

1

t

2

t

3

t

4

t

5

t

6

t

7

t

7MODE2

t

8MODE1

t

9MODE2

t

10

4

t

11

t

12

NOTES

1

See Timing Diagrams in Figures 1 and 2.

2

Guaranteed by design and characterization; not production tested.

3

All input signals are specified with tr = tf = 5 ns (10% to 90% of DVCC) and timed from a voltage level of (VIL + VIH)/2.

4

This is measured with the load circuit of Figure 3.

Specifications subject to change without notice.

1, 2, 3

Limit at T
(A Version) Unit Conditions/Comments

32 kHz max DAC Update Rate (Mode 1)
750 kHz max DAC Update Rate (Mode 2)
20 MHz max SCLK Frequency
20 ns min SCLK High Pulsewidth
20 ns min SCLK Low Pulsewidth
15 ns min SYNC Falling Edge to SCLK Falling Edge Setup Time
5 ns min DIN Setup Time
5 ns min DIN Hold Time
0 ns min SCLK Falling Edge to SYNC Rising Edge
10 ns min Minimum SYNC High Time (Standalone Mode)
400 ns min Minimum SYNC High Time (Daisy-Chain Mode)
10 ns min BUSY Rising Edge to SYNC Falling Edge
200 ns min 18th SCLK Falling Edge to SYNC Falling Edge (Standalone Mode)
10 ns min SYNC Rising Edge to SCLK Rising Edge (Daisy-Chain Mode)
20 ns max SCLK Rising Edge to D
20 ns min RESET Pulsewidth

MIN

, T

AGND = DGND = DACGND = 0 V. All specifications T

MAX

to T

MIN

Valid (Daisy-Chain Mode)

OUT

, unless otherwise noted.)

MAX

REV. B

–3–

AD5516

TIMING DIAGRAMS

SCLK

SYNC

DIN

BUSY

RESET

SCLK

SYNC

D

12 1718

t

MODE1

8

t

t

7

3

t

4

BIT 17 BIT 0

t

2

t

5

t

1

t

6

t

MODE2

LSBMSB

9

t

12

Figure 1. Serial Interface Timing Diagram

t

t

MODE2

7

IN

3

t

4

BIT 17 BIT 0 BIT 17 BIT 0

t

2

t

5

t

1

LSBMSB

t

10

t

6

D

OUT

BUSY

t

MODE1

8

INPUT WORD FOR DEVICE N

t

11

BIT 17 BIT 0

UNDEFINED INPUT WORD FOR DEVICE N

Figure 2. Daisy-Chaining Timing Diagram

200␮A

TO OUTPUT

PIN

C

L

50pF

200␮A

Figure 3. Load Circuit for D

I

OL

I

OH

Timing Specifications

OUT

INPUT WORD FOR DEVICE N+1

1.6V

REV. B–4–

AD5516

ABSOLUTE MAXIMUM RATINGS

(TA = 25°C, unless otherwise noted.)

1, 2

VDD to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +17 V

V

to AGND . . . . . . . . . . . . . . . . . . . . . . . . .+0.3 V to –17 V

SS

to AGND, DACGND . . . . . . . . . . . . . . . –0.3 V to +7 V

AV

CC

to DGND . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +7 V

DV

CC

Digital Inputs to DGND . . . . . . . . . . .–0.3 V to DV

Digital Outputs to DGND . . . . . . . . . .–0.3 V to DV

REF_IN to AGND, DACGND . . . . . . –0.3 V to AV

0–15 to AGND . . . . . . . . . . . . V

V

OUT

– 0.3 V to V

SS

+ 0.3 V

CC

+ 0.3 V

CC

+ 0.3 V

CC

+ 0.3 V

DD

AGND to DGND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

0–15 to AGND . . . . . . . . . . . . . V

R

FB

– 0.3 V to VDD+0.3 V

SS

Operating Temperature Range, Industrial . . . . . –40°C to +85°C

ORDERING GUIDE

Model Function Output Voltage Span Package Option

AD5516ABC-1 16 DACs ± 2.5 V 74-Lead CSPBGA
AD5516ABC-2 16 DACs ± 5 V 74-Lead CSPBGA
AD5516ABC-3 16 DACs ± 10 V 74-Lead CSPBGA
EVAL-AD5516-1EB Evaluation Board
EVAL-AD5516-2EB Evaluation Board
EVAL-AD5516-3EB Evaluation Board

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Junction Temperature (T
74-Lead CSPBGA Package, ␪

) . . . . . . . . . . . . . . . . . . . 150°C

J MAX

Thermal Impedance . . . 41°C/W

JA

Reflow Soldering

Peak Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C

Time at Peak Temperature . . . . . . . . . . . . . 10 sec to 40 sec

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause permanent

damage to the device. This is a stress rating only; functional operation of the device
at these or any other conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.

2

Transient currents of up to 100 mA will not cause SCR latch-up.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD5516 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.

REV. B

–5–

AD5516

PIN CONFIGURATION

1110987654321

A

B

C

D

E

F

G

H

J

K

LL

TOP VIEW

A

B

C

D

E

F

G

H

J

K

1110987654321

74-LEAD CSPBGA BALL CONFIGURATION

CSPBGA Ball CSPBGA Ball CSPBGA Ball CSPBGA Ball CSPBGA Ball
Number Name Number Name Number Name Number Name Number Name

A1 NC
A2 NC
A3 RESET
A4 BUSY
A5 DGND
A6 DV
A7 D
A8 D

CC

OUT

IN

A9 SYNC
A10 NC
A11 NC
B1 NC
B2 NC
B3 NC
B4 DCEN

NC = Not Internally Connected

B5 DGND
B6 DGND
B7 NC
B8 NC
B9 SCLK
B10 NC
B11 REF_IN
C1 V

OUT

0
C2 DACGND
C6 NC
C10 AV

CC

1
C11 NC
D1 R

FB

0
D2 DACGND
D10 AV

CC

2

D11 NC
E1 V

OUT

1
E2 NC
E10 AGND1
E11 PD
F1 V
F2 R

OUT

FB

2

1
F10 AGND2
F11 R
G1 R
G2 R
G10 V
G11 R
H1 V
H2 V

FB

FB

FB

OUT

FB

OUT

OUT

14
2
15

14

13

3
15

H10 V
H11 V
J1 R
J2 V

OUT

OUT

FB

OUT

3

J6 NC
J10 R

FB

12
J11 RFB11
K1 R
K2 V

FB

OUT

4

K3 RFB5
K4 NC
K5 V

2

SS

K6 VSS1
K7 V
K8 V

OUT

OUT

13
12

4

5

10
9

K9 R
K10 R
K11 V
L1 NC
L2 V
L3 R
L4 V
L5 NC
L6 V
L7 VDD1
L8 R
L9 V
L10 RFB8
L11 NC

FB

FB

OUT

OUT

FB

OUT

DD

FB

OUT

10
9

6

2

7

11

6

7

8

PIN FUNCTION DESCRIPTIONS

Mnemonic Function

AGND (1–2) Analog GND Pins
AV

(1–2) Analog Supply Pins. Voltage range from 4.75 V to 5.25 V.

CC

V

(1–2) VDD Supply Pins. Voltage range from 4.75 V to 15.75 V.

DD

V

(1–2) VSS Supply Pins. Voltage range from –4.75 V to –15.75 V.

SS

DGND Digital GND Pins
DV

CC

Digital Supply Pin. Voltage range from 2.7 V to 5.25 V.
DACGND Reference GND Supply for All 16 DACs
REF_IN Reference Input Voltage for All 16 DACs. The recommended value of REF_IN is 3 V.
V

(0–15) Analog Output Voltages from the 16 DAC Channels

OUT

R

(0–15) Feedback Resistors. For nominal output voltage range, connect each RFB to its corresponding V

FB

. Access to

OUT

the feedback resistors enables the user to increase the DAC current drive or generate programmable current

sources. They should not be used for gain adjustment.
SYNC Active Low Input. This is the frame synchronization signal for the serial interface. While SYNC is low, data is

transferred in on the falling edge of SCLK.

REV. B–6–

AD5516

PIN FUNCTION DESCRIPTIONS (continued)

Mnemonic Function

SCLK Serial Clock Input. Data is clocked into the shift register on the falling edge of SCLK. This operates at clock

speeds up to 20 MHz.

D

IN

D

OUT

1

DCEN

RESET

PD

2

1

BUSY Active Low Output. This signal tells the user that the analog calibration loop is active. It goes low during conversion.

NOTES

1

Internal pull-down device on this logic input. Therefore it can be left floating and will default to a logic low condition.

2

Internal pull-up device on this logic input. Therefore it can be left floating and will default to a logic high condition.

Serial Data Input. Data must be valid on the falling edge of SCLK.
Serial Data Output. D

data in the shift register for diagnostic purposes. Data is clocked out on D

can be used for daisy-chaining a number of devices together or for reading back the

OUT

on the rising edge of SCLK and is

OUT

valid on the falling edge of SCLK.
Active High Control Input. This pin is tied high to enable Daisy-Chain Mode.

Active Low Control Input. This resets all DAC registers to power-on value.
Active High Control Input. All DACs go into power-down mode when this pin is high. The DAC outputs go into

a high impedance state.

The duration of the pulse on BUSY determines the maximum DAC update rate, f

. Further writes to the

UPDATE

AD5516 are ignored while BUSY is active.

TERMINOLOGY
Integral Nonlinearity (INL)

This is a measure of the maximum deviation from a straight line
passing through the endpoints of the DAC transfer function. It is
expressed in LSBs.

Differential Nonlinearity (DNL)

Differential nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A specified DNL of –1 LSB maximum ensures
monotonicity.

Bipolar Zero Error

Bipolar zero error is the deviation of the DAC output from the ideal
midscale of 0 V. It is measured with 10...00 loaded to the DAC.
It is expressed in LSBs.

Positive Full-Scale Error

This is the error in the DAC output voltage with all 1s loaded to
the DAC. Ideally the DAC output voltage, with all 1s loaded to the
DAC registers, should be 2.5 V – 1 LSB (AD5516-1), 5 V – 1 LSB
(AD5516-2), and 10 V – 1 LSB (AD5516-3). It is expressed in LSBs.

Negative Full-Scale Error

This is the error in the DAC output voltage with all 0s loaded to
the DAC. Ideally the DAC output voltage, with all 0s loaded to the
DAC registers, should be –2.5 V (AD5516-1), –5 V (AD5516-2),
and –10 V (AD5516-3). It is expressed in LSBs.

Output Temperature Coefficient

This is a measure of the change in analog output with changes in
temperature. It is expressed in ppm/∞C of FSR.

DC Power Supply Rejection Ratio

DC power supply rejection ratio (PSRR) is a measure of the change
in analog output for a change in supply voltage (V
It is expressed in dB. V

and VSS are varied ± 5%.

DD

and VSS).

DD

DC Crosstalk

This is the dc change in the output level of one DAC at midscale
in response to a full-scale code change (all 0s to all 1s and vice
versa) and output change of another DAC. It is expressed in LSB.

Output Settling Time

This is the time taken from when the last data bit is clocked into
the DAC until the output has settled to within ±0.5 LSB of its
final value (see TPC 7).

Digital-to-Analog Glitch Impulse

This is the area of the glitch injected into the analog output when
the code in the DAC register changes state. It is specified as the
area of the glitch in nV-s when the digital code is changed by
1 LSB at the major carry transition (011...11 to 100...00 or

100...00 to 011...11).

Digital Crosstalk

This is the glitch impulse transferred to the output of one DAC at
midscale while a full-scale code change (all 1s to all 0s and vice
versa) is being written to another DAC. It is expressed in nV-s.

Analog Crosstalk

This is the area of the glitch transferred to the output (V
one DAC due to a full-scale change in the output (V

OUT

OUT

) of

) of

another DAC. The area of the glitch is expressed in nV-s.

Digital Feedthrough

This is a measure of the impulse injected into the analog outputs
from the digital control inputs when the part is not being written
to, i.e., SYNC is high. It is specified in nV-s and measured with
a worst-case change on the digital input pins, e.g., from all 0s to
all 1s and vice versa.

Output Noise Spectral Density

This is a measure of internally generated random noise. Random
noise is characterized as a spectral density (voltage per root hertz).
It is measured in nV/(Hz)

1/2

.

REV. B

–7–

AD5516–Typical Performance Characteristics

TEMPERATURE (ⴗC)

ERROR (LSB)

2.0

–40

1.0

0

–1.0

–0.5

–1.5

–2.0

–20 0 20 40 80

1.5

0.5

60

INL

+VE
DNL

–VE
DNL

REF_IN = 3V

1.0
REF_IN = 3V
TA = 25ⴗC

0.8

0.6

0.4

0.2

0

–0.2

DNL ERROR (LSB)

–0.4

–0.6

–0.8

–1.0

1000 2000 3000 40000

DAC CODE

TPC 1. Typical DNL Plot

3

REF_IN = 3V

2

1

BIPOLAR ZERO ERROR

0

ERROR (LSB)

–1

–2

–3

–40

NEGATIVE FS ERROR

POSITIVE FS ERROR

–20 0 20 40 80

TEMPERATURE (ⴗC)

1.0
REF_IN = 3V

= 25ⴗC

T

0.8

A

0.6

0.4

0.2

0

–0.2

INL ERROR (LSB)

–0.4

–0.6

–0.8

–1.0

0

1000 2000 3000 4000

DAC CODE

TPC 2. Typical INL Plot

TPC 3. Typical INL Error and DNL
Error vs. Temperature

0.003
AV

= +12V

DD

= –12V

AV

0.002

0.001

(V)

OUT

V

–0.001

–0.002

60

–0.003

SS

= 3V

REF_IN
MIDSCALE LOADED

0

–20 0 20 40 80

–40

TEMPERATURE (ⴗC)

60

0.01

0.008

0.006

0.004

0.002

(V)

OUT

V

–0.002

–0.004

–0.006

–0.008

–0.01

0.0

–8

AVDD = +12V

= –12V

AV

SS

REF_IN = 3V

= 25ⴗC

T

A

–6

–4 –2 0 2 64

CURRENT (mA)

MIDSCALE

8

TPC 4. Bipolar Zero Error and
Full-Scale Error vs. Temperature

3.0
TA = 25ⴗC

REF_IN = 3V

2.0

1.0

( V)

0

OUT

V

–1.0

–2.0

–3.0

TIME BASE = 2.5␮s/DIV

TPC 7. AD5516–1 Full-Scale
Settling Time

TPC 5. V

vs. Temperature

OUT

TPC 6. V

Source and Sink

OUT

Capability

= 25ⴗC

T

A

REF_IN = 3V

PD

V

OUT

5V/DIV

2V/DIV

2␮s/DIV

TPC 8. Exiting Power-Down to
Full Scale

–0.029

TA = 25ⴗC

REF_IN = 3V

–0.030

–0.031

–0.032

–0.033

OLD
VA LU E

CALIBRATION TIME

2.5␮s/DIV

5V

0V

TPC 9. AD5516–1 Major Code
Transition Glitch Impulse

NEW
VA LU E

BUSY

REV. B–8–

AD5516

450

400

350

300

250

200

FREQUENCY

150

100

50

0

V

(V)

OUT

TPC 10. AD5516–1 V

Repeatability;

OUT

Programming the Same Code
Multiple Times

30

REF_IN = 3V
TA = 25ⴗC

20

10

FREQUENCY (%)

40

REF_IN = 3V

= 25ⴗC

T

A

20

FREQUENCY (%)

0

2.48992.48962.4893

–10 0 10

LSBs

TPC 11. Bipolar Error Distribution

40

REF_IN = 3V

= 25ⴗC

T

A

20

FREQUENCY (%)

0
–10 0 10

LSBs

TPC 12. Positive Full-Scale
Error Distribution

2.5

2.0

1.5

1.0

ERROR (LSB)

0.5

REF_IN = 3V

= 25ⴗC

T

A

6

REF_IN = 3V

= 25ⴗC

T

A

5

4

3

ERROR (LSB)

2

1

0
–10 0 10

LSBs

TPC 13. Negative Full-Scale Error
Distribution

0

020406080100 120

STEP SIZE

130

TPC 14. Accuracy vs. Increment Step

0

0 1000 1500500 2000 2500

CODE

3000 3500 4000

TPC 15. Accuracy vs. Increment
Step, Using All 12 Mode 2 Bits

REV. B

–9–

AD5516

FUNCTIONAL DESCRIPTION

The AD5516 consists of sixteen 12-bit DACs in a single pack­age. A single reference input pin (REF_IN) is used to provide a
3V reference for all 16 DACs. To update a DAC’s output
voltage, the required DAC is addressed via the 3-wire serial
interface. Once the serial write is complete, the selected DAC
converts the code into an output voltage. The output amplifiers
translate the DAC output range to give the appropriate voltage
range (±2.5 V, ± 5 V, or ± 10 V) at output pins V

OUT

0 to V

OUT

15.

The AD5516 uses a self-calibrating architecture to achieve 12-bit
performance. The calibration routine servos to select the appro­priate voltage level on an internal 14-bit resolution DAC. BUSY
output goes low for the duration of the calibration and further
writes to the AD5516 are ignored while BUSY is low. BUSY low
time is typically 25 ms. Noise during the calibration (BUSY
low period) can result in the selection of a voltage within a
±0.25 LSB band around the normal selected voltage. See TPC 10.

It is essential to minimize noise on REFIN for optimal perfor­mance. The AD780’s specified decoupling makes it the ideal
reference to drive the AD5516.

Upon power-on, all DACs power up to a reset value (see the
RESET section).

DIGITAL-TO-ANALOG SECTION

The architecture of each DAC channel consists of a resistor
string DAC followed by an output buffer amplifier with offset
and gain. The voltage at the REF_IN pin provides the reference
voltage for all 16 DACs. The input coding to the DACs is offset
binary; this results in ideal output voltages as follows:

VDV

AD5516-1:

AD5516-2:

AD5516-3:

¥¥¥¥¥225

V

OUT

V

OUT

V

OUT

REF IN

=

32

VDV

¥¥¥

REF IN

=

32

VDV

¥¥¥

REF IN

=

32

.

__

N

.

__

N

¥

.

__

N

¥

REF IN

–

225

–

425

–

3

REF IN

REF IN

25

.

¥425

.

3

¥825

.

3

Where:

D = decimal equivalent of the binary code that is loaded to

the DAC register, i.e., 0–4095

N = DAC resolution = 12

Table I illustrates ideal analog output versus DAC code.

Table I. DAC Register Contents AD5516-1

MSB LSB Analog Output, V

1111 1111 1111 V

¥ 2.5/3 – 1 LSB

REF_IN

OUT

1000 0000 0000 0 V
0000 0000 0000 –V

REF_IN

¥ 2.5/3

MODES OF OPERATION

The AD5516 has two modes of operation.

Mode 1 (MODE bits = 00): The user programs a 12-bit data­word to one of 16 channels via the serial interface. This word is
loaded into the addressed DAC register and is then converted
into an analog output voltage. During conversion, the BUSY
output is low and all SCLK pulses are ignored. At the end of a
conversion BUSY goes high, indicating that the update of the
addressed DAC is complete. It is recommended that SCLK is not
pulsed while BUSY is low. Mode 1 conversion takes 25 ms typ.

Mode 2 (MODE bits = 01 or 10): Mode 2 operation allows the
user to increment or decrement the DAC output in 0.25 LSB steps,
resulting in a 14-bit monotonic DAC. The amount by which the
DAC output is incremented or decremented is determined by
Mode 2 bits DB11–DB0, e.g., for a 0.25 LSB increment/decrement
DB11...DB0 = 0000 0000 0001, while for a 2.5 LSB increment/
decrement, DB11...DB0 = 0000 0000 1010. The MODE bits
determine whether the DAC data is incremented (01) or dec­remented (10). The maximum amount that the user is allowed
to increment or decrement the DAC output is 4095 steps of

0.25 LSB, i.e., DB11...DB0 = 1111 1111 1111. Mode 2 update
takes approximately 1 ms. The Mode 2 feature allows increased
resolution, but overall increment/decrement accuracy varies with
increment/decrement step as shown in TPC 14 and TPC 15.

Mode 2 is useful in applications where greater resolution is
required, for example, in servo applications requiring fine-tune
to 14-bit resolution.

MSB LSB

00A3 A2 A1 A0 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

MODE

BITS

ADDRESS

BITS

DATA

BITS

Figure 4. Mode 1 Data Format

MSB LSB

01A3 A2 A1 A0 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

MODE

BITS

MSB LSB

10A3 A2 A1 A0 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

MODE

BITS

ADDRESS

BITS

ADDRESS

BITS

12 INCREMENT

BITS

12 DECREMENT

BITS

Figure 5. Mode 2 Data Format

REV. B–10–

AD5516

The user must allow 200 ns (min) between two consecutive
Mode 2 writes in Standalone Mode and 400 ns (min) between
two consecutive Mode 2 writes in Daisy-Chain Mode. During a
Mode 2 operation the BUSY signal remains high.

See Figures 4 and 5 for Mode 1 and Mode 2 data formats.

When MODE bits = 11, the device is in No Operation mode.
This may be useful in daisy-chain applications where the user
does not wish to change the settings of the DACs. Simply write
11 to the MODE bits and the following address and data bits
will be ignored.

SERIAL INTERFACE

The AD5516 has a 3-wire interface that is compatible with
SPI/QSPI/MICROWIRE, and DSP interface standards. Data is
written to the device in 18-bit words. This 18-bit word consists
of two mode bits, four address bits, and 12 data bits as shown
in Figure 4.

The serial interface works with both a continuous and burst
clock. The first falling edge of SYNC resets a counter that counts
the number of serial clocks to ensure the correct number of bits
is shifted in and out of the serial shift registers. In order for
another serial transfer to take place, the counter must be reset
by the falling edge of SYNC.

A3–A0

Four address bits (A3 = MSB Address, A0 = LSB). These are
used to address one of 16 DACs.

Table II. Selected DAC

A3 A2 A1 A0 Selected DAC

0 000 DAC 0
0 001 DAC 1
: :::
1 111 DAC 15

DB11–DB0

These are used to write a 12-bit word into the addressed DAC
register. Figures 1 and 2 show the timing diagram for a write
cycle to the AD5516.

SYNC FUNCTION

In both Standalone and Daisy-Chain Modes, SYNC is an edge­triggered input that acts as a frame synchronization signal and
chip enable. Data can only be transferred into the device while
SYNC is low. To start the serial data transfer, SYNC should be
taken low observing the minimum SYNC falling to SCLK falling
edge setup time, t

Standalone Mode (DCEN = 0)

.

3

After SYNC goes low, serial data will be shifted into the device’s
input shift register on the falling edges of SCLK for 18 clock
pulses. After the falling edge of the 18th SCLK pulse, data will
automatically be transferred from the input shift register to the
addressed DAC.

SYNC must be taken high and low again for further serial data
transfer. SYNC may be taken high after the falling edge of the
18th SCLK pulse, observing the minimum SCLK falling edge
to SYNC rising edge time, t

. If SYNC is taken high before the

6

18th falling edge of SCLK, the data transfer will be aborted and
the addressed DAC will not be updated. See the timing diagram
in Figure 1.

Daisy-Chain Mode (DCEN = 1)

I

n Daisy-Chain Mode, the internal gating on SCLK is disabled.

The SCLK is continuously applied to the input shift register
when SYNC is low. If more than 18 clock pulses are applied,
the data ripples out of the shift register and appears on the D

OUT

line. This data is clocked out on the rising edge of SCLK and is
valid on the falling edge. By connecting this line to the D

IN

input on the next device in the chain, a multidevice interface is
constructed. Eighteen clock pulses are required for each device
in the system. Therefore, the total number of clock cycles must
equal 18N, where N is the total number of devices in the chain.
See the timing diagram in Figure 2.

When the serial transfer to all devices is complete, SYNC should
be taken high. This prevents any further data being clocked into the
input shift register. A burst clock containing the exact number of
clock cycles may be used and SYNC taken high some time later.
After the rising edge of SYNC, data is automatically transferred
from each device’s input shift register to the addressed DAC.

RESET Function

The RESET function on the AD5516 can be used to reset all
nodes on this device to their power-on reset condition. This is
implemented by applying a low going pulse of 20 ns minimum
to the RESET Pin on the device.

Table III. Typical Power-On Values

Device Output Voltage

AD5516-1 –0.073 V
AD5516-2 –0.183 V
AD5516-3 –0.391 V

BUSY Output

During conversion, the BUSY output is low and all SCLK pulses
are ignored. At the end of a conversion, BUSY goes high indi­cating that the update of the addressed DAC is complete. It is
recommended that SCLK is not pulsed while BUSY is low.

MICROPROCESSOR INTERFACING

The AD5516 is controlled via a versatile 3-wire serial interface
that is compatible with a number of microprocessors and DSPs.

AD5516 to ADSP-2106x SHARC DSP Interface

The ADSP-2106x SHARC DSPs are easily interfaced to the
AD5516 without the need for extra logic.

The AD5516 expects a t

(SYNC falling edge to SCLK falling

3

edge setup time) of 15 ns min. Consult the ADSP-2106x User
Manual for information on clock and frame sync frequencies for
the SPORT Register and contents of the TDIV and RDIV Registers.

REV. B

–11–

AD5516

A data transfer is initiated by writing a word to the TX Register
after the SPORT has been enabled. In write sequences, data is
clocked out on each rising edge of the DSP’s serial clock and
clocked into the AD5516 on the falling edge of its SCLK. The
SPORT transmit control register should be set up as follows:

DTYPE = 00, Right Justify Data
ICLK = 1, Internal Serial Clock
TFSR = 1, Frame Every Word
INTF = 1, Internal Frame Sync
LTFS = 1, Active Low Frame Sync Signal
LAFS = 0, Early Frame Sync
SENDN = 0, Data Transmitted MSB First
SLEN = 10011, 18-Bit Data-Words (SLEN = Serial Word)

Figure 6 shows the connection diagram.

AD5516*

SYNC

D

IN

SCLK

*ADDITIONAL PINS OMITTED FOR CLARITY

ADSP-2106x*

TFS

DT

SCLK

Figure 6. AD5516 to ADSP-2106x Interface

AD5516 to MC68HC11

The serial peripheral interface (SPI) on the MC68HC11 is
configured for Master Mode (MSTR = 1), Clock Polarity Bit
(CPOL) = 0, and the Clock Phase Bit (CPHA) = 1. The SPI is
configured by writing to the SPI Control Register (SPCR)—see
the 68HC11 User Manual. SCK of the 68HC11 drives the SCLK
of the AD5516, the MOSI output drives the serial data line

) of the AD5516. The SYNC signal is derived from a port

(D

IN

line (PC7). When data is being transmitted to the AD5516, the
SYNC line is taken low (PC7). Data appearing on the MOSI
output is valid on the falling edge of SCK. Serial data from the
68HC11 is transmitted in 8-bit bytes with only eight falling
clock edges occurring in the transmit cycle. Data is transmitted
MSB first. In order to transmit 18 data bits, it is important to
left justify the data in the SPDR Register. PC7 must be pulled
low to start a transfer and taken high and low again before any
further read/write cycles can take place. A connection diagram is
shown in Figure 7.

AD5516*

SYNC

SCLK

D

IN

*ADDITIONAL PINS OMITTED FOR CLARITY

MC68HC11*

PC7

SCK

MOSI

Figure 7. AD5516 to MC68HC11 Interface

AD5516 to PIC16C6x/7x

The PIC16C6x/7x synchronous serial port (SSP) is configured
as an SPI master with the Clock Polarity Bit (CKP) = 0. This is
done by writing to the Synchronous Serial Port Control Register
(SSPCON). See the PIC16/17 Microcontroller User Manual. In this
example, I/O port RA1 is being used to provide a SYNC signal
and enable the serial port of the AD5516. This microcontroller
transfers only eight bits of data during each serial transfer opera­tion; therefore, three consecutive write operations are required.
Figure 8 shows the connection diagram.

AD5516*

SCLK

D

IN

SYNC

*ADDITIONAL PINS OMITTED FOR CLARITY

PIC16C6x/7x*

SCK/RC3

SDI/RC4

RA1

Figure 8. AD5516 to PIC16C6x/7x Interface

AD5516 to 8051

A serial interface between the AD5516 and the 80C51/80L51
microcontroller is shown in Figure 9. The AD5516 requires a
clock synchronized to the serial data. The 8051 serial interface
must therefore be operated in Mode 0. TxD of the microcon­troller drives the SCLK of the AD5516, while RxD drives the
serial data line. P1.1 is a bit programmable pin on the serial port
that is used to drive SYNC. The 80C51/80L51 provides the
LSB first, while the AD5516 expects MSB of the 18-bit word
first. Care should be taken to ensure the transmit routine takes
this into account.

AD5516*

SCLK

D

IN

SYNC

*ADDITIONAL PINS OMITTED FOR CLARITY

8051*

TxD

RxD

P1.1

Figure 9. AD5516 to 8051 Interface

When data is to be transmitted to the DAC, P1.1 is taken low.
Data on RxD is valid on the falling edge of TxD, so the clock
must be inverted as the AD5516 clocks data into the input shift
register on the rising edge of the serial clock. The 80C51/80L51
transmits its data in 8-bit bytes with only eight falling clock edges
occurring in the transmit cycle. As the DAC requires an 18-bit
word, P1.1 must be left low after the first eight bits are transferred
and brought high after the complete 18 bits have been transferred.
DOUT may be tied to RxD for data verification purposes when
the device is in Daisy-Chain Mode.

REV. B–12–

AD5516

APPLICATION CIRCUITS

The AD5516 is suited for use in many applications, such as level
setting, optical, industrial systems, and automatic test applications.
In level setting and servo applications where a fine-tune adjust is
required, the Mode 2 function increases resolution. The following
figures show the AD5516 used in some potential applications.

AD5516 in a Typical ATE System

The AD5516 is ideally suited for the level setting function in
automatic test equipment. A number of DACs are required to
control pin drivers, comparators, active loads, parametric mea­surement units, and signal timing. Figure 10 shows the AD5516
in such a system.

STORED

DATA AND

INHIBIT

PATTERN

PERIOD

GENERATION

AND
DELAY
TIMING

DACs

DAC

DAC

DAC

FORMATTER

COMPARE
REGISTER

SYSTEM BUS

ACTIVE

LOAD

DRIVER

PARAMETRIC

MEASUREMENT

UNIT

DAC

DAC

COMPARATOR

SYSTEM BUS

DUT

DAC

DAC

Figure 10. AD5516 in an ATE System

AD5516 in an Optical Network Control Loop

The AD5516 can be used in optical network control applica­tions that require a large number of DACs to perform a control
and measurement function. In the example shown in Figure 11,
the outputs of the AD5516 are fed into amplifiers and used to
control actuators that determine the position of MEMS mirrors
in an optical switch. The exact position of each mirror is measured
and the readings are multiplexed into an 8-channel, 14-bit ADC
(AD7865). The increment and decrement modes of the DACs are
useful in this application as they allow 14-bit resolution.

The control loop is driven by an ADSP-2106x, a 32-bit
SHARC® DSP.

S
E

0

N
S
O

15

R
S

ADSP-2106x

ADG609

ⴛ 2

0

7

AD8644

ⴛ 2

AD7865

AD5516

0

15

MEMS

MIRROR

ARRAY

Figure 11. AD5516 in an Optical Control Loop

AD5516 in a High Current Circuit

Access to the feedback loop of the AD5516 amplifier provides
greater flexibility, e.g., it enables the user to configure the device
as a digitally programmable current source or increase the out­put drive current. See Figure 12. Note that V

must be chosen

DD

so that the DAC output has enough headroom to drive the
BJT ~ 0.7 V above the maximum output voltage.

V

DD

V

AD5516-1

V

DAC

DD

0

V

OUT

R

0

FB

R

V

SS

X

= – 2.5V TO +2.5V

V

x

Figure 12. AD5516 in a High Current Circuit

Note it is not intended that the RFB nodes be used to alter
amplifier gain or for force/sense in remote sense applications.

POWER SUPPLY DECOUPLING

In any circuit where accuracy is important, careful consideration
of the power supply and ground return layout helps to ensure the
rated performance. The printed circuit board on which the AD5516
is mounted should be designed so that the analog and digital
sections are separated and confined to certain areas of the board. If
the AD5516 is in a system where multiple devices require an
AGND-to-DGND connection, the connection should be made at
one point only. The star ground point should be established as
close as possible to the device. For supplies with multiple pins

1, AVCC2), it is recommended to tie those pins together. The

(AV

CC

AD5516 should have ample supply bypassing of 10 mF in parallel
with 0.1 mF on each supply located as closely to the package as
possible, ideally right up against the device. The 10 mF capacitors
are the tantalum bead type. The 0.1 mF capacitor should have low
effective series resistance (ESR) and effective series inductance
(ESI), like the common ceramic types that provide a low impedance
path to ground at high frequencies, to handle transient currents
due to internal logic switching.

The power supply lines of the AD5516 should use as large a trace
as possible to provide low impedance paths and reduce the effects
of glitches on the power supply line. Fast switching signals such
as clocks should be shielded with digital ground to avoid radiating
noise to other parts of the board, and should never be run near
the reference inputs. A ground line routed between the D

IN

and
SCLK lines will help reduce crosstalk between them (not required
on a multilayer board as there will be a separate ground plane, but
separating the lines will help). It is essential to minimize noise
on REFIN.

Avoid crossover of digital and analog signals. Traces on opposite
sides of the board should run at right angles to each other. This
reduces the effects of feedthrough through the board. A micro­strip technique is by far the best, but not always possible with a
double-sided board. In this technique, the component side of
the board is dedicated to ground plane while signal traces are
placed on the solder side.

As is the case for all thin packages, care must be taken to avoid
flexing the package and to avoid a point load on the surface of
the package during the assembly process.

REV. B

–13–

AD5516

1.70

MAX

OUTLINE DIMENSIONS

74-Lead Chip Scale Ball Grid Array [CSPBGA]

(BC-74)

Dimensions shown in millimeters

12.00 BSC
SQ

A1

TOP VIEW

DETAIL A

COMPLIANT TO JEDEC STANDARDS MO-192ABD-1

11 10 9 8 7 6 5 4 3 2 1

1.00

BSC

0.30 MIN

BOTTOM

VIEW

1.00 BSC

DETAIL A

0.70

0.60

0.50

BALL DIAMETER

SEATING
PLANE

A1 CORNER

INDEX AREA

A
B
C
D
E

10.00 BSC

F

SQ

G
H
J
K
L

0.20 MAX
COPLANARITY

REV. B–14–

AD5516

Revision History

Location Page

8/03—Data Sheet changed from REV. A to REV. B.

Updated ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Changes to TPC 14 caption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Addition of TPC 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Changes to Mode 2 section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Changes to Figure 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Changes to Figure 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

8/02—Data Sheet changed from REV. 0 to REV. A.

Term LFBGA updated to CSPBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Global

Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Addition to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Changes to FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Changes to DIGITAL-TO-ANALOG section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Added AD5516 in a High Current Circuit section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Added Figure 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Updated BC-74 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

REV. B

–15–

C02792–0–8/03(B)

–16–