Datasheet AD549 Datasheet (Analog Devices)

Ultralow Input Bias Current

FEATURES

Ultralow bias current

60 fA max (AD549L)
250 fA max (AD549J)

Input bias current guaranteed over common mode

voltage range

Low offset voltage

0.25 mV max (AD549K)

1.00 mV max (AD549J)

Low offset drift

5 µV/°C max (AD549K)
20 µV/°C max (AD549J)

Low power

700 µA max supply current

Low input voltage noise

4 µV p-p 0.1 Hz to 10 Hz

MIL-STD-883B parts available

APPLICATIONS

Electrometer amplifiers
Photodiode preamp
pH electrode buffer
Vacuum ion gauge measurement

PRODUCT DESCRIPTION

The AD5491 is a monolithic electrometer operational amplifier
with very low input bias current. Input offset voltage and input
offset voltage drift are laser trimmed for precision performance.
The part’s ultralow input current is achieved with Topgate JFET
technology, a process development exclusive to Analog Devices,
Inc. This technology allows fabrication of extremely low input
current JFETs compatible with a standard junction isolated
bipolar process. The 10
results from the bootstrapped input stage, ensures that the input
current is essentially independent of common-mode voltage.

The AD549 is suited for applications that require very low input
current and low input offset voltage. It excels as a preamp for a
wide variety of current output transducers, such as photodiodes,
photomultiplier tubes, or oxygen sensors. The AD549 can also
be used as a precision integrator or low droop sample and hold.
The AD549 is pin compatible with standard FET and
electrometer op amps, allowing designers to upgrade the
performance of present systems at little additional cost.

15

Ω common-mode impedance, which

Operational Amplifier

AD549

CONNECTION DIAGRAM

GUARD PIN, CONNECTED TO CASE

NC

OFFSET NULL

INVERTING

INPUT

NONINVERTING

INPUT

NC = NO CONNECTION

The AD549 is available in a TO-99 hermetic package. The case
is connected to Pin 8 so that the metal case can be indepen­dently connected to a point at the same potential as the input
terminals, minimizing stray leakage to the case.

The AD549 is available in four performance grades. The J, K,
and L versions are rated over the commercial temperature range
of 0°C to +70°C. The S grade is specified over the military
temperature range of −55°C to +125°C, and is available
processed to MIL-STD-883B, Rev C. Extended reliability plus
screening is also available. Plus screening includes 168-hour
burn-in, as well as other environmental and physical tests
derived from MIL-STD-883B, Rev C.

PRODUCT HIGHLIGHTS

1. The AD549’s input currents are specified, 100% tested, and

guaranteed after the device is warmed up. Input current is
guaranteed over the entire common-mode input voltage
range.

2. The AD549’s input offset voltage and drift are laser

trimmed to 0.25 mV and 5 µV/°C (AD549K), and 1 mV
and 20 µV/°C (AD549J).

3. A maximum quiescent supply current of 700 µA minimizes

heating effects on input current and offset voltage.

4. AC specifications include 1 MHz unity gain bandwidth

and 3 V/µs slew rate. Settling time for a 10 V input step is
5 µs to 0.01%.

1

2

3

1

8

AD549

4

V–

10kΩ

VOS TRIM

Figure 1.

V+

7

5

OFFSET
NULL

5

4

6

OUTPUT

–15V

00511-001

Rev. D

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

1

Protected by Patent No. 4,639,683.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

www.analog.com

AD549

TABLE OF CONTENTS

Specifications..................................................................................... 3

Common-Mode Input Voltage Overload................................ 12

Absolute Maximum Ratings............................................................ 5

ESD Caution.................................................................................. 5

Typical Performance Characteristics ............................................. 6

Functional Description ..................................................................10

Minimizing Input Current ........................................................ 10

Circuit Board Notes ................................................................... 10

Offset Nulling.............................................................................. 11

AC Response with High Value Source and Feedback
Resistance

.................................................................................... 12

REVISION HISTORY

5/04—Data Sheet Changed from Rev. C to Rev. D

Updated Format..............................................................Universal

Changes to Features...................................................................... 1

Updated Outline Dimensions................................................... 18

Added Ordering Guide.............................................................. 18

Differential Input Voltage Overload ........................................ 13

Input Protection ......................................................................... 13

Sample and Difference Circuit to Measure Electrometer
Leakage Currents

Photodiode Interface ................................................................. 14

Temperature Compensated pH Probe Amplifier................... 17

Outline Dimensions....................................................................... 18

Ordering Guide .......................................................................... 18

........................................................................ 13

10/02—Data Sheet Changed from Rev. B to Rev. C.

Deleted PRODUCT HIGHLIGHTS #5..........................................1

Edits to SPECIFICATIONS..............................................................3

Deleted METALLIZATION PHOTOGRAPH ..............................3

Updated OUTLINE DIMENSIONS .............................................13

7/02—Data Sheet Changed from Rev. A to Rev. B.

Edits to SPECIFICATIONS..............................................................2

Rev. D | Page 2 of 20

AD549

SPECIFICATIONS

@ 25°C and VS = ±15 V dc, unless otherwise noted. All min and max specifications are guaranteed. Specifications in boldface are tested on
all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels.

Table 1.

AD549J AD549K AD549L AD549S
Parameter Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit

INPUT BIAS CURRENT1

Either Input, VCM = 0 V 150
Either Input, VCM = ±10 V 150 250 75 100 40 60 75 100 fA
Either Input at T

, VCM = 0 V 11 4.2 2.8 420 pA

MAX

Offset Current 50 30 20 30 fA
Offset Current at T

2.2 1.3 0.85 125 pA

MAX

INPUT OFFSET VOLTAGE2

Initial Offset 0.5
Offset at T

MAX

vs. Temperature 10
vs. Supply 32
vs. Supply, T

MIN

to T

32

MAX

Long-Term Offset Stability 15 15 15 15 µV/month

INPUT VOLTAGE NOISE

f = 0.1 Hz to 10 Hz 4 4
f = 10 Hz 90 90 90 90

f = 100 Hz 60 60 60 60
f = 1 kHz 35 35 35 35
f = 10 kHz 35 35 35 35

INPUT CURRENT NOISE

f = 0.1 Hz to 10 Hz 0.7 0.5 0.36 0.5 fA rms
f = 1 kHz 0.22 0.16 0.11 0.16

INPUT IMPEDANCE

Differential

V

= ±1 1013||1 1013||1 1013||1 1013||1 Ω||pF

DIFF

Common Mode

VCM = ±10 1015||0.8 1015||0.8 1015||0.8 1015||0.8 Ω||pF

OPEN-LOOP GAIN

VO @ ±10 V, RL = 10 kΩ

1000

300

VO @ ±10 V, RL = 10 kΩ,

T

to T

MAX

MIN

VO = ±10 V, RL = 2 kΩ

300 800 300 800 300 800 300 800 V/mV

250

100

VO = ±10 V, RL = 2 kΩ,

T

to T

MIN

MAX

80 200 80 200 80 200 25 150 V/mV

INPUT VOLTAGE RANGE

Differential3 ±20 ±20 ±20 ±20 V
Common-Mode Voltage

−10

Common-Mode Rejection Ratio

V = +10 V, −10 V
T

to T

MAX

MIN

90

80

80

76

OUTPUT CHARACTERISTICS

Voltage @ RL = 10 kΩ,

T

to T

MAX

MIN

Voltage @ RL = 2 kΩ, T
Short-Circuit Current
T

to T

MIN

9 9 9 6 mA

MAX

MIN

to T

−12 +12 −12 +12 −12 +12 −12 +12 V

MAX

−10
15

20

Load Capacitance Stability

G = +1 4000 4000 4000 4000 pF

75

250

0.15

1.0

1.9

2

20

10

100

10

100

300

100

+10 −10

90
80

+10 −10
35 15

100

0.25

0.4
5
32
32

6

1000

250

+10 −10

100
90

20

+10 −10
35 15

40

0.3

5
10
10

60

0.5

0.9
10
32
32

75

0.3

10
10
32

100

0.5

2.0
15
32
50

fA

mV
mV
µV/°C
µV/V
µV/V

4 4 µV p-p

nV/√

Hz

nV/√

Hz

nV/√

Hz

nV/√

Hz

fA/√

Hz

1000

300

250

100

100

90

90

80

20

+10 −10

+10 −10
35 15

1000 V/mV

300

250 V/mV

100

100 dB

90

90 dB

80

20

+10

+10
35

V

V
mA

Rev. D | Page 3 of 20

AD549

AD549J AD549K AD549L AD549S
Parameter Min Typ Max Min Typ Max Min Typ Max Min Typ Max Unit

FREQUENCY RESPONSE

Unity Gain, Small Signal 0.7 1.0 0.7 1.0 0.7 1.0 0.7 1.0 MHz
Full Power Response 50 50 50 50 kHz
Slew Rate 2 3 2 3 2 3 2 3 V/µs
Settling Time, 0.1% 4.5 4.5 4.5 4.5 µs
Settling Time, 0.01% 5 5 5 5 µs
Overload Recovery, 50%

Overdrive, G = −1

POWER SUPPLY

Rated Performance ±15 ±15 ±15 ±15 V
Operating
Quiescent Current 0.60

TEMPERATURE RANGE

Operating, Rated Performance 0 +70 0 +70 0 +70 −55 +125 °C
Storage −65 +150 −65 +150 −65 +150 −65 +150 °C

PACKAGE OPTION

TO-99 (H-08A) Chips AD549JH AD549KH AD549LH AD549SH/883B

1

Bias current specifications are guaranteed after five minutes of operation at TA = 25°C. Bias current increases by a factor of 2.3 for every 10°C rise in temperature.

2

Input offset voltage specifications are guaranteed after five minutes of operation at TA = 25°C.

3

Defined as max continuous voltage between the inputs, such that neither input exceeds ±10 V from ground.

2 2 2 2 µs

±5

±18 ±5

0.70

0.60

±18 ±5

0.60

0.70

±18 ±5

0.70

0.60

±18

0.70

V
mA

Rev. D | Page 4 of 20

AD549

ABSOLUTE MAXIMUM RATINGS

Table 2.

Parameter Rating

Supply Voltage ±18 V
Internal Power Dissipation 500 mW
Input Voltage
Output Short Circuit Duration Indefinite
Differential Input Voltage +VS and −VS
Storage Temperature Range (H) −65°C to +125°C
Operating Temperature Range
AD549J (K, L) 0°C to +70°C
AD549S −55°C to +125°C
Lead Temperature Range (Soldering, 60 sec) +300°C

1

±18 V

1

For supply voltages less than ±18 V, the absolute maximum input voltage is

equal to the supply voltage

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

Rev. D | Page 5 of 20

AD549

TYPICAL PERFORMANCE CHARACTERISTICS

20

800

15

+V

IN

10

–V

INPUT VOLTAGE (V)

5

0

0 5 10 15 20

SUPPLY VOLTAGE (V)

IN

Figure 2. Input Voltage Range vs. Supply Voltage

20

25°C

= 10kΩ

R

L

15

10

5

OTUPUT VOLTAGE SWING (V)

0

0 5 10 15 20

SUPPLY VOLTAGE (V)

Figure 3. Output Voltage Swing vs. Supply Voltage

30

700

600

500

AMPLIFIER QUIESCENT CURRENT (µA)

00511-002

400

0 5 10 15 20

SUPPLY VOLTAGE (±V)

00511-005

Figure 5. Quiescent Current vs. Supply Voltage

120

+V

OUT

–V

OUT

00511-003

110

100

90

80

COMMON-MODE REJECTION RATIO (dB)

70

–20 –10 0 10 20

INPUT COMMON-MODE VOLTAGE (V)

00511-006

Figure 6. CMRR vs. Input Common-Mode Voltage

3000

25

20

15

10

5

OTUPUT VOLTAGE SWING (V p-p)

0

10 100 1k 10k 100k

LOAD RESISTANCE (Ω)

VS =±15V

Figure 4. Output Voltage Swing vs. Load Resistance

00511-004

Rev. D | Page 6 of 20

1000

300

OPEN-LOOP GAIN (V/mV)

100

0 5 10 15 20

SUPPLY VOLTAGE (V)

Figure 7. Open-Loop Gain vs. Supply Voltage

00511-007

AD549

3000

50

45

1000

300

OPEN-LOOP GAIN (V/mV)

100

–55 –25 5 35 65 95 125

TEMPERATURE (°C)

Figure 8. Open-Loop Gain vs. Temperature

30

25

20

I (µV)

15

OS

IV

∆

10

5

00511-008

40

35

30

INPUT CURRENT (fA)

25

20

0 5 10 15 20

POWER SUPPLY VOLTAGE (V)

Figure 11. Input Bias Current vs. Supply Voltage

160

140

120

100

80

60

40

NOISE SPECTRAL DENSITY (nV/ Hz)

00511-011

0

01234567

WARMUP TIME (Minutes)

Figure 9. Change in Offset Voltage vs. Warm-Up Time

50

45

40

35

30

INPUT CURRENT (fA)

25

20

–10 –5 0 5 10

COMMON-MODE VOLTAGE (V)

Figure 10. Input Bias Current vs. Common-Mode Voltage

00511-009

00511-010

20

10 100 1k 10k

FREQUENCY (Hz)

Figure 12. Input Voltage Noise Spectral Density

100k

WHENEVER JOHNSON NOISE IS GREATER THAN
AMPLIFIER NOISE, AMPLIFIER NOISE CAN BE
CONSIDERED NEGLIGIBLE FOR THE APPLICATION

10k

1k

100

10

INPUT NOISE VOLTAGE (µV p-p)

1

0.1
100k 1M 10M 100M 1G 10G 100G

RESISTOR

JOHNSON NOISE

AMPLIFIER GENERATED NOISE

SOURCE RESISTANCE (Ω)

1kHz BANDWIDTH

10Hz BANDWIDTH

Figure 13. Noise vs. Source Resistance

00511-012

00511-013

Rev. D | Page 7 of 20

AD549

100

100

120

80

60

40

20

0

OEPN-LOOP GAIN (dB)

–20

–40

10 100 1k 10k 100k 1M 10M

FREQUENCY (Hz)

Figure 14. Open-Loop Frequency Response

40

35

30

25

20

15

10

OUTPUT VOLTAGE SWING (V)

5

0

10 100 1k 10k 100k 1M

FREQUENCY (Hz)

Figure 15. Large Signal Frequency Response

100

80

60

40

CMRR (dB)

20

0

–20

10 100 1k 10k 100k 10M1M

FREQUENCY (Hz)

Figure 16. CMRR vs. Fre quency

80

60

40

20

0

–20

–40

PHASE MARGIN (Degrees)

00511-014

00511-015

00511-016

100

80

+SUPPLY

60

40

PSRR (dB)

20

0

–20

10 100 1k 10k 100k 10M1M

–SUPPLY

FREQUENCY (Hz)

Figure 17. PSRR vs. Frequency Response

10

5

0

–5

OUTPUT VOLTAGE SWING (V)

–10

01 324

SETTLING TIME (µs)

10mV

5mV

1mV

10mV

5mV

1mV

Figure 18. Output Voltage Swing and Error vs. Settling Time

00511-017

00511-018

5

Rev. D | Page 8 of 20

AD549

10kΩ

+V

S

10kΩ

2

3

7

AD549

4

–V

0.1µF

5

0.1µF

S

Figure 22. Unity Gain Inverter

R

L

10kΩ

C

L

100pF

V

OUT

00511-022

V

IN

SQUARE
WAVE
INPUT

+V

S

0.1µF

2

7

AD549

3

5

R

4

0.1µF

–V

S

L

10kΩ

Figure 19. Unity Gain Follower

C

L

100pF

V

V

OUT

00511-019

IN

SQUARE
WAVE
INPUT

Figure 20. Unity Gain Follower Large Signal Pulse Response

Figure 21. Unity Gain Follower Small Signal Pulse Response

00511-020

00511-021

Figure 23. Unity Gain Inverter Large Signal Pulse Response

Figure 24. Unity Gain Inverter Small Signal Pulse Response

00511-023

00511-024

Rev. D | Page 9 of 20

AD549

FUNCTIONAL DESCRIPTION

MINIMIZING INPUT CURRENT

The AD549 has been optimized for low input current and offset
voltage. Careful attention to how the amplifier is used will
reduce input currents in actual applications.

The amplifier operating temperature should be kept as low as
possible to minimize input current. Like other JFET input
amplifiers, the AD549’s input current is sensitive to chip
temperature, rising by a factor of 2.3 for every 10°C. Figure 25 is
a plot of AD549’s input current versus its ambient temperature.

1nA

100pA

10pA

1pA

100fA

10fA

1fA

–55 –25 5 35 65 12595

TEMPERATURE (°C)

Figure 25. Input Bias Current vs. Ambient Temperature

On-chip power dissipation raises the chip operating tempera­ture, causing an increase in input bias current. Due to the
AD549’s low quiescent supply current, the chip temperature is
less than 3°C higher than its ambient temperature when the
(unloaded) amplifier is operating with 15 V supplies. The
difference in the input current is negligible.

However, heavy output loads can cause a significant increase in
chip temperature and a corresponding increase in the input
current. Maintaining a minimum load resistance of 10 Ω is
recommended. Input current versus additional power
dissipation due to output drive current is plotted in Figure 26.

6

5

4

BASED ON
TYPICAL I

3

2

NORMALIZED INPUT BIAS CURRENT

1

0 25 50 75 100 125 150 175 200

ADDITIONAL INTERNAL POWER DISSIPATION (mW)

Figure 26. Input Bias Current vs. Additional Power Dissipation

= 40fA

B

00511-025

00511-026

CIRCUIT BOARD NOTES

There are a number of physical phenomena that generate
spurious currents, which degrade the accuracy of low current
measurements. Figure 27 is a schematic of an I-to-V converter
with these parasitic currents modeled.

C

F

R

AD549

8

V

+V +

R

P

dC

F

6

p

dT

V

OUT

dV

C

p

dT

P

+

–

00511-027

in Figure 27.

2

.

2

f

S

R

P

V

S

3

II' =

C

p

Figure 27. Sources of Parasitic Leakage Currents

Finite resistance from input lines to voltages on the board,
modeled by resistor R
resistance of more than 10

, results in parasitic leakage. Insulation

P

15

Ω must be maintained between the
amplifier’s signal and supply lines in order to capitalize on the
AD549’s low input currents. Standard PC board material does
not have high enough insulation resistance. Therefore, the
AD549’s input leads should be connected to standoffs made of
insulating material with adequate volume resistivity (e.g.,
Teflon). The insulator’s surface must be kept clean in order to
preserve surface resistivity. For Teflon, an effective cleaning
procedure consists of swabbing the surface with high grade
isopropyl alcohol, rinsing with deionized water, and baking the
board at 80°C for 10 minutes.

In addition to high volume and surface resistivity, other
properties are desirable in the insulating material chosen.
Resistance to water absorption is important since surface water
films drastically reduce surface resistivity. The insulator chosen
should also exhibit minimal piezoelectric effects (charge
emission due to mechanical stress) and triboelectric effects
(charge generated by friction). Charge imbalances generated by
these mechanisms can appear as parasitic leakage currents.
These effects are modeled by variable capacitor C
Table 3 lists various insulators and their properties

Guarding the input lines by completely surrounding them with
a metal conductor biased near the input lines’ potential has two
major benefits. First, parasitic leakage from the signal line is
reduced since the voltage between the input line and the guard
is very low. Second, stray capacitance at the input node is

2

Electronic Measurements, pp. 15–17, Keithley Instruments, Inc., Cleveland,

Ohio, 1977.

Rev. D | Page 10 of 20

AD549

minimized. Input capacitance can substantially degrade signal
band width and the stability of the I-to-V converter. The case of
the AD549 is connected to Pin 8 so that it can be bootstrapped
near the input potential. This minimizes pin leakage and input
common-mode capacitance due to the case. Guard schemes for
inverting and noninverting amplifier topologies are illustrated
in Figure 28 and Figure 29.

C

F

GUARD

R

AD549

8

AD549

F

6

+

V

OUT

–

00511-028

V

OUT

6

+

R

8

F

2

I

N

3

Figure 28. Inverting Amplifier with Guard

GUARD

3

+

V

S

–

2

OFFSET NULLING

The AD549’s input offset voltage can be nulled by using balance
Pins 1 and 5, as shown in Figure 30. Nulling the input offset
voltage in this fashion introduces an added input offset voltage
drift component of 2.4 µV/°C per millivolt of nulled offset
(a maximum additional drift of 0.6 µV/°C for the AD549K,

1.2 µV/°C for the AD549L, and 2.4 µV/°C for the AD549J).

+V

S

7

2

6

AD549

5

1

3

4

10kΩ

–V

S

Figure 30. Standard Offset Null Circuit

The approach in Figure 31 can be used when the amplifier is
used as an inverter. This method introduces a small voltage
referenced to the power supplies in series with the amplifier’s
positive input terminal. The amplifier’s input offset voltage drift
with temperature is not affected. However, variation of the
power supply voltages causes offset shifts.

+

V

OUT

–

00511-030

R

I

–

00511-029

Figure 29. Noninverting Amplifier with Guard

Other guidelines include keeping the circuit layout as compact
as possible and keeping the input lines short. Keeping the
assembly rigid and minimizing sources of vibration will reduce
triboelectric and piezoelectric effects. All precision, high
impedance circuitry requires shielding against interference
noise. Low noise coaxial or triaxial cables should be used for
remote connections to the input signal lines.

Table 3. Insulating Materials and Characteristics

Volume Resistivity

Material

(V–CM)

Teflon® 1017 − 10
Kel-F® 1017 − 10
Sapphire 1016 − 10
Polyethylene 1014 − 10
Polystyrene 1012 − 10
Ceramic 1012 − 10
Glass Epoxy 1010 − 10
PVC 1010 − 10
Phenolic 105 − 10

G–Good with Regard to Property
M–Moderate with Regard to Property
W–Weak with Regard to Property

12

18

18

18

18

18

14

17

15

Minimal
Triboelectric Effects

W W G
W M G
M G G
M G M
W M M
W M W
W M W
G M G
W G W

R

AD549

0.1µF

F

6

+

V

OUT

100kΩ

–

00511-031

+V

S

–V

S

R

I

2

+

V

I

–

3

499kΩ 499kΩ

200Ω

Figure 31. Alternate Offset Null Circuit for Inverter

Minimal
Piezoelectric Effect

Resistance to
Water Absorption

Rev. D | Page 11 of 20

AD549

AC RESPONSE WITH HIGH VALUE SOURCE AND FEEDBACK RESISTANCE

Source and feedback resistances greater than 100 kΩ magnify
the effect of the input capacitances (stray and inherent to the
AD549) on the ac behavior of the circuit. The effects of
common-mode and differential input capacitances should be
taken into account since the circuit’s bandwidth and stability
can be adversely affected.

00511-032

Figure 32 Follower Pulse Response from 1 MΩ Source Resistance,

Case Not Bootstrapped

In an inverting configuration, the differential input capacitance
forms a pole in the circuit’s loop transmission. This can create
peaking in the ac response and possible instability. A feedback
capacitance can be used to stabilize the circuit. The inverter
pulse response with R

and RS equal to 1 MΩ appears in

F

Figure 34. Figure 35 shows the response of the same circuit with
a 1 pF feedback capacitance. Typical differential input
capacitance for the AD549 is 1 pF.

00511-034

Figure 34. Inverter Pulse Response with 1 MΩ Source and

Feedback Resistance

00511-033

Figure 33. Follower Pulse Response from 1 MΩ Source Resistance,

Case Bootstrapped

In a follower, the source resistance and input common-mode
capacitance form a pole that limits the bandwidth to ½πR

SCS

.
Bootstrapping the metal case by connecting Pin 8 to the output
minimizes capacitance due to the package. Figure

32 and

Figure 33 show the follower pulse response from a 1 MΩ source
resistance with and without the package connected to the
output. Typical common-mode input capacitance for the AD549
is 0.8 pF.

Rev. D | Page 12 of 20

00511-035

Figure 35. Inverter Pulse Response with 1 MΩ Source and Feedback

Resistance, 1pF Feedback Capacitance

COMMON-MODE INPUT VOLTAGE OVERLOAD

The rated common-mode input voltage range of the AD549 is
from 3 V less than the positive supply voltage to 5 V greater
than the negative supply voltage. Exceeding this range degrades
the amplifier’s CMRR. Driving the common-mode voltage
above the positive supply causes the amplifier’s output to
saturate at the upper limit of the output voltage. Recovery time
is typically 2 µs after the input has been returned to within the
normal operating range. Driving the input common-mode
voltage within 1 V of the negative supply causes phase reversal
of the output signal. In this case, normal operation is typically
resumed within 0.5 µs of the input voltage returning within
range.

AD549

DIFFERENTIAL INPUT VOLTAGE OVERLOAD

A plot of the AD549’s input currents versus differential input
voltage (defined as V

+ − VIN−) appears in Figure 36. The input

IN

current at either terminal stays below a few hundred femtoamps
until one input terminal is forced higher than 1 V to 1.5 V above
the other terminal. Under these conditions, the input current
limits at 30 µA.

100µ

10µ

1µ

100n

10n

1n

100p

10p

INPUT CURRENT (A)

1p

100f

10f

–5 –4 –3 –2 –1 0 1 2 3 4 5

Figure 36. Input Current vs. Differential Input Voltage

IIN–I

DIFFERENTIAL INPUT VOLTAGE (V) (VIN+– VIN–)

+

IN

00511-036

INPUT PROTECTION

The AD549 safely handles any input voltage within the supply
voltage range. Subjecting the input terminals to voltages beyond
the power supply can destroy the device or cause shifts in input
current or offset voltage if the amplifier is not protected.

A protection scheme for the amplifier as an inverter is shown in
Figure 37. R
inverting input to 1 mA for expected transient (less than 1 s)
overvoltage conditions, or to 100 µA for a continuous overload.
Since R
than the amplifier’s input resistance, it does not affect the
inverter’s dc gain. However, the Johnson noise of the resistor
adds root sum of squares to the amplifier’s input noise.

is chosen to limit the current through the

P

is inside the feedback loop, and is much lower in value

P

R

F

R

PROTECT

SOURCE

2

3

AD549

C

F

6

00511-037

Figure 37. Inverter with Input Current Limit

In the corresponding version of this scheme for a follower,
shown in Figure 38, R

and the capacitance at the positive input

P

terminal produce a pole in the signal frequency response at a
f = ½πRC. Again, the Johnson noise, R

, adds to the amplifier’s

P

input voltage noise.

R

PROTECT

SOURCE

3

2

AD549

6

00511-038

Figure 38. Follower with Input Current Limit

Figure 39 is a schematic of the AD549 as an inverter with an
input voltage clamp. Bootstrapping the clamp diodes at the
inverting input minimizes the voltage across the clamps and
keeps the leakage due to the diodes low. Low leakage diodes,
such as the FD333s, should be used and should be shielded
from light to keep photocurrents from being generated. Even
with these precautions, the diodes measurably increase input
current and capacitance.

R

AD549

F

6

00511-039

SOURCE

PROTECT

DIODES

2

3

Figure 39. Input Voltage Clamp with Diodes

SAMPLE AND DIFFERENCE CIRCUIT TO MEASURE ELECTROMETER LEAKAGE CURRENTS

There are a number of methods used to test electrometer
leakage currents, including current integration and direct
current-to-voltage conversion. Regardless of the method used,
board and interconnect cleanliness, proper choice of insulating
materials (such as Teflon or Kel-F), correct guarding and
shielding techniques, and care in physical layout are essential to
making accurate leakage measurements.

Figure 40 is a schematic of the sample and difference circuit. It
uses two AD549 electrometer amplifiers (A and B) as current­to-voltage converters with high value (10
(RSa and RSb). R1 and R2 provide for an overall circuit
sensitivity of 10 fA/mV (10 pA full scale). C
noise suppression and loop compensation. C
leakage polystyrene capacitor. An ultralow leakage Kel-F test
socket is used for contacting the device under test. Rigid Teflon
coaxial cable is used to make connections to all high impedance
nodes. The use of rigid coaxial cable affords immunity to error
induced by mechanical vibration and provides an outer
conductor for shielding. The entire circuit is enclosed in a
grounded metal box.

10

Ω) sense resistors

and CF provide

C

should be a low

C

Rev. D | Page 13 of 20

AD549

The test apparatus is calibrated without a device under test
present. After power is turned on, a five-minute stabilization
period is required. First, V

ERR1

and V
voltages are the errors caused by the offset voltages and leakage
currents of the current-to-voltage converters.

= 10 (VOSA –IBA × RSa)

V

ERR1

= 10 (VOSB –IBB × RSb)

V

ERR2

I (+)

–

V

OS

DEVICE
UNDER

+

TEST

I (–)

9.01kΩ

1kΩ

R2

R1

Figure 40. Sample and Difference Circuit for Measuring

Electrometer Leakage Currents

Once measured, these errors are subtracted from the readings
taken with a device under test present. Amplifier B closes the
feedback loop to the device under testing, in addition to pro­viding the current-to-voltage conversion. The offset error of the
device under testing appears as a common-mode signal and
does not affect the test measurement. As a result, only the
leakage current of the device under testing is measured.

– V

V

A

V

X

= 10[RSa × IB(+)]

ERR1

– V

= 10[RSb × IB(–)]

ERR2

are measured. These

ERR2

C

C

20pF

RSa

10

10

2

AD549L

3

3

AD549L

2

C

C

20pF

RSb

10

10

0.1µF

Ω

9.01kΩ

R1
1kΩ

A

8

GUARD

C

F

0.1µF

8

B

0.1µF

Ω

9.01kΩ

R1
1kΩ

C

F

R2

6

6

C

F

R2

CAL/TEST

VERR1/V

V

OUT

VERR2/V

+

A

–

–

B

+

00511-040

Although a series of devices can be tested after only one
calibration measurement, calibration should be updated
periodically to compensate for any thermal drift of the current­to-voltage converters or changes in the ambient environment.
Laboratory results have shown that repeatable measurements
within 10 fA can be realized when this apparatus is properly
implemented. These results are achieved in part by the design of
the circuit, which eliminates relays and other parasitic leakage
paths in the high impedance signal lines, and in part by the
inherent cancellation of errors through the calibration and
measurement procedure.

PHOTODIODE INTERFACE

The AD549’s low input current and low input offset voltage
make it an excellent choice for very sensitive photodiode
preamps (Figure 41). The photodiode develops a signal current,

, equal to

I

S

= R × P

I

S

where P is light power incident on the diode’s surface ,in Watts,

F

+

V

OUT

–

converts

F

00511-041

+

V

OUT

–

00511-042

and R is the photodiode responsivity in Amps/Watt. R
the signal current to an output voltage

= RF × I

V

OUT

S

R

F

109Ω

C

F

10pF

2

AD549

3

6

5

1

4

–V

S

10kΩ

1µF

Figure 41. Photodiode Preamp

DC error sources and an equivalent circuit for a small area
(0.2 mm square) photodiode are indicated in Figure 42.

R

F

109Ω

C

10pF

C

R

S

S

S

109Ω

20pF

IS–I

V

OS

A

+–

Figure 42. Photodiode Preamp DC Error Sources

Input current, IB, contributes an output voltage error, VE1,
proportional to the feedback resistance

= IB × R

V

E1

F

Rev. D | Page 14 of 20

AD549

µ

The op amp’s input voltage offset causes an error current
through the photodiode’s shunt resistance, R

I = VOS/R

S

S

The error current results in an error voltage (VE2) at the
amplifier’s output equal to

= (1 + RF/RS)V

V

E2

OS

Given typical values of photodiode shunt resistance (on the
order of 10
a large feedback resistance is used. Also, R

9

Ω), RF/RS can easily be greater than one, especially if

increases with

F/RS

temperature, since photodiode shunt resistance typically drops
by a factor of 2 for every 10°C rise in temperature. An op amp
with low offset voltage and low drift must be used in order to
maintain accuracy. The AD549K offers guaranteed maximum

0.25 mV offset voltage and 5 mV/°C drift for very sensitive
applications.

Photodiode Preamp Noise

Noise limits the signal resolution obtainable with the preamp.
The output voltage noise divided by the feedback resistance is
the minimum current signal that can be detected. This
minimum detectable current divided by the responsivity of the
photodiode represents the lowest light power that can be
detected by the preamp.

Noise sources associated with the photodiode, amplifier, and
feedback resistance are shown in Figure 43; Figure 44 is the
spectral density versus frequency plot of the contribution of
each of the noise sources to the output voltage noise (circuit
parameters in Figure 42 are assumed). Each noise source’s rms
contribution to the total output voltage noise is obtained by
integrating the square of its spectral density function over
frequency. The rms value of the output voltage noise is the
square root of the sum of all contributions. Minimizing the total
area under these curves optimizes the preamplifier’s resolution
for a given bandwidth.

IF

R

F

C

F

I

R

S

S

Figure 43. Photodiode Preamp Noise Sources

IN

C

S

EN

A

00511-043

The photodiode preamp in Figure 41 can detect a signal current
of 26 fA rms at a bandwidth of 16 Hz, which, assuming a
photodiode responsivity of 0.5 A/W, translates to a 52 fW rms
minimum detectable power. The photodiode used has a high
source resistance and low junction capacitance. C
signal bandwidth with R

, and also limits the peak in the noise

F

sets the

F

gain that multiplies the op amp’s input voltage noise contribu­tion. A single pole filter at the amplifier’s output limits the op
amp’s output voltage noise bandwidth to 26 Hz, comparable to
the signal bandwidth. This greatly improves the preamplifier’s
signal-to-noise ratio (in this case, by a factor of 3).

10

1µ

100n

VOLTAGE NOISE CONTRIBUTIONS

NOISE SPECTRAL DENSITY (nV Hz)

EN
CONTRIBUTION,
WITH FILTER

10n

1 10 100 1k 10k 100k 1M

Figure 44. Photodiode Preamp Noise Sources' Spectral Density vs. Frequency

IF AND CS, NO FILTERS

IF AND CS, WITH FILTERS

AD549

OPEN-LOOP GAIN

FREQUENCY (Hz)

EN CONTRIBUTION,
NO FILTER

00511-044

Log Ratio Amplifier

Logarithmic ratio circuits are useful for processing signals with
wide dynamic range. The AD549L’s 60 fA maximum input
current makes it possible to build a log ratio amplifier with 1%
log conformance for input currents ranging from 10 pA to
1 mA, a dynamic range of 160 dB.

The log ratio amplifier in Figure 45 provides an output voltage
proportional to the log base 10 of the ratio of input currents I1
and I2. Resistors R1 and R2 are provided for voltage inputs.
Since NPN devices are used in the feedback loop of the front
end amplifiers that provide the log transfer function, the output
is valid only for positive input voltages and input currents. The
input currents set the collector currents IC1 and IC2 of a
matched pair of log transistors, Q1 and Q2, to develop voltages

VA and VB:

VA , VB = –(kT/q)ln IC/IES

where IES is the transistors’ saturation current.

The difference of VA and VB is taken by the subtractor section
to obtain

VC = (kT/q)ln(IC2/IC1)

Rev. D | Page 15 of 20

AD549

R

V

V

VC is scaled up by the ratio of (R9 + R10)/R8, which is equal to
approximately 16 at room temperature, resulting in the output
voltage

V

= 1 × log(IC2/IC1)V

OUT

R8 is a resistor with a positive 3500 ppm/°C temperature
coefficient to provide the necessary temperature compensation.
The parallel combination of R15 and R7 is provided to keep the
subtractor section’s gain for positive and negative inputs
matched over temperature.

Frequency compensation is provided by R11, R12, C1, and C2.
The bandwidth of the circuit is 300 kHz at input signals greater
than 50 µA; bandwidth decreases smoothly with decreasing
signal levels.

To trim the circuit, set the input currents to 10 µA and trim A3’s
offset using the amplifier’s trim potentiometer so the output
equals 0. Then set I1 to 1 µA and adjust the output to equal 1 V
by trimming R10. Additional offset trims on amplifiers A1 and
A2 can be used to increase the voltage input accuracy and
dynamic range.

The very low input current of the AD549 makes this circuit
useful over a very wide range of signal currents. The total input
current (which determines the low level accuracy of the circuit)
is the sum of the amplifier input current, the leakage across the
compensating capacitor (negligible if a polystyrene or Teflon
capacitor is used), and the collector-to-collector and collector
to-base leakages of one side of the dual log transistors. The
magnitudes of these last two leakages depend on the amplifier’s
input offset voltage, and are typically less than 10 fA with 1 mV
offsets. The low level accuracy is limited primarily by the
amplifier’s input current, only 60 fA maximum when the
AD549L is used.

The effects of the emitter resistance of Q1 and Q2 can degrade
the circuit’s accuracy at input currents above 100 µA. The
networks composed of R13, D1, R16, R14, D2, and R17
compensate for these errors, so that this circuit has less than 1%
log conformance error at 1 mA input currents. The correct
value for R13 and R14 depends on the type of log transistors
used. 49.9 kΩ resistors were chosen for use with LM394
transistors. Smaller resistance values are needed for smaller log
transistors.

I1 IN

1

2

I2 IN

6

D1

R13

49.9kΩ

6

FOR EACH AMPLIFIE

PIN 7

D3

PIN 4

Q1, Q2 = LM394
DUAL LOG TRANSISTORS

R11

49.9kΩ

0.1µF

0.1µF

R15
1kΩ

*

1

*

R7

15kΩ

6

5

10kΩ

OUTPUT
OFFSET

R8

14.3kΩ

1kΩ

R10
2kΩ

R9

= 1V

V

OUT

V

= 1V

OUT

R3

20kΩ

R5

20kΩ

3

A3

AD549

2

4

R4

20kΩ

D4

R6

20kΩ

D1, D4 1N4148 DIODES
R8, R15 1kΩ + 350 ppm/°C TC RESISTOR

*

TELLAB QB1 OR PRECISION RESISTOR PT146

ALL OTHER RESISTORS ARE 1% METAL FILM

+V

S

–V

S

V

OUT

SCALE
FACTOR
ADJ

V

2

LOG

×

10

V

1

I

2

LOG

×

10

I

1

00511-045

10kΩ

V

4

3

A1

AD549

2

C1

100pF

R1

10kΩ

IN

R14

49.9kΩ

D2

R2

10kΩ

IN

100pF

2

AD549

3

C2

A2

4

1

Q1

Q2

1

OFFSET

5

A

R16
10kΩ

R17
10kΩ

B

5

10kΩ

V

2

OFFSET

1

Figure 45. Log Ratio Amplifier

Rev. D | Page 16 of 20

AD549

TEMPERATURE COMPENSATED pH PROBE AMPLIFIER

A pH probe can be modeled as a mV-level voltage source with a
series source resistance dependent upon the electrode’s
composition and configuration. The glass bulb resistance of a

6

typical pH electrode pair falls between 10

Ω and 109 Ω. It is
therefore important to select an amplifier with low enough
input currents such that the voltage drop produced by the
amplifier’s input bias current and the electrode resistance does
not become an appreciable percentage of a pH unit.

The circuit in Figure 46 illustrates the use of the AD549 as a pH
probe amplifier. As with other electrometer applications, the use
of guarding, shielding, Teflon standoffs, and so on is a must in
order to capitalize on the AD549’s low input current. If an
AD549L (60 fA max input current) is used, the error
contributed by the input current is held below 60 µV for pH

9

electrode source impedances up to 10

Ω Input offset voltage

(which can be trimmed) will be below 0.5 mV.

pH

AD590

IN STAINLESS

STEEL PROBE

OR AC2626

PROBE

OUTPUT

+
–

(A)

Figure 46. Temperature Compensated pH Amplified

3

2

12kΩ

1kΩ

7

AD549

4

8

SCALE FACTOR

ADJUST

0.1µF

0.1µF

1kΩ

The pH probe output is ideally 0 V at a pH of 7 independent of
temperature. The slope of the probe’s transfer function, though
predictable, is temperature dependent (−54.2 mV/pH at 0 and

−74.04 mV/pH at 100°C). By using an AD590 temperature
sensor and an AD535 analog divider, an accurate temperature
compensation network can be added to the basic pH probe
amplifier. Table 4 shows voltages at various points and illustrates
the compensation. The AD549 is set for a noninverting gain of

13.51. The output of the AD590 circuitry (Point C) is equal to
10 V at 100°C, and decreases by 26.8 mV/°C. The output of the
AD535 analog divider (Point D) is a temperature compensated
output voltage centered at 0 V for a pH of 7, and has a transfer
function of –1.00 V/pH unit. The output range spans from

−7.00 V (pH = 14) to +7.00 V (pH = 0).

+15V

0.1µF

14

10

11

1
2

AD535

Z

2

Z

1

X

1

X

2

OUT

5

0.1µF

–15V

6

(B)

(C)

+15V

26.6kΩ

(D)

12

Y

7

2

Y

6

1

OUTPUT

00511-046

Table 4. Illustration of Temperature Compensation

Point
Probe Temperature A (Probe Output) B (A 3 13.51) C (590 Output) D (10 B/C)

0 54.20 mV 0.732 V 7.32 V 1.00 V
25°C 59.16 mV 0.799 V 7.99 V 1.00 V
37°C 61.54 mV 0.831 V 8.31 V 1.00 V
60°C 66.10 mV 0.893 V 8.93 V 1.00 V
100°C 74.04 mV 1.000 V 10.00 V 1.00 V

Rev. D | Page 17 of 20

AD549

OUTLINE DIMENSIONS

REFERENCE PLANE

0.5000 (12.70)

0.1850 (4.70)

0.1650 (4.19)

0.3700 (9.40)

0.3350 (8.51)

0.3350 (8.51)

0.3050 (7.75)

0.0400 (1.02) MAX

0.0400 (1.02)

0.0100 (0.25)

COMPLIANT TO JEDEC STANDARDS MO-002AK

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

MIN

0.2500 (6.35) MIN

0.0500 (1.27) MAX

0.2000
(5.08)

BSC

0.0190 (0.48)

0.0160 (0.41)

0.0210 (0.53)

0.0160 (0.41)

BASE & SEATING PLANE

0.1000
(2.54)

BSC

0.1000 (2.54)
BSC

5

4

3

2

1

0.0340 (0.86)

0.0280 (0.71)

Figure 47. 8-Lead Metal Can [TO-99]

(H-08)

Dimensions shown in inches and (millimeters)

0.1600 (4.06)

0.1400 (3.56)

6

7

8

45° BSC

0.0450 (1.14)

0.0270 (0.69)

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD549JH 0°C to +70°C 8-Lead Metal Can (TO-99) H-08
AD549KH 0°C to +70°C 8-Lead Metal Can (TO-99) H-08
AD549LH 0°C to +70°C 8-Lead Metal Can (TO-99) H-08
AD549SH/883B –55°C to +125°C 8-Lead Metal Can (TO-99) H-08

Rev. D | Page 18 of 20

AD549

NOTES

Rev. D | Page 19 of 20

AD549

NOTES

© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.

C00511–0–5/04(D)

Rev. D | Page 20 of 20