Page 1
8-/10-/12-/14-Bit High Bandwidth
Data Sheet
FEATURES
12 MHz multiplying bandwidth
INL of ±0.25 LSB at 8-bit
8-lead TSOT and MSOP packages
2.5 V to 5.5 V supply operation
Pin-compatible 8-/10-/12-/14-bit current output DACs
±10 V reference input
50 MHz serial interface
2.7 MSPS update rate
Extended temperature range: –40°C to +125°C
4-quadrant multiplication
Power-on reset with brownout detect
<0.4 μA typical current consumption
Guaranteed monotonic
Qualified for automotive applications
APPLICATIONS
Portable battery-powered applications
Waveform generators
Analog processing
Instrumentation applications
Programmable amplifiers and attenuators
Digitally controlled calibration
Programmable filters and oscillators
Composite video
Ultrasound
Gain, offset, and voltage trimming
Multiplying DACs with Serial Interface
AD5450/AD5451/AD5452/AD5453
FUNCTIONAL BLOCK DIAGRAM
V
DDVREF
R
FB
AD5450/
SYNC
SCLK
SDIN
AD5451/
AD5452/
AD5453
POWER-ON
RESET
8-/10-/12-/14-BIT REF
R-2R DAC
DAC REGISTER
INPUT LATCH
CONTROL LOGIC
AND INPUT SHIFT
REGISTER
GND
Figure 1.
R
I
1
OUT
04587-001
GENERAL DESCRIPTION
The AD5450/AD5451/AD5452/AD54531 are CMOS 8-/10-/12-/
14-bit current output digital-to-analog converters, respectively.
These devices operate from a 2.5 V to 5.5 V power supply,
making them suited to several applications, including batterypowered applications.
As a result of manufacture on a CMOS submicron process,
these DACs offer excellent 4-quadrant multiplication
characteristics of up to 12 MHz.
These DACs use a double-buffered, 3-wire serial interface that
is compatible with SPI®, QSPI™, MICROWIRE™, and most DSP
interface standards. Upon power-up, the internal shift register
and latches are filled with 0s, and the DAC output is at zero scale.
1
U.S. Patent Number 5,689,257.
Rev. F
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
The applied external reference input voltage (V
) determines
REF
the full-scale output current. These parts can handle ±10 V
inputs on the reference, despite operating from a single-supply
power supply of 2.5 V to 5.5 V. An integrated feedback resistor
(R
) provides temperature tracking and full-scale voltage
FB
output when combined with an external current-to-voltage
precision amplifier.
The AD5450/AD5451/AD5452/AD5453 DACs are available in
small 8-lead TSOT, and the AD5452/AD5453 are also available
in MSOP packages. The AD5453 also comes in 8-lead LFCSP.
The EVAL-AD5443SDZ/EVAL-AD5446SDZ/EVALAD5453SDZ evaluation board is available for evaluating DAC
performance. For more information, see the UG-327 evaluation
board user guide.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2005–2012 Analog Devices, Inc. All rights reserved.
Page 2
AD5450/AD5451/AD5452/AD5453 Data Sheet
TABLE OF CONTENTS
Features.............................................................................................. 1
DAC Section................................................................................ 16
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Typical Performance Characteristics ............................................. 8
Terminology .................................................................................... 15
General Description ....................................................................... 16
REVISION HISTORY
4/12—Rev. E to Rev. F
Changes to General Description Section ...................................... 1
Deleted Evaluation Board for the DAC Section, Power Supplies
for the Evaluation Board Section, and Figure 64;
Renumbered Sequentially.............................................................. 25
Deleted Figure 65 and Figure 66................................................... 26
Deleted Figure 67............................................................................ 27
Changes to Ordering Guide.......................................................... 27
3/11—Rev. D to Rev. E
Changes to
Added Figure 54 (Renumbered Sequentially) ............................ 21
Added Figure 55 and Table 11 ..................................................... 22
2/11—Rev. C to Rev. D
Added 8-Lead LFCSP.........................................................Universal
Changes to Features Section............................................................ 1
Updated Outline Dimensions....................................................... 27
Changes to Ordering Guide.......................................................... 28
Added Automotive Products Section .......................................... 28
Function Section ............................................ 21
SYNC
Circuit Operation....................................................................... 16
Single-Supply Applications....................................................... 18
Adding Gain................................................................................ 18
Divider or Programmable Gain Element................................ 19
Reference Selection .................................................................... 19
Amplifier Selection .................................................................... 19
Serial Interface............................................................................ 21
Microprocessor Interfacing....................................................... 22
PCB Layout and Power Supply Decoupling ........................... 24
Outline Dimensions....................................................................... 26
Ordering Guide .......................................................................... 27
Automotive Products................................................................. 27
1/10—Rev. B to Rev. C
Changes to DAC Control Bits C1, C0.......................................... 21
Updated Outline Dimensions....................................................... 27
Changes to Ordering Guide.......................................................... 28
3/06—Rev. A to Rev. B
Updated Format.................................................................. Universal
Changes to Features ..........................................................................1
Changes to General Description .....................................................1
Changes to Specifications.................................................................4
Changes to Figure 27 and Figure 28............................................. 11
Change to Table 9 ........................................................................... 20
Changes to Table 12 ....................................................................... 26
Updated Outline Dimensions....................................................... 27
Changes to Ordering Guide.......................................................... 28
7/05—Rev. 0 to Rev. A
Added AD5453 ...................................................................Universal
Changes to Specifications.................................................................4
Change to Figure 21....................................................................... 10
Updated Outline Dimensions....................................................... 27
Changes to Ordering Guide.......................................................... 28
1/05—Revision 0: Initial Version
Rev. F | Page 2 of 28
Page 3
Data Sheet AD5450/AD5451/AD5452/AD5453
SPECIFICATIONS
VDD = 2.5 V to 5.5 V, V
noted. DC performance measured with OP177 and ac performance measured with AD8038, unless otherwise noted.
Table 1.
Parameter Min Typ Max Unit Test Conditions
STATIC PERFORMANCE
AD5450
Resolution 8 Bits
Relative Accuracy ±0.25 LSB
Differential Nonlinearity ±0.5 LSB Guaranteed monotonic
Total Unadjusted Error ±0.5 LSB
Gain Error ±0.25 LSB
AD5451
Resolution 10 Bits
Relative Accuracy ±0.25 LSB
Differential Nonlinearity ±0.5 LSB Guaranteed monotonic
Total Unadjusted Error ±0.5 LSB
Gain Error ±0.25 LSB
AD5452
Resolution 12 Bits
Relative Accuracy ±0.5 LSB
Differential Nonlinearity ±1 LSB Guaranteed monotonic
Total Unadjusted Error ±1 LSB
Gain Error ±0.5 LSB
AD5453
Resolution 14 Bits
Relative Accuracy ±2 LSB
Differential Nonlinearity −1/+2 LSB Guaranteed monotonic
Total Unadjusted Error ±4 LSB
Gain Error ±2.5 LSB
Gain Error Temperature Coefficient1 ±2 ppm FSR/°C
Output Leakage Current ±1 nA Data = 0x0000, TA = 25°C, I
±10 nA Data = 0x0000, TA = −40°C to +125°C, I
REFERENCE INPUT1
Reference Input Range ±10 V
V
Input Resistance 7 9 11 kΩ Input resistance, TC = −50 ppm/°C
REF
RFB Feedback Resistance 7 9 11 kΩ Input resistance, TC = −50 ppm/°C
Input Capacitance
Zero-Scale Code 18 22 pF
Full-Scale Code 18 22 pF
DIGITAL INPUTS/OUTPUTS1
Input High Voltage, VIH 2.0 V VDD = 3.6 V to 5 V
1.7 V VDD = 2.5 V to 3.6 V
Input Low Voltage, VIL 0.8 V VDD = 2.7 V to 5.5 V
0.7 V VDD = 2.5 V to 2.7 V
Output High Voltage, VOH VDD − 1 V VDD = 4.5 V to 5 V, I
V
Output Low Voltage, VOL 0.4 V VDD = 4.5 V to 5 V, I
0.4 V VDD = 2.5 V to 3.6 V, I
Input Leakage Current, IIL ±1 nA TA = 25°C
±10 nA TA = −40°C to +125°C
Input Capacitance 10 pF
= 10 V. Temperature range for Y version: −40°C to +125°C. All specifications T
REF
− 0.5 V VDD = 2.5 V to 3.6 V, I
DD
MIN
to T
MAX
= 200 μA
SOURCE
SOURCE
= 200 μA
SINK
= 200 μA
SINK
, unless otherwise
1
OUT
OUT
= 200 μA
1
Rev. F | Page 3 of 28
Page 4
AD5450/AD5451/AD5452/AD5453 Data Sheet
Parameter Min Typ Max Unit Test Conditions
DYNAMIC PERFORMANCE1
Reference-Multiplying BW 12 MHz V
Multiplying Feedthrough Error V
72 dB 100 kHz
64 dB 1 MHz
44 dB 10 MHz
Output Voltage Settling Time
Measured to ±1 mV of FS 100 110 ns
Measured to ±4 mV of FS 24 40 ns
Measured to ±16 mV of FS 16 33 ns
Digital Delay 20 40 ns Interface delay time
10% to 90% Settling Time 10 30 ns Rise and fall times, V
Digital-to-Analog Glitch Impulse 2 nV-s 1 LSB change around major carry, V
Output Capacitance
I
1 13 pF DAC latches loaded with all 0s
OUT
28 pF DAC latches loaded with all 1s
I
2 18 pF DAC latches loaded with all 0s
OUT
5 pF DAC latches loaded with all 1s
Digital Feedthrough 0.5 nV-s
Analog THD 83 dB V
Digital THD Clock = 1 MHz, V
50 kHz f
20 kHz f
Output Noise Spectral Density
SFDR Performance (Wide Band)
50 kHz f
20 kHz f
SFDR Performance (Narrow Band)
50 kHz f
20 kHz f
Intermodulation Distortion
POWER REQUIREMENTS
Power Supply Range 2.5
I
DD
Power Supply Sensitivity1
1
Guaranteed by design and characterization, not subject to production test.
71 dB
OUT
77 dB
OUT
25
nV/√Hz @ 1 kHz
OUT
OUT
78
74
dB
dB
OUT
OUT
87
85
79
dB
dB
dB f1 = 20 kHz, f2 = 25 kHz, clock = 1 MHz, V
0.4 10 μA TA = −40°C to +125°C, logic inputs = 0 V or V
5.5 V
0.6 μA TA = 25°C, logic inputs = 0 V or VDD
0.001 %/% ∆VDD = ±5%
= ±3.5 V, DAC loaded with all 1s
REF
= ±3.5 V, DAC loaded with all 0s
REF
V
REF
= 10 V, R
= 100 Ω; DAC latch alternately
LOAD
loaded with 0s and 1s
= 10 V, R
REF
LOAD
Feedthrough to DAC output with CS
alternate loading of all 0s and all 1s
= 3.5 V p-p, all 1s loaded, f = 1 kHz
REF
= 3.5 V
REF
Clock = 1 MHz, V
= 3.5 V
REF
Clock = 1 MHz, V
= 3.5 V
REF
= 100 Ω
= 0 V
REF
high and
= 3.5 V
REF
DD
Rev. F | Page 4 of 28
Page 5
Data Sheet AD5450/AD5451/AD5452/AD5453
TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. VDD = 2.5 V to 5.5 V,
V
= 10 V, temperature range for Y version: −40°C to +125°C. All specifications T
REF
Table 2.
Parameter1 V
f
50 MHz max Maximum clock frequency
SCLK
= 2.5 V to 5.5 V Unit Description
DD
t1 20 ns min SCLK cycle time
t2 8 ns min SCLK high time
t3 8 ns min SCLK low time
t4 8 ns min
SYNC
t5 5 ns min Data setup time
t6 4.5 ns min Data hold time
t7 5 ns min
t8 30 ns min
Update Rate 2.7 MSPS
SYNC
Minimum SYNC
Consists of cycle time, SYNC
output voltage settling time
1
Guaranteed by design and characterization, not subject to production test.
MIN
to T
, unless otherwise noted.
MAX
falling edge to SCLK active edge setup time
rising edge to SCLK active edge
high time
high time, data setup, and
t
1
SCLK
t
3
t
7
04587-002
SYNC
DIN
t
t
8
t
4
t
6
t
5
DB15 DB0
2
Figure 2. Timing Diagram
Rev. F | Page 5 of 28
Page 6
AD5450/AD5451/AD5452/AD5453 Data Sheet
ABSOLUTE MAXIMUM RATINGS
Transient currents of up to 100 mA do not cause SCR latch-up.
T
= 25°C, unless otherwise noted.
A
Table 3.
Parameter Rating
VDD to GND −0.3 V to +7 V
V
, RFB to GND −12 V to +12 V
REF
I
1 to GND −0.3 V to +7 V
OUT
Input Current to Any Pin Except Supplies ±10 mA
Logic Inputs and Output1 −0.3 V to VDD + 0.3 V
Operating Temperature Range, Extended
−40°C to +125°C
(Y Version)
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
θJA Thermal Impedance
8-Lead MSOP 206°C/W
8-Lead TSOT 211°C/W
Lead Temperature, Soldering (10 sec) 300°C
IR Reflow, Peak Temperature (<20 sec) 235°C
1
Overvoltages at SCLK,
, and SDIN are clamped by internal diodes.
SYNC
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. F | Page 6 of 28
Page 7
Data Sheet AD5450/AD5451/AD5452/AD5453
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1I
R
V
REF
V
SYNC
1
FB
AD5450/
2
AD5451/
AD5452/
3
DD
AD5453
4
8
7
6
5
I
OUT
GND
SCLK
SDIN
1
04587-003
Figure 3. 8-Lead TSOT Pin Configuration
I
OUT
GND
SCLK
SDIN
1
1
2
3
4
AD5452/
AD5453
8
7
6
5
R
FB
V
REF
V
DD
SYNC
04587-004
Figure 4. 8-Lead MSOP Pin Configuration
Table 4. Pin Function Descriptions
Pin No1
TSOT MSOP LFCSP Mnemonic Description
1 8 8 R
FB
DAC Feedback Resistor. Establish voltage output for the DAC by connecting to external
amplifier output.
2 7 7 V
3 6 6 V
4 5 5
DAC Reference Voltage Input.
REF
Positive Power Supply Input. These parts can operate from a supply of 2.5 V to 5.5 V.
DD
SYNC Active Low Control Input. This is the frame synchronization signal for the input data. Data is
loaded to the shift register upon the active edge of the following clocks.
5 4 4 SDIN
Serial Data Input. Data is clocked into the 16-bit input register upon the active edge of the serial
clock input. By default, in power-up mode data is clocked into the shift register upon the falling
edge of SCLK. The control bits allow the user to change the active edge to a rising edge.
6 3 3 SCLK
Serial Clock Input. By default, data is clocked into the input shift register upon the falling edge
of the serial clock input. Alternatively, by means of the serial control bits, the device can be
configured such that data is clocked into the shift register upon the rising edge of SCLK.
7 2 2 GND
8 1 1 I
1 DAC Current Output.
OUT
Ground Pin.
N/A N/A EPAD EPAD Exposed pad must be connected to ground.
1
N/A = not applicable.
1
OUT
NOTES
1. THE EXPOSED PAD MUST BE
CONNECTED TO GROUND.
2GND
3SCLK
4SDIN
AD5453
TOP VIEW
(Not to Scale)
Figure 5. 8-Lead LFCSP Pin Configuration
8R
FB
7V
REF
6V
DD
5SYNC
04587-205
Rev. F | Page 7 of 28
Page 8
AD5450/AD5451/AD5452/AD5453 Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
0.25
TA = 25°C
= 10V
V
0.20
REF
V
= 5V
DD
0.15
0.10
0.05
0
INL (LSB)
–0.05
–0.10
–0.15
–0.20
–0.25
0 32 64 96 128 160 192 224 256
CODE
Figure 6. INL vs. Code (8-Bit DAC)
04587-020
2.0
TA = 25°C
= 10V
V
1.6
REF
V
= 5V
DD
1.2
0.8
0.4
0
INL (LSB)
–0.4
–0.8
–1.2
–1.6
–2.0
0 2048 4096 6144 8192 10240 12288 14336 16384
CODE
Figure 9. INL vs. Code (14-Bit DAC)
04587-023
0.25
TA = 25°C
= 10V
V
0.20
REF
= 5V
V
DD
0.15
0.10
0.05
0
INL (LSB)
–0.05
–0.10
–0.15
–0.20
–0.25
0 128 256 384 512 640 768 896 1024
CODE
Figure 7. INL vs. Code (10-Bit DAC)
0.5
TA = 25°C
= 10V
V
0.4
REF
= 5V
V
DD
0.3
0.2
0.1
0
INL (LSB)
–0.1
–0.2
–0.3
–0.4
–0.5
0 512 1024 1536 2048 2560 3072 2584 4096
CODE
04587-021
04587-022
0.5
TA = 25°C
= 10V
V
0.4
REF
= 5V
V
DD
0.3
0.2
0.1
0
–0.1
DNL (LSB)
–0.2
–0.3
–0.4
–0.5
0 32 64 96 128 160 192 224 256
CODE
Figure 10. DNL vs. Code (8-Bit DAC)
0.5
TA = 25°C
= 10V
V
0.4
REF
= 5V
V
DD
0.3
0.2
0.1
0
–0.1
DNL (LSB)
–0.2
–0.3
–0.4
–0.5
0 128 256 384 512 640 768 896 1024
CODE
04587-024
04587-025
Figure 8. INL vs. Code (12-Bit DAC)
Figure 11. DNL vs. Code (10-Bit DAC)
Rev. F | Page 8 of 28
Page 9
Data Sheet AD5450/AD5451/AD5452/AD5453
1.0
TA = 25°C
= 10V
V
0.8
REF
= 5V
V
DD
0.6
0.4
0.2
0
–0.2
DNL (LSB)
–0.4
–0.6
–0.8
–1.0
0 512 1024 1536 2048 2560 3072 2584 4096
CODE
04587-026
2.0
TA = 25°C
VDD = 5V
1.5
AD5452
1.0
0.5
0
DNL (LSB)
–0.5
–1.0
–1.5
–2.0
2345678910
MAX DNL
MIN DNL
REFERENCE VOLTAGE (V)
04587-071
Figure 12. DNL vs. Code (12-Bit DAC)
2.0
TA = 25°C
= 10V
V
1.6
REF
= 5V
V
DD
1.2
0.8
0.4
0
–0.4
DNL (LSB)
–0.8
–1.2
–1.6
–2.0
0 2048 4096 6144 8192 10240 12288 14336 16384
CODE
Figure 13. DNL vs. Code (14-Bit DAC)
1.00
TA = 25°C
V
= 5V
DD
AD5452
MAX INL
0
MIN INL
2345678910
REFERENCE VOLTAGE (V)
INL (LSB)
–0.25
–0.50
–0.75
–1.00
0.75
0.50
0.25
04587-027
04587-070
Figure 15. DNL vs. Reference Voltage
0.5
TA = 25°C
V
= 10V
0.4
REF
VDD = 5V
AD5450
0.3
0.2
0.1
0
TUE (LSB)
–0.1
–0.2
–0.3
–0.4
–0.5
0 32 64 96 128 160 192 224 256
CODE
Figure 16. TUE vs. Code (8-Bit DAC)
0.25
TA = 25°C
V
= 10V
REF
VDD = 5V
AD5451
0
0 128 256 384 512 640 768 896 1024
CODE
TUE (LSB)
0.20
0.15
0.10
0.05
–0.05
–0.10
–0.15
–0.20
–0.25
04587-030
04587-031
Figure 14. INL vs. Reference Voltage
Figure 17. TUE vs. Code (10-Bit DAC)
Rev. F | Page 9 of 28
Page 10
AD5450/AD5451/AD5452/AD5453 Data Sheet
1.0
TA = 25°C
V
= 10V
0.8
REF
VDD = 5V
0.6
0.4
0.2
0
TUE (LSB)
–0.2
–0.4
–0.6
–0.8
–1.0
0 512 1024 1536 2048 2560 3072 2584 4096
CODE
04587-032
0.3
0.2
0.1
VDD = 3V
VDD = 5V
0
–0.1
GAIN ERROR (LSB)
–0.2
–0.3
–60 –40 –20 0 60 80 100 120 140
TEMPERATURE (°C)
4020
04587-073
Figure 18. TUE vs. Code (12-Bit DAC)
2.0
TA = 25°C
V
= 10V
1.6
REF
VDD = 5V
1.2
0.8
0.4
0
INL (LSB)
–0.4
–0.8
–1.2
–1.6
–2.0
0 2048 4096 6144 8192 10240 12288 14336 16384
CODE
Figure 19. TUE vs. Code (14-Bit DAC)
2.0
TA = 25°C
V
= 5V
DD
1.5
AD5452
1.0
0.5
0
TUE (LSB)
–0.5
–1.0
–1.5
–2.0
2345 8910
MAX TUE
MIN TUE
76
REFERENCE VOLTAGE (V)
Figure 20. TUE vs. Reference Voltage
04587-033
04587-072
Figure 21. Gain Error (LSB) vs. Temperature
2.0
TA = 25°C
V
= 5V
DD
1.5
AD5452
1.0
0.5
0
–0.5
GAIN ERROR (LSB)
–1.0
–1.5
–2.0
2345 8910
REFERENCE VOLTAGE (V)
76
Figure 22. Gain Error (LSB) vs. Reference Voltage
2.0
I
1 VDD = 5V
OUT
1.6
I
= 3V
OUT1VDD
1.2
0.8
1 LEAKAGE (nA)
OUT
I
0.4
0
–40 –20 0 20 40 60 80 100 120
Figure 23. I
TEMPERATURE (°C)
1 Leakage Current vs. Temperature
OUT
04587-074
04587-039
Rev. F | Page 10 of 28
Page 11
Data Sheet AD5450/AD5451/AD5452/AD5453
2.5
TA = 25°C
2.0
1.5
1.0
CURRENT (mA)
0.5
= 3V
V
DD
0
012345
INPUT VOLTAGE (V)
= 5V
V
DD
04587-038
1.8
TA = 25°C
1.6
1.4
1.2
1.0
0.8
0.6
THRESHOLD VOLTAGE (V)
0.4
0.2
0
3.0 3.5 4.54.0 5.0
2.5 5.5
VOLTAGE (V)
V
IH
V
IL
04587-076
Figure 24. Supply Current vs. Logic Input Voltage
0.7
0.6
0.5
A)
μ
0.4
0.3
CURRENT (
0.2
0.1
0
–40 –20 0 20 40 60 80 100 120
VDD = 5V
V
= 3V
DD
TEMPERATURE (°C)
Figure 25. Supply Current vs. Temperature
6
TA = 25°C
AD5452
LOADING 010101010101
5
4
3
CURRENT (mA)
2
1
0
1 10 100 1k 10k 100 k 1M 10M
FREQUENCY (Hz)
VDD = 5V
Figure 26. Supply Current vs. Update Rate
ALL 1s
ALL 0s
VDD = 3V
04587-075
04587-037
Figure 27. Thres hold Voltag e vs. Suppl y Voltage
10
0
ALL ON
DB13
–10
DB12
DB11
–20
DB10
–30
–40
GAIN (dB)
–50
–60
–70
–80
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
10k 100k 1M 10M 100M
FREQUENCY (Hz)
T
= 25°C
A
LOADING
ZS TO FS
VDD = 5V
V
= ±3.5V
REF
C
= 1.8pF
COMP
AD8038 AMPLIFI ER
Figure 28. Reference Multiplying Bandwidth vs. Frequency and Code
0.6
0.4
0.2
0
–0.2
–0.4
GAIN (dB)
–0.6
TA = 25°C
–0.8
V
= 5V
DD
V
= ±3.5V
REF
–1.0
C
= 1.8pF
COMP
AD8038 AMPLIFI ER
–1.2
10k 100k 1M 10M 100M
FREQUENCY (Hz)
Figure 29. Reference Multiplying Bandwidth—All 1s Loaded
04587-108
04587-109
Rev. F | Page 11 of 28
Page 12
AD5450/AD5451/AD5452/AD5453 Data Sheet
–
R
3
TA = 25°C
V
= 5V
DD
0
–3
GAIN (dB)
–6
V
= ±2V, AD8038 C
REF
V
= ±2V, AD8038 C
REF
V
= ±15V, AD8038 C
REF
V
= ±15V, AD8038 C
REF
V
= ±15V, AD8038 C
REF
–9
10k 100k 1M 10M 100M
= 1pF
COMP
= 1.5pF
COMP
= 1pF
COMP
= 1.5pF
COMP
= 1.8pF
COMP
FREQUENCY (Hz)
04587-079
10
TA = 25°C
V
= 3V
0
DD
AD8038 AMPLIFIER
–10
–20
–30
–40
–50
PSRR (dB)
–60
–70
–80
–90
–100
1 10 100 1k 10k 100k 1M 10M
FULL SCALE
ZERO SCALE
FREQUENCY (Hz)
04587-082
Figure 30. Reference Multiplying Bandwidth vs. Frequency and
Compensation Capacitor
0.08
0.06
0.04
0.02
0
–0.02
OUTPUT VOLTAGE (V)
–0.04
–0.06
50 200 225 250
VDD =5V
0x7FF TO 0x800
NRG = 2.154nVs
VDD = 3V
0x7FF TO 0x800
NRG = 1.794nVs
VDD =5V
0x800 TO 0x7FF
NRG = 0.694nVs
VDD =5V
0x800 TO 0x7FF
NRG = 0.694nVs
TIME (ns)
Figure 31. Midscale Transition, V
–1.66
–1.68
–1.70
–1.72
–1.74
VDD =5V
0x7FF TO 0x800
NRG = 2.154nVs
VDD = 3V
0x7FF TO 0x800
NRG = 1.794nVs
TA = 25°C
V
= 0V
DD
AD8038 AMPLIFIER
C
= 1.8pF
COMP
175100 125 15075
= 0 V
REF
TA = 25°C
= 3.5V
V
DD
AD8038 AMPLIFIER
= 1.8pF
C
COMP
Figure 33. Power Supply Rejection Ratio vs. Frequency
60
TA = 25°C
V
= 5V
DD
V
= ±3.5V
REF
–65
–70
–75
THD+N(dB)
–80
–85
04587-080
–90
100 1k 10k 100k
FREQUENCY (Hz)
04587-083
Figure 34. THD + Noise vs. Frequency
100
80
MCLK = 1MHz
60
(dB)
40
SFD
MCLK = 500kHz
MCLK = 200kHz
–1.76
OUTPUT VOLTAGE (V)
–1.78
–1.80
50 200 225 250
Figure 32. Midscale Transition, V
VDD =5V
0x800 TO 0x7FF
NRG = 0.694nVs
VDD =5V
0x800 TO 0x7FF
NRG = 0.694nVs
TIME (ns)
175100 125 15075
= 3.5 V
REF
04587-081
20
TA = 25°C
V
= ±3.5V
REF
AD8038 AMPLIFI ER
0
05
Figure 35. Wideband SFDR vs. f
20 30 4010
f
(kHz)
OUT
Frequency
OUT
04587-084
0
Rev. F | Page 12 of 28
Page 13
Data Sheet AD5450/AD5451/AD5452/AD5453
–20
0
TA = 25°C
= 5V
V
DD
V
= 3.5V
REF
AD8038 AMPLIFIER
–20
0
TA = 25°C
= 5V
V
DD
= 3.5V
V
REF
AD8038 AMPLIFIER
–40
–60
SFDR (dB)
–80
–100
–120
0 500k
Figure 36. Wideband SFDR, f
0
–20
–40
–60
SFDR (dB)
–80
–100
FREQUENCY (Hz)
= 20 kHz, Clock = 1 MHz
OUT
400k300k200k100k
TA = 25°C
= 5V
V
DD
= 3.5V
V
REF
AD8038 AMPLIFIER
–40
–60
SFDR (d B)
–80
–100
04587-085
–120
10k 30k
Figure 38. Narrow-Band SFDR, f
0
–20
–40
–60
SFDR (dB)
–80
–100
FREQUENCY (Hz)
= 20 kHz, Clock = 1 MHz
OUT
25k20k15k
TA = 25°C
V
= 5V
DD
= 3.5V
V
REF
AD8038 AMPLIFIER
04587-087
–120
0 500k
Figure 37. Wideband SFDR, f
FREQUENCY (Hz)
= 50 kHz, Clock = 1 MHz
OUT
400k300k200k100k
04587-086
–120
30k 70k
Figure 39. Narrow-Band SFDR , f
FREQUENCY (Hz)
= 50 kHz, Clock = 1 MHz
OUT
60k50k40k
04587-088
Rev. F | Page 13 of 28
Page 14
AD5450/AD5451/AD5452/AD5453 Data Sheet
0
–10
–20
–30
–40
–50
IMD (dB)
–60
–70
–80
–90
–100
10k 35k
Figure 40. Narrow-Band IMD, f
FREQUENCY (Hz)
= 20 kHz, 25 kHz, Clock = 1 MHz
OUT
T
= 25°C
A
V
= 3.5V
REF
AD8038 AMPLIFIER
30k25k20k15k
04587-089
80
70
60
FULL SCALE
LOADED TO DAC
50
40
30
20
OUTPUT NOI SE (nV/ Hz)
10
0
100 1k 10k 100k 1M
FREQUENCY (Hz)
TA = 25°C
AD8038 AMPLIFIER
MIDSCALE
LOADED TO DAC
ZERO SCALE
LOADED TO DAC
Figure 42. Output Noise Spectral Density
04587-091
0
–10
–20
–30
–40
–50
IMD (dB)
–60
–70
–80
–90
–100
0 500k
Figure 41. Wideband IMD, f
TA = 25°C
V
= 3.5V
REF
AD8038 AMPLIFIER
FREQUENCY (Hz)
= 20 kHz, 25 kHz, Clock = 1 MHz
OUT
400k300k200k100k
04587-090
Rev. F | Page 14 of 28
Page 15
Data Sheet AD5450/AD5451/AD5452/AD5453
TERMINOLOGY
Relative Accuracy (Endpoint Nonlinearity)
A measure of the maximum deviation from a straight line passing
through the endpoints of the DAC transfer function. It is measured after adjusting for zero and full scale and is normally
expressed in LSBs or as a percentage of the full-scale reading.
Differential Nonlinearity
The difference between the measured change and the ideal 1 LSB
change between any two adjacent codes. A specified differential
nonlinearity of −1 LSB maximum over the operating temperature
range ensures monotonicity.
Digital Feedthrough
When the device is not selected, high frequency logic activity
on the device’s digital inputs may be capacitively coupled
through the device and produce noise on the I
pins. This
OUT
noise is coupled from the outputs of the device onto follow-on
circuitry. This noise is digital feedthrough.
Multiplying Feedthrough Error
The error due to capacitive feedthrough from the DAC
reference input to the DAC I
1 terminal when all 0s are
OUT
loaded to the DAC.
Gain Error (Full-Scale Error)
A measure of the output error between an ideal DAC and the
actual device output. For these DACs, ideal maximum output is
V
− 1 LSB. Gain error of the DACs is adjustable to zero with
REF
external resistance.
Output Leakage Current
The current that flows into the DAC ladder switches when it is
turned off. For the I
all 0s to the DAC and measuring the I
1 terminal, it can be measured by loading
OUT
1 current.
OUT
Output Capacitance
Capacitance from I
1 to AGND.
OUT
Output Current Settling Time
The amount of time it takes for the output to settle to a specified
level for a full-scale input change. For these devices, it is specified
with a 100 Ω resistor to ground. The settling time specification
includes the digital delay from the
rising edge to the full-
SYNC
scale output change.
Digital-to-Analog Glitch Impulse
The amount of charge injected from the digital inputs to the
analog output when the inputs change state. This is normally
specified as the area of the glitch in either pA-s or nV-s, depending
on whether the glitch is measured as a current or voltage signal.
Total Harmonic Distortion (THD)
The DAC is driven by an ac reference. The ratio of the rms sum
of the harmonics of the DAC output to the fundamental value is
the THD. Usually only the lower-order harmonics, such as
second to fifth, are included.
2222
+++
VVVV
5432
THD
log20
=
V
1
Digital Intermodulation Distortion (IMD)
Second-order intermodulation measurements are the relative
magnitudes of the fa and fb tones generated digitally by the
DAC and the second-order products at 2fa − fb and 2fb − fa.
Compliance Voltage Range
The maximum range of (output) terminal voltage for which the
device provides the specified characteristics.
Spurious-Free Dynamic Range (SFDR)
The usable dynamic range of a DAC before spurious noise
interferes or distorts the fundamental signal. SFDR is the
measure of difference in amplitude between the fundamental
and the largest harmonically or nonharmonically related spur
from dc to full Nyquist bandwidth (half the DAC sampling rate
or f
/2). Narrow-band SFDR is a measure of SFDR over an
S
arbitrary window size, in this case 50% of the fundamental.
Digital SFDR is a measure of the usable dynamic range of the
DAC when the signal is a digitally generated sine wave.
Rev. F | Page 15 of 28
Page 16
AD5450/AD5451/AD5452/AD5453 Data Sheet
V
V
2
GENERAL DESCRIPTION
DAC SECTION
The AD5450/AD5451/AD5452/AD5453 are 8-/10-/12-/14-bit
current output DACs, respectively, consisting of a segmented
(4-bit) inverting R-2R ladder configuration. A simplified
diagram for the 12-bit AD5452 is shown in Figure 43.
V
REF
RR R
2R
2R
S1
DAC DATA LATCHES
2R
S2
S3
AND DRIVERS
2R
S12
Figure 43. AD5452 Simplified Ladder
2R
R
R
FB
I
1
OUT
AGND
04587-060
The feedback resistor, RFB, has a value of R. The value of R is
typically 9 kΩ (with a minimum value of 7 kΩ and a maximum
value of 11 kΩ). If I
1 is kept at the same potential as GND, a
OUT
constant current flows in each ladder leg, regardless of digital
input code. Therefore, the input resistance presented at V
REF
is
always constant and nominally of value R. The DAC output
(I
1) is code-dependent, producing various resistances and
OUT
capacitances. When choosing the external amplifier, take into
account the variation in impedance generated by the DAC on
the amplifier’s inverting input node.
Access is provided to the V
, RFB, and I
REF
1 terminals of the
OUT
DAC, making the device extremely versatile and allowing it to be
configured in several operating modes; for example, it can provide
a unipolar output or can provide 4-quadrant multiplication in
bipolar mode. Note that a matching switch is used in series with
the internal R
R
, power must be applied to V
FB
feedback resistor. If users attempt to measure
FB
to achieve continuity.
DD
CIRCUIT OPERATION
Unipolar Mode
Using a single op amp, these devices can easily be configured to
provide a 2-quadrant multiplying operation or a unipolar output
voltage swing, as shown in Figure 44. When an output amplifier
is connected in unipolar mode, the output voltage is given by
Note that the output voltage polarity is opposite to the V
polarity for dc reference voltages.
DD
V
DD
AD5450/
AD5451/
R1
V
REF
AD5452/
AD5453
SCLK SDIN
SYNC
µCONTROLLER
REF
NOTES
1. R1 AND R2 USED ONLY IF GAI N ADJUSTMENT I S REQUIRED.
. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
Figure 44. Unipolar Mode Operation
R2
R
FB
I
OUT
GND
C1
1
A1
V
AGND
These DACs are designed to operate with either negative or
positive reference voltages. The V
power pin is only used by
DD
the internal digital logic to drive the on and off states of the
DAC switches.
These DACs are designed to accommodate ac reference input
signals in the range of −10 V to +10 V.
With a fixed 10 V reference, the circuit shown in Figure 44 gives
a unipolar 0 V to −10 V output voltage swing. When V
signal, the circuit performs 2-quadrant multiplication.
Tabl e 5 shows the relationship between the digital code and
the expected output voltage for a unipolar operation using the
8-bit AD5450.
Table 5. Unipolar Code Table for the AD5450
Digital Input Analog Output (V)
1111 1111 −V
1000 0000 −V
0000 0001 −V
0000 0000 −V
(255/256)
REF
(128/256) = −V
REF
(1/256)
REF
(0/256) = 0
REF
REF
/2
= 0 TO –V
OUT
REF
is an ac
IN
REF
04587-009
V ×−=
OUT
D
n
2
V
REF
where:
D is the fractional representation of the digital word loaded to
the DAC.
D = 0 to 255 (8-bit AD5450).
= 0 to 1023 (10-bit AD5451).
= 0 to 4095 (12-bit AD5452).
= 0 to 16,383 (14-bit AD5453).
n is the number of bits.
Rev. F | Page 16 of 28
Page 17
Data Sheet AD5450/AD5451/AD5452/AD5453
Bipolar Mode
In some applications, it may be necessary to generate a full
4-quadrant multiplying operation or a bipolar output swing.
This can be easily accomplished by using another external
amplifier and some external resistors, as shown in Figure 45. In
this circuit, the second amplifier, A2, provides a gain of 2.
Biasing the external amplifier with an offset from the reference
voltage results in full 4-quadrant multiplying operation. The
transfer function of this circuit shows that both negative and
positive output voltages are created as the input data (D) is
incremented from Code 0 (V
(V
− 0 V ) to full scale (V
OUT
D
OUT
⎛
VV −
⎜
REF
⎝
⎞
×=
⎟
−1
n
2
⎠
OUT
OUT
V
= − V
= +V
REF
REF
) to midscale
REF
).
where:
D is the fractional representation of the digital word loaded to
the DAC.
D = 0 to 255 (8-bit AD5450).
= 0 to 1023 (10-bit AD5451).
= 0 to 4095 (12-bit AD5452).
n is the resolution of the DAC.
When V
multiplication. Tab l e 6 shows the relationship between the
digital code and the expected output voltage for a bipolar
operation using the 8-bit AD5450.
Table 6. Bipolar Code Table for the AD5450
Digital Input Analog Output (V)
1111 1111 +V
1000 0000 0
0000 0001 −V
0000 0000 −V
is an ac signal, the circuit performs 4-quadrant
IN
(127/128)
REF
(127/128)
REF
(128/128)
REF
R3
20kΩ
V
DD
V
DD
AD5450/
V
REF
±10V
NOTES
1. R1 AND R2 USED ONLY IF GAIN ADJUSTMENT I S REQUIRED.
2. MATCHING AND TRACKING IS E SSENTIAL FOR RESI STOR PAIRS
3. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
R1
ADJUST R1 FOR V
R3 AND R4.
IF A1/A2 IS A HIGH SPEED AMPLIFIER.
AD5451/
V
REF
AD5452/
AD5453
SCLK SDIN
SYNC
µCONTROLLER
= 0V WITH CODE 10000000 LOADE D TO DAC.
OUT
R2
R
FB
I
OUT
GND
C1
1
A1
AGND
10kΩ
R5
20kΩ
R4
A2
= –V
V
OUT
REF
TO +V
REF
04587-010
Figure 45. Bipolar Mode Operation (4-Quadrant Multiplication)
Rev. F | Page 17 of 28
Page 18
AD5450/AD5451/AD5452/AD5453 Data Sheet
V
Stability
In the I-to-V configuration, the I
of the DAC and the
OUT
inverting node of the op amp must be connected as close as
possible, and proper PCB layout techniques must be employed.
Because every code change corresponds to a step function, gain
peaking may occur if the op amp has limited gain bandwidth
product (GBP) and there is excessive parasitic capacitance at the
inverting node. This parasitic capacitance introduces a pole into
the open-loop response, which can cause ringing or instability
in the closed-loop applications circuit.
An optional compensation capacitor, C1, can be added in parallel
with R
for stability, as shown in Figure 44 and Figure 45. Too
FB
small a value of C1 can produce ringing at the output, and too
large a value can adversely affect the settling time. C1 should be
found empirically, but 1 pF to 2 pF is generally adequate for the
compensation.
Positive Output Voltage
The output voltage polarity is opposite to the V
polarity for
REF
dc reference voltages. To achieve a positive voltage output, an
applied negative reference to the input of the DAC is preferred
over the output inversion through an inverting amplifier
because of the resistors’ tolerance errors. To generate a negative
reference, the reference can be level-shifted by an op amp such
that the V
and GND pins of the reference become the virtual
OUT
ground and −2.5 V, respectively, as shown in Figure 47.
GND
–2.5V
VDD = +5V
V
DD
V
REF
GND
R
FB
I
OUT
C1
1
V
= 0V TO +2.5V
OUT
V
+5V
–5V
ADR03
OUTVIN
SINGLE-SUPPLY APPLICATIONS
Voltage-Switching Mode
Figure 46 shows these DACs operating in the voltage-switching
mode. The reference voltage, V
the output voltage is available at the V
configuration, a positive reference voltage results in a positive
output voltage, making single-supply operation possible. The
output from the DAC is voltage at a constant impedance (the
DAC ladder resistance); therefore, an op amp is necessary to
buffer the output voltage. The reference input no longer sees
constant input impedance, but one that varies with code;
therefore, the voltage input should be driven from a low
impedance source.
R
FB
V
NOTES
1. ADDITIONAL PINS OMITTED FOR CLARITY.
2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
I
IN
1V
OUT
GND
Figure 46. Single-Supply Voltage-Switching Mode
It is important to note that with this configuration VIN is limited
to low voltages because the switches in the DAC ladder do not
have the same source-drain drive voltage. As a result, their on
resistance differs, which degrades the integral linearity of the
DAC. Also, V
must not go negative by more than 0.3 V, or an
IN
internal diode turns on, causing the device to exceed the
maximum ratings. In this type of application, the full range of
multiplying capability of the DAC is lost.
, is applied to the I
IN
terminal. In this
REF
R1 R2
V
DD
V
DD
REF
1 pin, and
OUT
V
OUT
4587-011
NOTES
1. ADDITIONAL PINS OMITTED FOR CLARITY.
2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
Figure 47. Positive Output Voltage with Minimum Components
ADDING GAIN
In applications in which the output voltage is required to be
greater than V
amplifier, or it can be achieved in a single stage. It is important
to consider the effect of the temperature coefficients of the
DAC’s thin film resistors. Simply placing a resistor in series
with the R
coefficients and results in larger gain temperature coefficient
errors. Instead, increase the gain of the circuit by using the
recommended configuration shown in Figure 48. R1, R2, and
R3 should have similar temperature coefficients, but they need
not match the temperature coefficients of the DAC. This
approach is recommended in circuits where gains greater than 1
are required.
R1
IN
NOTES
1. ADDITIONAL PINS OMITTED FOR CLARITY.
2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
, gain can be added with an additional external
IN
resistor causes mismatches in the temperature
FB
V
DD
V
V
REF
R
GND
FB
I
OUT
DD
C1
1
R3
GAIN =
R2
R1 =
Figure 48. Increasing Gain of Current-Output DAC
V
OUT
R2 + R3
R2
R2R3
R2 + R3
04587-013
04587-012
Rev. F | Page 18 of 28
Page 19
Data Sheet AD5450/AD5451/AD5452/AD5453
A
Y
DIVIDER OR PROGRAMMABLE GAIN ELEMENT REFERENCE SELECTION
Current-steering DACs are very flexible and lend themselves to
many different applications. If this type of DAC is connected as
the feedback element of an op amp and R
is used as the input
FB
resistor as shown in Figure 49, the output voltage is inversely
proportional to the digital input fraction, D.
−n
For D = 1 − 2
V
OUT
, the output voltage is
V
−
=
D
V
−
ININ
=
()
−
21
n
−
As D is reduced, the output voltage increases. For small values
of the digital fraction, D, it is important to ensure that the
amplifier does not saturate and that the required accuracy is
met. For example, an 8-bit DAC driven with the binary code
0x10 (00010000), that is, 16 decimal, in the circuit of Figure 49
should cause the output voltage to be 16 times V
V
V
IN
I
1V
OUT
NOTE
DDITIONAL PINS OMITTED FOR CLARIT
Figure 49. Current-Steering DAC Used as a Divider or
Programmable Gain Element
DD
R
V
FB
DD
REF
GND
.
IN
V
OUT
4587-014
However, if the DAC has a linearity specification of ±0.5 LSB, D
can have weight anywhere in the range of 15.5/256 to 16.5/256.
Therefore, the possible output voltage is in the range of 15.5 V
to 16.5 V
—an error of 3%, even though the DAC itself has a
IN
IN
maximum error of 0.2%.
DAC leakage current is also a potential error source in divider
circuits. The leakage current must be counterbalanced by an
opposite current supplied from the op amp through the DAC.
Because only a fraction, D, of the current in the V
routed to the I
1 terminal, the output voltage changes as follows:
OUT
terminal is
REF
Output Error Voltage Dueto Leakage = (Leakage × R)/D
where R is the DAC resistance at the V
terminal.
REF
For a DAC leakage current of 10 nA, R = 10 kΩ, and a gain
(that is, 1/D) of 16, the error voltage is 1.6 mV.
When selecting a reference for use with this series of currentoutput DACs, pay attention to the reference’s output voltage
temperature coefficient specification. This parameter not only
affects the full-scale error, but also may affect the linearity (INL
and DNL) performance. The reference temperature coefficient
should be consistent with the system accuracy specifications.
For example, an 8-bit system is required to hold its overall
specification to within 1 LSB over the temperature range 0°C to
50°C, and the system’s maximum temperature drift should be
less than 78 ppm/°C.
A 12-bit system within 2 LSB accuracy requires a maximum
drift of 10 ppm/°C. Choosing a precision reference with a low
output temperature coefficient minimizes this error source.
Tabl e 7 lists some dc references available from Analog Devices
that are suitable for use with this range of current-output DACs.
AMPLIFIER SELECTION
The primary requirement for the current-steering mode is an
amplifier with low input bias currents and low input offset voltage.
The input offset voltage of an op amp is multiplied by the variable
gain of the circuit due to the code-dependent output resistance of
the DAC. A change in this noise gain between two adjacent digital
fractions produces a step change in the output voltage due to the
offset voltage of the amplifier’s input. This output voltage change
is superimposed on the desired change in output between the two
codes and gives rise to a differential linearity error, which if
large enough, could cause the DAC to be nonmonotonic.
The input bias current of an op amp generates an offset at the
voltage output as a result of the bias current flowing in the
feedback resistor, R
low enough to prevent significant errors in 12-bit applications.
However, for 14-bit applications, some consideration should be
given to selecting an appropriate amplifier.
Common-mode rejection of the op amp is important in voltageswitching circuits because it produces a code-dependent error
at the voltage output of the circuit. Most op amps have adequate
common-mode rejection for use at 8-, 10-, and 12-bit resolutions.
Provided that the DAC switches are driven from true wideband
low impedance sources (V
Consequently, the slew rate and settling time of a voltageswitching DAC circuit is determined largely by the output op
amp. To obtain minimum settling time in this configuration, it
is important to minimize capacitance at the V
output node in this application) of the DAC. This is done by using
low input-capacitance buffer amplifiers and careful board design.
. Most op amps have input bias currents
FB
and AGND), they settle quickly.
IN
node (the voltage
REF
Most single-supply circuits include ground as part of the analog
signal range, which in turn requires an amplifier that can handle
rail-to-rail signals. There is a large range of single-supply amplifiers
available from Analog Devices.
Rev. F | Page 19 of 28
Page 20
AD5450/AD5451/AD5452/AD5453 Data Sheet
Table 7. Suitable ADI Precision References
Part No. Output Voltage (V) Initial Tolerance (%) Temp Drift (ppm/°C) ISS (mA) Output Noise (μV p-p) Package
ADR01 10 0.05 3 1 20 SOIC-8
ADR01 10 0.05 9 1 20 TSOT-23, SC70
ADR02 5 0.06 3 1 10 SOIC-8
ADR02 5 0.06 9 1 10 TSOT-23, SC70
ADR03 2.5 0.10 3 1 6 SOIC-8
ADR03 2.5 0.10 9 1 6 TSOT-23, SC70
ADR06 3 0.10 3 1 10 SOIC-8
ADR06 3 0.10 9 1 10 TSOT-23, SC70
ADR431 2.5 0.04 3 0.8 3.5 SOIC-8
ADR435 5 0.04 3 0.8 8 SOIC-8
ADR391 2.5 0.16 9 0.12 5 TSOT-23
ADR395 5 0.10 9 0.12 8 TSOT-23
Table 8. Suitable ADI Precision Op Amps
0.1 Hz to 10 Hz
Part No. Supply Voltage (V) VOS (Max) (μV) IB (Max) (nA)
OP97 ±2 to ±20 25 0.1 0.5 600 SOIC-8
OP1177 ±2.5 to ±15 60 2 0.4 500 MSOP, SOIC-8
AD8551 2.7 to 5 5 0.05 1 975 MSOP, SOIC-8
AD8603 1.8 to 6 50 0.001 2.3 50 TSOT
AD8628 2.7 to 6 5 0.1 0.5 850 TSOT, SOIC-8
Noise (μV p-p)
Supply Current (μA) Package
Table 9. Suitable ADI High Speed Op Amps
Part No. Supply Voltage (V) BW @ ACL (MHz) Slew Rate (V/μs) VOS (Max) (μV) IB (Max) (nA) Package
AD8065 5 to 24 145 180 1500 0.006 SOIC-8, SOT-23, MSOP
AD8021 ±2.5 to ±12 490 120 1000 10500 SOIC-8, MSOP
AD8038 3 to 12 350 425 3000 750 SOIC-8, SC70-5
AD9631 ±3 to ±6 320 1300 10000 7000 SOIC-8
Rev. F | Page 20 of 28
Page 21
Data Sheet AD5450/AD5451/AD5452/AD5453
SERIAL INTERFACE
The AD5450/AD5451/AD5452/AD5453 have an easy-to-use
3-wire interface that is compatible with SPI, QSPI, MICROWIRE,
and most DSP interface standards. Data is written to the device in
16-bit words. This 16-bit word consists of two control bits and 8,
10, 12, or 14 data bits, as shown in Figure 50, Figure 51, Figure 52,
and Figure 53. The AD5453 uses all 14 bits of DAC data, the
AD5452 uses 12 bits and ignores the two LSBs, the AD5451 uses
10 bits and ignores the four LSBs, and the AD5450 uses 8 bits
and ignores the six LSBs.
DAC Control Bits C1, C0
Control Bits C1 and C0 allow the user to load and update the
new DAC code and to change the active clock edge. By default,
the shift register clocks data upon the falling edge; this can be
changed via the control bits. If changed, the DAC core is
inoperative until the next data frame, and a power recycle is
required to return it to active on the falling edge. A power cycle
resets the core to default condition. On-chip power-on reset
circuitry ensures that the device powers on with zero scale
loaded to the DAC register and I
Table 10. DAC Control Bits
C1 C0 Function Implemented
0 0 Load and update (power-on default)
0 1 Reserved
1 0 Reserved
1 1 Clock data to shift register upon rising edge
Function
SYNC
is an edge-triggered input that acts as a frame-
SYNC
synchronization signal and chip enable. Data can only be
transferred to the device while
data transfer,
minimum
SYNC
should be taken low, observing the
SYNC
falling to SCLK falling edge setup time, t4. To
minimize the power consumption of the device, the interface
powers up fully only when the device is being written to, that is,
upon the falling edge of
SYNC
buffers are powered down upon the rising edge of
After the falling edge of the 16
to transfer data from the input shift register to the DAC register.
line.
OUT
is low. To start the serial
SYNC
. The SCLK and SDIN input
.
SYNC
th
SCLK pulse, bring
SYNC
high
The serial interface to the AD5450 uses a 16-bit shift register.
Take care to avoid incomplete data sequences as these will be
latched to update the DAC output.
For example,
• Loading 0x3FFF (a complete data sequence) will update
the output to 10 V (full scale).
• User intends to write 0x3200 but after 12 active edges
SYNC
goes high (incomplete write sequence). This will
actually update the following code: 0xF200.
• The user expects an output of 5.6 V. However, if
SYNC
goes high after 12 valid clock edges then an incomplete
data sequence of 12 bits is loaded. To complete the shift
register the 4 LSBs from the previous sequence are taken
and used as the 4 MSBs missing. The addition of these
4 bits will put the part in rising edge mode and the output
will show no change. , , and
Figure 54 Figure 55 Tabl e 11
show the data frames for this example.
Also note that if more then 16-bits are loaded to the part before
SYNC
goes high the last 16-bits will be latched.
DB15 (MSB)
C1 C0
CONTROL BITS
DB7 DB6 DB5 DB4 DB3 DB2 DB0DB1
DATA BITS
DB0 (LSB)
XXXXXX
Figure 50. AD5450 8-Bit Input Shift Register Contents
DB15 (MSB)
DB5 DB4 DB3 DB2 DB0DB1C1 C0 DB7 DB6DB8DB9
DATA BITS
CONTROL BITS
Figure 51. AD5451 10-Bit Input Shift Register Contents
DB0 (LSB)
XXXX
DB15 (MSB)
CONTROL BITS
DB11 DB10
DB9
DB8
DB7 DB6 DB5 DB4
DATA BITS
DB3 DB2
DB1C1 C0
Figure 52. AD5452 12-Bit Input Shift Register Contents
DB0
DB0 (LSB)
X
X
DB15 (MSB)
C1 C0
CONTROL BITS
DB13 DB12
DB11
DB10
DB9 DB8 DB7 DB6
DATA BITS
DB5 DB4
DB3
Figure 53. AD5453 14-Bit Input Shift Register Contents
DB2
DB0 (LSB)
DB1
DB0
04587-005
04587-006
04587-007
04587-008
1
1
11
CONTROL BI TS
111 1
DATA BITS
Figure 54. AD5453 First Write, Complete Data Sequence (0x3FFF)
11
100
1
1
1
04587-054
Rev. F | Page 21 of 28
Page 22
AD5450/AD5451/AD5452/AD5453 Data Sheet
11
CONTROL BI TS
0
100 0
0
DATA BITS
Figure 55. AD5453 Second Write, Incomplete Data Sequence (0x3200) and Subsequent Additional Bits (0xF200)
00
0000
0
0
CONTROL BI TS
11
0
0
100 0
DATA BITS
ACTUAL DATA FRAMEINTENDED DATA FRAME
00
0011
0
0
04587-055
Table 11.
Writing
Sequence
Data Write in
Shift Register Action Expected
Data Transfer to
the Device Action Carried Out
1 0x3FFF Load and update 0x3FFF 0x3FFF Load and update 0x3FFF
2 0x3200 Load and update 0x3200 0xF200 Clock data to shift register upon rising edge (0xF200)
MICROPROCESSOR INTERFACING
Microprocessor interfacing to a AD5450/AD5451/AD5452
/AD5453 DAC is through a serial bus that uses standard protocol
and is compatible with microcontrollers and DSP processors.
The communication channel is a 3-wire interface consisting of
ADSP-2101/
ADSP-2103/
ADSP-2191*
TFS
DT
SCLK
AD5450/AD5451/
AD5452/AD5453*
SYNC
SDIN
SCLK
a clock signal, a data signal, and a synchronization signal. The
AD5450/AD5451/AD5452/AD5453 require a 16-bit word, with
the default being data valid upon the falling edge of SCLK, but
this is changeable using the control bits in the data-word.
ADSP-21xx-to-AD5450/AD5451/AD5452/AD5453 Interface
The ADSP-21xx family of DSPs is easily interfaced to a AD5450/
AD5451/AD5452/AD5453 DAC without the need for extra glue
logic. Figure 56 is an example of an SPI interface between the DAC
and the ADSP-2191M. SCK of the DSP drives the serial data line,
SDIN.
SPIxSEL
is driven from one of the port lines, in this case
SYNC
.
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 57. ADSP-2101/ADSP-2103/ADSP-2191
SPORT-to-AD5450/AD5451/AD5452/AD5453 Interface
Communication between two devices at a given clock speed is
possible when the following specifications are compatible:
frame
delay and frame
SYNC
setup-and-hold, data delay
SYNC
and data setup-and-hold, and SCLK width. The DAC interface
expects a t
(
4
falling edge to SCLK falling edge setup time)
SYNC
of 13 ns minimum. See the ADSP-21xx User Manual for infor-
mation on clock and frame
frequencies for the SPORT
SYNC
register. shows the setup for the SPORT control register. Tabl e 12
04587-051
ADSP-2191*
SPIxSEL
MOSI
SCK
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 56. ADSP-2191 SPI-to-AD5450/AD5451/AD5452/AD5453 Interface
AD5450/AD5451/
AD5452/AD5453*
SYNC
SDIN
SCLK
A serial interface between the DAC and DSP SPORT is shown
in Figure 57. In this example, SPORT0 is used to transfer data to
the DAC shift register. Transmission is initiated by writing a
word to the Tx register after the SPORT has been enabled. In a
write sequence, data is clocked out upon each rising edge of the
DSP’s serial clock and clocked into the DAC input shift register
upon the falling edge of its SCLK. The update of the DAC
output takes place upon the rising edge of the
SYNC
signal.
Rev. F | Page 22 of 28
Table 12. SPORT Control Register Setup
Name Setting Description
TFSW 1 Alternate framing
INVTFS 1 Active low frame signal
DTYPE 00 Right justify data
ISCLK 1 Internal serial clock
04587-100
TFSR 1 Frame every word
ITFS 1 Internal framing signal
SLEN 1111 16-bit data-word
ADSP-BF5xx-to-AD5450/AD5451/AD5452/AD5453 Interface
The ADSP-BF5xx family of processors has an SPI-compatible
port that enables the processor to communicate with SPIcompatible devices. A serial interface between the BlackFin
®
processor and the AD5450/AD5451/AD5452/AD5453 DAC is
shown in Figure 58. In this configuration, data is transferred
through the MOSI (master output, slave input) pin.
driven by the
SPIxSEL
pin, which is a reconfigured
SYNC
is
programmable flag pin.
Page 23
Data Sheet AD5450/AD5451/AD5452/AD5453
ADSP-BF5xx*
SPIxSEL
MOSI
SCK
AD5450/AD5451/
AD5452/AD5453*
SYNC
SDIN
SCLK
8051*
TxD
RxD
P1.1
AD5450/AD5451/
AD5452/AD5453*
SCLK
SDIN
SYNC
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 58. ADSP-BF5xx-to-AD5450/AD5451/AD5452/AD5453 Interface
The ADSP-BF5xx processor incorporates channel synchronous
serial ports (SPORT). A serial interface between the DAC and
the DSP SPORT is shown in Figure 59. When the SPORT is
enabled, initiate transmission by writing a word to the Tx register.
The data is clocked out upon each rising edge of the DSP’s serial
clock and clocked into the DAC’s input shift register upon the
falling edge its SCLK. The DAC output is updated by using the
transmit frame synchronization (TFS) line to provide a
SYNC
signal.
ADSP-BF5xx*
TFS
DT
SCLK
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 59. ADSP-BF5xx SPORT-to-AD5450/AD5451/AD5452/AD5453 Interface
AD5450/AD5451/
AD5452/AD5453*
SYNC
SDIN
SCLK
80C51/80L51-to-AD5450/AD5451/AD5452/AD5453 Interface
A serial interface between the DAC and the 80C51/80L51 is
shown in Figure 60. TxD of the 80C51/80L51 drives SCLK of
the DAC serial interface, and RxD drives the serial data line,
SDIN. P1.1 is a bit-programmable pin on the serial port and is used
to drive
. As data is transmitted to the switch, P1.1 is taken
SYNC
low. The 80C51/80L51 transmit data only in 8-bit bytes; therefore, only eight falling clock edges occur in the transmit cycle.
To load data correctly to the DAC, P1.1 is left low after the first
eight bits are transmitted, and a second write cycle is initiated to
transmit the second byte of data. Data on RxD is clocked out of
the microcontroller upon the rising edge of TxD and is valid upon
the falling edge. As a result, no glue logic is required between the
DAC and microcontroller interface. P1.1 is taken high following
the completion of this cycle. The 80C51/80L51 provide the LSB
of its SBUF register as the first bit in the data stream. The DAC
input register acquires its data with the MSB as the first bit received.
The transmit routine should take this into account.
*ADDITIONAL PINS OMITTED FOR CLARITY
04587-102
Figure 60. 80C51/80L51-to-AD5450/AD5451/AD5452/AD5453 Interface
04587-104
MC68HC11-to-AD5450/AD5451/AD5452/AD5453 Interface
Figure 61 is an example of a serial interface between the DAC
and the MC68HC11 microcontroller. The serial peripheral
interface (SPI) on the MC68HC11 is configured for master
mode (MSTR) = 1, clock polarity bit (CPOL) = 0, and clock
phase bit (CPHA) = 1. The SPI is configured by writing to the
SPI control register (SPCR); see the 68HC11 User Manual. SCK
of the 68HC11 drives the SCLK of the DAC interface; the MOSI
output drives the serial data line (SDIN) of the DAC.
The
is being transmitted to the / / / ,
the
signal is derived from a port line (PC7). When data
SYNC
AD5450 AD5451 AD5452 AD5453
line is taken low (PC7). Data appearing on the MOSI
SYNC
output is valid upon the falling edge of SCK. Serial data from the
68HC11 is transmitted in 8-bit bytes with only eight falling clock
edges occurring in the transmit cycle. Data is transmitted MSB
04587-103
first. To load data to the DAC, PC7 is left low after the first eight
bits are transferred, and a second serial write operation is performed
to the DAC. PC7 is taken high at the end of this procedure.
MC68HC11*
PC7
SCK
MOSI
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 61. MC68HC11-to-AD5450/AD5451/AD5452/AD5453 Interface
AD5450/AD5451/
AD5452/AD5453*
SYNC
SCLK
SDIN
04587-105
If the user wants to verify the data previously written to the
input shift register, the SDO line can be connected to MISO of
the MC68HC11. In this configuration with
SYNC
low, the shift
register clocks data out upon the rising edges of SCLK.
Rev. F | Page 23 of 28
Page 24
AD5450/AD5451/AD5452/AD5453 Data Sheet
MICROWIRE-to-AD5450/AD5451/AD5452/AD5453 Interface
Figure 62 shows an interface between the DAC and any
MICROWIRE-compatible device. Serial data is shifted out
upon the falling edge of the serial clock, SK, and is clocked into
the DAC input shift register upon the rising edge of SK, which
corresponds to the falling edge of the DAC’s SCLK.
MICROWIRE*
SK
SO
CS
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 62. MICROWIRE-to-AD5450/AD5451/AD5452/AD5453 Interface
AD5450/AD5451/
AD5452/AD5453*
SCLK
SDIN
SYNC
PIC16C6x/PIC16C7x-toAD5450/AD5451/AD5452/AD5453 Interface
The PIC16C6x/PIC16C7x synchronous serial port (SSP) is
configured as an SPI master with the clock polarity bit (CKP) = 0.
This is done by writing to the synchronous serial port control
register (SSPCON); see the PIC16/PIC17 Microcontroller
User Manual.
In this example, I/O Port RA1 is used to provide a
SYNC
signal
and enable the serial port of the DAC. This microcontroller
transfers only eight bits of data during each serial transfer
operation; therefore, two consecutive write operations are
required. shows the connection diagram. Figure 63
PIC16C6x/PIC16C7x*
SCK/RC3
SDI/RC4
RA1
AD5450/AD5451/
AD5452/AD5453*
SCLK
SDIN
SYNC
04587-106
PCB LAYOUT AND POWER SUPPLY DECOUPLING
In any circuit where accuracy is important, careful consideration
of the power supply and ground return layout helps to ensure
the rated performance. The printed circuit board on which a
AD5450/AD5451/AD5452/AD5453 DAC is mounted should be
designed so that the analog and digital sections are separated
and confined to certain areas of the board. If the DAC is in a
system where multiple devices require an AGND-to-DGND
connection, the connection should be made at one point only.
The star ground point should be established as close as possible
to the device.
These DACs should have ample supply bypassing of 10 μF in
parallel with 0.1 μF on the supply located as close to the package
as possible, ideally right up against the device. The 0.1 μF
capacitor should have low effective series resistance (ESR) and
low effective series inductance (ESI), like the common ceramic
types that provide a low impedance path to ground at high
frequencies, to handle transient currents due to internal logic
switching. Low ESR 1 μF to 10 μF tantalum or electrolytic
capacitors should also be applied at the supplies to minimize
transient disturbance and filter out low frequency ripple.
Components, such as clocks, that produce fast switching signals
should be shielded with a digital ground to avoid radiating noise
to other parts of the board, and they should never be run near
the reference inputs.
Avoid crossover of digital and analog signals. Traces on opposite
sides of the board should run at right angles to each other. This
reduces the effects of feedthrough through the board. A microstrip
technique is the best solution, but its use is not always possible
with a double-sided board. In this technique, the component
side of the board is dedicated to the ground plane and signal
traces are placed on the solder side.
*ADDITIONAL PI NS OMITTED FOR CLARITY
Figure 63. PIC16C6x/7x-to-AD5450/AD5451/AD5452/AD5453 Interface
04587-107
It is good practice to employ compact, minimum lead length
PCB layout design. Leads to the input should be as short as
possible to minimize IR drops and stray inductance.
The PCB metal traces between V
matched to minimize gain error. To optimize high frequency
performance, the I-to-V amplifier should be located as close to
the device as possible.
Rev. F | Page 24 of 28
and RFB should also be
REF
Page 25
Data Sheet AD5450/AD5451/AD5452/AD5453
Table 13. Overview of AD54xx and AD55xx Devices
Part No. Resolution No. DACs INL (LSB) Interface Package1 Features
AD5424 8 1 ±0.25 Parallel RU-16, CP-20
10 MHz BW, 17 ns CS
AD5426 8 1 ±0.25 Serial RM-10 10 MHz BW, 50 MHz serial
AD5428 8 2 ±0.25 Parallel RU-20
10 MHz BW, 17 ns CS
AD5429 8 2 ±0.25 Serial RU-10 10 MHz BW, 50 MHz serial
AD5450 8 1 ±0.25 Serial UJ-8 12 MHZ BW, 50 MHz serial interface
AD5432 10 1 ±0.5 Serial RM-10 10 MHz BW, 50 MHz serial
AD5433 10 1 ±0.5 Parallel RU-20, CP-20
10 MHz BW, 17 ns CS
AD5439 10 2 ±0.5 Serial RU-16 10 MHz BW, 50 MHz serial
AD5440 10 2 ±0.5 Parallel RU-24
10 MHz BW, 17 ns CS
AD5451 10 1 ±0.25 Serial UJ-8 12 MHz BW, 50 MHz serial interface
AD5443 12 1 ±1 Serial RM-10 10 MHz BW, 50 MHz serial
AD5444 12 1 ±0.5 Serial RM-10 12 MHz BW, 50 MHz serial
AD5415 12 2 ±1 Serial RU-24 10 MHz BW, 50 MHz serial
AD5405 12 2 ±1 Parallel CP-40
AD5445 12 2 ±1 Parallel RU-20, CP-20
AD5447 12 2 ±1 Parallel RU-24
10 MHz BW, 17 ns CS
10 MHz BW, 17 ns CS
10 MHz BW, 17 ns CS
AD5449 12 2 ±1 Serial RU-16 10 MHz BW, 50 MHz serial
AD5452 12 1 ±0.5 Serial UJ-8, RM-8 12 MHz BW, 50 MHz serial interface
AD5446 14 1 ±1 Serial RM-10 12 MHz BW, 50 MHz serial
AD5453 14 1 ±2 Serial UJ-8, RM-8 12 MHz BW, 50 MHz serial
AD5553 14 1 ±1 Serial RM-8 4 MHz BW, 50 MHz serial clock
AD5556 14 1 ±1 Parallel RU-28
4 MHz BW, 20 ns WR
AD5555 14 2 ±1 Serial RM-8 4 MHz BW, 50 MHz serial clock
AD5557 14 2 ±1 Parallel RU-38
4 MHz BW, 20 ns WR
AD5543 16 1 ±2 Serial RM-8 4 MHz BW, 50 MHz serial clock
AD5546 16 1 ±2 Parallel RU-28
4 MHz BW, 20 n WR
AD5545 16 2 ±2 Serial RU-16 4 MHz BW, 50 MHz serial clock
AD5547 16 2 ±2 Parallel RU-38
1
RU = TSSOP, CP = LFCSP, RM = MSOP, UJ = TSOT.
4 MHz BW, 20 ns WR
pulse width
pulse width
pulse width
pulse width
pulse width
pulse width
pulse width
pulse width
pulse width
pulse width
pulse width
Rev. F | Page 25 of 28
Page 26
AD5450/AD5451/AD5452/AD5453 Data Sheet
OUTLINE DIMENSIONS
2.90 BSC
2
1.95
BSC
56
0.65 BSC
2.80 BSC
*
1.00 MAX
SEATING
PLANE
0.20
0.08
8°
4°
0°
0.60
0.45
0.30
1.60 BSC
PIN 1
INDICATOR
*
0.90
0.87
0.84
0.10 MAX
847
13
0.38
0.22
*
COMPLIANT TO JEDEC STANDARDS MO-193-BA WITH
THE EXCEPTION OF PACKAGE HEIGHT AND THICKNESS.
Figure 64. 8-Lead Thin Small Outline Transistor Package [TSOT]
(UJ-8)
Dimensions shown in millimeters
3.20
3.00
2.80
8
5
4
0.40
0.25
5.15
4.90
4.65
1.10 MAX
(RM-8)
15° MAX
6°
0°
0.23
0.09
0.80
0.55
0.40
10-07-2009-B
3.20
3.00
2.80
PIN 1
IDENTIFIER
0.95
0.85
0.75
0.15
0.05
COPLANARITY
0.10
1
0.65 BSC
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 65. 8-Lead Mini Small Outline Package [MSOP]
Dimensions shown in millimeters
Rev. F | Page 26 of 28
Page 27
Data Sheet AD5450/AD5451/AD5452/AD5453
3.00
BSC SQ
PIN 1 INDEX
AREA
TOP VIEW
0.80
0.75
0.70
SEATING
PLANE
0.80 MAX
0.55 NOM
0.20 REF
0.35
0.30
0.25
0.50
0.40
0.30
0.05 MAX
0.02 NOM
0.65 BSC
5
EXPOSED
PAD
(BOTTOM VIEW)
4
2.48
2.38
2.23
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
8
1
P
N
I
N
I
D
R
(
1.74
1.64
1.49
1
I
.
0
R
O
C
A
T
)
2
4-16-2008-B
Figure 66. 8-Lead Lead Frame Chip Scale Package [LFCSP_WD]
3 mm × 3 mm Body, Very Very Thin, Dual Lead
(CP-8-3)
Dimensions shown in millimeters
ORDERING GUIDE
1, 2
Model
Resolution INL Temperature Range Package Description Package Option Branding
AD5450YUJZ-REEL 8 ±0.25 −40°C to +125°C 8-Lead TSOT UJ-8 D6Y
AD5450YUJZ-REEL7 8 ±0.25 −40°C to +125°C 8-Lead TSOT UJ-8 D6Y
AD5451YUJZ-REEL 10 ±0.25 −40°C to +125°C 8-Lead TSOT UJ-8 D6Z
AD5451YUJZ-REEL7 10 ±0.25 −40°C to +125°C 8-Lead TSOT UJ-8 D6Z
AD5452YUJZ-REEL 12 ±0.5 −40°C to +125°C 8-Lead TSOT UJ-8 D70
AD5452YUJZ-REEL7 12 ±0.5 −40°C to +125°C 8-Lead TSOT UJ-8 D70
AD5452YRM 12 ±0.5 −40°C to +125°C 8-Lead MSOP RM-8 D1Z
AD5452YRM-REEL 12 ±0.5 −40°C to +125°C 8-Lead MSOP RM-8 D1Z
AD5452YRMZ 12 ±0.5 −40°C to +125°C 8-Lead MSOP RM-8 D70
AD5452YRMZ-REEL 12 ±0.5 −40°C to +125°C 8-Lead MSOP RM-8 D70
AD5452YRMZ-REEL7 12 ±0.5 −40°C to +125°C 8-Lead MSOP RM-8 D70
AD5453WBCPZ-RL 14 ±2 −40°C to +125°C 8-Lead LFCSP_WD CP-8-3 DG3
AD5453YUJZ-REEL 14 ±2 −40°C to +125°C 8-Lead TSOT UJ-8 DAH
AD5453YUJZ-REEL7 14 ±2 −40°C to +125°C 8-Lead TSOT UJ-8 DAH
AD5453YRM 14 ±2 −40°C to +125°C 8-Lead MSOP RM-8 D26
AD5453YRM-REEL 14 ±2 −40°C to +125°C 8-Lead MSOP RM-8 D26
AD5453YRM-REEL7 14 ±2 −40°C to +125°C 8-Lead MSOP RM-8 D26
AD5453YRMZ 14 ±2 −40°C to +125°C 8-Lead MSOP RM-8 DAH
AD5453YRMZ-REEL 14 ±2 −40°C to +125°C 8-Lead MSOP RM-8 DAH
AD5453YRMZ-REEL7 14 ±2 −40°C to +125°C 8-Lead MSOP RM-8 DAH
EVAL-AD5453EBZ Evaluation Board
EVAL-AD5453SDZ Evaluation Board
1
Z = RoHS Compliant Part.
2
W = Qualified for Automotive Applications.
AUTOMOTIVE PRODUCTS
The AD5453WBCPZ-RL model is available with controlled manufacturing to support the quality and reliability requirements of
automotive applications. Note that this automotive model may have specifications that differ from the commercial models; therefore,
designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown are available for
use in automotive applications. Contact your local Analog Devices account representative for specific product ordering information and
to obtain the specific Automotive Reliability reports for these models.
Rev. F | Page 27 of 28
Page 28
AD5450/AD5451/AD5452/AD5453 Data Sheet
NOTES
©2005–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04587-0-4/12(F)
Rev. F | Page 28 of 28
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