Datasheet AD5444 Datasheet (Analog Devices)

12-Bit, High Bandwidth

FEATURES

±0.5 LSB INL

2.5 V to 5.5 V supply operation ±10 V reference input Extended temperature range: −40°C to +125°C 10-lead MSOP package Pin-compatible 12-bit current output DAC 50 MHz serial interface Guaranteed monotonic 4-quadrant multiplication Power-on reset with brownout detection <0.4 µA typical current consumption

APPLICATIONS

Portable battery-powered applications Waveform generators Analog processing Instrumentation applications Programmable amplifiers and attenuators Digitally controlled calibration Programmable filters and oscillators Composite video Ultrasound Gain, offset, and voltage trimming Automotive radar

Multiplying DAC with Serial Interface

GENERAL DESCRIPTION

The AD54441 is a CMOS 12-bit, current output digital-toanalog converter. The device operates from a single 2.5 V to

5.5 V power supply, making it suited to battery-powered applications as well as many other applications.

The DAC uses a double-buffered 3-wire serial interface that is compat ible with SPI®, QSPI™, MICROWI RE™, and most DSP interface standards. On power-up, the internal shift register and latches are filled with 0s, and the DAC output is at zero scale. As a result of manufacture on a CMOS submicron process, the part offers excellent 4-quadrant multiplication characteristics.

The applied external reference input voltage (V the full-scale output current. The part can handle ±10 V inputs on the reference despite operating from a single-supply power supply of 2.5 V to 5.5 V. An integrated feedback resistor (R provides temperature tracking and full-scale voltage output when combined with an external current-to-voltage precision amplifier. The AD5444 DAC is available in a small 10-lead MSOP package that is pin compatible with the AD5425/ AD5426/AD5432/AD5443 family of DACs.

US Patent Number 5,689,257.

FUNCTIONAL BLOCK DIAGRAM

AD5444

REF

R-2R DAC

12-BIT

OUT

AD5444

) determines

REF

)

POWER-ON

RESET

SYNC SCLK

SDIN

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

INPUT SHIFT REGISTER

DAC REGISTER

INPUT LATCH

CONTROL LOGIC AND

GND

Figure 1.

SDO

04588-001

www.analog.com

AD5444

TABLE OF CONTENTS

Specifications..................................................................................... 3

Divider or Programmable Gain Element................................ 16

Timing Characteristics..................................................................... 5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Te r m in o l o g y ...................................................................................... 8

Typical Performance Characteristics ............................................. 9

General Description....................................................................... 14

DAC Section................................................................................ 14

Circuit Operation ....................................................................... 14

Single-Supply Applications........................................................ 16

Adding Gain................................................................................ 16

REVISION HISTORY

10/04—Revision 0: Initial Version

Amplifier Selection .................................................................... 17

Reference Selection .................................................................... 17

Serial Interface................................................................................ 19

Microprocessor Interfacing....................................................... 20

PCB Layout and Power Supply Decoupling................................ 22

Evaluation Board for the DAC ................................................. 22

Power Supplies for the Evaluation Board................................ 22

Overview of AD54xx Devices....................................................... 26

Outline Dimensions....................................................................... 27

Ordering Guide .......................................................................... 27

Rev. 0 | Page 2 of 28

AD5444

SPECIFICATIONS

Temperature range for Y Version: −40°C to +125°C.

= 2.5 V to 5.5 V, V

The dc performance was measured with OP177; the ac performance was measured with AD8038, unless otherwise noted.

Table 1.

Parameter Min Typ Max Unit Conditions

STATIC PERFORMANCE

Resolution 12 Bits Relative Accuracy ±0.5 LSB Differential Nonlinearity ±1 LSB Guaranteed monotonic Total Unadjusted Error (TUE) ±1 LSB

Gain Error ±0.5 LSB Gain Error Temp Coefficient1 ±5 ppm FSR/°C Output Leakage Current ±1 nA Data = 0x0000, TA = 25°C, I

±10 nA Data = 0x0000, TA = −40°C to +125°C, I REFERENCE INPUT1

Reference Input Range ±10 V V

Input Resistance 7 9 11 kΩ Input resistance TC = −50 ppm/°C

REF

RFB Feedback Resistance 7 9 11 kΩ Input resistance TC = −50 ppm/°C Input Capacitance

Zero-Scale Code 18 22 pF

Full-Scale Code 18 22 pF

DIGITAL INPUTS/OUTPUTS1

Input High Voltage, VIH 2.0 V VDD = 3.6 V to 5 V

1.7 V VDD = 2.5 V to 3.6 V Input Low Voltage, VIL 0.8 V VDD = 2.7 V to 5.5 V

0.7 V VDD = 2.5 V to 2.7 V Output High Voltage, VOH VDD − 1 V VDD = 4.5 V to 5 V, I V Output Low Voltage, VOL 0.4 V VDD = 4.5 V to 5 V, I

0.4 V VDD = 2.5 V to 3.6 V, I Input Leakage Current, IIL ±1 nA TA = 25°C ±10 nA TA = −40°C to +125°C Input Capacitance 10 pF

DYNAMIC PERFORMANCE1

Reference Multiplying BW 10 MHz V Output Voltage Settling Time

Measured to ±1 mV of FS 100 110 ns

Measured to ±4 mV of FS 24 40 ns

Measured to ±16 mV of FS 16 33 ns Digital Delay 20 40 ns Interface delay time 10% to 90% Settling Time 10 30 ns Rise and fall time, V Digital-to-Analog Glitch Impulse 2 nV-s 1 LSB change around major carry, V Output Capacitance

1 13 pF DAC latches loaded with all 0s

OUT

28 pF DAC latches loaded with all 1s

2 18 pF DAC latches loaded with all 0s

OUT

5 pF DAC latches loaded with all 1s

Digital Feedthrough 0.5 nV-s

= 10 V, I

REF

2 = 0 V. All specifications T

OUT

− 0.5 V VDD = 2.5 V to 3.6 V, I

MIN

to T

, unless otherwise noted.

MAX

= ±3.5 V, DAC loaded all 1s

REF

= 10 V, R

REF

loaded with 0s and 1s

Feedthrough to DAC output with alternate loading of all 0s and all 1s

OUT

= 200 µA

SOURCE

= 200 µA

SOURCE

= 200 µA

SINK

= 200 µA

SINK

= 100 Ω, DAC latch alternately

LOAD

= 10 V, R

REF

= 100 Ω,

LOAD

REF

= 0 V

CS high and

OUT

Rev. 0 | Page 3 of 28

AD5444

Parameter Min Typ Max Unit Conditions

Analog THD 83 dB V Digital THD Clock = 1 MHz, V 50 kHz f 20 kHz f

OUT

71 dB 50 kHz f

77 dB 20 kHz f Output Noise Spectral Density 25 nV/√Hz @ 1 kHz SFDR Performance (Wideband) Clock = 10 MHz, V

50 kHz f 20 kHz f

OUT

78 dB

74 dB SFDR Performance (Narrow-Band) Clock = 1 MHz, V

50 kHz f 20 kHz f

OUT

87 dB

85 dB Intermodulation Distortion 79 dB f1 = 20 kHz, f2 = 25 kHz, Clock = 1 MHz, V

POWER REQUIREMENTS

Power Supply Range 2.5 5.5 V IDD 0.4 10 µA TA = −40°C to +125°C, logic inputs = 0 V or V

0.6 µA TA = 25°C, logic inputs = 0 V or V Power Supply Sensitivity1 0.001 %/% ∆VDD = ±5%

Guaranteed by design and characterization, not subject to production test.

= 3.5 V p-p, all 1s loaded, f = 1 kHz

REF

= 3.5 V

REF

OUT

= 3.5 V

REF

= 3.5 V

REF

= 3.5 V

REF

Rev. 0 | Page 4 of 28

AD5444

TIMING CHARACTERISTICS

Temperature range for Y Version: −40°C to +125°C. See Figure 2. Guaranteed by design and characterization, not subject to production test. All input signals are specified with tr = tf = 1 ns (10% to 90% of V

= 5 V, I

REF

All specifications T

2 = 0 V.

OUT

MIN

to T

, unless other wise noted.

MAX

Table 2.

Parameter VDD = 4.5 V to 5.5 V VDD = 2.5 V to 5.5 V Unit Conditions / Comments

50 50 MHz max Maximum Clock Frequency

SCLK

t1 20 20 ns min SCLK Cycle Time t2 8 8 ns min SCLK High Time t3 8 8 ns min SCLK Low Time t4 8 8 ns min

t5 5 5 ns min Data Setup Time t6 4.5 4.5 ns min Data Hold Time t7 5 5 ns min

t8 30 30 ns min t9 23 30 ns min SCLK Active Edge to SDO Valid

SCLK

Figure 2. Standalone Timing Diagram

SYNC

SDIN

DB15 DB0

) and timed from a voltage level of (VIL + VIH)/2.

SYNC Falling Edge to SCLK Active Edge Setup Time

SYNC Rising Edge to SCLK Active Edge Minimum

SYNC High Time

04588-002

SCLK

SYNC

SDIN

SDO

ALTERNATIVELY, DATA CAN BE CLOCKED INTO INPUT SHIFT REGISTER ON RISING EDGE OF SCLK AS DETERMINED BY CONTROL BITS. IN THIS CASE, DATA WOULD BE CLOCKED OUT OF SDO ON FALLING EDGE OF SCLK. TIMING AS ABOVE, WITH SCLK INVERTED.

DB15 (N) DB0 (N)

DB15 (N+1)

DB15 (N)

Figure 3. Daisy-Chain Timing Diagram

Rev. 0 | Page 5 of 28



DB0 (N+1)

DB0 (N)

04588-003

AD5444

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted. Transient currents of up to 100 mA do not cause SCR latch-up.

Table 3.

Parameter Rating

VDD to GND V

, RFB to GND

REF

1, I

OUT

Logic Inputs and Output

2 to GND

OUT

Input Current to Any Pin except Supplies ±10 mA Operating Temperature Range

Extended (Y Version) −40°C to +125°C

Storage Temperature Range Junction Temperature 150°C 10-lead MSOP θJA Thermal Impedance Lead Temperature, Soldering (10 s) 300°C

−0.3 V to +7 V

−12 V to +12 V

−0.3 V to +7 V

−0.3 V to VDD + 0.3 V

−65°C to +150°C

206°C/W

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Only one absolute maximum rating may be applied at any one time.

IR Reflow, Peak Temperature (<20 s) 235°C

Overvoltages at SCLK,

, and DIN are clamped by internal diodes.

SYNC

OUTPUT

Figure 4. Load Circuit for SDO Timing Specifications

20pF

200µA

OH (MIN)

OL (MAX)

04588-004

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. 0 | Page 6 of 28

AD5444

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

OUT

GND

SCLK

SDIN

(Not to Scale)

AD5444

TOP VIEW

REF

SDO

SYNC

04588-005

Figure 5. Pin Configuration MSOP (RM-10)

Table 4. Pin Function Descriptions

Pin No. Mnemonic Function

1 I 2 I

1 DAC Current Output.

OUT

2 DAC Analog Ground. This pin should normally be tied to the analog ground of the system.

OUT

3 GND Ground Pin. 4 SCLK

Serial Clock Input. By default, data is clocked into the input shift register on the falling edge of the serial clock input. Alternatively, by means of the serial control bits, the device can be configured such that data is clocked into the shift register on the rising edge of SCLK.

5 SDIN

Serial Data Input. Data is clocked into the 16-bit input register on the active edge of the serial clock input. By default on power-up, data is clocked into the shift register on the falling edge of SCLK. The control bits allow the user to change the active edge to the rising edge.

SYNC Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC is taken low, data

is loaded to the shift register on the active edge of the following clocks. The output updates on the rising edge of SYNC.

7 SDO

Serial Data Output. This pin allows a number of parts to be daisy-chained. By default, data is clocked into the shift register on the falling edge and out via SDO on the rising edge of SCLK. Data is always clocked out on the

alternate edge to loading data to the shift register. 8 VDD Positive Power Supply Input. This part can be operated from a supply of 2.5 V to 5.5 V. 9 V

DAC Reference Voltage Input.

REF

10 RFB DAC Feedback Resistor. Establishes voltage output for the DAC by connecting to an external amplifier output.

Rev. 0 | Page 7 of 28

AD5444

TERMINOLOGY

Relative Accuracy

Relative accuracy or endpoint nonlinearity is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after adjusting for zero scale and full scale and is normally expressed in LSBs or as a percentage of full-scale reading.

Digital Feedthrough

When the device is not selected, high frequency logic activity on the device’s digital inputs can be capacitively coupled through the device to show up as noise on the I

pins and, subse-

OUT

quently, into the following circuitry. This noise is digital feedthrough.

Differential Nonlinearity

Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of −1 LSB maximum over the operating temperature range ensures monotonicity.

Gain Error

Gain error or full-scale error is a measure of the output error between an ideal DAC and the actual device output. For this DAC, ideal maximum output is V

− 1 LSB. Gain error of the

REF

DAC is adjustable to zero with external resistance.

Output Leakage Current

Output leakage current is current that flows in the DAC ladder switches when these are turned off. For the I

1 terminal, it can

OUT

be measured by loading all 0s to the DAC and measuring the

1 current. Minimum current flows in the I

OUT

2 line when

OUT

the DAC is loaded with all 1s.

Output Capacitance

Capacitance from I

OUT

1 or I

2 to AGND.

OUT

Output Current Settling Time

The amount of time it takes for the output to settle to a specified level for a full-scale input change. For this device, it is specified with a 100 Ω resistor to ground. The settling time

SYNC

specification includes the digital delay from the

rising

edge to the full-scale output change.

Digital-to-Analog Glitch Impulse

The amount of charge injected from the digital inputs to the analog output when the inputs change state. This is normally specified as the area of the glitch in either pA-s or nV-s, depending upon whether the glitch is measured as a current or voltage signal.

Multiplying Feedthrough Error

The error due to capacitive feedthrough from the DAC reference input to the DAC I

1 terminal, when all 0s are

OUT

loaded to the DAC.

Total Harmonic Distortion (THD)

The DAC is driven by an ac reference. The ratio of the rms sum of the harmonics of the DAC output to the fundamental value is the THD. Usually only the lower-order harmonics such as second to fifth are included.

THD

log20

+++

VVVV

Digital Intermodulation Distortion

Second-order intermodulation (IMD) measurements are the relative magnitudes of the fa and fb tones generated digitally by the DAC and the second-order products at 2fa − fb and 2fb − fa.

Compliance Voltage Range

The maximum range of (output) terminal voltage for which the device provides the specified characteristics.

Spurious-Free Dynamic Range (SFDR)

The usable dynamic range of a DAC before spurious noise interferes or distorts the fundamental signal. SFDR is the measure of difference in amplitude between the fundamental and the largest harmonically or nonharmonically related spur from dc to full Nyquist bandwidth (half the DAC sampling rate or fs/2). Narrow-band SFDR is a measure of SFDR over an arbitrary window size, in this case 50% of the fundamental. Digital SFDR is a measure of the usable dynamic range of the DAC when the signal is a digitally generated sine wave.

Rev. 0 | Page 8 of 28

AD5444

TYPICAL PERFORMANCE CHARACTERISTICS

0.5 TA = 25°C

INL (LSB)

0.4

0.3

0.2

0.1

–0.1 –0.2

–0.3

–0.4

–0.5

= 10V

REF

= 5V

0 512 1024 1536 2048 2560 3072 3584 4096

CODE

Figure 6. INL vs. Code

1.0 TA = 25°C

0.8 V

= 10V

REF

= 5V

0.6

0.4

0.2

0.0

DNL (LSB)

–0.2 –0.4

–0.6

–0.8

–1.0

0 512 1024 1536 2048 2560 3072 3584 4096

CODE

Figure 7.DNL vs. Code

1.00

TA = 25°C V

0.75

0.50

0.25

INL (LSB)

–0.25

–0.50

–0.75

–1.00

= 5V

AD5444

MAX INL

MIN INL

2345678910

REFERENCE VOLTAGE (V)

Figure 8.INL vs. Reference Voltage

04588-006

04588-008

04588-047

2.0 TA = 25°C

1.5

1.0

0.5

DNL (LSB)

–05

–1.0

–1.5

–2.0

= 5V

AD5444

MAX DNL

2345678910

MIN DNL

REFERENCE VOLTAGE (V)

Figure 9.DNL vs. Reference Voltage

1.0 TA = 25°C

0.8 V

= 10V

REF

= 5V

0.6

0.4

0.2

0.0

TUE (LSB)

–0.2 –0.4

–0.6

–0.8

–1.0

0 512 1024 1536 2048 2560 3072 3584 4096

CODE

Figure 10.TUE vs. Code

2.0

TA = 25°C V

= 5V

1.5

AD5444

1.0

0.5

TUE (LSB)

–0.5

–1.0

–1.5

–2.0

2345 8910

MAX TUE

MIN TUE

REFERENCE VOLTAGE (V)

Figure 11.TUE vs. Reference Voltage

04588-048

04588-0-013

04588-052

Rev. 0 | Page 9 of 28

AD5444

0.3

0.2

0.1

–0.1

GAIN ERROR (LSB)

–0.2

REF

= 10V

VDD = 3V

VDD = 5V

2.5 TA = 25°C

2.0

1.5

VDD = 5V

1.0

SUPPLY CURRENT (mA)

0.5

VDD = 3V

–0.3

–60 –40 –20 0 60 80 100 120 140

4020

TEMPERATURE (°C)

Figure 12. Gain Error (LSB) vs. Temperature

2.0

TA = 25°C

= 10V

REF

1.5

= 5V

AD5444

1.0

0.5

–0.5

GAIN ERROR (LSB)

–1.0

–1.5

–2.0

2345 8910

REFERENCE VOLTAGE (V)

Figure 13. Gain Error (LSB) vs. Reference Voltage

2.0

1, VDD = 5V

1.6

OUT

04588-0-049

04588-051

0.0

012345

INPUT VOLTAGE (V)

Figure 15. Supply Current vs. Logic Input Voltage

0.7

0.6

0.5

0.4

0.3

0.2

SUPPLY CURRENT (µA)

0.1

0.0

–40 –20 0 20 40 60 80 100 120

VDD = 5V

VDD = 3V

TEMPERATURE (°C)

ALL 1s ALL 0s

Figure 16. Supply Current vs. Temperature

TA = 25°C AD5444 LOADING 0101 0101 0101

04588-018

04588-019

1, VDD = 3V

1.2

0.8

1 LEAKAGE (nA)

OUT

0.4

0.0 –40 –20 0 20 40 60 80 100 120

Figure 14. I

TEMPERATURE (°C)

1 Leakage Current vs. Temperature

OUT

04588-017

Rev. 0 | Page 10 of 28

SUPPLY CURRENT (mA)

1 10 100 1k 10k 100k 1M 10M

FREQUENCY (Hz)

VDD = 5V

VDD = 3V

Figure 17. Supply Current vs. Update Rate

04588-055

AD5444

1.8 TA = 25°C

1.6

1.4

1.2

1.0

0.8

0.6

THRESHOLD VOLTAGE (V)

0.4

0.2

2.5 5.5

3.0 3.5 4.54.0 5.0 SUPPLY VOLTAGE (V)

Figure 18. Thres hold Vol tage vs. Suppl y Voltag e

–10

–20

–30

–40

–50

GAIN (dB)

–60

–70

TA = 25°C

–80

LOADING ZS TO FS

–90

100 1k 10k 100k 1M 100M

ALL ON

DB11 DB10

DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1

ALLOFF

FREQUENCY (Hz)

VDD = 5V V

= ±3.5V

REF

= 1.8pF

COMP

AD8038 AMP

10M

Figure 19. Reference Multiplying Bandwidth vs. Frequency and Code

0.2 TA = 25°C V

= 5V

= ±3.5V

REF

= 1.8pF

COMP

AD8038 AMP

–0.2

04588-0-053

04588-054

TA = 25°C V

= 5V

–3

GAIN (dB)

–6

= ±2V, AD8038 C

REF

= ±2V, AD8038 C

REF

= ±15V, AD8038 C

REF

= ±15V, AD8038 C

REF

= ±15V, AD8038 C

REF

–9

10k 100k 1M 10M 100M

= 1pF

COMP

= 1.5pF

COMP

= 1pF

COMP

= 1.5pF

COMP

= 1.8pF

COMP

FREQUENCY (Hz)

Figure 21. Reference Multiplying Bandwidth vs. Frequency and

Compensation Capacitor

0.08

0.06

0.04

0.02

–0.02

OUTPUT VOLTAGE (V)

–0.04

–0.06

50 200 225 250

Figure 22. Midscale Transition, V

VDD =5V 0x7FF TO 0x800 NRG = 2.154nVs

VDD = 3V 0x7FF TO 0x800 NRG = 1.794nVs

VDD =5V 0x800 TO 0x7FF NRG = 0.694nVs

TIME (ns)

175100 125 15075

TA = 25°C V

REF

AD8038 AMP C

COMP

= 0 V

REF

= 0V

= 1.8pF

–1.66

–1.68

–1.70

–1.72

VDD =5V 0x7FF TO 0x800 NRG = 2.154nVs

VDD = 3V 0x7FF TO 0x800 NRG = 1.794nVs

TA = 25°C V

= 3.5V

REF

AD8038 AMP

= 1.8pF

COMP

04588-057

04588-058

–0.4

GAIN (dB)

–0.6

–0.8

100 1k 10k 100k 1M 100M

FREQUENCY (Hz)

10M

Figure 20. Reference Multiplying Bandwidth—All 1s Loaded

04588-056

Rev. 0 | Page 11 of 28

–1.74

OUTPUT VOLTAGE (V)

–1.76

–1.78

–1.80

50 200 225 250

Figure 23. Midscale Transition, V

VDD =5V 0x800 TO 0x7FF

NRG = 0.694nVs VDD =5V 0x800 TO 0x7FF NRG = 0.694nVs

TIME (ns)

175100 125 15075

= 3.5 V

REF

04588-059

AD5444

TA = 25°C V

AD8038 AMPLIFIER

–10 –20 –30 –40 –50

PSRR (dB)

–60 –70 –80 –90

–100

1 10 100 1k 10k 100k 1M 10M

–60

–65

= 3V

FULL SCALE

ZERO SCALE

FREQUENCY (Hz)

Figure 24. Power-Supply Rejection vs. Frequency

TA = 25°C

= 5V

= ±3.5V

REF

04588-060

–20

–40

–60

SFDR (dB)

–80

–100

–120

0 500k

Figure 27. Wideband SFDR , f

FREQUENCY (Hz)

= 20 kHz, Clock = 1 MHz

OUT

TA = 25°C V

REF

AD8038 AMP

400k300k200k100k

–20

TA = 25°C V

AD8038 AMP

DD REF

= 5V

= 3.5V

= 5V

= 3.5V

04588-063

–70

–75

THD + N (dB)

–80

–85

–90

100 1k 10k 100k

FREQUENCY (Hz)

Figure 25. THD + Noise vs. Frequency

04588-061

–40

–60

SFDR (dB)

–80

–100

–120

0 500k

Figure 28. Wideband SFDR , f

100

MCLK = 200kHz

Frequency

OUT

04588-062

= 3.5V

MCLK = 500kHz

20 30 4010

OUT

(kHz)

MCLK = 1MHz

SFDR (dB)

TA = 25°C V

REF

AD8038 AMP

050

Figure 26. Wideband SFDR vs. f

–20

–40

–60

SFDR (dB)

–80

–100

–120

10k 30k

Figure 29. Narrow-Band SFDR , f

FREQUENCY (Hz)

= 50 kHz, Clock = 1 MHz

OUT

FREQUENCY (Hz)

= 20 kHz, Clock = 1 MHz

OUT

400k300k200k100k

TA = 25°C V

REF

AD8038 AMP

25k20k15k

= 5V

= 3.5V

04588-064

04588-065

Rev. 0 | Page 12 of 28

AD5444

–20

–40

–60

SFDR (dB)

–80

–100

–120

30k 70k

Figure 30. Narrow-Band SFDR , f

FREQUENCY (Hz)

= 50 kHz, Clock = 1 MHz

OUT

TA = 25°C V

REF

AD8038 AMP

60k50k40k

–10

–20

–30

–40

–50

IMD (dB)

–60

–70

–80

–90

–100

10k 35k

Figure 31. Narrow-Band IMD, f

FREQUENCY (Hz)

= 20 kHz, 25 kHz, Clock = 1 MHz

OUT

TA = 25°C V

REF

AD8038 AMP

30k25k20k15k

= 5V

= 3.5V

04588-066

04588-067

–10

–20

–30

–40

–50

IMD (dB)

–60

–70

–80

–90

–100

0 500k

Figure 32. Wideband IMD, f

FREQUENCY (Hz)

= 20 kHz, 25 kHz, Clock = 1 MHz

OUT

TA = 25°C

REF

AD8038 AMP

400k300k200k100k

FULL SCALE LOADED TO DAC

OUTPUT NOISE (nV/ Hz)

100 1k 10k 100k 1M

FREQUENCY (Hz)

MIDSCALE LOADED TO DAC

ZERO SCALE LOADED TO DAC

TA = 25°C AD8038 AMP

Figure 33. Output Noise Spectral Density

= 3.5V

04588-068

04588-069

Rev. 0 | Page 13 of 28

AD5444

GENERAL DESCRIPTION

DAC SECTION

The AD5444 is a 12-bit current output DAC consisting of a segmented (4 bits) inverting R–2R ladder configuration. A simplified diagram for the 12-bit AD5444 is shown in Figure 34.

REF

The feedback resistor RFB has a value of R. The value of R is typically 9 kΩ (7 kΩ minimum, 11 kΩ maximum). If I kept at the same potential as GND, a constant current flows in each ladder leg, regardless of digital input code. Therefore, the input resistance presented at V nally of value R. The DAC output (I producing various resistances and capacitances. The external amplifier choice should take into account the variation in impedance generated by the DAC on the amplifiers inverting input node.

Access is provided to the V DAC, making the device extremely versatile and allowing it to be configured in several different operating modes, for example, to provide a unipolar output and in 4-quadrant multiplication in bipolar mode. Note that a matching switch is used in series with the internal R ure R

CIRCUIT OPERATION

Unipolar Mode

Using a single op amp, these devices can easily be configured to provide 2-quadrant multiplying operation or a unipolar output voltage swing, as shown in Figure 35.

RR R

DAC DATA LATCHES

AND DRIVERS

2R S12

OUT

Figure 34. Simplified Ladder

1 is

OUT

is always constant and nomi-

REF

) is code-dependent,

OUT

, RFB, and I

REF

feedback resistor. If users attempt to meas-

terminals of the

OUT

, power must be applied to VDD to achieve continuity.

04464-029

When an output amplifier is connected in unipolar mode, the output voltage is given by

V ×−=

OUT

REF

where:

D is the fractional representation of the digital word loaded to

the DAC:

D = 0 to 4095. n is the number of bits.

Note that the output voltage polarity is opposite to the V

REF

polarity for dc reference voltages.

This DAC is designed to operate with either negative or positive reference voltages. The V

power pin is used by the internal

digital logic only to drive the DAC switches’ on and off states. The DAC is also designed to accommodate ac reference input signals in the range of −10 V to +10 V. With a fixed 10 V reference, the circuit shown in Figure 35 gives an unipolar 0 V to −10 V output voltage swing. When V

is an ac signal, the

circuit performs 2-quadrant multiplication.

Table 5 shows the relationship between digital code and expected output voltage for unipolar operation.

Table 5. Unipolar Code Table

Digital Input Analog Output (V)

1111 1111 1111 −V 1000 0000 0000 −V 0000 0000 0001 −V 0000 0000 0000 −V

(4095/4096)

REF

(2048/4096) = −V

REF

(1/4096)

REF

(0/4096) = 0

REF

NOTES:

R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.

C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED,

IF A1 IS A HIGH SPEED AMPLIFIER.

AD5444

REF

SCLKSYNC

µCONTROLLER

Figure 35. Unipolar Operation

SDIN

OUT

Rev. 0 | Page 14 of 28

AGND

= 0V TO –V

OUT

REF

04588-030

AD5444

Bipolar Operation

In some applications, it might be necessary to generate a full 4-quadrant multiplying operation or a bipolar output swing. This can be easily accomplished by using another external amplifier and some external resistors, as shown in Figure 36. In this circuit, the second amplifier, A2, provides a gain of 2. Biasing the external amplifier with an offset from the reference voltage results in a full 4-quadrant multiplying operation. The transfer function of this circuit shows that both negative and positive output voltages are created as the input data ( incremented from code zero (V 0 V) to full scale (

OUT

= +V

OUT

REF

×=

−1

⎛

VV −

⎜ ⎝

⎞ ⎟ ⎠

REF

OUT

= −V

) to midscale (V

REF

D) is

OUT

where:

D is the fractional representation of the digital word loaded to

the DAC:

D = 0 to 4095. n is the resolution of the DAC.

When V

is an ac signal, the circuit performs 4-quadrant

multiplication.

−

Table 6. Bipolar Code Table

Digital Input Analog Output (V)

1111 1111 1111 +V

(2047/2048)

REF

1000 0000 0000 0 0000 0000 0001 −V 0000 0000 0000 −V

(2047/2048)

REF

(0/2048)

REF

Stability

In the I-to-V configuration, the I

of the DAC and the invert-

OUT

ing node of the op amp must be connected as closely as possible, and proper PCB layout techniques must be employed. Because every code change corresponds to a step function, gain peaking might occur if the op amp has limited GBP and excessive parasitic capacitance exists at the inverting node. This parasitic capacitance introduces a pole into the open-loop response that can cause ringing or instability in the closed-loop applications circuit.

An optional compensation capacitor, C1, can be added in parallel with R

for stability, as shown in Figure 35 and

Figure 36. Too small a value for C1 can produce ringing at the output, while too large a value can adversely affect the settling time. C1 should be found empirically, but 1 pF to 2 pF is generally adequate for the compensation.

Table 6 shows the relationship between digital code and the expected output voltage for bipolar operation.

SDIN

NOTES:

ADJUST R1 FOR V

IF A1/A2 IS A HIGH SPEED AMPLIFIER.

REF

±10V

AD5444

REF

SCLKSYNC

µCONTROLLER

Figure 36. Bipolar Operation (4-Quadrant Multiplication)

20kΩ

OUT

R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED. MATCHING AND TRACKING IS ESSENTIAL FOR RESISTOR PAIRS

R3 AND R4. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED,

AGND

OUT

10kΩ

= 0V WITH CODE 10000000 LOADED TO DAC.

20kΩ

=–V

REF

TO +V

OUT

REF

04588-031

Rev. 0 | Page 15 of 28

AD5444

SINGLE-SUPPLY APPLICATIONS

Voltage Switching Mode of Operation

Figure 37 shows the AD5444 DAC operating in the voltageswitching mode. The reference voltage, V I

1 pin, I

OUT

available at the V

2 is connected to AGND, and the output voltage is

OUT

terminal. In this configuration, a positive

REF

reference voltage results in a positive output voltage, making single-supply operation possible. The output from the DAC is voltage at a constant impedance (the DAC ladder resistance). Therefore, an op amp is necessary to buffer the output voltage. The reference input no longer sees a constant input impedance, but one that varies with code, so the voltage input should be driven from a low impedance source.

FBVDD

OUT

NOTES:

ADDITIONAL PINS OMITTED FOR CLARITY.

C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED,

IF A1 IS A HIGH SPEED AMPLIFIER.

GND

REF

Figure 37. Single-Supply Voltage Switching Mode Operation

It is important to note that, with this configuration, VIN is limited to low voltages, because the switches in the DAC ladder do not have the same source-drain drive voltage. As a result, their on resistance differs, which degrades the integral linearity of the DAC. Also, V

must not go negative by more than 0.3 V,

or an internal diode turns on, exceeding the maximum ratings of the device. In this type of application, the full range of multiplying capability of the DAC is lost.

Positive Output Voltage

The output voltage polarity is opposite to the V dc reference voltages. To achieve a positive voltage output, an applied negative reference to the input of the DAC is preferred over the output inversion through an inverting amplifier because of the resistor’s tolerance errors. To generate a negative reference, the reference can be level-shifted by an op amp such that the V

and GND pins of the reference become the virtual

OUT

ground and −2.5 V, respectively, as shown in Figure 38.

, is applied to the

REF

OUT

04588-032

polarity for

REF

VDD = 5V

GND

OUT

= 0V TO +2.5V

OUT

ADR03

OUTVIN

GND

+5V

–2.5V

–5V

NOTES:

ADDITIONAL PINS OMITTED FOR CLARITY.

C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED,

IF A1 IS A HIGH SPEED AMPLIFIER.

Figure 38. Positive Voltage Output with Minimum Components

ADDING GAIN

In applications in which the output voltage is required to be greater than V

, gain can be added with an additional external

amplifier, or it can be achieved in a single stage. It is important to take into consideration the effect of the temperature coefficients of the DAC’s thin film resistors. Simply placing a resistor in series with the R

resistor can cause mismatches in

the temperature coefficients and result in larger gain temperature coefficient errors. Instead, increase the gain of the circuit by using the recommended configuration shown in Figure 39. R1, R2, and R3 should all have similar temperature coefficients, but they need not match the temperature coefficients of the DAC. This approach is recommended in circuits where gains of greater than 1 are required.

NOTES:

1 2

IF A1 IS A HIGH SPEED AMPLIFIER.

REF

GND

ADDITIONAL PINS OMITTED FOR CLARITY. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED,

OUT

Figure 39. Increasing Gain of Current Output DAC

GAIN =

R1 =

OUT

R2 + R3

R2R3

R2 + R3

DIVIDER OR PROGRAMMABLE GAIN ELEMENT

Current-steering DACs are very flexible and lend themselves to many different applications. If this type of DAC is connected as the feedback element of an op amp and R resistor, as shown in Figure 40, then the output voltage is inversely proportional to the digital input fraction,

For

D = 1 − 2

−n

, the output voltage is

is used as the input

04588-033

04588-034

= −VIN/D = −VIN/(1 − 2−n)

OUT

Rev. 0 | Page 16 of 28

AD5444

OUT

NOTES:

ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 40. Current-Steering DAC Used as a Divider

or Programmable Gain Element

FBVDD

GND

REF

OUT

04588-035

As D is reduced, the output voltage increases. For small values of the digital fraction,

D, it is important to ensure that the

amplifier does not saturate and that the required accuracy is met. For example, an 8-bit DAC driven with the binary code 0x10 (0001 0000), that is, 16 decimal, in the circuit of Figure 40 should cause the output voltage to be 16 × V DAC has a linearity specification of ±0.5 LSB, then

. However, if the

D can, in

fact, have a weight in the range of 15.5/256 to 16.5/256, so that the possible output voltage is in the range 15.5 V

to 16.5 VIN.

This is an error of 3%, even though the DAC itself has a maximum error of 0.2%.

DAC leakage current is also a potential error source in divider circuits. The leakage current must be counterbalanced by an opposite current supplied from the op amp through the DAC. Because only a fraction, is routed to the I

D, of the current into the V

1 terminal, the output voltage has to change,

OUT

terminal

REF

as follows:

Output Error Voltage Due to DAC Leakage = (Leakage × R)/D

where

R is the DAC resistance at the V

For a DAC leakage current of 10 nA, gain (1/

D) of 16, the error voltage is 1.6 mV.

terminal.

REF

R equal to 10 kΩ, and a

AMPLIFIER SELECTION

The primary requirement for the current-steering mode is an amplifier with low input bias currents and low input offset voltage. The input offset voltage of an op amp is multiplied by the variable gain (due to the code-dependent output resistance of the DAC) of the circuit. A change in this noise gain between two adjacent digital fractions produces a step change in the output voltage due to the amplifier’s input offset voltage. This output voltage change is superimposed upon the desired change in output between the two codes and gives rise to a differential

linearity error, which, if large enough, could cause the DAC to be nonmonotonic.

The input bias current of an op amp also generates an offset at the voltage output as a result of the bias current flowing in the feedback resistor, R

. Most op amps have input bias

currents low enough to prevent any significant errors in 12-bit applications.

Common-mode rejection of the op amp is important in voltage switching circuits, because it produces a code-dependent error at the voltage output of the circuit. Most op amps have adequate common-mode rejection for use at 8-bit, 10-bit, and 12-bit resolution.

Provided that the DAC switches are driven from true wideband low impedance sources (V

and AGND), they settle quickly.

Consequently, the slew rate and settling time of a voltage switching DAC circuit is determined largely by the output op amp. To obtain minimum settling time in this configuration, it is important to minimize capacitance at the V

node (voltage

REF

output node in this application) of the DAC. This is done by using low input, capacitance buffer amplifiers and careful board design.

Most single-supply circuits include ground as part of the analog signal range, which, in turn, requires an amplifier that can handle rail-to-rail signals. A large range of single-supply amplifiers is available from Analog Devices.

REFERENCE SELECTION

When selecting a reference for use with the AD5444 current output DAC, pay attention to the reference’s output voltage temperature coefficient specification. This parameter affects not only the full-scale error, but can also affect the linearity (INL and DNL) performance. The reference temperature coefficient should be consistent with the system accuracy specifications. For example, an 8-bit system required to hold its overall specification to within 1 LSB over the temperature range 0°C to 50°C dictates that the maximum system drift with temperature should be less than 78 ppm/°C.

A 12-bit system with the same temperature range to overall specification within 2 LSBs requires a maximum drift of 10 ppm/°C. By choosing a precision reference with low output temperature coefficient, this error source can be minimized. Table 7 suggests some of the dc references available from Analog Devices that are suitable for use with this range of current output DACs.

Rev. 0 | Page 17 of 28

AD5444

Table 7. Suitable ADI Precision References

Temperature Drift

Reference Output Voltage (V) Initial Tolerance (%)

ADR01 10 0.1 3 20 SC70, TSOT, SOIC ADR02 5 0.1 3 10 SC70, TSOT, SOIC ADR03 2.5 0.2 3 10 SC70, TSOT, SOIC ADR425 5 0.04 3 3.4 MSOP, SOIC

(ppm/°C)

Table 8. Suitable ADI Precision Op Amps

Part No. Max Supply Voltage (V) Max VOS (µV) Max IB (nA) GBP (MHz) Slew Rate (V/µs)

OP97 ±20 25 0.1 0.9 0.2 OP1177 ±18 60 2 1.3 0.7 AD8551 6 5 0.05 1.5 0.4

Table 9. Suitable ADI High Speed Op Amps

Part No. Max Supply Voltage (V) Max VOS (µV) Max IB (nA) BW @ A

AD8065 ±12 1500 0.01 145 180 AD8021 ±12 1000 1000 200 100 AD8038 ±5 3000 0.75 350 425 AD9631 ±5 10000 7000 320 1300

0.1 Hz to 10 Hz Noise (µV p-p)

(MHz) Slew Rate (V/µs)

Package

Rev. 0 | Page 18 of 28

AD5444

SERIAL INTERFACE

The AD5444 has an easy-to-use 3-wire interface that is compatible with SPI, QSPI, MICROWIRE, and DSP interface standards. Data is written to the device in 16-bit words. This 16-bit word consists of two control bits and 12 data bits, as shown in Figure 41. The AD5444 uses 12 bits and ignores the 2 LSBs.

DAC Control Bits C1, C0

Control Bits C1 and C0 allow the user to load and update the new DAC code and to change the active clock edge. By default, the shift register clocks data on the falling edge, but this can be changed via the control bits. If changed, the DAC core is inoperative until the next data frame. A power cycle resets this back to the default condition. On-chip power-on reset circuitry ensures that the device powers on with zero scale loaded to the DAC register and I

OUT

line.

Table 10. DAC Control Bits

C1 C0 Function Implemented

0 0 Load and update (power-on default) 0 1 Disable SDO 1 0 No operation 1 1 Clock data to shift register on rising edge

SYNC

Function

SYNC

is an edge-triggered input that acts as a frame synchronization signal. Data can be transferred into the device only while SYNC

is low. To start the serial data transfer, taken low, observing the minimum falling edge setup time, t

. To minimize the power consumpt ion

SYNC

should be

falling to SCLK

of the device, the interface powers up fully only when the device

SYNC

is being written to, that is, on the falling edge of

The SCLK and DIN input buffers are powered down on the

SYNC

rising edge of

After the falling edge of the 16th SCLK pulse, bring

SYNC

high

to transfer data from the input shift register to the DAC register.

Daisy-Chain Mode

Daisy-chain mode is the default power-on mode. To disable the daisy-chain function, write 01 to the control word. In daisychain mode, the internal gating on the SCLK is disabled. The SCLK is continuously applied to the input shift register when SYNC

is low. If more then 16 clock pulses are applied, the data ripples out of the shift register and appears on the SDO line. This data is clocked out on the rising edge of the SCLK (this is the default; use the control word to change the active edge) and is valid for the next device on the falling edge (default). By connecting this line to the SDIN input on the next device in the chain, a multidevice interface is constructed. 16 clock pulses are required for each device in the system. Therefore, the total number of clock cycles must equal 16

N, where N is the number

of devices in the chain.

When the serial transfer to all devices is complete,

SYNC

should be taken high. This prevents any further data from being clocked into the shift register. A burst clock containing the exact

SYNC

number of clock cycles can be used, and time later. After the rising edge of

SYNC

taken high some

, data is automatically transferred from each device’s input register to the addressed DAC.

When the control bits = 10, the device is in no operation mode. This can be useful in daisy-chain applications where the user does not want to change the settings of a particular DAC in the chain. Simply write 10 to the control bits for that DAC, and the following data bits are ignored.

DB0 (LSB)DB15 (MSB)

C1 C0

CONTROL

BITS

DB10 DB9 DB8 DB7 DB6 DB5

DB11

Figure 41. AD5444 12-Bit Input Shift Register Contents

DB4 DB3 DB2 DB1 DB0 X X

DATA BITS

04588-0-031

Rev. 0 | Page 19 of 28

AD5444

MICROPROCESSOR INTERFACING

Microprocessor interfacing to the AD5444 DAC is through a serial bus that uses standard protocol compatible with microcontrollers and DSP processors. The communications channel is a 3-wire interface consisting of a clock signal, a data signal, and a synchronization signal. The AD5444 requires a 16-bit word, with the default being data valid on the falling edge of SCLK, but this is changeable using the control bits in the data-word.

ADSP-21xx to AD5444 Interface

The ADSP-21xx family of DSPs is easily interfaced to the AD5444 DAC without the need for extra glue logic. Figure 42 is an example of an SPI interface between the DAC and the ADSP-2191M. SCK of the DSP drives the serial data line, DIN. SYNC

is driven from one of the port lines, in this case SPIxSEL.

ADSP-2191*

SPIxSEL

MOSI

SCK

AD5444*

SYNC SDIN SCLK

Table 11 shows the setup for the SPORT control register.

Table 11. SPORT Control Register Setup

Name Setting Description

TFSW 1 Alternate framing INVTFS 1 Active low frame signal DTYPE 00 Right-justify data ISCLK 1 Internal serial clock TFSR 1 Frame every word ITFS 1 Internal framing signal SLEN 1111 16-bit data-word

ADSP-BF5xx-to-AD5444 Interface

The ADSP-BF5xx family of processors has an SPI-compatible port that enables the processor to communicate with SPIcompatible devices. A serial interface between the ADSP-BF5xx and the AD5444 DAC is shown in Figure 46. In this configuration, data is transferred through the MOSI (master output/slave input) pin.

SYNC

is driven by the SPI chip select pin, which is a

reconfigured programmable flag pin.

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 42. ADSP-2191 SPI to AD5444 Interface

A serial interface between the DAC and DSP SPORT is shown in Figure 43. In this interface example, SPORT0 is used to transfer data to the DAC shift register. Transmission is initiated by writing a word to the Tx register after the SPORT has been enabled. In a write sequence, data is clocked out on each rising edge of the DSP’s serial clock and clocked into the DAC input shift register on the falling edge of its SCLK. The update of the

SYNC SDIN

SCLK

SYNC

AD5444*

signal.

DAC output takes place on the rising edge of the

ADSP-2101/ ADSP-2103/ ADSP-2191*

*ADDITIONAL PINS OMITTED FOR CLARITY

TFS

SCLK

Figure 43. ADSP-2101/ADSP-2103/ADSP-2191 SPORT to

AD5444 Interface

Communication between two devices at a given clock speed is possible when the following specifications are compatible: frame sync delay and frame sync setup-and-hold, data delay and data setup-and-hold, and SCLK width. The DAC interface expects a t of 13 ns minimum. See the

(

SYNC

falling edge to SCLK falling edge setup time)

ADSP-21xx User Manual for

information on clock and frame sync frequencies for the SPORT register.

ADSP-BF5xx*

04588-074

*ADDITIONAL PINS OMITTED FOR CLARITY

SPIxSEL

MOSI

SCK

Figure 44. ADSP-BF5xx-to-AD5444 Interface

SYNC SDIN SCLK

AD5444*

04588-039

The ADSP-BF5xx processor incorporates channel synchronous serial ports (SPORT). A serial interface between the DAC and the DSP SPORT is shown in Figure 46. When the SPORT is enabled, initiate transmission by writing a word to the Tx register. The data is clocked out on each rising edge of the DSP’s serial clock and clocked into the DAC’s input shift register on the falling edge of its SCLK. The DAC output is updated by using the transmit frame synchronization (TFS) line to provide

SYNC

04588-075

signal.

ADSP-BF5xx*

TFS

SCLK

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 45. ADSP-BF5xx to AD5444 Interface

SYNC SDIN

SCLK

AD5444*

04588-040

Rev. 0 | Page 20 of 28

AD5444

80C51/80L51 to AD544 Interface

A serial interface between the DAC and the 80C51/80L51 is shown in Figure 46. TxD of the 80C51/80L51 drives SCLK of the DAC serial interface, while RxD drives the serial data line, SDIN. P1.1 is a bit-programmable pin on the serial port and is used to drive

SYNC

. When data is to be transmitted to the switch, P1.1 is taken low. The 80C51/80L51 transmits data only in 8-bit bytes; therefore, only eight falling clock edges occur in the transmit cycle. To load data correctly to the DAC, P1.1 is left low after the first eight bits are transmitted, and a second write cycle is initiated to transmit the second byte of data.

Data on RxD is clocked out of the microcontroller on the rising edge of TxD and is valid on the falling edge. As a result, no glue logic is required between the DAC and microcontroller interface. P1.1 is taken high following the completion of this cycle. The 80C51/80L51 provides the LSB of its SBUF register as the first bit in the data stream. The DAC input register requires its data with the MSB as the first bit received. The transmit routine should take this into account.

8051*

*ADDITIONAL PINS OMITTED FOR CLARITY

TxD

RxD

P1.1

Figure 46. 80C51/80L51 to AD5444 Interface

AD5444*

SCLK

SDIN SYNC

MC68HC11 Interface to AD5444 Interface

Figure 47 is an example of a serial interface between the DAC and the MC68HC11 microcontroller. The serial peripheral interface (SPI) on the MC68HC11 is configured for master mode (MSTR) = 1, clock polarity bit (CPOL) = 0, and the clock phase bit (CPHA) = 1. The SPI is configured by writing to the SPI control register (SPCR); see the

68HC11 User Manual. SCK

of the 68HC11 drives the SCLK of the DAC interface, the MOSI output drives the serial data line (SDIN) of the AD5444.

SYNC

The is being transmitted to the AD5444, the

signal is derived from a port line (PC7). When data

SYNC

line is taken low (PC7). Data appearing on the MOSI output is valid on the falling edge of SCK. Serial data from the 68HC11 is transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. Data is transmitted MSB first. To load data to the DAC, PC7 is left low after the first eight bits are transferred, and a second serial write operation is performed to the DAC. PC7 is taken high at the end of this procedure.

04588-041

MC68HC11*

PC7

SCK

MOSI

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 47. 68HC11/68L11 to AD5444 Interface

AD5444*

SYNC

SCLK

SDIN

If the user wants to verify the data previously written to the input shift register, the SDO line can be connected to MISO of

SYNC

the MC68HC11, and, with

low, the shift register clocks

data out on the rising edges of SCLK.

MICROWIRE to AD5444 Interface

Figure 48 shows an interface between the DAC and any MICROWIRE-compatible device. Serial data is shifted out on the falling edge of the serial clock, SK, and is clocked into the DAC input shift register on the rising edge of SK, which corresponds to the falling edge of the DAC’s SCLK.

MICROWIRE*

SK SO CS

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 48. MICROWIRE to AD5444 Interface

AD5444*

SCLK SDIN SYNC

PIC16C6x/7x to AD5444 Interface

The PIC16C6x/7x synchronous serial port (SSP) is configured as an SPI master with the clock polarity bit (CKP) = 0. This is done by writing to the synchronous serial port control register (SSPCON); see the

In this example, I/O port RA1 is used to provide a

PIC16/17 Microcontroller User Manual.

SYNC

signal and enable the serial port of the DAC. This microcontroller transfers only eight bits of data during each serial transfer operation; therefore, two consecutive write operations are required. Figure 49 shows the connection diagram.

PIC16C6x/7x*

SCK/RC3

SDI/RC4

RA1

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 49. PIC16C6x/7x to AD5444 Inter face

AD5444*

SCLK SDIN SYNC

04588-042

04588-043

04588-044

Rev. 0 | Page 21 of 28

AD5444

PCB LAYOUT AND POWER SUPPLY DECOUPLING

In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The printed circuit boards on which the AD5444 are mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. If the DACs are in systems in which multiple devices require an AGND-to-DGND connection, the connection should be made at one point only. The star ground point should be established as close as possible to the devices.

The DAC should have ample supply bypassing of 10 µF in parallel with 0.1 µF on the supply located as close to the package as possible, ideally right up against the device. The 0.1 µF capacitor should have low effective series resistance (ESR) and effective series inductance (ESI), like the common ceramic types that provide a low impedance path to ground at high frequencies, to handle transient currents due to internal logic switching. Low ESR, 1 µF to 10 µF tantalum or electrolytic capacitors should also be applied at the supplies to minimize transient disturbance and filter out low frequency ripple.

Fast-switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other parts of the board, and should never be run near the reference inputs.

Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough through the board. A microstrip technique is by far the best, but not always possible with a

double-sided board. In this technique, the component side of the board is dedicated to the ground plane, while signal traces are placed on the solder side.

It is good practice to employ compact, minimum lead-length PCB layout design. Leads to the input should be as short as possible to minimize IR drops and stray inductance.

The PCB metal traces between V matched to minimize gain error. To maximize high frequency performance, the I-to-V amplifier should be located as close to the device as possible.

EVALUATION BOARD FOR THE DAC

The evaluation board consists of an AD5444 DAC and a current-to-voltage amplifier, AD8065. Included on the evaluation board is a 10 V reference, ADR01. An external reference can also be applied via an SMB input.

The evaluation kit consists of a CD-ROM with self-installing PC software to control the DAC. The software allows the user to write a code to the device.

POWER SUPPLIES FOR THE EVALUATION BOARD

The board requires ±12 V and +5 V supplies. The 12 V VDD and V is used to power the DAC (V

Both supplies are decoupled to their respective ground plane with 10 µF tantalum and 0.1 µF ceramic capacitors.

and RFB should also be

REF

are used to power the output amplifier, while the 5 V supply

) and transceivers (VCC).

DD1

Rev. 0 | Page 22 of 28

AD5444

OUT

TP1

10µF

0.1µF

AD8065AR

4.7pF

10µF

0.1µF

AD5444

SDIN

SCLK

10µF

0.1µF

C10

V–

V+

OUT

SYNC

REF

OUT

SDO/LDAC

REF

GND

LK1

OUT

0.1µF

10µF

GND

ADR01AR

TRIM

AGND

C16

10µF

C15

0.1µF

P2–4

04588-070

SCLK

C14

10µF

C12

P1–25

P1–26

P1–27

10µF

C13

C11

0.1µF

P2–3

P2–2

P2–1

P1–28

P1–29

P1–30

SDIN

SYNC

SDO/LDAC

LK2

SDO

LDAC

SYNC

SDIN

P1–19

P1–20

P1–21

P1–22

P1–23

P1–2

P1–3

P1–4

P1–5

P1–13

P1–24

Figure 50. Schematic of the AD5444 Evaluation Board

Rev. 0 | Page 23 of 28

AD5444

Figure 51. Component-Side Artwork

04588-072

04588-071

Figure 52. Silkscreen—Component-Side Artwork (Top)

Rev. 0 | Page 24 of 28

AD5444

04588-073

Figure 53. Solder-Side Artwork

Rev. 0 | Page 25 of 28

AD5444

OVERVIEW OF AD54XX DEVICES

Table 12.

Part No. Resolution No. DACs INL(LSB) Interface Package Features

AD5424 8 1 ±0.25 Parallel RU-16, CP-20 AD5426 8 1 ±0.25 Serial RM-10 10 MHz BW, 50 MHz Serial

AD5428 8 2 ±0.25 Parallel RU-20 AD5429 8 2 ±0.25 Serial RU-10 10 MHz BW, 50 MHz Serial AD5450 8 1 ±0.25 Serial RJ-8 10 MHz BW, 50 MHz Serial AD5432 10 1 ±0.5 Serial RM-10 10 MHz BW, 50 MHz Serial AD5433 10 1 ±0.5 Parallel RU-20, CP-20 AD5439 10 2 ±0.5 Serial RU-16 10 MHz BW, 50 MHz Serial AD5440 10 2 ±0.5 Parallel RU-24 AD5451 10 1 ±0.25 Serial RJ-8 10 MHz BW, 50 MHz Serial AD5443 12 1 ±1 Serial RM-10 10 MHz BW, 50 MHz Serial AD5444 12 1 ±0.5 Serial RM-8 50 MHz Serial Interface

AD5415 12 2 ±1 Serial RU-24 10 MHz BW, 58 MHz Serial AD5445 12 2 ±1 Parallel RU-20, CP-20

AD5447 12 2 ±1 Parallel RU-24 AD5449 12 2 ±1 Serial RU-16 10 MHz BW, 50 MHz Serial

AD5452 12 1 ±0.5 Serial RJ-8, RM-8 10 MHz BW, 50 MHz Serial AD5446 14 1 ±1 Serial RM-8 10 MHz BW, 50 MHz Serial AD5453 14 1 ±2 Serial UJ-8, RM-8 10 MHz BW, 50 MHz Serial AD5553 14 1 ±1 Serial RM-8 4 MHz BW, 50 MHz Serial Clock AD5556 14 1 ±1 Parallel RU-28 AD5555 14 2 ±1 Serial RM-8 4 MHz BW, 50 MHz Serial Clock AD5557 14 2 ±1 Parallel RU-38

AD5543 16 1 ±2 Serial RM-8 4 MHz BW, 50 MHz Serial Clock AD5546 16 1 ±2 Parallel RU-28

AD5545 16 2 ±2 Serial RU-16 4 MHz BW, 50 MHz Serial Clock AD5547 16 2 ±2 Parallel RU-38

10 MHz BW, 17 ns

10 MHz BW, 17 ns 10 MHz BW, 17 ns

4 MHz BW, 20 ns

CS Pulse Width

CS Pulse Width CS Pulse Width

WR Pulse Width

Rev. 0 | Page 26 of 28

AD5444

OUTLINE DIMENSIONS

3.00 BSC

PIN 1

0.50 BSC

0.95

0.85

0.75

0.15

0.00

0.27

0.17

COPLANARITY

0.10 COMPLIANT TO JEDEC STANDARDS MO-187BA

Figure 54. 10-Lead Mini Small Outline Package [MSOP]

ORDERING GUIDE

Model Resolution INL Temperature Range Package Description Package Option Branding

AD5444YRM 12 ±0.5 −40°C to +125°C MSOP RM-10 D27 AD5444YRM-REEL 12 ±0.5 −40°C to +125°C MSOP RM-10 D27 AD5444YRM-REEL7 12 ±0.5 −40°C to +125°C MSOP RM-10 D27 EVAL-AD5444EB Evaluation Board

4.90 BSC

1.10 MAX

SEATING PLANE

0.23

0.08

(RM-10)

Dimensions shown in millimeters

8° 0°

0.80

0.60

0.40

Rev. 0 | Page 27 of 28

AD5444

NOTES

D05186–0–10/04(0)

Rev. 0 | Page 28 of 28

Datasheet AD5444 Datasheet (Analog Devices)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

SPECIFICATIONS

TIMING CHARACTERISTICS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TERMINOLOGY

TYPICAL PERFORMANCE CHARACTERISTICS

GENERAL DESCRIPTION

DAC SECTION

CIRCUIT OPERATION

Unipolar Mode

Bipolar Operation

Stability

SINGLE-SUPPLY APPLICATIONS

Voltage Switching Mode of Operation

Positive Output Voltage

ADDING GAIN

DIVIDER OR PROGRAMMABLE GAIN ELEMENT

AMPLIFIER SELECTION

REFERENCE SELECTION

SERIAL INTERFACE

DAC Control Bits C1, C0

Daisy-Chain Mode

MICROPROCESSOR INTERFACING

ADSP-21xx to AD5444 Interface

ADSP-BF5xx-to-AD5444 Interface

80C51/80L51 to AD544 Interface

MC68HC11 Interface to AD5444 Interface

MICROWIRE to AD5444 Interface

PIC16C6x/7x to AD5444 Interface

PCB LAYOUT AND POWER SUPPLY DECOUPLING

EVALUATION BOARD FOR THE DAC

POWER SUPPLIES FOR THE EVALUATION BOARD

OVERVIEW OF AD54XX DEVICES

OUTLINE DIMENSIONS

ORDERING GUIDE