Datasheet AD5432, AD5443 Datasheet (ANALOG DEVICES)

S

查询AD5426供应商

8-/10-/12-Bit High Bandwidth

Multiplying DACs with Serial Interface

FEATURES

3.0 V to 5.5 V Supply Operation
50 MHz Serial Interface
10 MHz Multiplying Bandwidth
ⴞ10 V Reference Input
Low Glitch Energy < 2 nV-s
Extended Temperature Range –40ⴗC to +125ⴗC
10-Lead MSOP Package
Pin Compatible 8-, 10-, and 12-Bit Current

Output DACs
Guaranteed Monotonic
4-Quadrant Multiplication
Power-On Reset with Brownout Detection
Daisy-chain Mode
Readback Function

0.4 ␮A Typical Power Consumption

APPLICATIONS
Portable Battery-Powered Applications
Waveform Generators
Analog Processing
Instrumentation Applications
Programmable Amplifiers and Attenuators
Digitally Controlled Calibration
Programmable Filters and Oscillators
Composite Video
Ultrasound
Gain, Offset, and Voltage Trimming

GENERAL DESCRIPTION

The AD5426/AD5432/AD5443 are CMOS 8-, 10-, and 12-bit
current output digital-to-analog converters, respectively.

These devices operate from a 3.0 V to 5.5 V power supply,
making them suited to battery-powered applications and many
other applications.

These DACs utilize double buffered 3-wire serial interface that
is compatible with SPI

®

, QSPI™, MICROWIRE™, and most
DSP interface standards. In addition, a serial data out pin (SDO)
allows for daisy-chaining when multiple packages are used. Data
readback allows the user to read the contents of the DAC register
via the SDO pin. On power-up, the internal shift register and
latches are filled with 0s and the DAC outputs are at zero scale.

As a result of manufacture on a CMOS submicron process, they
offer excellent 4-quadrant multiplication characteristics, with
large signal multiplying bandwidths of 10 MHz.

AD5426/AD5432/AD5443

*

FUNCTIONAL BLOCK DIAGRAM

V

DD

AD5426/
AD5432/
AD5443

POWER-ON

RESET

YNC

SCLK

SDIN

The applied external reference input voltage (V
the full-scale output current. An integrated feedback resistor (R

V

REF

8-/10-/12-BIT

R-2R DAC

DAC REGISTER

INPUT LATCH

CONTROL LOGIC AND

INPUT SHIFT REGISTER

GND

R

) determines

REF

R

FB

I

OUT

I

OUT

SDO

1

2

)

FB

provides temperature tracking and full-scale voltage output when
combined with an external current to voltage precision amplifier.

The AD5426/AD5432/AD5443 DACs are available in small
10-lead MSOP packages.

*U.S. Patent No. 5,689,257

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

AD5426/AD5432/AD5443–SPECIFICATIONS

1

(VDD = 3 V to 5.5 V, V
performance with AD8038, unless otherwise noted.)

Parameter Min Typ Max Unit Conditions

STATIC PERFORMANCE

AD5426

Resolution 8 Bits
Relative Accuracy ±0.25 LSB
Differential Nonlinearity ±0.5 LSB Guaranteed monotonic

AD5432

Resolution 10 Bits
Relative Accuracy ±0.5 LSB
Differential Nonlinearity ±1 LSB Guaranteed monotonic

AD5443

Resolution 12 Bits
Relative Accuracy ±1 LSB
Differential Nonlinearity –1/+2 LSB Guaranteed monotonic

Gain Error ±10 mV
Gain Error Temperature Coefficient
Output Leakage Current ±5nA Data = 0x0000, T

REFERENCE INPUT

Reference Input Range ±10 V

Input Resistance 8 10 12 kΩ Input resistance TC = –50 ppm/°C

V

REF

Resistance 8 10 12 kΩ Input resistance TC = –50 ppm/°C

R

FB

Input Capacitance

Code All 0s 3 6 pF
Code All 1s 5 8 pF

DIGITAL INPUTS/OUTPUT

Input High Voltage, V
Input Low Voltage, V
Input Leakage Current, I
Input Capacitance 4 10 pF

= 4.5 V to 5.5 V

V

DD

Output Low Voltage, V
Output High Voltage, V

= 3 V to 3.6 V

V

DD

Output Low Voltage, V
Output High Voltage, V

DYNAMIC PERFORMANCE

Reference Multiplying Bandwidth 10 MHz V
Output Voltage Settling Time V
AD5426 50 100 ns Measured to ±16 mV of full scale
AD5432 55 110 ns Measured to ±4 mV of full scale
AD5443 90 160 ns Measured to ± 1 mV of full scale
Digital Delay 40 75 ns Interface Delay Time
10% to 90% Rise/Fall Time 15 30 ns Rise and fall time, V
Digital-to-Analog Glitch Impulse 2 nV-s 1 LSB change around major carry, V
Multiplying Feedthrough Error DAC latch loaded with all 0s. V

Output Capacitance

22225pF All 0s loaded

I

OUT

11217pF All 0s loaded

I

OUT

Digital Feedthrough 0.1 nV-s Feedthrough to DAC output with SYNC high and

Total Harmonic Distortion –81 dB V
Digital THD Clock = 1 MHz

50 kHz f

Output Noise Spectral Density 25 nV/√Hz @ 1 kHz

OUT

= 10 V, I

REF

2

IL

x = O V. All specifications T

OUT

2

2

IH

1.7 V

±5 ppm FSR/°C

to T

MIN

, unless otherwise noted. DC performance measured with OP177, AC

MAX

±25 nA Data = 0x0000, I

= 25°C, I

A

OUT

OUT

0.6 V

IL

OL

OH

OL

OH

2

VDD – 1 V I

VDD – 0.5 V I

2 ␮A

0.4 V I

0.4 V I

= 200 ␮A

SINK

= 200 ␮A

SOURCE

= 200 ␮A

SINK

= 200 ␮A

SOURCE

= ±3.5 V; DAC loaded all 1s

REF

= 10 V; R

REF

= 100 Ω, C

LOAD

REF

= 10 V, R

LOAD

LOAD

= ±3.5 V

REF

= 15 pF

= 100 Ω

= 0 V

REF

70 dB 1 MHz
48 dB 10 MHz

10 12 pF All 1s loaded

25 30 pF All 1s loaded

alternate loading of all 0s and all 1s

= 3.5 V pk-pk; all 1s loaded, f = 1 kHz

REF

73 dB

REV. 0–2–

AD5426/AD5432/AD5443

Parameter Min Typ Max Unit Conditions

SFDR Performance (Wide Band) AD5443, 4096 codes V

Clock = 10 MHz

50 kHz f
20 kHz f

OUT

OUT

SFDR Performance (Narrow Band)

Clock = 1 MHz

50 kHz f
20 kHz f

OUT

OUT

Intermodulation Distortion

Clock = 1 MHz

f1 = 20 kHz, f2 = 25 kHz 78 dB

POWER REQUIREMENTS

Power Supply Range 3.0 5.5 V
I

DD

NOTES

1

Temperature range is as follows: Y version: –40°C to +125°C.

2

Guaranteed by design and characterization, not subject to production test.

Specifications subject to change without notice.

75 dB
76 dB

87 dB
87 dB

0.4 5 ␮A Logic inputs = 0 V or V

0.6 ␮AT

= 25°C, logic inputs = 0 V or V

A

= 3.5 V

REF

DD

DD

REV. 0

–3–

AD5426/AD5432/AD5443

S

S

1

TIMING CHARACTERISTICS

(VDD = 3 V to 5.5 V, V

Parameter 3.0 V to 5.5 V 4.5 V to 5.5 V Unit Conditions/Comments

f

SCLK

t

1

t

2

t

3

2

t

4

t

5

t

6

t

7

t

8

3

t

9

50 50 MHz max Max clock frequency
20 20 ns min SCLK cycle time
88 ns min SCLK high time
88 ns min SCLK low time
13 13 ns min SYNC falling edge to SCLK active edge setup time
55 ns min Data setup time
33 ns min Data hold time
55 ns min SYNC rising edge to SCLK active edge
30 30 ns min Minimum SYNC high time
80 45 ns typ SCLK active edge to SDO valid
120 65 ns max

NOTES

1

See Figures 1 and 2. Temperature range is as follows: Y version: –40°C to +125°C. Guaranteed by design and characterization, not subject to production test.
All input signals are specified with tr = tf = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.

2

Falling or rising edge as determined by control bits of serial word.

3

Daisy-chain and readback modes cannot operate at max clock frequency. SDO timing specifications measured with load circuit as shown in Figure 3.

Specifications subject to change without notice.

SCLK

t

2

YNC

t

8

t

4

= 10 V, I

REF

t

1

t

3

2 = O V. All specifications T

OUT

t

7

MIN

to T

, unless otherwise noted.)

MAX

t

6

t

DIN

ALTERNATIVELY, DATA MAY BE CLOCKED INTO INPUT SHIFT REGISTER ON RISING EDGE OF
SCLK AS DETERMINED BY CONTROL BITS. TIMING AS PER ABOVE, WITH SCLK INVERTED.

DB15 DB0

5

Figure 1. Standalone Mode Timing Diagram

t

1

SCLK

t

t

4

YNC

t

6

t

5

SDIN

SDO

ALTERNATiVELY, DATA MAY BE CLOCKED INTO INPUT SHIFT REGISTER ON RISING EDGE OF SCLK AS
DETERMINED BY CONTROL BITS. IN THIS CASE, DATA WOULD BE CLOCKED OUT OF SDO ON FALLING
EDGE OF SCLK. TIMING AS PER ABOVE, WITH SCLK INVERTED.

DB15 (N) DB0 (N)

2

t

3

DB15
(N+1)

t

9

DB15(N)

DB0 (N+1)

DB0(N)

t

7

t

8

Figure 2. Daisy-chain and Readback Modes Timing Diagram

REV. 0–4–

AD5426/AD5432/AD5443

ABSOLUTE MAXIMUM RATINGS

(TA = 25°C, unless otherwise noted.)

1, 2

VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

V

REF, RFB

I

OUT

Logic Inputs and Output

to GND . . . . . . . . . . . . . . . . . . . . . . –12 V to +12 V

1, I

2 to GND . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

OUT

3

. . . . . . . . . . . –0.3 V to VDD + 0.3 V

Operating Temperature Range

Extended Industrial (Y Version) . . . . . . . . –40°C to +125°C

Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C

10-lead MSOP θ

Thermal Impedance . . . . . . . . . . . 206°C/W

JA

Lead Temperature, Soldering (10 seconds) . . . . . . . . . . 300°C

IR Reflow, Peak Temperature (<20 seconds) . . . . . . . . 235°C

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma­nent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.

2

Transient currents of up to 100 mA will not cause SCR latchup.

3

Overvoltages at SCLK, SYNC, and DIN, will be clamped by internal diodes.

ORDERING GUIDE

I

OL

V

+ V

OH (MIN)

I

OH

OL (MAX)

2

TO

OUTPUT

PIN

C

L

20pF

200␮A

200␮A

Figure 3. Load Circuit for SDO Timing Specifications

Resolution INL Package Package

Model (Bit) (LSB) Temperature Range Description Branding Option

AD5426YRM 8 ±0.25 –40°C to +125°C MSOP D1Q RM-10
AD5426YRM-REEL 8 ±0.25 –40°C to +125°C MSOP D1Q RM-10
AD5426YRM-REEL7 8 ± 0.25 –40°C to +125°C MSOP D1Q RM-10
AD5432YRM 10 ± 0.5 –40°C to +125°C MSOP D1R RM-10
AD5432YRM-REEL 10 ± 0.5 –40°C to +125°C MSOP D1R RM-10
AD5432YRM-REEL7 10 ±0.5 –40°C to +125°C MSOP D1R RM-10
AD5443YRM 12 ± 1 –40°C to +125°C MSOP D1S RM-10
AD5443YRM-REEL 12 ± 1 –40°C to +125°C MSOP D1S RM-10
AD5443YRM-REEL7 12 ±1 –40°C to +125°C MSOP D1S RM-10
EVAL-AD5426EB Evaluation Kit
EVAL-AD5432EB Evaluation Kit
EVAL-AD5443EB Evaluation Kit

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD5426/AD5432/AD5443 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.

REV. 0

–5–

AD5426/AD5432/AD5443

PIN CONFIGURATION

I

1

110

OUT

I

2

29

OUT

GND

SCLK

SDIN

AD5426/
AD5432/

38

AD5443

47

(Not to Scale)

56

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Function

1I

2I

1 DAC Current Output.

OUT

2 DAC Analog Ground. This pin should normally be tied to the analog ground of the system.

OUT

3GND Ground Pin.

4 SCLK Serial Clock Input. By default, data is clocked into the input shift register on the falling edge of the serial

clock input. Alternatively, by means of the serial control bits, the device may be configured such that data is
clocked into the shift register on the rising edge of SCLK.

5SDIN Serial Data Input. Data is clocked into the 16-bit input register on the active edge of the serial clock input.

By default, on power-up, data is clocked into the shift register on the falling edge of SCLK. The control bits
allow the user to change the active edge to rising edge.

6 SYNC Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes

low, it powers on the SCLK and DIN buffers, and the input shift register is enabled. Data is loaded to the
shift register on the active edge of the following clocks (power-on default is falling clock edge). In standalone
mode, the serial interface counts clocks and data is latched to the shift register on the 16th active clock edge.

7SDO Serial Data Output. This allows a number of parts to be daisy-chained. By default, data is clocked into the

shift register on the falling edge and out via SDO on the rising edge of SCLK. Data will always be clocked
out on the alternate edge to loading data to the shift register. Writing the Readback control word to the
shift register makes the DAC register contents available for readback on the SDO pin, clocked out on the
opposite edges to the active clock edge.

8V

9V

10 R

DD

REF

FB

Positive Power Supply Input. These parts can be operated from a supply of 3 V to 5.5 V.

DAC Reference Voltage Input.

DAC Feedback Resistor pin. Establish voltage output for the DAC by connecting to external amplifier output.

R

FB

V

REF

V

DD

SDO

SYNC

REV. 0–6–

Typical Performance Characteristics–AD5426/AD5432/AD5443

0.20
TA = 25ⴗC

= 10V

V

0.15

REF

= 5V

V

DD

0.10

0.05

0

INL (LSB)

–0.05

–0.10

–0.15

–0.20

050100 150 250200

CODE

TPC 1. INL vs. Code (8-Bit DAC)

0.20
TA = 25ⴗC

= 10V

V

0.15

REF

= 5V

V

DD

0.10

0.05

0

DNL (LSB)

–0.05

–0.10

–0.15

–0.20

0 200

50 100 150 250

CODE

TPC 4. DNL vs. Code (8-Bit DAC)

0.5
TA = 25ⴗC

0.4

0.3

0.2

0.1

INL (LSB)

–0.1

–0.2

–0.3

–0.4

–0.5

= 10V

V

REF

= 5V

V

DD

0

0 200 400 800600 1000

CODE

TPC 2. INL vs. Code (10-Bit DAC)

0.5

TA = 25ⴗC

0.4

0.3

0.2

0.1

–0.1

DNL (LSB)

–0.2

–0.3

–0.4

–0.5

= 10V

V

REF

= 5V

V

DD

0

0 200 400 800600 1000

CODE

TPC 5. DNL vs. Code (10-Bit DAC)

1.0
TA = 25ⴗC

0.8

0.6

0.4

0.2

INL (LSB)

–0.2

–0.4

–0.6

–0.8

–1.0

= 10V

V

REF

= 5V

V

DD

0

0 500 1000 1500 2000 2500 3000 3500 4000

CODE

TPC 3. INL vs. Code (12-Bit DAC)

1.0
TA = 25ⴗC

0.8

0.6

0.4

0.2

–0.2

DNL (LSB)

–0.4

–0.6

–0.8

–1.0

= 10V

V

REF

= 5V

V

DD

0

0 500 1000 2000 2500 3000 35001500 4000

CODE

TPC 6. DNL vs. Code (12-Bit DAC)

0.6

0.5

0.4

0.3

0.2

0.1

INL (LSB)

0

–0.1

–0.2

–0.3

2345678910

MAX INL

MIN INL

REFERENCE VOLTAGE

TA = 25ⴗC

= 10V

V

REF

= 5V

V

DD

AD5443

TPC 7. INL vs. Reference Voltage

–0.40

TA = 25ⴗC

= 10V

V

REF

= 5V

V

–0.45

DD

AD5443

–0.50

–0.55

DNL (LSB)

–0.60

MIN DNL

–0.65

–0.70

2345678910

REFERENCE VOLTAGE

TPC 8. DNL vs. Reference Voltage

5

4

3

2

1

0

–1

ERROR (mV)

–2

–3

–4

V

–5

–60 –40 –20 0 20 40 60 80 100 120 140

REF

= 10V

VDD = 5V

VDD = 3V

TEMPERATURE (ⴗC)

TPC 9. Gain Error vs. Temperature

REV. 0

–7–

AD5426/AD5432/AD5443

2.0

1.5

LSB

–0.5

–1.0

–1.5

–2.0

1.0

0.5

0

MAX INL

MAX DNL

MIN INL

MIN DNL

0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
V

BIAS

TPC 10. Linearity vs. V

Voltage Applied to I

0.5

0.4

0.3

0.2

0.1

0

–0.1

VOLTAGE (mV)

–0.2

–0.3

–0.4

–0.5

OFFSET ERROR

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

V

BIAS

TA = 25ⴗC
V

REF

V

DD

AD5443

(V)

BIAS

OUT2

GAIN ERROR

TA = 25ⴗC

= 2.5V

V

REF

= 3V AND 5V

V

DD

(V)

= 0V

= 3V

TPC 13. Gain and Offset Errors
vs. V

Voltage Applied to I

BIAS

OUT2

4

TA = 25ⴗC

3

= 2.5V

V

REF

= 3V

V

DD

2

AD5443

1

0

LSB

–1

–2

–3

–4

–5

0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0

MAX INL

V

BIAS

(V)

TPC 11. Linearity vs. V
Voltage Applied to I

3

2

1

MAX DNL

0.5 1.0 2.5

LSB

–1

–2

–3

0

MIN INL

MIN DNL

V

BIAS

MAX INL

1.5 2.0

(V)

TPC 14. Linearity vs. V
Voltage Applied to I

MAX DNL

MIN DNL

MIN INL

BIAS

OUT2

TA = 25ⴗC
V

REF

= 5V

V

DD

AD5443

BIAS

OUT2

= 0V

0.5

TA = 25ⴗC

0.4

0.3

0.2

0.1

–0.1

VOLTAGE (mV)

–0.2

–0.3

–0.4

–0.5

= 0V

V

REF

= 3V AND 5V

V

DD

0

0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
V

OFFSET ERROR

(V)

BIAS

GAIN ERROR

TPC 12. Gain and Offset Errors vs.
V

Voltage Applied to I

BIAS

4

TA = 25ⴗC

= 2.5V

V

3

REF

= 5V

V

DD

AD5443

2

1

0

LSB

–1

–2

–3

–4

–5

0.5 1.0 1.5 2.0

MAX DNL

V

BIAS

TPC 15. Linearity vs. V
Voltage Applied to I

(V)

OUT2

MIN DNL

MIN INL

OUT2

MAX INL

BIAS

0.7

0.6

0.5

0.4

0.3

CURRENT (mA)

0.2

0.1

0

VDD = 5V

TA = 25ⴗC

VDD = 3V

INPUT VOLTAGE (V)

TPC 16. Supply Current vs.
Logic Input Voltage,
(SCLK, DATA = 0)

SYNC

1.6

1.4

1.2

1.0

0.8

LEAKAGE (nA)

0.6

OUT

I

0.4

0.2

543210

0

–40 –20 0 20 40 60 80 100 120

TPC 17. I
vs. Temperature

I

OUT1 VDD

TEMPERATURE (

Leakage Current

OUT1

I

OUT1 VDD

3V

ⴗ

C)

5V

0.50

0.45

0.40

0.35

A)

0.30

␮

0.25

0.20

CURRENT (

0.15
ALL 1s

0.10

0.05

0

–40

–60 –20 0 20 40 60 80 100 140

VDD = 5V

VDD = 3V

ALL 0s

TEMPERATURE (

ⴗ

C)

ALL 0s

ALL 1s

TA = 25ⴗC

TPC 18. Supply Current vs.
Temperature

120

REV. 0–8–

AD5426/AD5432/AD5443

3.5
TA = 25ⴗC
AD5443

3.0
LOADING 010101010101

2.5

2.0

(A)

DD

I

1.5

VCC = 5V

1.0

0.5

0

FREQUENCY (Hz)

VCC = 3V

10M1M100k10k1k100101

TPC 19. Supply Current vs.
Update Rate

3.00

TA = 25ⴗC
V

= 5V

DD

AD8038 AMPLIFIER

0.00

–3.00

GAIN (dB)

–6.00

V

= ⴞ2V, AD8038 CC 1.47pF

REF

= ⴞ2V, AD8038 CC 1pF

V

REF

V

= ⴞ0.15V, AD8038 CC 1pF

REF

= ⴞ0.15V, AD8038 CC 1.47pF

V

REF

= ⴞ3.51V, AD8038 CC 1.8pF

V

REF

–9.00

10k 100k 1M 10M 100M

FREQUENCY (Hz)

TPC 22. Reference Multiplying
Bandwidth vs. Frequency and
Compensation Capacitor

100M

6

TA = 25ⴗC
LOADING
ZS TO FS

ALL ON

DB11

DB10

DB9

DB8

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

ALL OFF

FREQUENCY (Hz)

TA = 25ⴗC

V

= 5V

DD

= ⴞ3.5V

V

REF

INPUT

= 1.8pF

C

COMP

AD8038 AMPLIFIER

0

–6
–12
–18
–24
–30
–36
–42
–48
–54

GAIN (dB)

–60
–66
–72
–78
–84
–90
–96

–102

110100 1k 10k 100k 1M 10M 100M

TPC 20. Reference Multiplying
Bandwidth vs. Frequency and Code

0.060

VDD 5V, 0V REF
NRG = 2.049nVs

0.050

7FFH TO 800H

0.040

0.030

0.020

0.010

OUTPUT VOLTAGE (V)

0.000

–0.010

–0.020

VDD 3V, 0V REF
NRG = 0.088nVs
800H TO 7FFH

VDD 5V, 0V REF
NRG = 0.119nVs,
800H TO 7FFH

TIME (ns)

TA = 25ⴗC
V

REF

AD8038 AMP
C

COMP

AD5443

VDD 3V, 0V REF
NRG = 1.877nVs
7FFH TO 800H

= 0V

= 1.8pF

250200150100500

300

TPC 23. Midscale Transition
V

= 0 V

REF

0.2

0

–0.2

GAIN (dB)

–0.4

TA = 25ⴗC
V

= 5V

DD

–0.6

–0.8

= ⴞ3.5V

V

REF

= 1.8pF

C

COMP

AD8038 AMPLIFIER

110100 1k 10k 100k 1M 100M

FREQUENCY (Hz)

10M

TPC 21. Reference Multiplying
Bandwidth—All Ones Loaded

–1.700

VDD 5V, 3.5V REF
NRG = 1.184nVs
7FFH TO 800H

–1.710

–1.720

–1.730

–1.740

OUTPUT VOLTAGE (V)

VDD 3V, 3.5V REF
NRG = 1.433nVs
7FFH TO 800H

VDD 3V, 3.5V REF
NRG = 0.647nVs
800H TO 7FFH

TA = 25ⴗC
V

= 3.5V

REF

AD8038 AMP
C

= 1.8pF

COMP

AD5443

–1.750

VDD 5V, 3.5V REF, NRG = 0.364nVs,

–1.760

800H TO 7FFH

TIME (ns)

250

200150100500

TPC 24. Midscale Transition
V

= 3.5 V

REF

300

20

TA = 25ⴗC

= 3V

V

DD

0

AMP = AD8038

–20

–40

–60

–80

FULL SCALE

ZERO SCALE

PSRR (dB)

–100

–120

110100 1k 10k 100k 1M 10M

FREQUENCY (Hz)

TPC 25. Power Supply Rejection vs.
Frequency

REV. 0

–60

TA = 25ⴗC

= 3V

V

DD

–65

V

REF

= 3.5V p-p

–70

–75

THD + N (dB)

–80

–85

–90

110100 1k 10k 100k 1M

FREQUENCY (Hz)

TPC 26. THD and Noise vs.
Frequency

–9–

0.7

0.6

0.5

0.4

V

DD

0.3

CURRENT (␮A)

0.2

V

0.1

DD

= 3V

0

TEMPERATURE (ⴗC)

TPC 27. Supply Current
vs. Temperature

= 5V

ALL 1s
ALL 0s

100806040200–20–40

120

AD5426/AD5432/AD5443

1.8

TA = 25ⴗC

1.6

1.4

1.2

1.0

0.8

0.6

0.4

THRESHOLD VOLTAGE (V)

0.2

0

V

IH

VOLTAGE (V)

TPC 28. Threshold Voltages
vs. Supply Voltage

0

–10

–20

–30

–40

–50

–60

SFDR (dB)

–70

–80

–90

–100

50

100 150 200 250 300

0

FREQUENCY (Hz)

TPC 31. Wideband SFDR
f

= 50 kHz, Update = 1 MHz

OUT

V

IL

TA = 25ⴗC
V

REF

AD8038 AMP
AD5443

350 400 450 500

5.04.54.03.53.02.5

= 3.5V

5.5

100

80

60

40

SFDR (dB)

20

0

MCLK = 1MHz

TA = 25ⴗC
V

= 3.5V

REF

AD8038 AMP
AD5443

MCLK = 200kHz

MCLK = 500kHz

3020100

f

(kHz)

OUT

TPC 29. Wideband SFDR vs.
f

Frequency (AD5443)

OUT

0

–10

–20

–30

–40

–50

–60

SFDR (dB)

–70

–80

–90

–100

0

100 150 200 250 300

50

FREQUENCY (Hz)

TA = 25ⴗC
V
AD8038 AMP

AD5443

350 400 450 500

TPC 32. Wideband SFDR
f

= 20 kHz, Update = 1 MHz

OUT

REF

40

= 3.5V

80

60

40

SFDR (dB)

TA = 25ⴗC

20

V

REF

AD8038 AMP
AD5426

50

0

MCLK = 500kHz

MCLK = 1MHz

= 3.5V

f

OUT

MCLK = 200kHz

3020100

(kHz)

50

40

TPC 30. Wideband SFDR vs.
f

Frequency (AD5426)

OUT

0

–10

–20

–30

–40

–50

–60

SFDR (dB)

–70

–80

–90

–100

25

35 40 45 50 55

30

FREQUENCY (Hz)

TA = 25ⴗC
V

= 3.5V

REF

AD8038 AMP
AD5443

60 65 70 75

TPC 33. Narrowband (±50%)
SFDR f

= 50 kHz,

OUT

Update = 1 MHz

0

–10

–20

–30

–40

–50

–60

SFDR (dB)

–70

–80

–90

–100

12

14 16 18 20 22

10

FREQUENCY (Hz)

TPC 34. Narrowband (±50%)
SFDR f

= 20 kHz,

OUT

Update = 1 MHz

TA = 25ⴗC
V

= 3.5V

REF

AD8038 AMP
AD5443

24 26 28 30

0

TA = 25ⴗC

–10

V

= 3.5V

REF

AD8038 AMP

–20

AD5443

–30

–40

–50

dB

–60

–70

–80

–90

–100

10 15 20 25 3530

FREQUENCY (Hz)

TPC 35. Narrowband (±50%)
IMD, f

= 20 kHz, 25 kHz,

OUT

Update = 1 MHz

REV. 0–10–

AD5426/AD5432/AD5443

TERMINOLOGY
Relative Accuracy

Relative accuracy or endpoint nonlinearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
adjusting for 0 and full scale and is normally expressed in LSBs
or as a percentage of full-scale reading.

Differential Nonlinearity

Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of –1 LSB max over
the operating temperature range ensures monotonicity.

Gain Error

Gain error or full-scale error is a measure of the output error
between an ideal DAC and the actual device output. For these
DACs, ideal maximum output is V

– 1 LSB. Gain error of

REF

the DACs is adjustable to 0 with external resistance.

Output Leakage Current

Output leakage current is current that flows in the DAC ladder
switches when these are turned off. For the I

1 terminal, it

OUT

can be measured by loading all 0s to the DAC and measuring
the I

1 current. Minimum current will flow in the I

OUT

OUT

2 line

when the DAC is loaded with all 1s.

Output Capacitance

Capacitance from I

Output Current Settling Time

OUT

1 or I

2 to AGND.

OUT

This is the amount of time it takes for the output to settle to a
specified level for a full scale input change. For these devices, it
is specified with a 100 Ω resistor to ground.

The settling time specification includes the digital delay from
SYNC rising edge to the full-scale output charge.

Digital to Analog Glitch Impulse

The amount of charge injected from the digital inputs to the
analog output when the inputs change state. This is normally
specified as the area of the glitch in either pA-secs or nV-secs
depending upon whether the glitch is measured as a current or
voltage signal.

Digital Feedthrough

When the device is not selected, high frequency logic activity on
the device digital inputs may be capacitively coupled through the
device to show up as noise on the I

pins and subsequently

OUT

into the following circuitry. This noise is digital feedthrough.

Multiplying Feedthrough Error

This is the error due to capacitive feedthrough from the DAC
reference input to the DAC I

1 terminal, when all 0s are

OUT

loaded to the DAC.

Total Harmonic Distortion (THD)

The DAC is driven by an ac reference. The ratio of the rms
sum of the harmonics of the DAC output to the fundamental
value is the THD. Usually only the lower order harmonics are
included, such as second to fifth.

VVVV

+++

2232425

THD

=

20

Digital Intermodulation Distortion

()

log

V

1

2

Second-order intermodulation distortion (IMD) measurements
are the relative magnitude of the fa and fb tones generated digi­tally by the DAC and the second-order products at 2fa – fb and
2fb – fa.

Spurious-Free Dynamic Range (SFDR)

It is the usable dynamic range of a DAC before spurious noise
interferes or distorts the fundamental signal. SFDR is the mea­sure of difference in amplitude between the fundamental and
the largest harmonically or nonharmonically related spur from
dc to full Nyquist bandwidth (half the DAC sampling rate, or

/2). Narrow band SFDR is a measure of SFDR over an arbi-

f

S

trary window size, in this case 50% of the fundamental. Digital
SFDR is a measure of the usable dynamic range of the DAC
when the signal is digitally generated sine wave.

REV. 0

–11–

AD5426/AD5432/AD5443

DAC SECTION

The AD5426, AD5432, and AD5443 are 8-, 10-, and 12-bit cur­rent output DACs consisting of a standard inverting R-2R ladder
configuration. A simplified diagram for the 8-bit AD54246 is
shown in Figure 4. The feedback resistor R

has a value of R.

FB

The value of R is typically 10 kΩ (minimum 8 kΩ and maximum
12 kΩ). If I

OUT

1 and I

are kept at the same potential, a con-

OUT2

stant current flows in each ladder leg, regardless of digital input
code. Therefore, the input resistance presented at V
constant and nominally of value R. The DAC output (I

is always

REF

OUT

) is
code-dependent, producing various resistances and capacitances.
External amplifier choice should take into account the variation
in impedance generated by the DAC on the amplifiers inverting
input node.

V

REF

DAC DATA LATCHES

2RS12RS22R

AND DRIVERS

RRR

2RS82R

S3

R

A

R

FB

I

1

OUT

2

I

OUT

Figure 4. Simplified Ladder

Access is provided to the V

REF

, RFB, I

OUT

1, and I

2 terminals

OUT

of the DAC, making the device extremely versatile and allowing
it to be configured in several different operating modes, for
example, to provide a unipolar output, 4-quadrant multiplica­tion in bipolar mode, or in single-supply modes of operation.
Note that a matching switch is used in series with the internal

feedback resistor. If users attempt to measure RFB, power

R

FB

must be applied to V

to achieve continuity.

DD

SERIAL INTERFACE

The AD5426/AD5432/AD5443 have an easy to use 3-wire inter­face that is compatible with SPI/QSPI/MICROWIRE and DSP
interface standards. Data is written to the device in 16 bit words.
This 16-bit word consists of 4 control bits and either 8, 10, or
12 data bits as shown in Figure 5. The AD5443 uses all 12 bits of
DAC data. The AD5432 uses 10 bits and ignores the 2 LSBs,
while the AD5426 uses 8 bits and ignores the last 4 bits.

Low Power Serial Interface

To minimize the power consumption of the device, the interface
powers up fully only when the device is being written to, i.e., on
the falling edge of SYNC. The SCLK and D

input buffers are

IN

powered down on the rising edge of SYNC.

DAC Control Bits C3 to C0

Control Bits C3 to C0 allow control of various functions of the
DAC as seen in Table I. Default settings of the DAC on power
on are as follows:

Data clocked into shift register on falling clock edges; daisy-chain
mode is enabled. Device powers on with zero-scale load to the
DAC register and I

OUT

lines.

The DAC control bits allow the user to adjust certain features
on power-on, for example, daisy-chaining may be disabled if not
in use, active clock edge may be changed to rising edge, and DAC
output may be cleared to either zero or midscale. The user may
also initiate a readback of the DAC register contents for verifi­cation purposes.

Table I. DAC Control Bits

C3 C2 C1 C0 Function Implemented

0000 No Operation (Power-On Default)
0001 Load and Update
0010 Initiate Readback
0011 Reserved
0100 Reserved
0101 Reserved
0110 Reserved
0111 Reserved
1000 Reserved
1001 Daisy-chain Disable
1010 Clock Data to Shift Register On Rising Edge
1011 Clear DAC Output to Zero
1100 Clear DAC Output to Midscale
1101 Reserved
1110 Reserved
1111 Reserved

DB15 (MSB)

C3 C2 C1 C0

CONTROL BITS

DB7 DB6 DB5 DB4 DB3 DB2 DB0DB1

DATA BITS

Figure 5a. AD5426 8-Bit Input Shift Register Contents

DB15 (MSB)

C3 C2 C1 C0

CONTROL BITS

DB7 DB6DB8DB9

DB5 DB4 DB3 DB2 DB0DB1

DATA BITS

Figure 5b. AD5432 10-Bit Input Shift Register Contents

DB15 (MSB)

C3 C2 C1 C0

CONTROL BITS

DB11 DB10

DB9

DB8

DB7 DB6 DB5 DB4

DATA BITS

Figure 5c. AD5443 12-Bit Input Shift Register Contents

XX

DB3 DB2

DB0 (LSB)

XX

DB0 (LSB)

XX

DB0 (LSB)

DB1

DB0

REV. 0–12–

AD5426/AD5432/AD5443

SYNC Function

SYNC is an edge-triggered input that acts as a frame synchroni­zation signal and chip enable. Data can be transferred into the
device only while SYNC is low. To start the serial data transfer,
SYNC should be taken low observing the minimum SYNC
falling to SCLK falling edge setup time, t

.

4

Daisy-Chain Mode

Daisy-chain is the default power-on mode. To disable the daisy­chain function, write 1001 to control word. In daisy-chain mode
the internal gating on SCLK is disabled. The SCLK is continuously
applied to the input shift register when SYNC is low. If more
than 16 clock pulses are applied, the data ripples out of the shift
register and appears on the SDO line. This data is clocked out on
the rising edge of SCLK (this is the default, use the control word
to change the active edge) and is valid for the next device on the
falling edge (default). By connecting this line to the D

input on

IN

the next device in the chain, a multidevice interface is constructed.
16 clock pulses are required for each device in the system. There­fore, the total number of clock cycles must equal 16N where N is
the total number of devices in the chain. See the timing diagram
in Figure 3.

When the serial transfer to all devices is complete, SYNC should
be taken high. This prevents any further data being clocked into
the input shift register. A burst clock containing the exact number
of clock cycles may be used and SYNC taken high some time
later. After the rising edge of SYNC, data is automatically trans­ferred from each device’s input shift register to the addressed DAC.

When control bits = 0000, the device is in No Operation mode.
This may be useful in daisy-chain applications where the user
does not want to change the settings of a particular DAC in the
chain. Simply write 0000 to the control bits for that DAC and
the following data bits will be ignored.

Standalone Mode

After power-on, write 1001 to control word to disable daisy-chain
mode. The first falling edge of SYNC resets a counter that counts
the number of serial clocks to ensure the correct number of bits
are shifted in and out of the serial shift registers. A rising edge on
SYNC during a write causes the write cycle to be aborted.

After the falling edge of the 16th SCLK pulse, data will automati­cally be transferred from the input shift register to the DAC. For
another serial transfer to take place, the counter must be reset by
the falling edge of SYNC.

CIRCUIT OPERATION
Unipolar Mode

Using a single op amp, these devices can easily be configured to
provide 2-quadrant multiplying operation or a unipolar output
voltage swing as shown in Figure 6.

When an output amplifier is connected in unipolar mode, the
output voltage is given by

VV

=×–

OUT REF

D

n

2

where D is the fractional representation of the digital word
loaded to the DAC, and n is the number of bits.

D= 0 to 255 (8-bit AD5426)

= 0 to 1023 (10-bit AD5432)
= 0 to 4095 (12-bit AD5443)

Note that the output voltage polarity is opposite to the V

REF

polarity for dc reference voltages.

REV. 0

–13–

These DACs are designed to operate with either negative or
positive reference voltages. The V

power pin is used by

DD

only the internal digital logic to drive the DAC switches’ on
and off states.

These DACs are also designed to accommodate ac reference
input signals in the range of –10 V to +10 V.

V

DD

V

DD

V

REF

V

R1

NOTES

1. R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.

2. C1 PHASE COMPENSATION (1pF – 2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.

AD5426/

REF

AD5432/AD5443

SCLK SDIN GND

SYNC

MICROCONTROLLER

R2

R

FB

I

OUT

I

OUT

C1

1

2

AGND

A1

V

OUT

0 TO –V

=

REF

Figure 6. Unipolar Operation

With a fixed 10 V reference, the circuit shown in Figure 6 will
give a unipolar 0 V to –10 V output voltage swing. When V

IN

is an ac signal, the circuit performs 2-quadrant multiplication.

Table II shows the relationship between digital code and expected
output voltage for unipolar operation (AD5426, 8-bit device).

Table II. Unipolar Code Table

Digital Input Analog Output (V)

1111 1111 –V
1000 0000 –V
0000 0001 –V
0000 0000 –V

(255/256)

REF

(128/256) = –V

REF

(1/256)

REF

(0/256) = 0

REF

REF

/2

Bipolar Operation

In some applications, it may be necessary to generate full
4-quadrant multiplying operation or a bipolar output swing.
This can be easily accomplished by using another external
amplifier and some external resistors as shown in Figure 7. In
this circuit, the second amplifier A2 provides a gain of 2. Bias­ing the external amplifier with an offset from the reference
voltage results in full 4-quadrant multiplying operation. The
transfer function of this circuit shows that both negative and
positive output voltages are created as the input data (D) is
incremented from code zero (V

= 0 V ) to full scale (V

(V

OUT

VV

=×

OUT REF

OUT

OUT






= –V

= +V

D

1–

n

2

REF

).

REF



V

–



REF



) to midscale

where D is the fractional representation of the digital word
loaded to the DAC and n is the resolution of the DAC.

D= 0 to 255 (8-bit AD5426)

= 0 to 1023 (10-bit AD5432)
= 0 to 4095 (12-bit AD5443)

When V

is an ac signal, the circuit performs 4-quadrant

IN

multiplication.

AD5426/AD5432/AD5443

V

REF

10V

ⴞ

R1

V

REF

AD5432/AD5443

SYNC

V

DD

V

DD

AD5426/

SCLK SDIN

R

FB

GND

10k

I

I

R3

OUT

OUT

⍀

R2

C1

1

2

A1

10k

R4

⍀

R5

20k

⍀

A2

V

=

OUT

to +V

–V

REF

REF

MICROCONTROLLER

NOTES

1. R1 AND R2 ARE USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.
ADJUST R1 FOR V

2. MATCHING AND TRACKING IS ESSENTIAL FOR RESISTOR PAIRS R3 AND R4.

3. C1 PHASE COMPENSATION (1pF–2pF) MAY BE REQUIRED IF A1/A2 IS
A HIGH SPEED AMPLIFIER.

= 0 V WITH CODE 10000000 LOADED TO DAC.

OUT

Figure 7. Bipolar Operation

Table III shows the relationship between digital code and the
expected output voltage for bipolar operation (AD5426, 8-bit
device).

Table III. Bipolar Code Table

Digital Input Analog Output (V)

1111 1111 +V

(127/128)

REF

1000 0000 0
0000 0001 –V
0000 0000 –V

(127/128)

REF

(128/128)

REF

Stability

In the I-to-V configuration, the I

of the DAC and the invert-

OUT

ing node of the op amp must be connected as close as possible,
and proper PCB layout techniques must be employed. Since
every code change corresponds to a step function, gain peaking
may occur if the op amp has limited GBP and there is excessive
parasitic capacitance at the inverting node. This parasitic capaci­tance introduces a pole into the open-loop response which can
cause ringing or instability in closed-loop applications.

An optional compensation capacitor, C1 can be added in parallel with

for stability as shown in Figures 6 and 7. Too small a value of

R

FB

C1 can produce ringing at the output, while too large a value can
adversely affect the settling time. C1 should be found empirically
but 1 pF to 2 pF is generally adequate for compensation.

SINGLE-SUPPLY APPLICATIONS
Current Mode Operation

These DACs are specified and tested to guarantee operation in
single-supply applications. Figure 8 shows a typical circuit for
operation with a single 3.0 V to 5 V supply. In the current mode
circuit of Figure 8, I

OUT2

an amount applied to V

and hence I

.

BIAS

1 is biased positive by

OUT

AGND

V

DD

V

V

IN

V

REF

GND

NOTES

1. ADDITIONAL PINS OMITTED FOR CLARITY

2. C1 PHASE COMPENSATION (1pF– 2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.

R

BIAS

FB

I

OUT

I

OUT

A2

DD

V

C1

1

2

A1

V

OUT

Figure 8. Single-Supply Current Mode Operation

In this configuration, the output voltage is given by

VDRRVVV

=×

()

{}

OUT FB DAC BIAS IN BIAS

×−

()

+

As D varies from 0 to 255 (AD5426), 1023 (AD5432) or 4095
(AD5443), the output voltage varies from

VV to V V V

==−2

OUT BIAS OUT BIAS IN

V

should be a low impedance source capable of sinking and

BIAS

sourcing all possible variations in current at the I

2 terminal

OUT

without any problems.

It is important to note that V

is limited to low voltages because

IN

the switches in the DAC ladder no longer have the same source­drain drive voltage. As a result, their on resistance differs, which
degrades the linearity of the DAC. See TPCs 10 to 15.

REV. 0–14–

AD5426/AD5432/AD5443

V

OUT

V

DD

GND

I

OUT

2

I

OUT

1

R

FB

V

DD

V

REF

C1

NOTES

1. ADDITIONAL PINS OMITTED FOR CLARITY

2. C1 PHASE COMPENSATION (1pF– 2pF) MAY BE
REQUIRED IF A1 IS A HIGH SPEED AMPLIFIER.

R

3

R

2

R2

V

IN

R1 = R2R3
R2 + R3

GAIN = R2 + R3
R2

A1

Voltage Switching Mode of Operation

Figure 9 shows these DACs operating in the voltage-switching
mode. The reference voltage, V
I

2 is connected to AGND, and the output voltage is available

OUT

at the V

terminal. In this configuration, a positive reference

REF

, is applied to the I

IN

OUT

1 pin,

voltage results in a positive output voltage making single-supply
operation possible. The output from the DAC is voltage at a
constant impedance (the DAC ladder resistance), thus an
op amp is necessary to buffer the output voltage. The reference
input no longer sees a constant input impedance, but one that
varies with code. So, the voltage input should be driven from a
low impedance source.

V

DD

R

V

FB

V

IN

1

I

OUT

I

2

OUT

NOTES

1. ADDITIONAL PINS OMITTED FOR CLARITY

2. C1 PHASE COMPENSATION (1pF– 2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.

DD

GND

V

REF

R2R1

A1

V

OUT

Figure 9. Single-Supply Voltage Switching
Mode Operation

Also, VIN must not go negative by more than 0.3 V or an internal
diode will turn on, exceeding the max ratings of the device. In
this type of application, the full range of multiplying capability
of the DAC is lost.

POSITIVE OUTPUT VOLTAGE

Note that the output voltage polarity is opposite to the V

REF

polarity for dc reference voltages. To achieve a positive voltage
output, an applied negative reference to the input of the DAC is
preferred over the output inversion through an inverting amplifier
because of the resistor tolerance errors. To generate a negative
reference, the reference can be level shifted by an op amp such
that the V

and GND pins of the reference become the virtual

OUT

ground and –2.5 V, respectively, as shown in Figure 10.

VDD = 5V

ADR03

V

V

IN

OUT

GND

1

2

C1

1/2 AD8552

V

=

OUT

0 to +2.5V

+ 5V

A2 A1

–5V

Figure 10. Positive Voltage Output with Minimum
of Components

–2.5V

1/2 AD8552

NOTES

1. ADDITIONAL PINS OMITTED FOR CLARITY

2. C1 PHASE COMPENSATION (1pF– 2pF) MAY BE
REQUIRED IF A1 IS A HIGH SPEED AMPLIFIER.

V

R

FB

DD

I

V

REF

GND

I

OUT

OUT

resistors of the DAC. Simply placing a resistor in series with the

resistor will causing mismatches in the temperature coefficients,

R

FB

resulting in larger gain temperature coefficient errors. Instead, the
circuit of Figure 11 is a recommended method of increasing the
gain of the circuit. R1, R2, and R3 should all have similar temper­ature coefficients, but they need not match the temperature
coefficients of the DAC. This approach is recommended in circuits
where gains of great than 1 are required.

Figure 11. Increasing Gain of Current Output DAC

USED AS A DIVIDER OR PROGRAMMABLE GAIN
ELEMENT

Current steering DACs are very flexible and lend themselves to
many different applications. If this type of DAC is connected as
the feedback element of an op amp and R

is used as the input

FB

resistor as shown in Figure 12, then the output voltage is
inversely proportional to the digital input fraction D.

For D = 1–2

n

the output voltage is

VVDV

=− =− −

OUT IN IN

−

n

12

()

As D is reduced, the output voltage increases. For small values
of the digital fraction D, it is important to ensure that the
amplifier does not saturate and also that the required accuracy
is met. For example, an 8-bit DAC driven with the binary code
0x10 (00010000), i.e., 16 decimal, in the circuit of Figure 12
should cause the output voltage to be 16 ⫻ V

. However, if the

IN

DAC has a linearity specification of ±0.5 LSB then D can in
fact have the weight anywhere in the range 15.5/256 to 16.5/256
so that the possible output voltage will be in the range 15.5 V

IN

to 16.5 VIN—an error of +3% even though the DAC itself has a
maximum error of 0.2%.

V

V

IN

I

1

OUT

I

2

OUT

DD

V

R

DD

FB

V

REF

GND

V

OUT

ADDING GAIN

In applications where the output voltage is required to be greater
than V
or it can also be achieved in a single stage. It is important to
consider the effect of temperature coefficients of the thin film

REV. 0

, gain can be added with an additional external amplifier

IN

Figure 12. Current Steering DAC Used as a Divider
or Programmable Gain Element

–15–

NOTE
ADDITIONAL PINS OMITTED FOR CLARITY

AD5426/AD5432/AD5443

DAC leakage current is also a potential error source in divider
circuits. The leakage current must be counterbalanced by an
opposite current supplied from the op amp through the DAC.
Since only a fraction D of the current into the V
routed to the I

1 terminal, the output voltage has to change

OUT

terminal is

REF

as follows:

Output Error Voltage Due to DAC Leakage = (Leakage ⫻ R)/D

where R is the DAC resistance at the V

terminal. For a DAC

REF

leakage current of 10 nA, R = 10 kΩ and a gain (i.e., 1/D) of 16
the error voltage is 1.6 mV.

REFERENCE SELECTION

When selecting a reference for use with the AD5426 series of
current output DACs, pay attention to the references output
voltage temperature coefficient specification. This parameter not
only affects the full-scale error, but can also affect the linearity
(INL and DNL) performance. The reference temperature coeffi­cient should be consistent with the system accuracy specifications.
For example, an 8-bit system required to hold its overall specifi­cation to within 1 LSB over the temperature range 0°C to 50°C
dictates that the maximum system drift with temperature should be
less than 78 ppm/°C. A 12-bit system with the same temperature
range to overall specification within 2 LSBs requires a maximum
drift of 10 ppm/°C. By choosing a precision reference with low
output temperature coefficient, this error source can be minimized.
Table IV suggests some references available from Analog Devices
that are suitable for use with this range of current output DACs.

AMPLIFIER SELECTION

The primary requirement for the current-steering mode is an
amplifier with low input bias currents and low input offset volt­age. The input offset voltage of an op amp is multiplied by the
variable gain (due to the code dependent output resistance of
the DAC) of the circuit. A change in this noise gain between
two adjacent digital fractions produces a step change in the
output voltage due to the amplifier’s input offset voltage. This
output voltage change is superimposed on the desired change in
output between the two codes and gives rise to a differential
linearity error, which, if large enough, could cause the DAC to
be nonmonotonic. In general, the input offset voltage should be
a fraction (~ <1/4) of an LSB to ensure monotonic behavior
when stepping through codes.

The input bias current of an op amp also generates an offset at
the voltage output as a result of the bias current flowing in the
feedback resistor R

. Most op amps have input bias currents low

FB

enough to prevent any significant errors in 12-bit applications.

Common-mode rejection of the op amp is important in voltage
switching circuits since it produces a code dependent error at
the voltage output of the circuit. Most op amps have adequate
common-mode rejection for use at 8-, 10-, and 12-bit resolution.

Provided the DAC switches are driven from true wideband low
impedance sources (V

and AGND), they settle quickly. Conse-

IN

quently, the slew rate and settling time of a voltage switching DAC
circuit is determined largely by the output op amp. To obtain
minimum settling time in this configuration, it is important to
minimize capacitance at the V

node (voltage output node in

REF

this application) of the DAC. This is done by using low inputs
capacitance buffer amplifiers and careful board design.

Table IV. Suitable ADI Precision References Recommended for Use with AD5426/AD5432/AD5443 DACs

Part No. Output Voltage Initial Tolerance Temperature Drift 0.1 Hz to 10 Hz Noise Package

ADR01 10 V 0.1% 3 ppm/°C 20 ␮V p-p SC70, TSOT, SOIC
ADR02 5 V 0.1% 3 ppm/°C 10 ␮V p-p SC70, TSOT, SOIC
ADR03 2.5 V 0.2% 3 ppm/°C 10 ␮V p-p SC70, TSOT, SOIC
ADR425 5 V 0.04% 3 ppm/°C 3.4 ␮V p-p MSOP, SOIC

Table V. Some Precision ADI Op Amps Suitable for Use with AD5426/AD5432/AD5443 DACs

Part No. Max Supply Voltage (V) VOS(max) (␮V) IB(max) (nA) GBP (MHz) Slew Rate (V/␮s)

OP97 ±20 25 0.1 0.9 0.2
OP1177 ±18 60 2 1.3 0.7
AD8551 +6 5 0.05 1.5 0.4

Table VI. Listing of Some High Speed ADI Op Amps Suitable for Use with AD5426/AD5432/AD5443 DACs

Max Supply Voltage BW @ A

CL

Slew Rate VOS(max) IB(max)

Part No. (V) (MHz) (V/␮s) (␮V) (nA)

AD8065 ±12 145 180 1500 0.01
AD8021 ±12 200 100 1000 1000
AD8038 ± 5 350 425 3000 0.75
AD9631 ± 5 320 1300 10000 7000

REV. 0–16–

AD5426/AD5432/AD5443

SCLK

TxD

8051*

SYNC

P1.1

SDIN

RxD

AD5426/
AD5432/
AD5443*

*

ADDITIONAL PINS OMITTED FOR CLARITY

Most single-supply circuits include ground as part of the analog
signal range, which in turns requires an amplifier that can handle
rail-to-rail signals, there is a large range of single-supply amplifiers
available from Analog Devices.

MICROPROCESSOR INTERFACING

Microprocessor interfacing to this family of DACs is via a serial bus
that uses standard protocol compatible with microcontrollers and
DSP processors. The communications channel is a 3-wire interface
consisting of a clock signal, a data signal, and a synchronization
signal. The AD5426/AD5432/AD5443 requires a 16-bit word
with the default being data valid on the falling edge of SCLK,
but this is changeable via the control bits in the data-word.

ADSP-21xx to AD5426/AD5432/AD5443 Interface

The ADSP-21xx family of DSPs are easily interface to this family
of DACs without extra glue logic. Figure 13 shows an example of
an SPI interface between the DAC and the ADSP-2191M. SCK
of the DSP drives the serial data line, DIN. SYNC is driven from
one of the port lines, in this case SPIxSEL.

ADSP-2191*

SPIxSEL

MOSI

SCK

*

ADDITIONAL PINS OMITTED FOR CLARITY

SYNC

SDIN

SCLK

AD5426/
AD5432/

AD5443*

Figure 13. ADSP-2191 SPI to AD5426/AD5432/AD5443
Interface

A serial interface between the DAC and DSP SPORT is shown
in Figure 14. In this interface example, SPORT0 is used to
transfer data to the DAC shift register. Transmission is initiated
by writing a word to the Tx register after the SPORT has been
enabled. In a write sequence, data is clocked out on each rising
edge of the DSPs serial clock and clocked into the DAC input
shift register on the falling edge of its SCLK. The update of the
DAC output takes place on the rising edge of the SYNC signal.

Communication between two devices at a given clock speed is
possible when the following specs are compatible: frame sync delay
and frame sync setup and hold, data delay and data setup and
hold, and SCLK width. The DAC interface expects a t

(SYNC

4

falling edge to SCLK falling edge setup time) of 13 ns minimum.
Consult the ADSP-21xx User Manual for information on clock
and frame sync frequencies for the SPORT register.

The SPORT control register should be set up as follows:

TFSW = 1, Alternate Framing
INVTFS = 1, Active Low Frame Signal
DTYPE = 00, Right Justify Data
ISCLK = 1, Internal Serial Clock
TFSR = 1, Frame Every Word
ITFS = 1, Internal Framing Signal
SLEN = 1111, 16-Bit Data-Word

80C51/80L51 to AD5426/AD5432/AD5443 Interface

A serial interface between the DAC and the 8051 is shown in
Figure 15. TxD of the 8051 drives SCLK of the DAC serial
interface, while RxD drives the serial data line, D

. P3.3 is a

IN

bit-programmable pin on the serial port and is used to drive
SYNC. When data is to be transmitted to the switch, P3.3 is
taken low. The 80C51/80L51 transmits data only in 8-bit bytes;
thus, only eight falling clock edges occur in the transmit cycle.
To load data correctly to the DAC, P3.3 is left low after the first
eight bits are transmitted, and a second write cycle is initiated to
transmit the second byte of data. Data on RxD is clocked out of
the microcontroller on the rising edge of TxD and is valid on the
falling edge. As a result, no glue logic is required between the
DAC and microcontroller interface. P3.3 is taken high following
the completion of this cycle. The 8051 provides the LSB of its
SBUF register as the first bit in the data stream. The DAC input
register requires its data with the MSB as the first bit received.
The transmit routine should take this into account.

ADSP-2101/
ADSP-2103/

ADSP-2191*

SCLK

*

ADDITIONAL PINS OMITTED FOR CLARITY

Figure 14. ADSP-2101/ADSP-2103/ADSP-2191 SPORT
to AD5426/AD5432/AD5443 Interface

REV. 0

TFS

AD5426/
AD5432/

AD5443*

SYNC

DT

SDIN

SCLK

Figure 15. 80C51/80L51 to AD5426/AD5432/AD5443
Interface

–17–

AD5426/AD5432/AD5443

SCLK

SCK/RC3

PIC16C6x/7x*

SYNC

RA1

SDIN

SDI /RC4

AD5426/
AD5432/
AD5443*

*

ADDITIONAL PINS OMITTED FOR CLARITY

MC68HC11 Interface to AD5426/AD5432/AD5443 Interface

Figure 16 shows an example of a serial interface between the
DAC and the MC68HC11 microcontroller. The serial peripheral
interface (SPI) on the MC68HC11 is configured for master
mode (MSTR = 1), clock polarity bit (CPOL) = 0, and the clock
phase bit (CPHA) = 1. The SPI is configured by writing to the
SPI control register (SPCR)—see the 68HC11 User Manual.
SCK of the 68HC11 drives the SCLK of the DAC interface, the
MOSI output drives the serial data line (D

) of the AD5516.

IN

The SYNC signal is derived from a port line (PC7). When data is
being transmitted to the AD5516, the SYNC line is taken low
(PC7). Data appearing on the MOSI output is valid on the falling
edge of SCK. Serial data from the 68HC11 is transmitted in 8-bit
bytes with only eight falling clock edges occurring in the transmit
cycle. Data is transmitted MSB first. To load data to the DAC,
PC7 is left low after the first eight bits are transferred, and a second
serial write operation is performed to the DAC. PC7 is taken high
at the end of this procedure.

If the user wants to verify the data previously written to the input
shift register, the SDO line could be connected to MISO of the
MC68HC11, and with SYNC low, the shift register would clock
data out on the rising edges of SCLK.

MC68HC11*

PC7

SCK

MOSI

*

ADDITIONAL PINS OMITTED FOR CLARITY

SYNC

SCLK

SDIN

Figure 16. 68HC11/68L11 to AD5426/AD5432/AD5443
Interface

MICROWIRE to AD5426/AD5432/AD5443 Interface

Figure 17 shows an interface between the DAC and any
MICROWIRE compatible device. Serial data is shifted out on
the falling edge of the serial clock, SK, and is clocked into the
DAC input shift register on the rising edge of SK, which corre­sponds to the falling edge of the DACs SCLK.

MICROWIRE*

SK

SO

CS

*

ADDITIONAL PINS OMITTED FOR CLARITY

SCLK

SDIN

SYNC

Figure 17. MICROWIRE to AD5426/AD5432/AD5443
Interface

AD5426/
AD5432/

AD5443*

AD5426/
AD5432/
AD5443*

PIC16C6x/7x to AD5426/AD5432/AD5443

The PIC16C6x/7x synchronous serial port (SSP) is configured
as an SPI master with the clock polarity bit (CKP) = 0. This is
done by writing to the synchronous serial port control register
(SSPCON). See the PIC16/17 Microcontroller User Manual. In
this example, I/O port RA1 is being used to provide a SYNC signal
and to enable the serial port of the DAC. This microcontroller
transfers only eight bits of data during each serial transfer operation;
therefore, two consecutive write operations are required. Figure 18
shows the connection diagram.

Figure 18. PIC16C6x/7x to AD5426/AD5432/AD5443
Interface

PCB LAYOUT AND POWER SUPPLY DECOUPLING

In any circuit where accuracy is important, careful consideration
of the power supply and ground return layout helps to ensure
the rated performance. The printed circuit board on which the
AD5426/AD5432/AD5443 is mounted should be designed so
that the analog and digital sections are separated, and confined
to certain areas of the board. If the DAC is in a system where
multiple devices require an AGND-to-DGND connection, the
connection should be made at one point only. The star ground
point should be established as close as possible to the device.

These DACs should have ample supply bypassing of 10 ␮F in
parallel with 0.1 ␮F on the supply located as close to the pack­age as possible, ideally right up against the device. The 0.1 ␮F
capacitor should have low effective series resistance (ESR) and
effective series inductance (ESI), such as the common ceramic
types that provide a low impedance path to ground at high
frequencies, to handle transient currents due to internal logic
switching. Low ESR 1 ␮F to 10 ␮F tantalum or electrolytic
capacitors should also be applied at the supplies to minimize
transient disturbance and filter out low frequency ripple.

Fast switching signals such as clocks should be shielded with
digital ground to avoid radiating noise to other parts of the board,
and should never be run near the reference inputs.

Avoid crossover of digital and analog signals. Traces on opposite
sides of the board should run at right angles to each other. This
reduces the effects of feedthrough through the board. A micros­trip technique is by far the best, but not always possible with a
double-sided board. In this technique, the component side of the
board is dedicated to ground plane while signal traces are placed
on the solder side.

It is good practice to employ compact, minimum lead length
PCB layout design. Leads to the input should be as short as
possible to minimize IR drops and stray inductance.

The PCB metal traces between V

and RFB should also be

REF

matched to minimize gain error. To maximize on high frequency
performance, the I-to-V amplifier should be located as close to
the device as possible.

REV. 0–18–

AD5426/AD5432/AD5443

EVALUATION BOARD FOR THE AD5426/AD5432/AD5443
SERIES OF DACS

The board consists of a 12-bit AD5443 and a current to voltage
amplifier AD8065. Included on the evaluation board is a 10 V
reference ADR01. An external reference may also be applied via
an SMB input.

The evaluation kit consists of a CD-ROM with self-installing
PC software to control the DAC. The software simply allows
the user to write a code to the device.

P1–3

P1–2

P1–4

P1–5

P1–13

P1–19
P1–20
P1–21
P1–22
P1–23
P1–24
P1–25
P1–26
P1–27
P1–28
P1–29
P1–30

SCLK

SDIN

SYNC

LDAC

SDO

LK2

J3

J4

J5

J6

A

B

P2–3

P2–2

P2–1

P2–4

SCLK

SDIN

SYNC

SDO/LDAC

C11

0.1␮F

C13

0.1␮F

C15

0.1␮F

+

+

+

4

5

6

C12

10␮F

C14

10␮F

C16

10␮F

U1

SCLK

SDIN

SYNC

SDO/LDAC

AD5426/
AD5432/
AD5443

V

DD

AGND

V

SSVDD1

8

V

DD

10

R

FB

1

I

1

OUT

2

2

I

OUT

37

GND

9

V

REF

V

DD

C3

10␮FC40.1␮F

OPERATING THE EVALUATION BOARD
Power Supplies

The board requires ±12 V, and +5 V supplies. The +12 V V

DD

and VSS are used to power the output amplifier, while the +5 V
is used to power the DAC (V

) and transceivers (VCC).

DD1

Both supplies are decoupled to their respective ground plane
with 10 ␮F tantalum and 0.1 ␮F ceramic capacitors.

Link1 (LK1) is provided to allow selection between the on-board
reference (ADR01) or an external reference applied through J2.
For the AD5426/AD5432/AD5443 use Link2 in the SDO position.

V

DD1

+

C1

0.1␮FC210␮F

V

REF

2

+V

IN

U2

ADR01AR

5

TRIM

GND

R1 = 0⍀

C7 10␮F

C6

4.7pF

V

REF

J2

6

V

OUT

C5

0.1␮F

AD8065AR

LK1

V

SS

2

3

U3

V

DD

C8 0.1␮F

4

V–

V+

7

C9 10␮F

C10 0.1␮F

+

TP1

V

6

+

OUT

J1

4

REV. 0

Figure 19. Schematic of AD5426/AD5432/AD5443 Evaluation Board

–19–

AD5426/AD5432/AD5443

P1

SDO

LK2

SCLK

SDIN

SYNC

SDO/LDAC

J3

J4

J5

J6

SCLK

SDIN

SYNC

SDO/LDAC

U1

C1
C2

C15

C11

U3

C8

C6

R1

VREF

LK1

J2

VREF

C16

C10 C13

TP1

J1
VOUT

C4

U2

C3

C14C9

LDAC

P2

EVAL–AD5426/
AD5432/AD5443EB

VDD1

VDD

VSS

AGND

Figure 20. Silkscreen—Component Side View (Top Layer)

C7

C12

Figure 21. Silkscreen—Component Side View (Bottom Layer)

REV. 0–20–

AD5426/AD5432/AD5443

Overview of AD54xx Devices

Part No. Resolution No. DACs INL tS max Interface Package Features

AD5403* 82±0.25 60 ns Parallel CP-40 10 MHz Bandwidth,

10 ns CS Pulse Width,
4-Quadrant Multiplying Resistors

AD5410* 81±0.25 100 ns Serial RU-16 10 MHz Bandwidth, 50 MHz Serial,

4-Quadrant Multiplying Resistors

AD5413* 82±0.25 100 ns Serial RU-24 10 MHz Bandwidth, 50 MHz Serial,

4-Quadrant Multiplying Resistors

AD5424 8 1 ±0.25 60 ns Parallel RU-16, CP-20 10 MHz Bandwidth,

17 ns CS Pulse Width

AD5425 8 1 ±0.25 100 ns Serial RM-10 Byte Load, 10 MHz Bandwidth,

50 MHz Serial

AD5426 8 1 ±0.25 100 ns Serial RM-10 10 MHz Bandwidth, 50 MHz Serial
AD5428 8 2 ±0.25 60 ns Parallel RU-20 10 MHz Bandwidth,

17 ns CS Pulse Width

AD5429 8 2 ±0.25 100 ns Serial RU-10 10 MHz Bandwidth, 50 MHz Serial
AD5450 8 1 ±0.25 100 ns Serial RJ-8 10 MHz Bandwidth, 50 MHz Serial
AD5404* 10 2 ±0.5 70 ns Parallel CP-40 10 MHz Bandwidth,

17 ns CS Pulse Width,
4-Quadrant Multiplying Resistors

AD5411* 10 1 ±0.5 110 ns Serial RU-16 10 MHz Bandwidth, 50 MHz Serial,

4-Quadrant Multiplying Resistors

AD5414* 10 2 ±0.5 110 ns Serial RU-24 10 MHz Bandwidth, 50 MHz Serial,

4-Quadrant Multiplying Resistors

AD5432 10 1 ±0.5 110 ns Serial RM-10 10 MHz Bandwidth, 50 MHz Serial
AD5433 10 1 ±0.5 70 ns Parallel RU-20, CP-20 10 MHz Bandwidth,

17 ns CS Pulse Width

AD5439 10 2 ±0.5 110 ns Serial RU-16 10 MHz Bandwidth, 50 MHz Serial
AD5440 10 2 ±0.5 70 ns Parallel RU-24 10 MHz Bandwidth,

17 ns CS Pulse Width

AD5451 10 1 ±0.25 110 ns Serial RJ-8 10 MHz Bandwidth, 50 MHz Serial
AD5405 12 2 ±1 120 ns Parallel CP-40 10 MHz Bandwidth,

17 ns CS Pulse Width,
4-Quadrant Multiplying Resistors

AD5412* 12 1 ±1 160 ns Serial RU-16 10 MHz Bandwidth, 50 MHz Serial,

4-Quadrant Multiplying Resistors

AD5415 12 2 ±1 160 ns Serial RU-24 10 MHz Bandwidth, 50 MHz Serial,

4-Quadrant Multiplying Resistors

AD5443 12 1 ±1 160 ns Serial RM-10 10 MHz Bandwidth, 50 MHz Serial
AD5444 12 1 ±0.5 160 ns Serial RM-10 10 MHz Bandwidth, 50 MHz Serial
AD5445 12 1 ±1 120 ns Parallel RU-20, CP-20 10 MHz Bandwidth,

17 ns CS Pulse Width

AD5446 14 1 ±2 180 ns Serial RM-10 10 MHz Bandwidth, 50 MHz Serial
AD5447 12 2 ±1 120 ns Parallel RU-24 10 MHz Bandwidth,

17 ns CS Pulse Width

AD5449 12 2 ±1 160 ns Serial RU-16 10 MHz Bandwidth,

17 ns CS Pulse Width

AD5452 12 1 ±0.5 160 ns Serial RJ-8, RM-8 10 MHz Bandwidth, 50 MHz Serial
AD5453 14 1 ±2 180 ns Serial RJ-8, RM-8 10 MHz Bandwidth, 50 MHz Serial

*Future parts, contact factory for availability

REV. 0

–21–

AD5426/AD5432/AD5443

OUTLINE DIMENSIONS

10-Lead Mini Small Outline Package [MSOP]

(RM-10)

Dimensions shown in millimeters

3.00 BSC

6

10

5

4.90 BSC

1.10 MAX

SEATING
PLANE

0.23

0.08

8ⴗ
0ⴗ

3.00 BSC

PIN 1

0.95

0.85

0.75

0.15

0.00

COPLANARITY

1

0.50 BSC

0.27

0.17

0.10

COMPLIANT TO JEDEC STANDARDS MO-187BA

0.80

0.60

0.40

REV. 0–22–

–23–

D03162–0–1/04(0)

–24–