Datasheet AD5441 Datasheet (ANALOG DEVICES)

12-Bit Serial Input

FEATURES

2.5 V to 5.5 V supply operation
True 12-bit accuracy
5 V operation @ <1 μA
Fast 3-wire serial input
Fast 5 μs settling time

1.9 MHz, 4-quadrant multiply BW
Upgrade for
Standard and rotated pinout

APPLICATIONS

Ideal for PLC applications in industrial control
Programmable amplifiers and attenuators
Digitally controlled calibration and filters
Motion control systems

GENERAL DESCRIPTION

The AD5441 is an improved high accuracy 12-bit multiplying
digital-to-analog converter (DAC) in space-saving 8-lead
packages. Featuring serial input, double buffering, and excellent
analog performance, the AD5441 is ideal for applications where
PC board space is at a premium. Improved linearity and gain
error performance permit reduced part counts through the
elimination of trimming components. Separate input clock and
load DAC control lines allow full user control of data loading
and analog output.

The circuit consists of a 12-bit serial-in/parallel-out shift register, a
12-bit DAC register, a 12-bit CMOS DAC, and control logic.
Serial data is clocked into the input register on the rising edge of
the clock pulse. When the new data-word is clocked in, it is
loaded into the DAC register with the
DAC register is converted to an output current by the DAC.

Consuming only 1 µA from a single 5 V power supply, the
AD5441 is the ideal low power, small size, high performance
solution to many application problems.

The AD5441 is specified over the extended industrial (−40°C to
+125°C) temperature range. It is available in an 8-lead LFCSP
and an 8-lead MSOP.

DAC8043 and DAC8043A

LD

input pin. Data in the

Multiplying DAC

AD5441

FUNCTIONAL BLOCK DIAGRAM

V

DD

V

REF

LD

CLK

SRI

AD5441

DAC

12

DAC REG

12

12-BIT SHIFT

REGISTER

Figure 1.

R

FB

I

OUT

GND

06492-001

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2008 Analog Devices, Inc. All rights reserved.

AD5441

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description......................................................................... 1

Revision History ............................................................................... 2

Specifications..................................................................................... 3

Electrical Characteristics............................................................. 3

Timing Characteristics..................................................................... 4

Absolute Maximum Ratings............................................................ 5

Thermal Resistance ...................................................................... 5

ESD Caution.................................................................................. 5

Pin Configurations and Function Descriptions ...........................6

REVISION HISTORY

1/08—Revision 0: Initial Version

Typical Performance Characteristics ..............................................7

Te r mi n ol o g y .................................................................................... 10

Parameter Definitions.................................................................... 11

General Circuit Information..................................................... 11

Output Impedance ..................................................................... 11

Applications Information.......................................................... 11

Unipolar 2-Quadrant Multiplying ........................................... 11

Bipolar 4-Quadrant Multiplying.............................................. 12

Interface Logic Information...................................................... 12

Digital Section ............................................................................ 12

Outline Dimensions .......................................................................13

Ordering Guide .......................................................................... 13

Rev. 0 | Page 2 of 16

AD5441

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

VDD = 5 V, V

Table 1.

Parameter Symbol Min Typ Max Unit Condition

STATIC PERFORMANCE

Resolution N 12 Bits
Relative Accuracy INL ±0.5 LSB
Differential Nonlinearity DNL ±0.5 LSB All grades monotonic to 12 bits
Gain Error G
Gain Temperature Coefficient
Output Leakage Current I
±25 nA TA = –40°C, +125°C, data = 000H, I
Zero-Scale Error I
±0.15 LSB TA = −40°C, +125°C, data = 000H

REFERENCE INPUT

Input Resistance R
Input Capacitance

ANALOG OUTPUT

Output Capacitance
4 pF Data = FFFH

DIGITAL INPUTS

Digital Input Low VIL 0.8 V
Digital Input High VIH 2.4 V
Input Leakage Current IIL 1 μA V
Input Capacitance

AC CHARACTERISTICS

Output Current Settling Time tS 5 μs To ±0.01% of full-scale, external op amp OP42

0.5 μs To ±0.01% of full-scale, 100 Ω terminated to ground
DAC Glitch Q 40 nVs Data = 000H to FFFH to 000H, V
1 nVs Data = 000H to FFFH to 000H, V
Digital Feedthrough 5 nV Using external op amp OP42
Feedthrough (V
Total Harmonic Distortion THD −85 dB V
Output Noise Density en 17 nV/√Hz 10 Hz to 100 kHz between RFB and I
Multiplying Bandwidth BW 1.9 MHz −3 dB, V

SUPPLY CHARACTERISTICS

Power Supply Range V
Positive Supply Current IDD 10 μA V
Power Dissipation P
Power Supply Sensitivity PSS 0.002 %/% ΔVDD = ±5%

1

These parameters are guaranteed by design and not subject to production testing.

= 10 V, −40°C < TA < +155°C, unless otherwise noted.

REF

±1 LSB Data = FFFH

FSE

1

TCGFS ±5 ppm/°C I

LKG

±0.03 LSB Data = 000H

ZSE

7 15 kΩ Absolute temperature coefficient < 50 ppm/°C

1

1

1

1

) FT 1.4 mV p-p V

OUT/VREF

1

REF

C

5 pF

REF

C

OUT

CIL 4.0 pF V

DD RANGE

DISS

±5 nA Data = 000H, I

1 pF Data = 000H

2.5 5.5 V

2.5 5.5 μW V

pin measured

OUT

pin measured

OUT

= 0 V to 5 V

LOGI C

= 0 V

LOGI C

REF

REF

= 20 V p-p, data = 000H, f = 10 kHz

REF

= 6 V rms, data = FFFH, f = 1 kHz

REF

, V

= 100 mV rms, data = FFFH

REF

= 0 V or VDD

LOGI C

= 0 V or VDD

LOGI C

OUT/VREF

pin measured

OUT

= 0 V, OP42
= 0 V, 100 Ω

OUT

Rev. 0 | Page 3 of 16

AD5441

TIMING CHARACTERISTICS

All input control signals are specified with tR = tF = 2 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2; VDD + 2.5 V
to 5.5 V, V

Table 2. Timing Characteristics

Parameter 2.5 V 5.5 V Unit Conditions/Comments

t

DS

t

DH

t

CH

t

CL

t

LD

t

LD1

t

ASB

= 10 V; temperature range = −40°C to +125°C; all specifications T

REF

10 5 ns min Data setup
5 5 ns min Data hold
15 10 ns min Clock width high
15 10 ns min Clock width low
20 10 ns min Load pulse width
0 0 ns min

0 0 ns min

LD DAC high to MSB CLK high
LSB CLK to

to T

MIN

LD DAC

, unless otherwise noted.

MAX

SRI

CLK

LD

SRI

CLK

LD

FS

V

OUT

ZS

D11 D10D9D8 D6D5 D4D3D2D1D0D7

t

LD1

DATA LOADED MSB(D11) FIRST DAC REGISTER L OAD

t

CL

Dxx

tDSt

t

ASB

DH

t

CH

t

LD

±1LSB

ERROR BAND

6492-005

Figure 2. Timing Diagram

Table 3. Control Logic Truth Table

CLK

1

↑
↑

LD

H Shift register data advanced one bit Latched

L Shift register data advanced one bit Transparent

Serial Shift Register Function DAC Register Function

H or L L No effect Updated with current shift register contents
L

1

equals positive logic transition. ↑

1

↑

No effect Latched all 12 bits

Rev. 0 | Page 4 of 16

AD5441

ABSOLUTE MAXIMUM RATINGS

Table 4.

Parameter Rating

VDD to GND −0.3 V, +8 V
V

to GND ±18 V

REF

RFB to GND ±18 V
Logic Inputs to GND −0.3 V, VDD + 0.3 V
I

to GND −0.3 V, VDD + 0.3 V

OUT

I

Short Circuit to GND 50 mA

OUT

Package Power Dissipation (TJ max − TA)/θ

JA

Maximum Junction Temperature (TJ max) 150°C
Operating Temperature Range −40°C to +125°C
Storage Temperature Range −65°C to +150°C
Lead Temperature (Soldering, 10 sec) 300°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

THERMAL RESISTANCE

θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.

Table 5.

Package Type θ

JA

θ

JC

Unit

8-Lead MSOP 142 44 °C/W
8-Lead LFCSP

1

Exposed pad soldered to application board.

1

75 18 °C/W

ESD CAUTION

Rev. 0 | Page 5 of 16

AD5441

V

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

V

REF

R

I

OUT

GND

FB

1

AD5441

2

TOP VIEW

3

(Not to Scale)

4

V

8

DD

7

CLK

6

SRI

5

LD

06492-003

REF

R

I

OUT

GND

FB

1

AD5441

2

TOP VIEW

3

(Not to Scale)

4

V

8

DD

7

CLK

6

SRI

5

LD

06492-004

Figure 3. 8-Lead LFCSP Pin Configuration

Figure 4. 8-Lead MSOP Pin Configuration

Table 6. Pin Function Descriptions

Pin No. Mnemonic Description

1 V

DAC Reference Input Pin. Establishes DAC full-scale voltage. Constant input resistance vs. code.

REF

2 RFB Internal Matching Feedback Resistor. Connect to external op amp output.
3 I

DAC Current Output, full-scale output 1 LSB less than reference input voltage −V

OUT

REF

.
4 GND Analog and Digital Ground.
5

LD Load Strobe, Level-Sensitive Digital Input. Transfers shift-register data to DAC register while active low.

Table 3 for operation.

See
6 SRI 12-Bit Serial Register Input. Data loads directly into the shift register MSB first. Extra leading bits are ignored.
7 CLK Clock Input. Positive-edge clocks data into shift register.
8 VDD Positive Power Supply Input. Specified range of operation 5 V ± 10%.

Rev. 0 | Page 6 of 16

AD5441

TYPICAL PERFORMANCE CHARACTERISTICS

0.5
TA=25°C

V

= 10V

REF

0.4
V

=3V

DD

0.3

0.2

0.1

0

INL (LSB)

–0.1

–0.2

–0.3

–0.4

–0.5

0 500 1000 1500 2000 2500 3000 3500 4000

CODE

Figure 5. INL vs. Code, 3 V

0.5

TA= 25°C

=10V

V

0.4

REF

=3V

V

DD

0.3

0.2

0.1

0

DNL (LSB)

–0.1

–0.2

–0.3

–0.4

–0.5

0 500 1000 1500 2000 2500 3000 3500 4000

CODE

Figure 6. DNL vs. Code, 3 V

0.25

MAX INL

0.20

0.15

0.10

0.05

0

INL (LSB)

–0.05

–0.10

–0.15

–0.20

MIN INL

012 5 10

37648

REFERENCE VOL TAGE

Figure 7. INL vs. Reference, 5 V

06492-039

06492-037

TA= 25°C
V

= 5V

DD

06492-042

9

0.5
TA=25°C

= 10V

V

REF

0.4

= 5V

V

DD

0.3

0.2

0.1

0

INL (LSB)

–0.1

–0.2

–0.3

–0.4

–0.5

0 500 1000 1500 2000 2500 3000 3500 4000

CODE

Figure 8. INL vs. Code, 5 V

0.5

TA= 25°C

= 10V

V

0.4

REF

= 5V

V

DD

0.3

0.2

0.1

0

DNL (LSB)

–0.1

–0.2

–0.3

–0.4

–0.5

0 500 1000 1500 2000 2500 3000 3500 4000

CODE

Figure 9. DNL vs. Code, 5 V

100

75

50

FREQUENCY

25

0

–1.0 –0. 5 0 0.5 1.0

TOTAL UNADJUST ED ERROR (LSB)

Figure 10. Total Unadjusted Error Histogram

06492-040

06492-038

06492-048

Rev. 0 | Page 7 of 16

AD5441

4

2

0

INL (LSB)

–2

–4

–2000 –1000 0 1000 2000

OP AMP OFFSET, VOS (µV)

Figure 11. Integral Nonlinearity Error vs. External Op Amp

1400

= 25°C

T

A

V

REF

V

DD

OP42

= 10V

= 5V

0.050
TA = 25°C

0.045

0.040

0.035

0.030

0.025

0.020

CURRENT (µA)

0.015

0.010

0.005

0

–60 –40

06492-049

VDD = 3V

VDD = 5V

–20

0 20406080100120

TEMPERATURE ( °C)

06492-044

Figure 14. Supply Current vs. Temperature

50

1200

1000

800

600

CURRENT (µA)

400

200

0

10k 100k 1M 10M 100M

FREQUENCY (Hz)

Figure 12. Supply Current vs. Clock Frequency

0.20
TA = 25°C

0.18

0.16

0.14

0.12

0.10

0.08

CURRENT (µA)

0.06

0.04

0.02

0

0 0. 5 1.0 1.5 2.0 2.5 3.0 3.5 4. 0 4.5 5.0

INPUT VOLTAGE (V)

Figure 13. Supply Current vs. Logic Input Voltage

F55

FFF

800

40

30

20

FREQUENCY

10

06492-035

0

0123

FULL-SCAL E TEMPERATURE COEFFI CIENT (ppm/°C)

06492-046

Figure 15. Full-Scale Output Temperature Coefficient Histogram

5.34

5.32

5.30

5.28

5.26

5.24

5.22

5.20

OUTPUT VO LTAGE (V )

5.18

5.16

06492-043

5.14

5.12
–0.2 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4

LDAC

TIME (µs)

TA = 25°C
V

= 10V

REF

V

= 5V

DD

7FF TO 800
RISING EDGE

6

5

4

3

2

1

0

–1

–2

–3

–4

–5

–6

–7

–8

–9

–10

(V)

LOAD

V

06492-033

Figure 16. Midscale Transitions

Rev. 0 | Page 8 of 16

AD5441

–20

–32

4

–8

ALL BITS

ON

100

TA = 25°C
V

= 10V

REF

V

= 5V

80

60

DD

–44

ATTENUATIO N (dB)

–56

–68

–80

100 1k 10k 100k 1M 10M

FREQUENCY (Hz)

TA = 25°C
V

= 100mV rms

REF

V

= 5V

DD

Figure 17. Reference Multiplying Bandwidth

06492-045

PSRR (dB)

40

20

0

1k 10k 100k 1M 10M

FREQUENCY (Hz)

Figure 18. PSRR vs. Frequency

06492-027

Rev. 0 | Page 9 of 16

AD5441

TERMINOLOGY

Relative Accuracy (INL)

Relative accuracy or endpoint nonlinearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
adjusting for zero and full scale and is normally expressed in
LSBs or as a percentage of the full-scale reading.

Differential Nonlinearity (DNL)

DNL is the difference between the measured change and the
ideal 1 LSB change between any two adjacent codes. A specified
differential nonlinearity of −1 LSB maximum over the operating
temperature range ensures monotonicity.

Gain Error

Gain error or full-scale error is a measure of the output error
between an ideal DAC and the actual device output. For these
DACs, ideal maximum output is V
DACs is adjustable to zero with external resistance.

Zero Scale Error

Calculated from worst-case R

I

(LSB) = (R

ZSE

REF

× I

× 4096)/V

LKG

Output Leakage Current

Output leakage current is the current that flows into the DAC
ladder switches when they are turned off. For the I
it can be measured by loading all 0s to the DAC and measuring
the I

current.

OUT

Output Capacitance

Capacitance from I

1 to AGND.

OUT

Digital-to-Analog Glitch Impulse

The amount of charge injected from the digital inputs to the
analog output when the inputs change state. This is normally
specified as the area of the glitch in either pA-s or nV-s,
depending on whether the glitch is measured as a current or
voltage signal.

− 1 LSB. Gain error of the

REF

REF

.

REF

terminal,

OUT

Digital Feedthrough

When the device is not selected, high frequency logic activity
on the digital inputs of the device may be capacitively coupled
through the device and produce noise on the I

pins. This

OUT

noise is coupled from the outputs of the device onto follow-on
circuitry. This noise is digital feedthrough.

Multiplying Feedthrough Error

This is the error due to capacitive feedthrough from the DAC
reference input to the DAC I

1 terminal when all 0s are

OUT

loaded to the DAC.

Total Harmonic Distortion (THD)

The DAC is driven by an ac reference. The ratio of the rms sum
of the harmonics of the DAC output to the fundamental value is
the THD. Usually only the lower order harmonics, such as
second to fifth, are included.

2222

V5V4V3V2

THD

log20

=

V1

+++

Compliance Voltage Range

The maximum range of (output) terminal voltage for which the
device provides the specified characteristics.

Output Noise Spectral Density

Calculation from

= √4KTRB

e

n

where:

K is Boltzmann Constant (J/°K).
R is resistance ().
T is the resistor temperature (°K).
B is the 1 Hz bandwidth.

Rev. 0 | Page 10 of 16

AD5441

Ω

Ω

V

V

V

2

PARAMETER DEFINITIONS

GENERAL CIRCUIT INFORMATION

The AD5441 is a 12-bit multiplying DAC with a low
temperature coefficient. It contains an R-2R resistor ladder
network, data input and control logic, and two data registers.

The digital circuitry forms an interface in which serial data can
be loaded under microprocessor control into a 12-bit shift register
and then transferred, in parallel, to the 12-bit DAC register.

The analog portion of the AD5441 contains an inverted R-2R
ladder network consisting of silicon-chrome, highly stable
(50 ppm/°C), thin-film resistors, and 12 pairs of NMOS current­steering switches, see
weighted currents into either I
current in each ladder leg, regardless of digital input code. This
constant current results in a constant input resistance at V
equal to R. The V
or current, ac or dc, that is within the limits stated in the
Absolute Maximum Ratings.

REF

*THESE SWI TCHES PERMANENTLY ON.

NOTES

1. SWIT CHES SHOWN F OR DIGITAL INPUT S HIGH.

10kΩ

20kΩS220kΩ

S1

BIT 1 (MSB) BIT 2 BIT 3 BIT 12 (LSB)

The 12 output current steering NMOS FET switches are in
series with each R-2R resistor.

To further ensure accuracy across the full temperature range,
MOS switches that are always on were included in series with
the feedback resistor and the terminating resistor of the R-2R
ladder.

Figure 19 shows the location of the series switches.

Figure 19. These switches steer binarily

or GND; this yields a constant

OUT

input may be driven by any reference voltage

REF

10k

DIGITAL INPUTS

Figure 19. Simplified DAC Circuit

20kΩ

S3

10k

20kΩ

S12

20kΩ

*

10kΩ

*

REF

GND

I

OUT

R

FEEDBACK

During any testing of the resistor ladder or R
incoming inspection), V

must be present to turn on these

DD

series switches.

OUTPUT IMPEDANCE

The output resistance of the AD5441, as in the case of the
output capacitance, varies with the digital input code. This
resistance, looking back into the I

terminal, may be between

OUT

10 kΩ (the feedback resistor alone when all digital inputs are
low) and 7.5 kΩ (the feedback resistor in parallel with approximate
30 kΩ of the R-2R ladder network resistance when any single bit
logic is high). Static accuracy and dynamic performance are
affected by these variations.

APPLICATIONS INFORMATION

In most applications, linearity depends upon the potential of

and GND pins being at the same voltage potential. The

the I

OUT

DAC is connected to an external precision op amp inverting input.
The external amplifiers noninverting input should be tied directly
to ground without the usual bias current compensating resistor (see
Figure 20 and Figure 22). The selected amplifier should have a low
input bias current and low drift over temperature. The amplifiers
input offset voltage should be nulled to less than 200 mV (less than
10% of 1 LSB). All grounded pins should tie to a single common
ground point to avoid ground loops. The V

power supply should

DD

have a low noise level with adequate bypassing. It is best to operate
the AD5441 from the analog power supply and grounds.

UNIPOLAR 2-QUADRANT MULTIPLYING

The most straightforward application of the AD5441 is in the

06492-021

2-quadrant multiplying configuration shown in
reference input signal is replaced with a fixed dc voltage reference,
the DAC output provides a proportional dc voltage output
according to the transfer equation

= −D/4096 × V

V

OUT

REF

where:

D is the decimal data loaded into the DAC register.
V

is the externally applied reference voltage source.

REF

(such as

FEEDBACK

Figure 20. If the

DD

V

DD

R1

V

REF

AD5441

CLK SRI

LD

µCONTROLLER

REF

NOTES

1. R1 AND R2 USED ONLY IF GAIN ADJUS TMENT I S REQUIRED.
. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED

IF A1 IS A HIGH SPEED AMPLIFIER.

R2

R

FB

I

OUT

GND

C1

1

AGND

A1

V

= 0 TO –V

OUT

REF

06492-023

Figure 20. Unipolar (2-Quadrant) Operation

Rev. 0 | Page 11 of 16

AD5441

V

BIPOLAR 4-QUADRANT MULTIPLYING

Figure 22 shows a suggested circuit to achieve 4-quadrant
multiplying operation. The summing amplifier multiplies V
by 2 and offsets the output with the reference voltage so that a
midscale digital input code of 2048 places V
full-scale voltage is V
The positive full-scale output is −(V

when the DAC is loaded with all zeros.

REF

− 1 LSB) when the DAC

REF

at 0 V. The negative

OUT2

is loaded with all ones. Therefore, the digital coding is offset
binary. The voltage output transfer equation for various input
data and reference (or signal) values follows

= (D/2048 − 1) − V

V

OUT2

REF

where:

D is the decimal data loaded into the DAC register.
V

is the externally applied reference voltage source.

REF

INTERFACE LOGIC INFORMATION

The AD5441 has been designed for ease of operation. The
timing diagram in
sequence. Note that the most significant bit (MSB) is loaded
first. Once the 12-bit input register is full, the data is transferred
to the DAC register by taking

Figure 2 illustrates the input register loading

LD

momentarily low.

V

DD

V

DD

V

REF

±10V

NOTES

1. R1 AND R2 ARE USED ONLY IF GAI N ADJUSTMENT I S REQUIRED.
ADJUST R1 FOR V

2. MATCHING AND TRACKING IS E SSENTIAL FOR RESI STOR PAIRS
R3 AND R4.

3. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
IF A1/A2 IS A HIGH SPEED AMPLIFIER.

R1

V

REF

AD5441

CLK S RILD

µCONTROLLER

= 0V WITH CODE 10000000 LOADED TO DAC.

OUT

Figure 22. Bipolar (4-Quadrant) Operation

OUT1

R3

20kΩ

R2

R

FB

I

1

OUT

GND

AGND

DIGITAL SECTION

The digital inputs of the AD5441, SRI, LD, and CLK, are TTL­compatible. The input voltage levels affect the amount of current
drawn from the supply; peak supply current occurs as the digital
input (V
for the supply current vs. logic input voltage graph. Maintaining
the digital input voltage levels as close as possible to the supplies,
V

DD

digital inputs of the AD5441 were designed with ESD resistance
incorporated through careful layout and the inclusion of input
protection circuitry.
and series resistor; this input structure is duplicated on each
digital input. High voltage static charges applied to the inputs
are shunted to the supply and ground rails through forward­biased diodes. These protection diodes were designed to clamp
the inputs to well below dangerous levels during static discharge
conditions.

C1

A1

) passes through the transition region. See Figure 13

IN

and GND, minimizes supply current consumption. The

Figure 21 shows the input protection diodes

DD

LD, CLK, SRI

R4

10kΩ

GND

Figure 21. Digital Input Protection

R5

20kΩ

A2

5kΩ

= –V

V

OUT

REF

TO +V

REF

06492-024

06492-020

Rev. 0 | Page 12 of 16

AD5441

OUTLINE DIMENSIONS

3.25

3.00 SQ

2.75

2.95

INDICATOR

0.90 MAX

0.85 NOM

SEATING

PLANE

PIN 1

12° MAX

TOP

VIEW

0.70 MAX

0.65 TYP

0.30

0.23

0.18

2.75 SQ

2.55

0.05 MAX

0.01 NOM

0.20 REF

Figure 23. 8-Lead Lead Frame Chip Scale Package [LFCSP_VD]

3 mm × 3 mm Body, Very Thin, Dual Lead

Dimensions are shown in millimeters

3.20

3.00

2.80

0.60 MAX

0.50

0.40

0.30

(CP-8-2)

0.60 MAX

5

EXPOSED

PA D

(BOTTO M VIEW)

4

0.50
BSC

8

1.60

1.45

1.30

1

1.89

1.74

1.59

PIN 1
INDICATOR

61507-B

8

5

4

SEATING
PLANE

5.15

4.90

4.65

1.10 MAX

0.23

0.08

8°
0°

0.80

0.60

0.40

3.20

3.00

1

2.80

PIN 1

0.65 BSC

0.95

0.85

0.75

0.15

0.38

0.00

0.22

COPLANARITY

0.10

COMPLIANT TO JEDEC STANDARDS MO-187-AA

Figure 24. 8-Lead Mini Small Outline Package [MSOP]

(RM-8)

Dimensions are shown in millimeters

ORDERING GUIDE

Model INL (LSB) Temperature Range Package Description Package Option Branding

AD5441BCPZ-R2
AD5441BCPZ-REEL7
AD5441BRMZ
AD5441BRMZ-REEL7

1

Z = RoHS Compliant Part.

1

1

1

1

±0.5 −40°C to +125°C 8-Lead LFCSP_VD CP-8-2 DBD
±0.5 −40°C to +125°C 8-Lead LFCSP_VD CP-8-2 DBD
±0.5 −40°C to +125°C 8-Lead MSOP RM-8 DBC
±0.5 −40°C to +125°C 8-Lead MSOP RM-8 DBC

Rev. 0 | Page 13 of 16

AD5441

NOTES

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AD5441

NOTES

Rev. 0 | Page 15 of 16

AD5441

NOTES

©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06492-0-1/08(0)

T

Rev. 0 | Page 16 of 16

TTT