Datasheet AD5429 Datasheet (Analog Devices)

Dual 8-,10-,12-Bit High Bandwidth

FEATURES

10 MHz multiplying bandwidth
50 MHz serial interface

2.5 V to 5.5 V supply operation
±10 V reference input
Pin compatible 8-, 10-, and 12-bit DACs
Extended temperature range: −40°C to +125°C
16-lead TSSOP package
Guaranteed monotonic
Power-on reset
Daisy-chain mode
Readback function

0.5 µA typical current consumption

APPLICATIONS

Portable battery-powered applications
Waveform generators
Analog processing
Instrumentation applications
Programmable amplifiers and attenuators
Digitally controlled calibration
Programmable filters and oscillators
Composite video
Ultrasound
Gain, offset, and voltage trimming

Multiplying DACs with Serial Interface

AD5429/AD5439/AD5449

FUNCTIONAL BLOCK DIAGRAM

V

A

REF

8-/10-/12-BIT
R-2R DAC A

8-/10-/12-BIT
R-2R DAC B

V

B

REF

REF

RFB

R

R

A

FB

I

1A

OUT

I

2A

OUT

I

1B

OUT

2B

I

OUT

RFBB

RFB

R

) determines

04464-0-001

AD5429/AD5439/AD5449

V

DD

SYNC
SCLK

SDIN

SDO

CLR

SHIFT

REGISTER

POWER-ON

RESET

INPUT

REGISTER

INPUT

REGISTER

DAC

REGISTER

LDAC

DAC

REGISTER

LDAC

Figure 1.

GENERAL DESCRIPTION

The AD5429/AD5439/AD54491 are CMOS 8-, 10-, and 12-bit
dual-channel current output digital-to-analog converters,
respectively. These devices operate from a 2.5 V to 5.5 V power
supply, making them suited to battery-powered and other
applications.

The applied external reference input voltage (V
the full-scale output current. An integrated feedback resistor

) provides temperature tracking and full-scale voltage

(R

FB

output when combined with an external current-to-voltage
precision amplifier.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Anal og Devices. Trademarks and
registered trademarks are the property of their respective owners.

These DACs utilize a double-buffered, 3-wire serial interface
that is compatible with SPI®, QSPI™, MICROWIRE™, and most
DSP interface standards. In addition, a serial data out pin (SDO)
allows daisy-chaining when multiple packages are used. Data
readback allows the user to read the contents of the DAC
register via the SDO pin. On power-up, the internal shift
register and latches are filled with zeros and the DAC outputs
are at zero scale.

As a result of manufacture on a CMOS submicron process,
these parts offer excellent 4-quadrant multiplication character­istics, with large signal multiplying bandwidths of 10 MHz.

The AD5429/AD5439/AD5449 DAC are available in 16-lead
TSSOP packages.

1

US Patent Number 5,689,257.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

www.analog.com

AD5429/AD5439/AD5449

TABLE OF CONTENTS

Specifications..................................................................................... 3

Timing Characteristics..................................................................... 5

Absolute Maximum Ratings............................................................ 7

ESD Caution.................................................................................. 7

Pin Configuration and Function Descriptions............................. 8

Te r m in o l o g y ...................................................................................... 9

Typical Performance Characteristics ........................................... 10

General Description....................................................................... 15

Unipolar Mode ............................................................................ 15

Bipolar Operation....................................................................... 16

Stability ........................................................................................ 16

Single-Supply Applications........................................................ 17

Positive Output Voltage ............................................................. 17

REVISION HISTORY

Adding Gain................................................................................ 18

Divider or Programmable Gain Element................................ 18

Reference Selection .................................................................... 19

Amplifier Selection .................................................................... 19

Serial Interface................................................................................ 20

Microprocessor Interfacing....................................................... 22

PCB Layout and Power Supply Decoupling................................ 24

Power Supplies for the Evaluation Board................................ 24

Evaluation Board for the DACs................................................ 24

Overview of AD54xx Devices....................................................... 28

Outline Dimensions....................................................................... 29

Ordering Guide .......................................................................... 29

7/04—Revision 0: Initial Version

Rev. 0 | Page 2 of 32

AD5429/AD5439/AD5449

SPECIFICATIONS

VDD = 2.5 V to 5.5 V, V
with OP1177, ac performance with AD9631, unless otherwise noted. Temperature range for Y version is −40°C to +125°C.

Table 1.

Parameter Min Typ Max Unit Conditions

STATIC PERFORMANCE
AD5429

Resolution 8 Bits
Relative Accuracy ±0.5 LSB
Differential Nonlinearity ±1 LSB Guaranteed monotonic

AD5439

Resolution 10 Bits
Relative Accuracy ±0.5 LSB
Differential Nonlinearity ±1 LSB Guaranteed monotonic

AD5449

Resolution 12 Bits
Relative Accuracy ±1 LSB
Differential Nonlinearity −1/+2 LSB Guaranteed monotonic
Gain Error ±10 mV
Gain Error Temp Coefficient

Output Leakage Current ±5 nA Data = 0000H, TA = 25°C, I
±10 nA Data = 0000H, I
REFERENCE INPUT1 Typical resistor TC = −50 ppm/°C

Reference Input Range ±10 V

V

A,V

B Input Resistance 8 10 12 kΩ DAC input resistance

REF

REF

V

A/B Input Resistance Mismatch 1.6 2.5 % Typ = 25°C, max = 125°C

REF

DIGITAL INPUTS/OUTPUT1

Input High Voltage, VIH 1.7 V VDD = 2.5 V to 5.5 V

Input Low Voltage, VIL 0.8 V VDD = 2.7 V to 5.5 V

0.7 V VDD = 2.5 V to 2.7 V

Input Leakage Current, IIL 1 µA

Input Capacitance 10 pF

VDD = 4.5 V to 5.5 V

Output Low Voltage, VOL 0.4 V I
Output High Voltage, VOH VDD − 1 V I

VDD = 2.5 V to 3.6 V

Output Low Voltage, VOL 0.4 V I
Output High Voltage, VOH VDD − 0.5 V I

DYNAMIC PERFORMANCE1

Reference Multiplying BW 10 MHz V

Output Voltage Settling Time

AD5429 50 100 ns
AD5439 55 110 ns

AD5449 90 160 ns R
Digital Delay 20 40 ns
Digital-to-Analog Glitch Impulse 3 nV-s

Multiplying Feedthrough Error −75 dB

= 10 V, I

REF

2A, I

OUT

1

2B = 0 V. All specifications T

OUT

±5 ppm FSR/°C

MIN

to T

= 200 µA

SINK

SOURCE

= 200 µA

SINK

SOURCE

unless otherwise noted. DC performance measured

MAX,

1

OUT

1

OUT

= 200 µA

= 200 µA

= 5 V p-p, DAC loaded all 1s

REF

Measured to ±4 mV of FS, R

= 0s

C

LOAD

= 100 Ω,

LOAD

DAC latch alternately loaded with 0s
and 1s

= 100 Ω, C

LOAD

LOAD

= 15 pF

1 LSB change around major carry,
V

= 0 V

REF

DAC latch loaded with all 0s,
reference = 10 kHz

Rev. 0 | Page 3 of 32

AD5429/AD5439/AD5449

Parameter Min Typ Max Unit Conditions

Output Capacitance 2 pF DAC latches loaded with all 0s
4 pF DAC latches loaded with all 1s
Digital Feedthrough 5 nV-s

Total Harmonic Distortion −75 dB V

−75 dB

Output Noise Spectral Density 25 nV/√Hz @ 1 kHz

SFDR PERFORMANCE (Wideband) AD5449, 65 k codes, V

Clock = 10 MHz

500 kHz fout 55 dB
100 kHz fout 63 dB
50 kHz fout 65 dB

Clock = 25 MHz

500 kHz fout 50 dB
100 kHz fout 60 dB
50 kHz fout 62 dB

SFDR PERFORMANCE (Narrow Band) AD5449, 65 k codes, V

Clock = 10 MHz

500 kHz fout 73 dB
100 kHz fout 80 dB
50 kHz fout 87 dB

Clock = 25 MHz

500 kHz fout 70 dB
100 kHz fout 75 dB
50 kHz fout 80 dB

INTERMODULATION DISTORTION AD5449, 65 k codes, V

Clock = 10 MHz

f1 = 400 kHz, f2 = 500 kHz 65 dB
f1 = 40 kHz, f2 = 50 kHz 72 dB

Clock = 25 MHz

f1 = 400 kHz, f2 = 500 kHz 51 dB
f1 = 40 kHz, f2 = 50 kHz 65 dB

POWER REQUIREMENTS

Power Supply Range 2.5 5.5 V
IDD 10 µA Logic inputs = 0 V or VDD
Power Supply Sensitivity1 0.001 %/% ∆VDD = ±5%

1

Guaranteed by design and characterization, not subject to production test.

Feedthrough to DAC output with CS high
and alternate loading of all 0s and all 1s

= 5 V p-p, all 1s loaded, f = 1 kHz

REF

= 5 V, sine wave generated from

V

REF

digital code

REF

REF

REF

= 3.5 V

= 3.5 V

= 3.5 V

Rev. 0 | Page 4 of 32

AD5429/AD5439/AD5449

TIMING CHARACTERISTICS

VDD = 2.5 V to 5.5 V, V

See Figure 2 and Figure 3. Temperature range for Y version is −40°C to +125°C. Guaranteed by design and characterization, not subject to
production test. All input signals are specified with tr = tf = ns (10% to 90% of V

= 5 V, I

REF

2 = 0 V. All specifications T

OUT

MIN

to T

, unless otherwise noted.

MAX

) and timed from a voltage level of (VIL + VIH)/2.

DD

Table 2.

Parameter Limit at T

f

50 MHz max Max clock frequency

SCLK

MIN

, T

Unit Conditions/Comments

MAX

1

t1 20 ns min SCLK cycle time
t2 8 ns min SCLK high time
t3 8 ns min SCLK low time
t4 13 ns min

SYNC falling edge to SCLK falling edge setup time
t5 5 ns min Data setup time
t6 4 ns min Data hold time
t7 5 ns min
t8 30 ns min
t9 0 ns min
t10 12 ns min
t

11

2

t

12

10 ns min
25 ns min SCLK active edge to SDO valid, strong SDO driver

SYNC rising edge to SCLK falling edge

Minimum

SCLK falling edge to

SYNC high time

LDAC falling edge
LDAC pulse width
SCLK falling edge to

LDAC rising edge

60 ns min SCLK active edge to SDO valid, weak SDO driver

1

Falling or rising edge as determined by the control bits of the serial word. Strong or weak SDO driver selected via the control register.

2

Daisy-chain and readback modes cannot operate at maximum clock frequency. SDO timing specifications are measured with a load circuit, as shown in Figure 4.

Rev. 0 | Page 5 of 32

AD5429/AD5439/AD5449

SCLK

t

4

t

8

SYNC

DB15

NOTES

1

ASYNCHRONOUS LDAC UPDATE MODE

2

SYNCHRONOUS LDAC UPDATE MODE

ALTERNATIVELY, DATA CAN BE CLOCKED INTO INPUT SHIFT REGISTER ON RISING EDGE OF SCLK AS
DETERMINED BY CONTROL BITS. TIMING AS ABOVE, WITH SCLK INVERTED.

t

4

DB15

(N)

LDAC

LDAC

SCLK

SYNC

SDIN

SDO

DIN

1

2

t

1

t

2

t

6

t

5

t

3

t

7

DB0

t

10

t

9

t

11

04464-0-002

Figure 2. Standalone Mode Timing Diagram

t

1

t

2

t

6

t

5

t

3

DB15

DB0

(N+1)

(N)

t

12

DB15

(N)

DB0

(N+1)

DB0

(N)

t

7

t

8

ALTERNATIVELY, DATA CAN BE CLOCKED INTO INPUT SHIFT REGISTER ON RISING EDGE OF SCLK AS
DETERMINED BY CONTROL BITS. IN THIS CASE, DATA WOULD BE CLOCKED OUT OF SDO ON FALLING
EDGE OF SCLK. TIMING AS ABOVE, WITH SCLK INVERTED.

04464-0-003

Figure 3. Daisy-Chain and Readback Modes Timing Diagram

TO OUTPUT

PIN

200µAI

C

L

50pF

200µAI

OL

VOH (MIN) + VOL (MAX)

OH

2

04464-0-004

Figure 4. Load Circuit for SDO Timing Specifications

Rev. 0 | Page 6 of 32

AD5429/AD5439/AD5449

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

VDD to GND −0.3 V to +7 V
V

, RFB to GND −12 V to +12 V

REF

I

1, I

OUT

2 to GND −0.3 V to +7 V

OUT

Input Current to Any Pin except Supplies ±10 mA
Logic Inputs and Output

1

−0.3 V to VDD + 0.3 V

Operating Temperature Range

Extended (Y Version) −40°C to +125°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability. Only one absolute maximum rating may be
applied at any one time.

Transient currents of up to 100 mA do not cause SCR latch-up.

= 25°C unless otherwise noted.

T

A

16-Lead TSSOP θJA Thermal Impedance 150°C/W
Lead Temperature, Soldering (10 s) 300°C
IR Reflow, Peak Temperature (< 20 s) 235°C

1

Overvoltages at SCLK,

Current should be limited to the maximum ratings given.

SYNC

, and DIN are clamped by internal diodes.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. 0 | Page 7 of 32

AD5429/AD5439/AD5449

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

1A

I

OUT

2

I

2A

OUT

3

R

A

FB

V

REF

GND

LDAC

SCLK

SDIN SDO

AD5429/

4

AD5439/

A

AD5449

5

TOP VIEW

(Not to Scale)

6

7

8

NC = NO CONNECT

16

I

1B

OUT

15

I

2B

OUT

14

R

B

FB

13

V

B

REF

12

V

DD

11

CLR

10

SYNC

9

04464-0-005

Figure 5. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Function

1 I
2 I

1A DAC A Current Output.

OUT

OUT

2A

DAC A Analog Ground. This pin should typically be tied to the analog ground of the system, but can be biased to

achieve single-supply operation.
3 RFBA DAC Feedback Resistor Pin. Establish voltage output for the DAC by connecting to an external amplifier output.
4 V

A DAC A Reference Voltage Input Pin.

REF

5 GND Ground Pin.
6

LDAC Load DAC Input. Allows asynchronous or synchronous updates to the DAC output. The DAC is asynchronously

updated when this signal goes low. Alternatively, if this line is held permanently low, an automatic or synchronous

update mode is selected whereby the DAC is updated on the 16th clock falling edge when the device is in

SYNC when in daisy-chain mode.

7 SCLK

standalone mode, or on the rising edge of

Serial Clock Input. By default, data is clocked into the input shift register on the falling edge of the serial clock

input. Alternatively, by means of the serial control bits, the device can be configured such that data is clocked into

the shift register on the rising edge of SCLK.
8 SDIN

Serial Data Input. Data is clocked into the 16-bit input register on the active edge of the serial clock input. By

default, on power-up, data is clocked into the shift register on the falling edge of SCLK. The control bits allow the

user to change the active edge to rising edge.
9 SDO

Serial Data Output. This allows a number of parts to be daisy-chained. By default, data is clocked into the shift

register on the falling edge and out via SDO on the rising edge of SCLK. Data is always clocked out on the

alternate edge to loading data to the shift register. Writing the readback control word to the shift register makes

the DAC register contents available for readback on the SDO pin, clocked out on the next 16 opposite clock edges

to the active clock edge.
10

SYNC Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it

powers on the SCLK and DIN buffers, and the input shift register is enabled. Data is loaded to the shift register on

the active edge of the following clocks. In standalone mode, the serial interface counts clocks, and data is latched

to the shift register on the16th active clock edge.
11

CLR Active Low Control Input. This pin clears the DAC output, input, and DAC registers. Configuration mode allows the

user to enable the hardware

CLR pin as a clear to zero scale or midscale as required.
12 VDD Positive Power Supply Input. These parts can be operated from a supply of 2.5 V to 5.5 V.
13 V

B DAC B Reference Voltage Input Pin.

REF

14 RFBB DAC B Feedback Resistor Pin. Establish voltage output for the DAC by connecting to an external amplifier output.
15 I

OUT

2B

DAC B Analog Ground. This pin typically should be tied to the analog ground of the system, but can be biased to
achieve single-supply operation.

16 I

1B DAC B Current Output.

OUT

Rev. 0 | Page 8 of 32

AD5429/AD5439/AD5449

(

(

)

TERMINOLOGY

Relative Accuracy

Relative accuracy or endpoint nonlinearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
adjusting for zero and full scale and is typically expressed in
LSBs or as a percentage of full-scale reading.

Differential Nonlinearity

Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ±1 LSB maximum
over the operating temperature range ensures monotonicity.

Gain Error

Gain error or full-scale error is a measure of the output error
between an ideal DAC and the actual device output. For these
DACs, ideal maximum output is V

− 1 LSB. Gain error of the

REF

DACs is adjustable to zero with external resistance.

Output Leakage Current

Output leakage current is current that flows in the DAC ladder
switches when these are turned off. For the I

1 terminal, it can

OUT

be measured by loading all 0s to the DAC and measuring the

1 current. Minimum current flows in the I

I

OUT

2 line when

OUT

the DAC is loaded with all 1s.

Output Capacitance

Capacitance from I

OUT

1 or I

2 to AGND.

OUT

Output Current Settling Time

The amount of time needed for the output to settle to a
specified level for a full-scale input change. For these devices,
it is specified with a 100 Ω resistor to ground.

Digital-to-Analog Glitch lmpulse

The amount of charge injected from the digital inputs to the
analog output when the inputs change state. This is normally
specified as the area of the glitch in either pA-s or nV-s,
depending upon whether the glitch is measured as a current
or voltage signal.

Digital Feedthrough

When the device is not selected, high frequency logic activity on
the device digital inputs is capacitively coupled through the
device to show up as noise on the I

pins and subsequently

OUT

into the following circuitry. This noise is digital feedthrough.

Multiplying Feedthrough Error

The error due to capacitive feedthrough from the DAC
reference input to the DAC I

1 terminal, when all 0s are

OUT

loaded to the DAC.

Digital Crosstalk

The glitch impulse transferred to the outputs of one DAC in
response to a full-scale code change (all 0s to all 1s and vice
versa) in the input register of the other DAC. It is expressed in
nV-s.

Analog Crosstalk

The glitch impulse transferred to the output of one DAC due to
a change in the output of another DAC. It is measured by
loading one of the input registers with a full-scale code change
(all 0s to all 1s and vice versa), while keeping

pulse

low and monitor the output of the DAC whose

LDAC

LDAC

high. Then

digital code was not changed. The area of the glitch is expressed
in nV-s.

Channel-to-Channel Isolation

The proportion of input signal from the reference input of one
DAC that appears at the output of the other DAC. It is expressed
in dB.

Total Harmonic Distortion (THD)
The DAC is driven by an ac reference. The ratio of the rms sum
of the harmonics of the DAC output to the fundamental value is
the THD. Usually only the lower-order harmonics are included,
such as second to fifth.

2

2

2

THD

2

3

=

2

log20

V

1

)

+++

VVVV

5

4

Intermodulation Distortion

The DAC is driven by two combined sine wave references of
frequencies fa and fb. Distortion products are produced at
sum and difference frequencies of mfa ± nfb, where m,
n = 0, 1, 2, 3… Intermodulation terms are those for which m or
n is not equal to zero. The second-order terms include (fa + fb)
and (fa − fb) and the third-order terms are (2fa + fb), (2fa − fb),
(f + 2fa + 2fb) and (fa − 2fb). IMD is defined as

IMD log20=

productsdistortiondiffandsumtheofsumrms

lfundamentatheofamplituderms

Compliance Voltage Range

The maximum range of (output) terminal voltage for which the
device provides the specified characteristics.

Rev. 0 | Page 9 of 32

AD5429/AD5439/AD5449

TYPICAL PERFORMANCE CHARACTERISTICS

0.20
TA = 25°C
V

= 10V

0.15

0.10

REF

V

= 5V

DD

0.20

0.15

0.10

TA = 25°C

= 10V

V

REF

= 5V

V

DD

0.05

0

INL (LSB)

–0.05

–0.10

–0.15

–0.20

0 50 100 150 200 250

CODE

Figure 6. INL vs. Code (8-Bit DAC)

0.5

TA = 25°C

0.4

V

= 10V

REF

V

= 5V

DD

0.3

0.2

0.1

0

INL (LSB)

–0.1

–0.2

–0.3

–0.4

–0.5

0 200 400 600 800 1000

CODE

Figure 7. INL vs. Code (10-Bit DAC)

1.0

TA = 25°C

INL (LSB)

0.8

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

= 10V

V

REF

= 5V

V

DD

20001500500 10000 2500 3000 3500 4000

CODE

Figure 8. INL vs. Code (12-Bit DAC)

04462-0-007

04462-0-008

04462-0-009

0.05

0

DNL (LSB)

–0.05

–0.10

–0.15

–0.20

0 50 100 150 200 250

CODE

Figure 9. DNL vs. Code (8-Bit DAC)

0.5
TA = 25°C

0.4

V

= 10V

REF

V

= 5V

DD

0.3

0.2

0.1

0

DNL (LSB)

–0.1

–0.2

–0.3

–0.4

–0.5

0 200 400 600 800 1000

CODE

Figure 10. DNL vs. Code (10-Bit DAC)

1.0

TA = 25°C

0.8

0.6

0.4

0.2

0

DNL (LSB)

–0.2

–0.4

–0.6

–0.8

–1.0

= 10V

V

REF

= 5V

V

DD

20001500500 10000 2500 3000 3500 4000

CODE

Figure 11. DNL vs. Code (12-Bit DAC)

04462-0-010

04462-0-011

04462-0-012

Rev. 0 | Page 10 of 32

AD5429/AD5439/AD5449

0.6

0.5

0.4

0.3

0.2

0.1

INL (LSB)

0

–0.1

–0.2

–0.3

–0.40

–0.45

–0.50

TA = 25°C
V

= 10V

REF

V

= 5V

DD

MAX INL

MIN INL

65342789

REFERENCE VOLTAGE

Figure 12. INL vs. Reference Voltage

TA = 25°C

= 10V

V

REF

= 5V

V

DD

10

04462-0-013

8

7

6

5

4

3

CURRENT (mA)

2

1

0

VDD = 5V

VDD = 3V

VDD = 2.5V

1.00.50
INPUT VOLTAGE (V)

Figure 15. Supply Current vs. Logic Input Voltage

1.6

1.4

1.2

1.0

I

OUT

TA = 25°C

1 VDD 5V

5.0

4.54.03.53.02.52.01.5

04462-0-022

–0.55

DNL (LSB)

–0.60

–0.65

–0.70

MIN DNL

65342789

REFERENCE VOLTAGE

Figure 13. DNL vs. Reference Voltage

5

4

3

2

1

0

–1

ERROR (mV)

–2

–3

–4

–5

–60 –40 –20 0 20 40 60 80 100 120 140

V

REF

VDD = 5V

VDD = 2.5V

= 10V

TEMPERATURE (°C)

Figure 14. Gain Error vs. Temperature

0.8

0.6

LEAKAGE (nA)

0.4

OUT

I

0.2

10

04462-0-014

04462-0-015

0

0.50

0.45

0.40

0.35

0.30

0.25

0.20

CURRENT (µA)

0.15

0.10

0.05

0

–60 –40 –20 0 20 40 60 80 100 120 140

I

OUT

4020–20 0–40 60 80 100 120

TEMPERATURE (°C)

Figure 16. I

1 Leakage Current vs. Temperature

OUT

VDD = 5V

ALL 0s

ALL 1s

VDD = 2.5V

ALL 0sALL 1s

TEMPERATURE (°C)

Figure 17. Supply Current vs. Temperature

1 VDD 3V

TA = 25°C

04462-0-023

04462-0-024

Rev. 0 | Page 11 of 32

AD5429/AD5439/AD5449

14

TA = 25°C
LOADING ZS TO FS

12

10

VDD = 5V

3

0

TA = 25°C

= 5V

V

DD

8

(mA)

DD

I

6

4

2

0

10k1k10 1001 100k 1M 10M 100M

FREQUENCY (Hz)

= 3V

V

DD

V

= 2.5V

DD

Figure 18. Supply Current vs. Update Rate

6

TA = 25°C

0

LOADING

–6

ZS TO FS

–12

–18

–24

–30

–36

–42

–48

GAIN (dB)

–54

–60

–66

–72
–78
–84
–90
–96

–102

1 100 1k 10k 100k 1M 10M 100M

ALL ON
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0

ALL OFF

10

FREQUENCY (Hz)

AD8038 AMPLIFIER

C

V

REF

COMP

TA = 25°C

= 5V

V

DD

= ±3.5V

INPUT

=1.8pF

Figure 19. Reference Multiplying Bandwidth vs. Frequency and Code

0.2

0

–0.2

GAIN (dB)

–0.4

TA = 25°C

–0.6

V

= 5V

DD

V

= ±3.5V

REF

C

= 1.8pF

COMP

AD8038 AMPLIFIER

–0.8

10k1k10 1001 100k 1M 10M 100M

FREQUENCY (Hz)

Figure 20. Reference Multiplying Bandwidth–All 1s Loaded

04462-0-025

04462-0-026

04462-0-027

–3

GAIN (dB)

V

= ±2V, AD8038 CC 1.47pF

REF

–6

V

= ±2V, AD8038 CC 1pF

REF

= ±0.15V, AD8038 CC 1pF

V

REF

= ±0.15V, AD8038 CC 1.47pF

V

REF

V

= ±3.51V, AD8038 CC 1.8pF

REF

–9

10k 100k 1M 10M 100M

FREQUENCY (Hz)

Figure 21. Reference Multiplying Bandwidth vs. Frequency and

Compensation Capacitor

0.045
7FF TO 800H

0.040

0.035

0.030

0.025

0.020

0.015

0.010

OUTPUT VOLTAGE (V)

0.005

0
–0.005
–0.010

0 20 40 60 80 100 120 140 160 180 200

VDD = 5V

VDD = 3V

VDD = 5V

TIME (ns)

Figure 22. Midscale Transition, V

TA = 25°C
V

REF

AD8038 AMPLIFIER
C

COMP

800 TO 7FFH
VDD = 3V

REF

= 0V

= 1.8pF

= 0 V

–1.68

7FF TO 800H

VDD = 5V

VDD = 3V

VDD = 5V

800 TO 7FFH

0 20 40 60 80 100 120 140 160 180 200

TIME (ns)

OUTPUT VOLTAGE (V)

–1.69

–1.70

–1.71

–1.72

–1.73

–1.74

–1.75

–1.76

–1.77

Figure 23. Midscale Transition, V

TA = 25°C
V

REF

AD8038 AMPLIFIER
C

COMP

VDD = 3V

REF

= 3.5V

= 1.8pF

= 3.5 V

04462-0-028

04462-0-041

04462-0-042

Rev. 0 | Page 12 of 32

AD5429/AD5439/AD5449

20

TA = 25°C

= 3V

V

DD

AMP = AD8038

0

–20

–40

–60

PSRR (dB)

–80

–100

–120

1 100 1k 10k 100k 1M 10M

10

FULL SCALE

ZERO SCALE

FREQUENCY (Hz)

Figure 24. Power Supply Rejection vs. Frequency

–60

TA = 25°C

= 3V

V

DD

V

= 3.5V p-p

REF

–65

–70

–75

THD + N (dB)

–80

–85

–90

100 1k1 10 10k 100k 1M

FREQUENCY (Hz)

04462-0-043

04462-0-044

90

80

70

60

50

40

SFDR (dB)

30

20

10

MCLK = 5MHz

MCLK = 10MHz

MCLK = 25MHz

TA = 25°C

= 3.5V

V

REF

0

0 100 200 300 400 500 600 700 800 900 1000

f

(kHz)

OUT

Figure 27. Wideband SFDR vs. f

AD8038 AMPLIFIER

Frequency

OUT

0

–10

–20

–30

–40

–50

SFDR (dB)

–60

–70

–80

–90

0

24681012

FREQUENCY (MHz)

TA = 25°C
V

= 5V

DD

AMP = AD8038
65k CODES

04462-0-046

04462-0-047

Figure 25. THD + Noise vs. Frequency

100

MCLK = 1MHz

80

MCLK = 200kHz

60

MCLK = 0.5MHz

SFDR (dB)

40

20

0

0 20 40 60 80 100 120 140 160 180 200

f

(kHz)

OUT

Figure 26. Wideband SFDR vs. f

TA = 25°C

= 3.5V

V

REF

AD8038 AMPLIFIER

Frequency

OUT

04462-0-045

Rev. 0 | Page 13 of 32

Figure 28. Wideband SFDR, f

0

–10

–20

–30

–40

–50

SFDR (dB)

–60

–70

–80

–90

–100

0

0.5 1.5 3.0 3.5 4.01.0 2.0 2.5 4.5 5.0

Figure 29. Wideband SFDR, f

= 100 kHz, Clock = 25 MHz

OUT

FREQUENCY (MHz)

= 500 kHz, Clock = 10 MHz

OUT

TA = 25°C



V

= 5V

DD

AMP = AD8038
65k CODES

044620-048

AD5429/AD5439/AD5449

0

–10

–20

–30

–40

–50

SFDR (dB)

–60

–70

–80

–90

0

0.5 1.5 3.0 3.5 4.01.0 2.0 2.5 4.5 5.0

Figure 30. Wideband SFDR, f

0

–10

–20

–30

–40

–50

–60

SFDR (dB)

–70

–80

–90

–100

250 750300 350 400 650 700

Figure 31. Narrow-Band Spectral Response, f

20

0

–20

–40

–60

SFDR (dB)

–80

–100

FREQUENCY (MHz)

= 50 kHz, Clock = 10 MHz

OUT

450 500 550 600

FREQUENCY (MHz)

TA = 25°C
V

= 5V

DD

AMP = AD8038
65k CODES

TA = 25°C



= 3V

V

DD

AMP = AD8038
65k CODES

= 500 kHz, Clock = 25 MHz

OUT

TA = 25°C



V

= 3V

DD

AMP = AD8038
65k CODES

04462-0-049

04462-0-050

0

–10

–20

–30

–40

–50

(dB)

–60

–70

–80

–90

–100

70 12075 80 85 115

Figure 33. Narrow-Band IMD, f

95

90 100 105 110

FREQUENCY (MHz)

= 90 kHz, 100 kHz, Clock = 10 MHz

OUT

TA = 25°C
V

DD

AMP = AD8038
65k CODES

0

–10

–20

–30

–40

–50

(dB)

–60

–70

–80

–90

–100

0 400

50 300 350100 150 200 250

Figure 34. Wideband IMD, f

FREQUENCY (kHz)

= 90 kHz, 100 kHz, Clock = 25 MHz

OUT

TA = 25°C
V

DD

AMP = AD8038
65k CODES

OUTPUT NOISE (nV/ Hz)

300

250

200

150

100

ZERO SCALE LOADED TO DAC

MIDSCALE LOADED TO DAC

FULL SCALE LOADED TO DAC

50

TA = 25°C
AMP = AD8038





= 3V

= 5V

04462-0-052

04462-0-053

–120

50 150

60 70 80 130 140

Figure 32. Narrow-Band SFDR, f

90 100 110 120

FREQUENCY (MHz)

= 100 kHz, Clock = 25 MHz

OUT

04462-0-051

Rev. 0 | Page 14 of 32

0

100 1k 10k 100k

FREQUENCY (Hz)

Figure 35. Output Noise Spectral Density

04462-0-054

AD5429/AD5439/AD5449

GENERAL DESCRIPTION

The AD5429/AD5439/AD5449 are 8-, 10-, and 12-bit dual­channel current output DACs consisting of a standard inverting
R−2R ladder configuration. A simplified diagram of one DAC
channel for the AD5449 is shown in Figure 36. The feedback
resistor R
(minimum 8 kΩ and maximum 12 kΩ). If I

has a value of R. The value of R is typically 10 kΩ

FB

OUT

1 and I

OUT

2 are
kept at the same potential, a constant current flows in each
ladder leg, regardless of digital input code. Therefore, the input
resistance presented at V

V

A

REF

RR R

2R

S1

DAC DATA LATCHES

Access is provided to the V

is always constant.

REF

2R

2R

S2

S3

AND DRIVERS

2R

S12

Figure 36. Simplified Ladder

REF

, RFB, I

OUT

1, and I

2R

2R

2 terminals of

OUT

R
I
I

OUT
OUT

A

FB

1A
2A

04464-0-006

the DACs, making the devices extremely versatile and allowing
them to be configured in several operating modes, such as
unipolar mode, bipolar output mode, or single-supply mode.

UNIPOLAR MODE

Using a single op amp, these devices can easily be configured to
provide 2-quadrant multiplying operation or a unipolar output
voltage swing, as shown in Figure 37.

When an output amplifier is connected in unipolar mode, the
output voltage is given by

OUT

REF

n

DVV 2/×−=

where D is the fractional representation of the digital word
loaded to the DAC, and n is the number of bits.

D = 0 to 255 (AD5429)
= 0 to 1023 (AD5439)
= 0 to 4095 (AD5449)

With a fixed 10 V reference, the circuit shown in Figure 37 gives
a unipolar 0 V to −10 V output voltage swing. When V

is an ac

IN

signal, the circuit performs 2-quadrant multiplication.

Table 5 shows the relationship between digital code and the
expected output voltage for unipolar operation for the AD5429.

Table 5. Unipolar Code Table

Digital Input Analog Output (V)

1111 1111 −V
1000 0000 −V
0000 0001 −V
0000 0000 −V

(4095/4096)

REF

(2048/4096) = −V

REF

(1/4096)

REF

(0/4096) = 0

REF

REF

/2

V

DD

V

DD

V

REF

R1

NOTES:

1. R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.

2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.

3. DAC B OMITTED FOR CLARITY.

AD5429/

V

AD5439/

REF

AD5449

SCLKSYNC

µCONTROLLER

SDIN GND

RFBA

I

I

OUT

OUT

R2

C1

1A

2A

AGND

A1

V

= 0V TO –V

OUT

REF

04464-0-007

Figure 37. Unipolar Operation

Rev. 0 | Page 15 of 32

AD5429/AD5439/AD5449

(

)

BIPOLAR OPERATION

In some applications, it might be necessary to generate full
4-quadrant multiplying operation or a bipolar output swing.
This can be easily accomplished by using another external
amplifier and three external resistors, as shown in Figure 38.

When V
multiplication. When connected in bipolar mode, the output
voltage is

where D is the fractional representation of the digital word
loaded to the DAC, and n is the number of bits.

D = 0 to 255 (AD5429)
= 0 to 1023 (AD5439)
= 0 to 4095 (AD5449)

Table 6 shows the relationship between digital code and the
expected output voltage for bipolar operation with the AD5429.

Table 6. Bipolar Code Table

Digital Input Analog Output (V)

1111 1111 +V
1000 0000 0
0000 0001 −V
0000 0000 −V

is an ac signal, the circuit performs 4-quadrant

IN

n

−1

VDVV −×=

OUT

REF

2/

REF

(2047/2048)

REF

(2047/2048)

REF

(2048/2048)

REF

STABILITY

In the I-to-V configuration, the I
inverting node of the op amp must be connected as closely as
possible, and proper PCB layout techniques must be employed.
Because every code change corresponds to a step function, gain
peaking can occur, if the op amp has limited GBP and there is
excessive parasitic capacitance at the inverting node. This
parasitic capacitance introduces a pole into the open loop
response, which can cause ringing or instability in the closed­loop applications circuit.

As shown in Figure 37 and Figure 38, an optional compensation
capacitor, C1, can be added in parallel with R
small a value of C1 can produce ringing at the output, while too
large a value can adversely affect the settling time. C1 should be
found empirically, but 1 pF to 2 pF is generally adequate for the
compensation.

of the DAC and the

OUT

for stability. Too

FB

R3

20kΩ

V

DD

V

R1

V

±10V

REF

V

REF

µCONTROLLER

AD5429/
AD5439/

AD5449

SCLKSYNC

DD

SDIN

R2

R5

RFBA

I

1A

OUT

I

2A

OUT

GND

NOTES:

1. R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.
ADJUST R1 FOR V

2. MATCHING AND TRACKING IS ESSENTIAL FOR RESISTOR PAIRS
R3 AND R4.

3. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED,
IF A1/A2 IS A HIGH SPEED AMPLIFIER.

4. DAC B AND ADDITIONAL PINS OMITTED FOR CLARITY.

C1

A1

AGND

OUT

R4

10kΩ

= 0V WITH CODE 10000000 LOADED TO DAC.

20kΩ

A2

V

=–V

REF

TO +V

OUT

REF

04464-0-008

Figure 38. Bipolar Operation

Rev. 0 | Page 16 of 32

AD5429/AD5439/AD5449

V

SINGLE-SUPPLY APPLICATIONS

Voltage-Switching Mode

Figure 39 shows the DACs operating in voltage-switching mode.
The reference voltage, V
connected to AGND, and the output voltage is available at the
V

terminal. In this configuration, a positive reference voltage

REF

results in a positive output voltage, making single-supply
operation possible. The output from the DAC is voltage at a
constant impedance (the DAC ladder resistance). Therefore, an
op amp is necessary to buffer the output voltage. The reference
input no longer sees a constant input impedance, but one that
varies with code. So, the voltage input should be driven from a
low impedance source.

, is applied to the I

IN

OUT

1 pin, I

OUT

2 is

POSITIVE OUTPUT VOLTAGE

The output voltage polarity is opposite to the V
dc reference voltages. To achieve a positive voltage output, an
applied negative reference to the input of the DAC is preferred
over the output inversion through an inverting amplifier
because of the resistor’s tolerance errors. To generate a negative
reference, the reference can be level-shifted by an op amp such
that the V

and GND pins of the reference become the virtual

OUT

ground and −2.5 V, respectively, as shown in Figure 40.

polarity for

REF

Note that V

is limited to low voltages, because the switches in

IN

the DAC ladder no longer have the same source-drain drive
voltage. As a result, their on resistance differs and this degrades
the integral linearity of the DAC. Also, V

must not go negative

IN

by more than 0.3 V or an internal diode turns on, exceeding the
maximum ratings of the device. In this type of application, the
DAC’s full range of multiplying capability is lost.

V

DD

R

V

FB

DD

1

I

IN

+

5V

1/2 AD8552

–5V

OUT

I

2

OUT

GND

NOTES:

1. ADDITIONAL PINS OMITTED FOR CLARITY.

2. C1 PHASE COMPENSATION (1pF–2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.

Figure 39. Single-Supply Voltage-Switching Mode

VDD = +5V

ADR03

V

V

IN

OUT

GND

V

REF

DD

8-/10-/12-BIT

DAC

GND

–2.5V

V

R

R

1

2

V

V

REF

OUT

04464-0-009

C

R

FB

I

1

OUT

I

2

OUT

1

1/2 AD8552

V

= 0V TO +2.5V

OUT

NOTES

1. ADDITIONAL PINS OMITTED FOR CLARITY.

2. C1 PHASE COMPENSATION (1pF–2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.

04464-0-010

Figure 40. Positive Voltage Output with Minimum Components

Rev. 0 | Page 17 of 32

AD5429/AD5439/AD5449

ADDING GAIN

In applications in which the output voltage is required to be
greater than V
amplifier, or it can be achieved in a single stage. Be sure to take
into consideration the effect of temperature coefficients of the
thin film resistors of the DAC. Simply placing a resistor in series
with the R
coefficients, resulting in larger gain temperature coefficient
errors. Instead, the circuit of Figure 41 is a recommended
method of increasing the gain of the circuit. R
should all have similar temperature coefficients, but they need
not match the temperature coefficients of the DAC. This
approach is recommended in circuits in which gains of > 1
are required.

DIVIDER OR PROGRAMMABLE GAIN ELEMENT

Current-steering DACs are very flexible and lend themselves to
many different applications. If this type of DAC is connected as
the feedback element of an op amp, and R
resistor, as shown in Figure 42, then the output voltage is
inversely proportional to the digital input fraction D. For

D = 1 − 2

OUT

, gain can be added with an additional external

IN

resistor causes mismatches in the temperature

FB

, R2, and R3

1

is used as the input

FB

n

the output voltage is

n

−

()

VDVV

−−=−= 21//

ININ

V

DD

As D is reduced, the output voltage increases. For small values
of the digital fraction D, it is important to ensure that the
amplifier does not saturate and also that the required accuracy
is met. For example, an 8-bit DAC driven with the binary code
0 × 10 (00010000)—that is, 16 decimal—in the circuit of
Figure 42 should cause the output voltage to be 16 × V

.

IN

However, if the DAC has a linearity specification of ±0.5 LSB,
then D can, in fact, have a weight in the range 15.5/256 to

16.5/256, so that the possible output voltage is in the range

15.5 V

to 16.5 VIN with an error of +3%, even though the DAC

IN

itself has a maximum error of 0.2%.

DAC leakage current is also a potential error source in divider
circuits. The leakage current must be counterbalanced by an
opposite current supplied from the op amp through the DAC.
Because only a fraction D of the current into the V
is routed to the I

1 terminal, the output voltage has to change

OUT

terminal

REF

as follows:

Output Error Voltage Due to DAC Leakage = (Leakage × R)/D

where R is the DAC resistance at the V

terminal. For a DAC

REF

leakage current of 10 nA, R = 10 kΩ and a gain (that is, 1/D) of
16, the error voltage is 1.6 mV.

V

R2

V

IN

NOTES:

1. ADDITIONAL PINS OMITTED FOR CLARITY.

2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.

V

REF

8-/10-/12-BIT

GND

R

DD

DAC

FB

I

OUT

I

OUT

C1

1

2

V

GAIN =

R1 =

OUT

R2 + R3

R2R3

R2 + R3

R2

04464-0-011

R3

R2

Figure 41. Increasing Gain of Current Output DAC

V

V

IN

R

I

1

OUT

I

2

OUT

NOTE:

1. ADDITIONAL PINS OMITTED FOR CLARITY.

DD

V

DD

FB

V

REF

GND

V

OUT

04464-0-012

Figure 42. Current-Steering DAC Used as a Divider

or Programmable Gain Element

Rev. 0 | Page 18 of 32

AD5429/AD5439/AD5449

REFERENCE SELECTION

When selecting a reference for use with the AD5429/AD5439/
AD5449 family of current output DACs, pay attention to the
reference’s output voltage temperature coefficient specification.
This parameter affects not only the full-scale error, but also
the linearity (INL and DNL) performance. The reference
temperature coefficient should be consistent with the system
accuracy specifications. For example, an 8-bit system required
to hold its overall specification to within 1 LSB over the
temperature range 0°C to 50°C dictates that the maximum
system drift with temperature should be less than 78 ppm/°C.
A 12-bit system with the same temperature range to overall
specification within 2 LSBs requires a maximum drift of
10 ppm/°C. By choosing a precision reference with low output
temperature coefficient, this error source can be minimized.
Table 7 lists some of the references available from Analog
Devices that are suitable for use with this range of current
output DACs.

AMPLIFIER SELECTION

The primary requirement for the current-steering mode is an
amplifier with low input bias currents and low input offset
voltage. The input offset voltage of an op amp is multiplied by
the variable gain (due to the code-dependent output resistance
of the DAC) of the circuit. A change in this noise gain between
two adjacent digital fractions produces a step change in the
output voltage due to the amplifier’s input offset voltage. This

output voltage change is superimposed upon the desired change
in output between the two codes and gives rise to a differential
linearity error, which, if large enough, could cause the DAC to
be nonmonotonic. The input bias current of an op amp also
generates an offset at the voltage output as a result of the bias
current flowing in the feedback resistor R

. Most op amps have

FB

input bias currents low enough to prevent any significant errors
in 12-bit applications.

Common-mode rejection of the op amp is important in
voltage-switching circuits, because it produces a code­dependent error at the voltage output of the circuit. Most
op amps have adequate common-mode rejection for use at
8-, 10-, and 12-bit resolution.

Provided that the DAC switches are driven from true wideband
low impedance sources (V

and AGND), they settle quickly.

IN

Consequently, the slew rate and settling time of a voltage­switching DAC circuit is determined largely by the output
op amp. To obtain minimum settling time in this configuration,
it is important to minimize capacitance at the V

REF

node
(voltage output node in this application) of the DAC. This is
done by using low input capacitance buffer amplifiers and
careful board design.

Most single-supply circuits include ground as part of the analog
signal range, which in turns requires an amplifier that can
handle rail-to-rail signals. Analog Devices supplies a large range
of single-supply amplifiers.

Table 7. Suitable ADI Precision References Recommended for Use with AD5429/AD5439/AD5449 DACs

Reference Output Voltage Initial Tolerance Temperature Drift 0.1 Hz to 10 Hz Noise Package

ADR01 10 V 0.1% 3 ppm/°C 20 µV p-p SC70, TSOT, SOIC
ADR02 5 V 0.1% 3 ppm/°C 10 µV p-p SC70, TSOT, SOIC
ADR03 2.5 V 0.2% 3 ppm/°C 10 µV p-p SC70, TSOT, SOIC
ADR425 5 V 0.04% 3 ppm/°C 3.4 µV p-p MSOP, SOIC

Table 8. Precision ADI Op Amps Suitable for Use with AD5429/AD5439/AD5449 DACs

Part No. Max Supply Voltage (V) V

OP97 ±20 25 0.1 0.9 0.2
OP1177 ±18 60 2 1.3 0.7
AD8551 ±6 5 0.05 1.5 0.4

(max) µV IB (max) nA GBP MHz Slew Rate V/µs

OS

Table 9. High Speed ADI Op Amps Suitable for Use with AD5429/AD5439/AD5449 DACs

Part No. Max Supply Voltage (V) BW @ ACL (MHz) Slew Rate (V/µs) V

AD8065 ±12 145 180 1500 0.01
AD8021 ±12 200 100 1000 1000
AD8038 ±5 350 425 3000 0.75

(max) µV IB max (nA)

OS

Rev. 0 | Page 19 of 32

AD5429/AD5439/AD5449

SERIAL INTERFACE

The AD5429/AD5439/AD5449 have an easy to use, 3-wire
interface that is compatible with SPI, QSPI, MICROWIRE, and
DSP interface standards. Data is written to the device in 16-bit
words. This 16-bit word consists of 4 control bits and either
8, 10, or 12 data bits, as shown in Figure 43, Figure 44, and
Figure 45.

Low Power Serial Interface

To minimize the power consumption of the device, the interface
powers up fully only when the device is being written to, that is,
on the falling edge of

are powered down on the rising edge of

DAC Control Bits C3–C0

Control bits C3 to C0 allow control of various functions of
the DAC, as shown in Table 11. Default setting of the DAC at
power-on are as follows.

Data is clocked into the shift register on falling clock edges;
daisy-chain mode is enabled. The device powers on with zero­scale load to the DAC register and I
bits allow the user to adjust certain features at power-on; for
example, daisy-chaining can be disabled if not in use, active
clock edge can be changed to rising edge, and DAC output can
be cleared to either zero scale or midscale. The user can also
initiate a readback of the DAC register contents for verification.

Control Register (Control Bits = 1101)

While maintaining software compatibility with the single­channel current output DACs (AD5426/AD5432/AD5443),
these DACs also feature some additional interface functionality.
Set the control bits to 1101 to enter control register mode.
Figure 46 shows the contents of the control register. The
following sections describe the functions of the control register.

. The SCLK and DIN input buffers

SYNC

.

SYNC

lines. The DAC control

OUT

SDO Control (SDO1 and SDO2)

The SDO bits enable the user to control the SDO output driver
strength, disable the SDO output, or configure it as an open­drain driver. The strength of the SDO driver affects the timing
of t

, and, when stronger, allows a faster clock cycle.

12

Table 10. SDO Control Bits

SDO2 SDO1 Function Implemented

0 0 Full SDO driver
0 1 SDO configured as open-drain
1 0 Weak SDO driver
1 1 Disable SDO output

Daisy-Chain Control (DSY)

DSY allows the enabling or disabling of daisy-chain mode.
A 1 enables daisy-chain mode, and 0 disables daisy-chain mode.
When disabled, a readback request is accepted, SDO is auto­matically enabled, the DAC register contents of the relevant
DAC are clocked out on SDO, and, when complete, SDO is
disabled again.

Hardware

The default setting for the hardware

Bit (HCLR)

CLR

bit is to clear the

CLR
registers and DAC output to zero code. A 1 in the HCLR bit
allows the

pin to clear the DAC outputs to midscale and

CLR

a 0 clears to zero scale.

Active Clock Edge (SCLK)

The default active clock edge is falling edge. Write a 1 to this bit
to clock data in on the rising edge, or a 0 for falling edge.

C3 C2

C3 C2

C3 C2

C0 DB7 DB6 DB5 DB4 DB3

C1

Figure 43. AD5429 8-Bit Input Shift Register Contents

C0 DB9 DB8 DB7 DB6 DB5

C1

Figure 44. AD5439 10-Bit Input Shift Register Contents

C0 DB11 DB10 DB9 DB8 DB7

C1

Figure 45. AD5449 12-Bit Input Shift Register Contents

DB2 DB1 DB0 0 0 0 0

DATA BITSCONTROL BITS

DB4 DB3 DB2 DB1 DB0 0 0

DATA BITSCONTROL BITS

DB6 DB5 DB4 DB3 DB2 DB1 DB0

DATA BITSCONTROL BITS

Rev. 0 | Page 20 of 32

DB0 (LSB)DB15 (MSB)

04464-0-013

DB0 (LSB)DB15 (MSB)

04464-0-014

DB0 (LSB)DB15 (MSB)

04464-0-015

AD5429/AD5439/AD5449

Function

SYNC

is an edge-triggered input that acts as a frame synchron-

SYNC
ization signal and chip enable. Data can be transferred into the

device only while

should be taken low, observing the minimum

SYNC
falling to SCLK falling edge setup time, t

is low. To start the serial data transfer,

SYNC

.

4

SYNC

Daisy-Chain Mode

Daisy-chain mode is the default power-on mode. To disable the
daisy-chain function, write 1001 to the control word. In daisy­chain mode, the internal gating on SCLK is disabled. The SCLK
is continuously applied to the input shift register when

SYNC

is

low. If more than 16 clock pulses are applied, the data ripples
out of the shift register and appears on the SDO line. This data
is clocked out on the rising edge of SCLK (this is the default, use
the control word to change the active edge) and is valid for the
next device on the falling edge (default). By connecting this line
to the SDIN input on the next device in the chain, a multidevice
interface is constructed. For each device in the system, 16 clock
pulses are required. Therefore, the total number of clock cycles
must equal 16, where N is the total number of devices in the
chain. See Figure 3.

When the serial transfer to all devices is complete,

SYNC

should

be taken high. This prevents additional data from being clocked
into the input shift register. A burst clock containing the exact
number of clock cycles can be used and

time later. After the rising edge of

SYNC

taken high some

SYNC
, data is automatically

transferred from each device’s input shift register to the
addressed DAC. When control bits = 0000, the device is in no
operation mode. This might be useful in daisy-chain applica­tions, in which the user does not wish to change the settings of a
particular DAC in the chain. Write 0000 to the control bits for
that DAC, and the following data bits are ignored.

Standalone Mode

After power-on, write 1001 to the control word to disable daisy­chain mode. The first falling edge of

resets a counter that

SYNC

counts the number of serial clocks to ensure that the correct
number of bits are shifted in and out of the serial shift registers.
A

edge during the 16-bit write cycle causes the device to

SYNC

abort the current write cycle.

After the falling edge of the 16th SCLK pulse, data is automat­ically transferred from the input shift register to the DAC. In
order for another serial transfer to take place, the counter must
be reset by the falling edge of

Function

LDAC

The

function allows asynchronous or synchronous

LDAC

SYNC

.

updates to the DAC output. The DAC is asynchronously
updated when this signal goes low. Alternatively, if this line is
held permanently low, an automatic or synchronous update
mode is selected, whereby the DAC is updated on the 16th clock
falling edge when the device is in standalone mode, or on the
rising edge of

when in daisy-chain mode.

SYNC

Table 11. DAC Control Bits

C3 C2 C1 C0 DAC Function Implemented

0 0 0 0 A and B No operation (power-on default)
0 0 0 1 A Load and update
0 0 1 0 A Initiate readback
0 0 1 1 A Load input register
0 1 0 0 B Load and update
0 1 0 1 B Initiate readback
0 1 1 0 B Load input register
0 1 1 1 A and B Update DAC outputs
1 0 0 0 A and B Load input registers
1 0 0 1 - Daisy chain disable
1 0 1 0 - Clock data to shift register on rising edge
1 0 1 1 - Clear DAC output to zero scale
1 1 0 0 - Clear DAC output to midscale
1 1 0 1 - Control word
1 1 1 0 - Reserved
1 1 1 1 - No operation

11

CONTROL BITS

1 SDO2 SDO1 DSY HCLR SCLK

0

Figure 46. Control Register Loading Sequence

XXXXXXX

DB0 (LSB)DB15 (MSB)

04464-0-016

Rev. 0 | Page 21 of 32

AD5429/AD5439/AD5449

Software

Load and update mode can also function as a software update
function, irrespective of the voltage level on the

MICROPROCESSOR INTERFACING

Microprocessor interfacing to this family of DACs is via a serial
bus that uses standard protocol compatible with microcon­trollers and DSP processors. The communications channel is
a 3-wire interface consisting of a clock signal, a data signal, and
a synchronization signal. The AD5429/AD5439/AD5449
require a 16-bit word with the default being data valid on the
falling edge of SCLK, but this is changeable via the control bits
in the data-word.

ADSP-21xx to AD5429/AD5439/AD5449 Interface

The ADSP-21xx family of DSPs is easily interfaced to this
family of DACs without the need for extra glue logic. Figure 47
is an example of an SPI interface between the DAC and the
ADSP-2191M. SCK of the DSP drives the serial data line, DIN.
SYNC is driven from one of the port lines, in this case SPIxSEL.

ADSP-2191*

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 47. ADSP-2191 SPI to AD5429/AD5439/AD5449 Interface

A serial interface between the DAC and DSP SPORT is shown
in Figure 48. In this interface example, SPORT0 is used to
transfer data to the DAC shift register. Transmission is initiated
by writing a word to the Tx register after the SPORT has been
enabled. In a write sequence, data is clocked out on each rising
edge of the DSP’s serial clock and clocked into the DAC input
shift register on the falling edge of its SCLK. The update of the
DAC output takes place on the rising edge of the SYNC signal.

ADSP-2101/
ADSP-2103/
ADSP-2191*

LDAC

SPIxSEL

MOSI

SCLK

Function

SCK

TFS

DT

pin.

LDAC

AD5429/AD5439/

AD5449*

SYNC
SDIN
SCLK

AD5429/AD5439/

AD5449*

SYNC
SDIN

SCLK

04464-0-027

Communication between two devices at a given clock speed is
possible when the following specifications are compatible:
frame sync delay and frame sync setup-and-hold, data delay and
data setup-and-hold, and SCLK width. The DAC interface
expects a t

SYNC falling edge to SCLK falling edge setup time)

4

of 13 ns minimum. See the ADSP-21xx User Manual for details
on clock and frame sync frequencies for the SPORT register.

Table 12 shows how the SPORT control register must be set up.

Table 12.

Name Setting Description

TFSW 1 Alternate framing
INVTFS 1 Active low frame signal
DTYPE 00 Right-justify data
ISCLK 1 Internal serial clock
TFSR 1 Frame every word
ITFS 1 Internal framing signal
SLEN 1111 16-bit data-word

80C51/80L51 to AD5429/AD5439/AD5449 Interface

A serial interface between the DAC and the 80C51/80L51 is
shown in Figure 49. TxD of the 80C51/80L51drives SCLK of the
DAC serial interface, while RxD drives the serial data line, DIN.
P1.1 is a bit-programmable pin on the serial port and is used to

SYNC

drive

. When data is to be transmitted to the switch, P1.1
is taken low. The 80C51/80L51 transmit data only in 8-bit bytes;
thus, only eight falling clock edges occur in the transmit cycle.
To load data correctly to the DAC, P1.1 is left low after the first
eight bits are transmitted, and a second write cycle is initiated to
transmit the second byte of data. Data on RXD is clocked out of
the microcontroller on the rising edge of TXD and is valid on
the falling edge. As a result, no glue logic is required between
the DAC and microcontroller interface. P1.1 is taken high
following the completion of this cycle. The 80C51/80L51
provide the LSB of the SBUF register as the first bit in the data
stream. The DAC input register requires its data with the MSB
as the first bit received. The transmit routine should take this
into account.

80C51*

TxD

RxD

P1.1

AD5429/AD5439/

AD5449*

SCLK

SDIN
SYNC

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 48. ADSP-2101/ADSP-2103/ADSP-2191 SPORT to

AD5429/AD5439/AD5449 Interface

04464-0-028

Rev. 0 | Page 22 of 32

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 49. 80C51/80L51 to AD5429/AD5439/AD5449 Interface

04464-0-029

AD5429/AD5439/AD5449

MC68HC11 to AD5429/AD5439/AD5449 Interface

Figure 50 is an example of a serial interface between the DAC
and the MC68HC11 microcontroller. The serial peripheral
interface (SPI) on the MC68HC11 is configured for master
mode (MSTR) = 1, clock polarity bit (CPOL) = 0, and the
clock phase bit (CPHA) = 1. The SPI is configured by writing
to the SPI control register (SPCR)—see the 68HC11 User
Manual. The SCK of the 68HC11 drives the SCLK of the DAC
interface; the MOSI output drives the serial data line (D

IN

) of

the AD5429/AD5439/AD5449.

SYNC

The

signal is derived from a port line (PC7). When data
is being transmitted to the AD5429/AD5439/AD5449, the
SYNC

line is taken low (PC7). Data appearing on the MOSI
output is valid on the falling edge of SCK. Serial data from the
68HC11 is transmitted in 8-bit bytes with only 8 falling clock
edges occurring in the transmit cycle. Data is transmitted MSB
first. To load data to the DAC, PC7 is left low after the first eight
bits are transferred, and a second serial write operation is
performed to the DAC. PC7 is taken high at the end of this
procedure.

MC68HC11*

PC7

SCK

MOSI

AD5429/AD5439/

AD5449*

SYNC
SCLK
SDIN

MICROWIRE to AD5429/AD5439/AD5449 Interface

Figure 51 shows an interface between the DAC and any
MICROWIRE compatible device. Serial data is shifted out on
the falling edge of the serial clock, SK, and is clocked into the
DAC input shift register on the rising edge of SK, which
corresponds to the falling edge of the DAC’s SCLK.

MICROWIRE*

SK
SO
CS

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 51. MICROWIRE to AD5429/AD5439/AD5449 Interface

AD5429/AD5439/

AD5449*

SCLK
SDIN
SYNC

PIC16C6x/7x to AD5429/AD5439/AD5449

The PIC16C6x/7x synchronous serial port (SSP) is configured
as an SPI master with the clock polarity bit (CKP) = 0. This is
done by writing to the synchronous serial port control register
(SSPCON). See the PIC16/17 Microcontroller User Manual.
In this example, the I/O port RA1 is used to provide a

SYNC

signal and enable the serial port of the DAC. This micro­controller transfers only eight bits of data during each serial
transfer operation; therefore, two consecutive write operations
are required. Figure 52 shows the connection diagram.

04464-0-031

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 50. MCH68HC11/68L11 to AD5429/AD5439/AD5449 Interface

If the user wants to verify the data previously written to the
input shift register, the SDO line can be connected to MISO of
the MC68HC11, and, with

SYNC

low, the shift register clocks

data out on the rising edges of SCLK.

04464-0-030

PIC16C6x/7x*

SCK/RC3

SDI/RC4

RA1

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 52. PIC16C6x/7x to AD5429/AD5439/AD5449 Interface

AD5429/AD5439/

AD5449*

SCLK
SDIN
SYNC

04464-0-032

Rev. 0 | Page 23 of 32

AD5429/AD5439/AD5449

PCB LAYOUT AND POWER SUPPLY DECOUPLING

In any circuit where accuracy is important, careful consider­ation of the power supply and ground return layout helps to
ensure the rated performance. The printed circuit board on
which the DAC is mounted should be designed so that the
analog and digital sections are separated and confined to
certain areas of the board. If the DAC is in a system in which
multiple devices require an AGND to DGND connection, the
connection should be made at one point only. The star ground
point should be established as close as possible to the device.

These DACs should have ample supply bypassing of 10 µF
in parallel with 0.1 µF on the supply located as close to the
package as possible, ideally right up against the device. The

0.1 µF capacitor should have low effective series resistance
(ESR) and effective series inductance (ESI), like the common
ceramic types that provide a low impedance path to ground at
high frequencies, to handle transient currents due to internal
logic switching. Low ESR 1 µF to 10 µF tantalum or electrolytic
capacitors should also be applied at the supplies to minimize
transient disturbance and filter out low frequency ripple.

Fast switching signals such as clocks should be shielded with
digital ground to avoid radiating noise to other parts of the
board, and should never be run near the reference inputs.

Avoid crossover of digital and analog signals. Traces on opposite
sides of the board should run at right angles to each other. This
reduces the effects of feedthrough on the board. A microstrip
technique is by far the best, but not always possible with a
double-sided board. In this technique, the component side of
the board is dedicated to the ground plane, while signal traces
are placed on the soldered side.

It is good practice to employ compact, minimum lead-length
PCB layout design. Leads to the input should be as short as
possible to minimize IR drops and stray inductance.

The PCB metal traces between V
matched to minimize gain error. To maximize high frequency
performance, the I-to-V amplifier should be located as close to
the device as possible.

and RFB should also be

REF

POWER SUPPLIES FOR THE EVALUATION BOARD

The board requires ±12 V and +5 V supplies. The 12 V VDD
and V

are used to power the output amplifier, while the 5 V

SS

is used to power the DAC (V

Both supplies are decoupled to their respective ground plane
with 10 µF tantalum and 0.1 µF ceramic capacitors.

) and transceivers (VCC).

DD1

EVALUATION BOARD FOR THE DACS

The evaluation board includes a DAC from the AD5429/
AD5439/AD5449 family and a current-to-voltage amplifier,
AD8065. On the evaluation board is a 10 V reference, ADR01.
An external reference can also be applied via an SMB input.

The evaluation kit consists of a CD-ROM with self-installing
PC software to control the DAC. The software allows the user to
write a code to the device.

Rev. 0 | Page 24 of 32

AD5429/AD5439/AD5449

TP1

C8

SS

V

8
J

A

REF

V

AD5449

6
–

1
P

J1

0.1µF
4

2

A

REF

V

9
1
–

1
P

A

OUT

V

C9

6

AD8065AR

7

V–

V+

3

U3

9
J

2

1

0

2

2

2

–

–

–

1

1

1

P

P

P

+

C10

10µF

B
V

B

REF

V

4

3

2

2

–

–

1

1

P

P

0.1µF

DD

V

A
B

LK1

C5

0.1µF

REF

6

5

2

2

–

–

1

1

P

P

4

1

OUT

V

U2

IN

+V

3

DD

V

DD

V

C12

+

C11

3
–

2
P

0

9

8

7

3

2

2

2

–

–

–

–

1

1

1

1

P

P

P

P

4

GND

TRIM

5

C4

0.1µF

+

C3

10µF

1

D
N
G
A

C14

10µF

+

C13

0.1µF

2
–

2
P

DD

V

SS

V

C16

10µF

0.1µF

1
–

2
P

10µF

+

C15

0.1µF

4
–

2
P

04464-0-023

B

OUT

V

J2

TP2

+

C18

+

C2

1

DD

V

C1

10µF

C19

10µF

0.1µF

U1

C17

2
1

SS

V

1.8pF

DD

V

0.1µF

6

4

V–

2

4

6

1

1

B

B

1

FB

R

OUT

I

K

N

I

L

D

C

S

S

8

0

7

1

C20

10µF

AD8065AR

7

V+

3

U4

5

3

1

B

B

2

FB

R

OUT

I

C
N
Y
S

+

C21

0.1µF

DD

V

1

2

4

A

A

2

1

OUT

OUT

I

I

C

O

A

D

D

S

L

6

9

+

C7

10µF

C6

1.8pF

3
1

B

A

REF

REF

V

V

5

D
N
G

R
L
C

1
1

AD5429/AD5439/

7

C

K

N

I

L

D

C

S

S

4

3

J

J

Ω

k

1

0

R

1

DD

V

Ω

k

2

0

R

1

DD

V

R3

10kΩ

DD

V

K

N

I

L

D

C

S

S

3
–

1
P

C

N

A

Y

D

S

L

6

5

J

J

2

4

–

–

1

1

P

P

J

R
L
C

O
D
S

A

B

2
K
L

C
A
D
L

5
–

1
P

3
1
–

1
P

Figure 53. Schematic of the Evaluation Board

Rev. 0 | Page 25 of 32

AD5429/AD5439/AD5449

Figure 54. Component-Side Artwork

04464-0-024

04464-0-025

Figure 55. Silkscreen—Component-Side View ( Top)

Rev. 0 | Page 26 of 32

AD5429/AD5439/AD5449

04464-0-026

Figure 56. Solder-Side Artwork

Rev. 0 | Page 27 of 32

AD5429/AD5439/AD5449

OVERVIEW OF AD54xx DEVICES

Table 13.

Part No. Resolution No. DACs INL (LSB) Interface Package Features

AD5424 8 1 ±0.25 Parallel RU-16, CP-20
AD5426 8 1 ±0.25 Serial RM-10 10 MHz BW, 50 MHz Serial

AD5428 8 2 ±0.25 Parallel RU-20
AD5429 8 2 ±0.25 Serial RU-10 10 MHz BW, 50 MHz Serial
AD5450 8 1 ±0.25 Serial RJ-8 10 MHz BW, 50 MHz Serial
AD5432 10 1 ±0.5 Serial RM-10 10 MHz BW, 50 MHz Serial
AD5433 10 1 ±0.5 Parallel RU-20, CP-20
AD5439 10 2 ±0.5 Serial RU-16 10 MHz BW, 50 MHz Serial
AD5440 10 2 ±0.5 Parallel RU-24
AD5451 10 1 ±0.25 Serial RJ-8 10 MHz BW, 50 MHz Serial
AD5443 12 1 ±1 Serial RM-10 10 MHz BW, 50 MHz Serial
AD5444 12 1 ±0.5 Serial RM-8 10 MHz BW, 50 MHz Serial

AD5415 12 2 ±1 Serial RU-24 10 MHz BW, 58 MHz Serial
AD5445 12 2 ±1 Parallel RU-20, CP-20

AD5447 12 2 ±1 Parallel RU-24
AD5449 12 2 ±1 Serial RU-16 10 MHz BW, 50 MHz Serial

AD5452 12 1 ±0.5 Serial RJ-8, RM-8 10 MHz BW, 50 MHz Serial
AD5446 14 1 ±1 Serial RM-8 10 MHz BW, 50 MHz Serial
AD5453 14 1 ±2 Serial UJ-8, RM-8 10 MHz BW, 50 MHz Serial
AD5553 14 1 ±1 Serial RM-8 4 MHz BW, 50 MHz Serial Clock
AD5556 14 1 ±1 Parallel RU-28
AD5555 14 2 ±1 Serial RM-8 4 MHz BW, 50 MHz Serial Clock
AD5557 14 2 ±1 Parallel RU-38

AD5543 16 1 ±2 Serial RM-8 4 MHz BW, 50 MHz Serial Clock
AD5546 16 1 ±2 Parallel RU-28

AD5545 16 2 ±2 Serial RU-16 4 MHz BW, 50 MHz Serial Clock
AD5547 16 2 ±2 Parallel RU-38

10 MHz BW, 17 ns

10 MHz BW, 17 ns

10 MHz BW, 17 ns

10 MHz BW, 17 ns

10 MHz BW, 17 ns
10 MHz BW, 17 ns

4 MHz BW, 20 ns

4 MHz BW, 20 ns

4 MHz BW, 20 ns

4 MHz BW, 20 ns

CS Pulse Width

CS Pulse Width

CS Pulse Width

CS Pulse Width

CS Pulse Width
CS Pulse Width

WR Pulse Width

WR Pulse Width

WR Pulse Width

WR Pulse Width

Rev. 0 | Page 28 of 32

AD5429/AD5439/AD5449

OUTLINE DIMENSIONS

5.10

5.00

4.90

0.15

0.05

4.50

4.40

4.30

PIN 1

16

0.65

BSC

COPLANARITY

COMPLIANT TO JEDEC STANDARDS MO-153AB

0.10

0.30

0.19

9

81

1.20
MAX

SEATING
PLANE

6.40
BSC

0.20

0.09
8°

0°

0.75

0.60

0.45

Figure 57. 16-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-16)

Dimensions shown in millimeters

ORDERING GUIDE

Model Resolution INL (LSBs) Temperature Range Package Description Package Option

AD5429YRU 8 ±0.5 −40°C to +125°C TSSOP RU-16
AD5429YRU-REEL 8 ±0.5 −40°C to +125°C TSSOP RU-16
AD5429YRU-REEL7 8 ±0.5 −40°C to +125°C TSSOP RU-16
AD5439YRU 10 ±0.5 −40°C to +125°C TSSOP RU-16
AD5439YRU-REEL 10 ±0.5 −40°C to +125°C TSSOP RU-16
AD5439YRU-REEL7 10 ±0.5 −40°C to +125°C TSSOP RU-16
AD5449YRU 12 ±1 −40°C to +125°C TSSOP RU-16
AD5449YRU-REEL 12 ±1 −40°C to +125°C TSSOP RU-16
AD5449YRU-REEL7 12 ±1 −40°C to +125°C TSSOP RU-16
EVAL-AD5429EB Evaluation Board
EVAL-AD5439EB Evaluation Board
EVAL-AD5449EB Evaluation Board

Rev. 0 | Page 29 of 32

AD5429/AD5439/AD5449

NOTES

Rev. 0 | Page 30 of 32

AD5429/AD5439/AD5449

NOTES

Rev. 0 | Page 31 of 32

AD5429/AD5439/AD5449

NOTES

© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.

D04464–0–7/04(0)

Rev. 0 | Page 32 of 32