Datasheet AD5428 Datasheet (Analog Devices)

Dual 8-,10-,12-Bit, High Bandwidth

FEATURES

10 MHz multiplying bandwidth
Fast parallel interface (58 MSPS write cycle)
AD7528 upgrade (AD5428)
AD7547 upgrade (AD5447)

2.5 V to 5.5 V supply operation
±10 V reference input
20- and 24-lead TSSOP packages
Dual 8-, 10-, and 12-bit current output DACs
Guaranteed monotonic
4-quadrant multiplication
Power-on reset
Readback function

0.5 µA typical current consumption

APPLICATIONS

Portable battery-powered applications
Waveform generators
Analog processing
Instrumentation applications
Programmable amplifiers and attenuators
Digitally controlled calibration
Programmable filters and oscillators
Composite video
Ultrasound
Gain, offset, and voltage trimming

Multiplying DACs with Parallel Interface

AD5428/AD5440/AD5447

FUNCTIONAL BLOCK DIAGRAM

V

A

REF

AD5428/AD5440/AD5447

DATA

INPUTS

V

DB0

DB7
DB9

DB11

DAC A/B

R/W

DGND

DD

INPUT

BUFFER

CS

CONTROL

LOGIC

POWER-ON

RESET

LATCH

LATCH

8-/10-/12-BIT
R-2R DAC A

8-/10-/12-BIT
R-2R DAC B

B

V

REF

R

R

Figure 1. AD5428/AD5440/AD5447

GENERAL DESCRIPTION

The AD5428/AD5440/AD54471 are dual CMOS 8-, 10-, and
12-bit current output digital-to-analog converters (DACs),
respectively.

These devices operate from a 2.5 V to 5.5 V power supply,
making them suited to battery-powered and other applications.

The DACs utilize data readback, allowing the user to read the
contents of the DAC register via the DB pins. On power-up, the
internal register and latches are filled with zeros and the DAC
outputs are at zero scale.

As a result of manufacture on a CMOS submicron process, they
offer excellent 4-quadrant multiplication characteristics, with
large signal multiplying bandwidths of up to 10 MHz.

R

FB

I

OUT

AGND

R

FB

I

OUT

A

A

B

B

04462-0-001

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

The applied external reference input voltage (V

REF)

the full-scale output current. An integrated feedback resistor

) provides temperature tracking and full-scale voltage

(R

FB

output when combined with an external I-to-V precision
amplifier.

The AD5428 is available in a small 20-lead TSSOP package,
while the AD5440/AD5447 DACs are available in small 24-lead
TSSOP packages.

1

US Patent Number 5,689,257.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

www.analog.com

determines

AD5428/AD5440/AD5447

TABLE OF CONTENTS

Specifications..................................................................................... 3

Used as a Divider or Programmable Gain Element............... 19

Timing Characteristics..................................................................... 5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configurations and Function Descriptions ........................... 7

Te r m in o l o g y .................................................................................... 10

Typical Performance Characteristics........................................... 11

General Description................................................................... 16

Circuit Operation ....................................................................... 16

Single-Supply Applications........................................................ 18

Positive Output Voltage ............................................................. 19

Adding Gain................................................................................ 19

REVISION HISTORY

7/04—Revision 0: Initial Version

Reference Selection .................................................................... 20

Amplifier Selection .................................................................... 20

Parallel Interface ......................................................................... 20

Microprocessor Interfacing....................................................... 20

PCB Layout and Power Supply Decoupling ........................... 21

Evaluation Board for the DACs................................................ 21

Power Supplies for the Evaluation board................................ 21

Bill of Materials............................................................................... 25

Overview of AD54xx Devices....................................................... 26

Outline Dimensions....................................................................... 27

Ordering Guide .......................................................................... 28

Rev. 0 | Page 2 of 28

AD5428/AD5440/AD5447

SPECIFICATIONS

Temperature range for Y version is –40°C to +125°C.

= 2.5 V to 5.5 V, V

V

DD

REF

A = V

B = +10 V, AGND = 0 V. All specifications T

REF

MIN

to T

, unless otherwise noted. DC performance

MAX

measured with OP1177, AC performance with AD8038, unless otherwise noted.

Table 1.

Parameter Min Typ Max Unit Conditions

STATIC PERFORMANCE
AD5428
Resolution 8 Bits
Relative Accuracy ±0.25 LSB
Differential Nonlinearity ±1 LSB Guaranteed monotonic
AD5440
Resolution 10 Bits
Relative Accuracy ±0.5 LSB
Differential Nonlinearity ±1 LSB Guaranteed monotonic
AD5447
Resolution 12 Bits
Relative Accuracy ±1 LSB
Differential Nonlinearity –1/+2 LSB Guaranteed monotonic
Gain Error ±10 m V
Gain Error Temp CoefficientT1 ±5 ppm FSR/°C
Output Leakage Current ±10 nA Data = 0000H, TA = 25°C.
±25 nA Data = 0000H.
REFERENCE INPUT1
Reference Input Range ±10 V
V

A, V

B Input Resistance 8 10 12 k Ω Input resistance TC = –50 ppm/°C

REF

A to V

B Input

REF

1.6 2.5 % Typ = 25°C, max = 125°C

V

REF

REF

Resistance Mismatch
R

A,RFBB Input Resistance 8 10 12 k Ω Input resistance TC = –50 ppm/°C

FB

Input Capacitance
Code 0 3 6 pF

Code 4095 5 8 pF
DIGITAL INPUTS/OUTPUT1
Input High Voltage, VIH 1.7 V VDD = 2.5 V to 5.5 V
Input Low Voltage, V

IL

0.8 V VDD = 2.7 V to 5.5 V

0.7 V VDD = 2.5 V to 2.7 V
Input Leakage Current, IIL 2 µA
Input Capacitance 4 10 pF
V

= 4.5 V to 5.5 V

DD

Output Low Voltage, VOL 0.4 V I
Output High Voltage, VOH
V

= 2.5 V to 3.6 V

DD

V

−1

DD

V I

Output Low Voltage, VOL 0.4 V I
Output High Voltage, VOH

V

− 0.5

DD

V I

= 200 µA

SINK

SOURCE

= 200 µA

SINK

SOURCE

= 200 µA

= 200 µA
DYNAMIC PERFORMANCE1
Reference Multiplying BW 10 MHz V
Output Voltage Settling Time V

= ±3.5 V, DAC loaded all 1s

REF

= ±10 V, R

REF

= 100 Ω, C

LOAD

LOAD

= 15 pF
DAC latch alternatively loaded with 0s and 1s
AD5428 30 60 ns Measured to ±16 mV of FS
AD5440 35 70 ns Measured to ±4 mV of FS
AD5447 80 120 ns Measured to ±1 mV of FS

Rev. 0 | Page 3 of 28

AD5428/AD5440/AD5447

Parameter Min Typ Max Unit Conditions

Digital Delay 20 40 ns Interface delay time
10% to 90% Settling Time 15 30 Ns
Digital-to-Analog Glitch Impulse 2

nV-s

Multiplying Feedthrough Error –75 dB DAC latches loaded with all 0s. Reference = 10 kHz
Output Capacitance
I

2 22 25 pF DAC latches loaded with all 0s

OUT

10 12 pF DAC latches loaded with all 1s
I

1 12 17 pF DAC latches loaded with all 0s

OUT

25 30 pF DAC latches loaded with all 1s
Digital Feedthrough 1

Total Harmonic Distortion

−81

Output Noise Spectral Density 25

dB V

nV−s

nV/√Hz @ 1 kHz

SFDR Performance (Wideband) AD5447, 65 k codes, V
Clock = 10 MHz
500 kHz f
100 kHz f
50 kHz f

OUT

OUT

OUT

55 dB
63 dB

65 dB
Clock = 25 MHz
500 kHz f
100 kHz f
50 kHz f

OUT

OUT

OUT

50 dB

60 dB

62 dB
SFDR Performance (Narrow Band) AD5447, 65 k codes, V
Clock = 10 MHz
500 kHz f
100 kHz f
50k Hz f

OUT

OUT

OUT

73 dB

80 dB

87 dB
Clock = 25 MHz
500 kHz f
100 kHz f
50 kHz f

OUT

OUT

OUT

70 dB

75 dB

80 dB
Intermodulation Distortion AD5447, 65 k codes, V
Clock = 10 MHz
f1 = 400 kHz, f2 = 500 kHz 65 dB
f1 = 40 kHz, f2 = 50 kHz 72 dB
Clock = 25 MHz
f1 = 400 kHz, f2 = 500 kHz 51 dB
f1 = 40 kHz, f2 = 50 kHz 65 dB
POWER REQUIREMENTS
Power Supply Range 2.5 5.5 V
IDD 0.6 µA TA = 25°C. Logic inputs = 0 V or V

0.5 10 µA Logic inputs = 0 V or V
Power Supply Sensitivity1 0.001 %/% ∆VDD = ±5%

Rise and fall time, V

= 10 V, R

REF

LOAD

= 100 Ω

1 LSB change around major carry, V

Feedthrough to DAC output with

CS high and

alternate loading of all 0s and all 1s

= 3.5 V p-p, all 1s loaded, f = 1 kHz

REF

= 3.5 V

REF

= 3.5 V

REF

= 3.5 V

REF

DD

DD

REF

= 0 V

1

Guaranteed by design, not subject to production test.

Rev. 0 | Page 4 of 28

AD5428/AD5440/AD5447

B

TIMING CHARACTERISTICS

Temperature range for Y version is –40°C to +125°C. Guaranteed by design and characterization, not subject to production test.

All input signals are specified with tr = tf = 1 ns (10% to 90% of V
timing measured with load circuit in Figure 3. V

= 2.5 V to 5.5 V, V

DD

) and timed from a voltage level of (VIL + VIH)/2. Digital output

DD

= 10 V, I

REF

2 = 0 V. All specifications T

OUT

otherwise noted.

Table 2.

Parameter Limit at T

MIN

, T

Unit Conditions/Comments

MAX

Write Mode

R/

t1 0 ns min
t2 0 ns min
t3 10 ns min

W to CS setup time

R/

W to CS hold time

CS low time
t4 10 ns min Address setup time
t

5

0 ns min Address hold time
t6 6 ns min Data setup time
t7 0 ns min Data hold time

R/

t8 5 ns min
t

9

7 ns min

W high to CS low

CS min high time

Data Readback Mode

t10 0 ns typ Address setup time
t11 0 ns typ Address hold time
t12 5 ns typ Data access time
25 ns max
t13 5 ns typ Bus relinquish time

10 ns max

MIN

to T

MAX

, unless

DACA/DAC

DATA

R/W

CS

t

1

t

3

t

t

8

DATA VALID DATA VALID

t

2

t

4

5

t

8

t

9

t

10

t

7

Figure 2. Timing Diagram

TO OUTPUT

PIN

200µAI

C

L

50pF

200µAI

OL

V

OH (MIN)

OH

Figure 3. Load Circuit for Data Output Timing Specifications

t

+ V

2

12

OL (MAX)

t

11

04462-0-003

t

2

t

13

04462-0-002

Rev. 0 | Page 5 of 28

AD5428/AD5440/AD5447

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

VDD to GND –0.3 V to +7 V
V

A, V

REF

I

OUT

Logic Inputs and Output
Operating Temperature Range

Automotive (Y Version)
Storage Temperature Range –65°C to +150°C
Junction Temperature 150°C
20-lead TSSOP θJA Thermal Impedance 143°C/W
24-lead TSSOP θJA Thermal Impedance 128°C/W
Lead Temperature, Soldering

(10 seconds)
IR Reflow, Peak Temperature

(< 20 seconds)

1

Overvoltages at DBx, CS, and W/R are clamped by internal diodes. Current

should be limited to the maximum ratings given.

B, RFBA, RFBB to DGND –12 V to +12 V

REF

1, I

2 to DGND –0.3 V to +7 V

OUT

1

–0.3 V to VDD + 0.3 V
–40°C to +125°C

300°C

235°C

Stresses above those listed in Absolute Maximum Ratings may
cause permanent damage to the device. This is a stress rating
only; functional operation of the device at these or any other
conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability. Only one absolute maximum rating may be applied
at any one time.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. 0 | Page 6 of 28

AD5428/AD5440/AD5447

B

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

AGND

I

OUT

R

V

REF

DGND

DAC A/

FB

DB7
DB6
DB5
DB4

A
A
A

10

1

2

3

AD5428

4

TOP VIEW

(Not to Scale)

5

6

7

8

9

20

19

18

17

16

15

14

13

12

11

B

I

OUT

R

B

FB

V

B

REF

V

DD

R/W
CS
DB0 (LSB)
DB1
DB2
DB3

04462-0-004

Figure 4. Pin Configuration 20-Lead TSSOP (RU-20)

Table 4. AD5428 Pin Function Descriptions

Pin No. Mnemonic Function

1 AGND

DAC Ground Pin. Typically, this pin should be tied to the analog ground of the system, but may be biased to
achieve single-supply operation.

2, 20 I

OUT

A, I

B DAC Current Outputs.

OUT

3, 19 RFBA, RFBB DAC Feedback Resistor Pins. Establish voltage output for the DAC by connecting to external amplifier output.
4, 18 V

REF

A, V

B DAC Reference Voltage Input Terminals.

REF

5 DGND Digital Ground Pin.
6 DAC A/B Selects DAC A or B. Low selects DAC A, or, alternatively, high selects DAC B.
7 to14 DB7 to DB0 Parallel Data Bits 7 through 0.
15

CS Chip Select Input. Active low. Used in conjunction with R/W to load parallel data to the input latch or to read

data from the DAC register.

16

W Read/Write. When low, used in conjunction with CS to load parallel data. When high, used in conjunction

R/

CS to read back contents of the DAC register.

with

17 VDD Positive Power Supply Input. This part can be operated from a supply of 2.5 V to 5.5 V.

Rev. 0 | Page 7 of 28

AD5428/AD5440/AD5447

AGND

I

OUT

R

FB

V

REF

DGND

DAC A/B

DB9
DB8
DB7
DB6
DB5
DB4

1

2

A

3

A

4

A

AD5440

TOP VIEW

5

(Not to Scale)

6

7

8

9

10

11

12

NC = NO CONNECT

24

23

22

21
20

19

18

17

16

15

14

13

B

I

OUT

B

R

FB

V

B

REF

V

DD

R/W
CS
NC
NC
DB0 (LSB)
DB1
DB2
DB3

04462-0-005

Figure 5. Pin Configuration 24-Lead TSSOP (RU-24)

Table 5. AD5440 Pin Function Descriptions

Pin No. Mnemonic Function

1 AGND

2, 24 I

OUT

A, I

OUT

DAC Ground pin. Typically, this pin should be tied to the analog ground of the system, but may be biased to
achieve single-supply operation.

B DAC Current Outputs.
3, 23 RFBA, RFBB DAC Feedback Resistor Pins. Establish voltage output for the DAC by connecting to external amplifier output.
4, 22 V

REF

A, V

B DAC Reference Voltage Input Terminals.

REF

5 DGND Digital Ground pPin.
6 DAC A/B Selects DAC A or B. Low selects DAC A, or, alternatively, high selects DAC B.
7 to16 DB9 to DB0 Parallel Data Bits 9 through 0.

19

20

CS

R/

W

Chip Select Input. Active low. Used in conjunction with R/W to load parallel data to the input latch or to read
data from the DAC register.

Read/Write. When low, used in conjunction with

CS to load parallel data. When high, used in conjunction with

CS to read back contents of the DAC register.

21 VDD Positive Power Supply Input. This part can be operated from a supply of 2.5 V to 5.5 V.

Rev. 0 | Page 8 of 28

AD5428/AD5440/AD5447

AGND

I

OUT

R

FB

V

REF

DGND

DAC A/B

DB11
DB10

DB9
DB8
DB7
DB6

A
A
A

10

11
12

1

2

3

4

AD5447

5

TOP VIEW

(Not to Scale)

6

7

8

9

24

I

23

22

21
20

19

18

17

16

15

14

13

B

OUT

B

R

FB

B

V

REF

V

DD

R/W
CS
DB0 (LSB)
DB1
DB2
DB3
DB4
DB5

04462-0-006

Figure 6. Pin Configuration 24-Lead TSSOP (RU-24)

Table 6. AD5447 Pin Function Descriptions

Pin No. Mnemonic Function

1 AGND

DAC Ground pin. Typically, this pin should be tied to the analog ground of the system, but may be biased to
achieve single-supply operation.

2, 24 I

OUT

A, I

B DAC Current Outputs.

OUT

3, 23 RFBA, RFBB DAC Feedback Resistor Pins. Establish voltage output for the DAC by connecting to external amplifier output.
4, 22 V

REF

A, V

B DAC Reference Voltage Input Terminals.

REF

5 DGND Digital Ground Pin.
6 DAC A/B Selects DAC A or B. Low selects DAC A, or, alternatively, high selects DAC B.
7 to 18 DB11 to DB0 Parallel Data Bits 11 through 0.
19

CS Chip Select Input. Active low. Used in conjunction with R/W to load parallel data to the input latch or to read

data from the DAC register. When

CS and R/W are held low, the latches are transparent; any changes on the

data lines will be reflected on the relevant DAC output.

20

W Read/Write. When low, used in conjunction with CS to load parallel data. When high, used in conjunction with

R/

CS to read back contents of DAC register. When CS and R/W are held low, the latches are transparent; any
changes on the data lines are reflected on the relevant DAC output.

21 VDD Positive Power Supply Input. This part can be operated from a supply of 2.5 V to 5.5 V.

Rev. 0 | Page 9 of 28

AD5428/AD5440/AD5447

(

TERMINOLOGY

Relative Accuracy

Relative accuracy or endpoint nonlinearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
adjusting for zero and full scale and is typically expressed in
LSBs or as a percentage of full-scale reading.

Differential Nonlinearity

Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of −1 LSB max over
the operating temperature range ensures monotonicity.

Gain Error

Gain error or full-scale error is a measure of the output error
between an ideal DAC and the actual device output. For these
DACs, ideal maximum output is V
DACs is adjustable to zero with external resistance.

Output Leakage Current

Output leakage current flows in the DAC ladder switches when
these are turned off. For the I
by loading all 0s to the DAC and measuring the I
Minimum current flows in the I
loaded with all 1s.

Output Capacitance

Capacitance from I

OUT

1 or I

OUT

Output Current Settling Time

This is the amount of time it takes for the output to settle to a
specified level for a full-scale input change. For these devices, it
is specified with a 100 Ω resistor to ground.

Digital-to-Analog Glitch lmpulse

The amount of charge injected from the digital inputs to the
analog output when the inputs change state. This is normally
specified as the area of the glitch in either pA-secs or nV-secs
depending upon whether the glitch is measured as a current or
voltage signal.

– 1 LSB. Gain error of the

REF

1 terminal, it can be measured

OUT

1 current.

OUT

2 line when the DAC is

OUT

2 to AGND.

Digital Feedthrough

When the device is not selected, high frequency logic activity on
the device digital inputs is capacitively coupled through the
device to show up as noise on the I

pins and subsequently

OUT

into the following circuitry. This noise is digital feedthrough.

Multiplying Feedthrough Error

This is the error due to capacitive feedthrough from the DAC
reference input to the DAC I

1 terminal, when all 0s are

OUT

loaded to the DAC.

Total Harmonic Distortion (THD)

The DAC is driven by an ac reference. The ratio of the rms sum
of the harmonics of the DAC output to the fundamental value is
the THD. Usually only the lower-order harmonics are included,
such as second to fifth.

2

2

2

THD

2

3

2

log20

=

V

1

)

VVVV

+++

5

4

Digital Intermodulation Distortion

Second-order intermodulation distortion (IMD) measurements
are the relative magnitude of the fa and fb tones generated
digitally by the DAC and the second-order products at 2fa − ffb
and 2fb − fa.

Spurious-Free Dynamic Range (SFDR)

SFDR is the usable dynamic range of a DAC before spurious
noise interferes or distorts the fundamental signal. SFDR is the
measure of difference in amplitude between the fundamental
and the largest harmonically- or nonharmonically-related spur
from dc to full Nyquist bandwidth (half the DAC sampling rate,
or fs/2). Narrow-band SFDR is a measure of SFDR over an
arbitrary window size, in this case 50%, of the fundamental.
Digital SFDR is a measure of the usable dynamic range of the
DAC when the signal is digitally generated sine wave.

Rev. 0 | Page 10 of 28

AD5428/AD5440/AD5447

TYPICAL PERFORMANCE CHARACTERISTICS

0.20

0.15

0.10

TA = 25°C

= 10V

V

REF

V

= 5V

DD

0.20

0.15

0.10

TA = 25°C
V

= 10V

REF

V

= 5V

DD

0.05

0

INL (LSB)

–0.05

–0.10

–0.15

–0.20

0 50 100 150 200 250

CODE

Figure 7. INL vs. Code (8-Bit DAC)

0.5
TA = 25°C

0.4

V

= 10V

REF

V

= 5V

DD

0.3

0.2

0.1

0

INL (LSB)

–0.1

–0.2

–0.3

–0.4

–0.5

0 200 400 600 800 1000

CODE

Figure 8. INL vs. Code (10-Bit DAC)

04462-0-007

04462-0-008

0.05

0

DNL (LSB)

–0.05

–0.10

–0.15

–0.20

0 50 100 150 200 250

CODE

Figure 10. DNL vs. Code (8-Bit DAC)

0.5
TA = 25°C

0.4

V

= 10V

REF

V

= 5V

DD

0.3

0.2

0.1

0

DNL (LSB)

–0.1

–0.2

–0.3

–0.4

–0.5

0 200 400 600 800 1000

CODE

Figure 11. DNL vs. Code (10-Bit DAC)

04462-0-010

04462-0-011

INL (LSB)

1.0

0.8

0.6

0.4

0.2

–0.2

–0.4

–0.6

–0.8

–1.0

1.0

TA = 25°C
V

= 10V

REF

= 5V

V

DD

0

DNL (LSB)

20001500500 10000 2500 3000 3500 4000

CODE

04462-0-009

Figure 9. INL vs. Code (12-Bit DAC)

0.8

0.6

0.4

0.2

–0.2

–0.4

–0.6

–0.8

–1.0

TA = 25°C
V

= 10V

REF

= 5V

V

DD

0

20001500500 10000 2500 3000 3500 4000

CODE

04462-0-012

Figure 12. DNL vs. Code (12-Bit DAC)

Rev. 0 | Page 11 of 28

AD5428/AD5440/AD5447

0.6

0.5

INL (LSB)

0.4

0.3

0.2

0.1

0

–0.1

–0.2

–0.3

Figure 13. INL vs. Reference Voltage

MAX INL

MIN INL

65342 78910

REFERENCE VOLTAGE

TA = 25°C
V

= 10V

REF

VDD = 5V

04462-0-013

8

7

6

5

4

3

CURRENT (mA)

2

1

0

TA = 25°C

VDD = 5V

VDD = 3V

VDD = 2.5V

1.00.50
INPUT VOLTAGE (V)

4.54.03.53.02.52.01.5

Figure 16. Supply Current vs. Logic Input Voltage

5.0

04462-0-022

–0.40

TA = 25°C
V

= 10V

REF

V

= 5V

DD

–0.45

–0.50

–0.55

DNL (LSB)

–0.60

–0.65

–0.70

MIN DNL

65342789

REFERENCE VOLTAGE

Figure 14. DNL vs. Reference Voltage

5

4

3

2

1

0

–1

ERROR (mV)

–2

–3

–4

–5

–60 –40 –20 0 20 40 60 80 100 120 140

V

REF

VDD = 5V

V

DD

= 10V

= 2.5V

TEMPERATURE (°C)

Figure 15. Gain Error vs. Temperature

1.6

1.4

1.2

1.0

0.8

0.6

LEAKAGE (nA)

0.4

OUT

I

0.2

10

04462-0-014

04462-0-015

0

0.50

0.45

0.40

0.35

0.30

0.25

0.20

CURRENT (µA)

0.15

0.10

0.05

0

–60 –40 –20 0 20 40 60 80 100 120 140

I

OUT

I

OUT

4020–20 0–40 60 80 100 120

TEMPERATURE (°C)

Figure 17. I

1 Leakage Current vs. Temperature

OUT

VDD = 5V

ALL 0s

ALL 1s

VDD = 2.5V

ALL 0sALL 1s

TEMPERATURE (°C)

Figure 18. Supply Current vs. Temperature

1 VDD 5V

1 VDD 3V

TA = 25°C

04462-0-023

04462-0-024

Rev. 0 | Page 12 of 28

AD5428/AD5440/AD5447

14

TA = 25°C
LOADING ZS TO FS

12

10

V

= 5V

DD

3

0

TA = 25°C

= 5V

V

DD

8

(mA)

DD

I

6

4

2

0

10k1k10 1001 100k 1M 10M 100M

FREQUENCY (Hz)

V

= 3V

DD

= 2.5V

V

DD

Figure 19. Supply Current vs. Update Rate

6

TA = 25°C

0

LOADING

–6

ZS TO FS

–12

–18

–24

–30

–36

–42

–48

GAIN (dB)

–54

–60

–66

–72
–78
–84
–90
–96

–102

1 100 1k 10k 100k 1M 10M 100M

ALL ON
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0

ALL OFF

10

FREQUENCY (Hz)

AD8038 AMPLIFIER

C

V

REF

COMP

TA = 25°C

= 5V

V

DD

= ±3.5V

INPUT

=1.8pF

Figure 20. Reference Multiplying Bandwidth vs. Frequency and Code

04462-0-025

04462-0-026

–3

GAIN (dB)

V

= ±2V, AD8038 CC 1.47pF

REF

–6

–9

10k 100k 1M 10M 100M

= ±2V, AD8038 CC 1pF

V

REF

= ±0.15V, AD8038 CC 1pF

V

REF

V

= ±0.15V, AD8038 CC 1.47pF

REF

= ±3.51V, AD8038 CC 1.8pF

V

REF

FREQUENCY (Hz)

04462-0-028

Figure 22. Reference Multiplying Bandwidth vs. Frequency and

Compensation Capacitor

0.045
7FF TO 800H

0.040

0.035

0.030

0.025

0.020

0.015

0.010

OUTPUT VOLTAGE (V)

0.005

0
–0.005
–0.010

0 20 40 60 80 100 120 140 160 180 200

VDD = 5V

VDD = 3V

VDD = 5V

TIME (ns)

Figure 23. Midscale Transition, V

TA = 25°C
V

REF

AD8038 AMPLIFIER
C

COMP

800 TO 7FFH

VDD = 3V

REF

= 0V

= 1.8pF

= 0 V

04462-0-041

0.2

0

–0.2

GAIN (dB)

–0.4

TA = 25°C

–0.6

–0.8

= 5V

V

DD

= ±3.5V

V

REF

= 1.8pF

C

COMP

AD8038 AMPLIFIER

10k1k10 1001 100k 1M 10M 100M

FREQUENCY (Hz)

Figure 21. Reference Multiplying Bandwidth–All Ones Loaded

OUTPUT VOLTAGE (V)

04462-0-027

Rev. 0 | Page 13 of 28

–1.68

–1.69

–1.70

–1.71

–1.72

–1.73

–1.74

–1.75

–1.76

–1.77

7FF TO 800H

VDD = 5V

VDD = 3V

VDD = 5V

800 TO 7FFH

0 20 40 60 80 100 120 140 160 180 200

TIME (ns)

Figure 24. Midscale Transition, V

TA = 25°C
V

REF

AD8038 AMPLIFIER
C

COMP

VDD = 3V

REF

= 3.5V

= 1.8pF

= 3.5 V

04462-0-042

AD5428/AD5440/AD5447

20

TA = 25°C
V

= 3V

DD

AMP = AD8038

0

–20

–40

–60

PSRR (dB)

–80

–100

–120

1 100 1k 10k 100k 1M 10M

10

Figure 25. Power Supply Rejection vs. Frequency

FULL SCALE

ZERO SCALE

FREQUENCY (Hz)

04462-0-043

90

80

70

60

50

40

SFDR (dB)

30

20

10

MCLK = 5MHz

MCLK = 10MHz

MCLK = 25MHz

TA = 25°C

= 3.5V

V

REF

0

0 100 200 300 400 500 600 700 800 900 1000

f

(kHz)

OUT

Figure 28. Wideband SFDR vs. f

AD8038 AMPLIFIER

Frequency

OUT

04462-0-046

–60

TA = 25°C
V

= 3V

DD

V

= 3.5V p-p

REF

–65

–70

–75

THD + N (dB)

–80

–85

–90

100 1k1 10 10k 100k 1M

FREQUENCY (Hz)

Figure 26. THD + Noise vs. Frequency

100

MCLK = 1MHz

80

MCLK = 200kHz

60

MCLK = 0.5MHz

SFDR (dB)

40

20

0

0 20 40 60 80 100 120 140 160 180 200

f

(kHz)

OUT

Figure 27. Wideband SFDR vs. f

TA = 25°C
V

= 3.5V

REF

AD8038 AMPLIFIER

Frequency

OUT

04462-0-044

04462-0-045

0

–10

–20

–30

–40

–50

SFDR (dB)

–60

–70

–80

–90

0

2 4 6 8 10 12

Figure 29. Wideband SFDR, f

0

–10

–20

–30

–40

–50

SFDR (dB)

–60

–70

–80

–90

–100

0.5 1.5 3.0 3.5 4.01.0 2.0 2.5 4.5 5.0

0

Figure 30. Wideband SFDR, f

FREQUENCY (MHz)

= 100 kHz, Clock = 25 MHz

OUT

FREQUENCY (MHz)

= 500 kHz, Clock = 10 MHz

OUT

TA = 25°C
V

= 5V

DD

AMP = AD8038
65k CODES

TA = 25°C



V

= 5V

DD

AMP = AD8038
65k CODES

04462-0-047

044620-048

Rev. 0 | Page 14 of 28

AD5428/AD5440/AD5447

0

–10

–20

–30

–40

–50

SFDR (dB)

–60

–70

–80

–90

0

0.5 1.5 3.0 3.5 4.01.0 2.0 2.5 4.5 5.0

Figure 31. Wideband SFDR, f

FREQUENCY (MHz)

= 50 kHz, Clock = 10 MHz

OUT

TA = 25°C

= 5V

V

DD

AMP = AD8038
65k CODES

04462-0-049

0

–10

–20

–30

–40

–50

(dB)

–60

–70

–80

–90

–100

70 12075 80 85 115

Figure 34. Narrow-Band IMD, f

95

90 100 105 110

FREQUENCY (MHz)

= 90 kHz, 100 kHz, Clock = 10 MHz

OUT

TA = 25°C



VDD = 3V
AMP = AD8038
65k CODES

04462-0-052

0

–10

–20

–30

–40

–50

–60

SFDR (dB)

–70

–80

–90

–100

250 750300 350 400 650 700

Figure 32. Narrow-Band Spectral Response, f

20

0

–20

–40

–60

SFDR (dB)

–80

–100

450 500 550 600

FREQUENCY (MHz)

OUT

TA = 25°C



V

= 3V

DD

AMP = AD8038
65k CODES

04462-0-050

= 500 kHz, Clock = 25 MHz

TA = 25°C



V

= 3V

DD

AMP = AD8038
65k CODES

0

–10

–20

–30

–40

–50

(dB)

–60

–70

–80

–90

–100

0 400

50 300 350100 150 200 250

Figure 35. Wideband IMD, f

300

ZERO SCALE LOADED TO DAC

250

200

150

100

OUTPUT NOISE (nV/ Hz)

50

MIDSCALE LOADED TO DAC

FREQUENCY (kHz)

= 90 kHz, 100 kHz, Clock = 25 MHz

OUT

FULL SCALE LOADED TO DAC

TA = 25°C



V

DD

AMP = AD8038
65k CODES

TA = 25°C
AMP = AD8038

= 5V

04462-0-053

–120

50 150

60 70 80 130 140

Figure 33. Narrow-Band SFDR, f

90 100 110 120

FREQUENCY (MHz)

= 100 kHz, Clock = 25 MHz

OUT

04462-0-051

Rev. 0 | Page 15 of 28

0

100 1k 10k 100k

FREQUENCY (Hz)

Figure 36. Output Noise Spectral Density

04462-0-054

AD5428/AD5440/AD5447

GENERAL DESCRIPTION CIRCUIT OPERATION

The AD5428, AD5440 and AD5447 are dual 8-, 10- and 12-bit
current output DACs consisting of a standard inverting R-2R
ladder configuration. A simplified diagram for the 8-bit
AD5428 is shown in Figure 37. The feedback resistor R

has a

FB

value of R. The value of R is typically 10 kΩ (minimum 8 kΩ
and maximum 12 kΩ). If I

OUT

1 and I

2 are kept at the same

OUT

potential, a constant current flows in each ladder leg, regardless
of digital input code. Therefore, the input resistance presented

is always constant and nominally of value R. The DAC

at V

REF

output (I

) is code dependent, producing various resistances

OUT

and capacitances. External amplifier choice should take into
account the variation in impedance generated by the DAC on
the amplifier’s inverting input node.

V

REF

Access is provided to the V

RR R

2R 2R 2R 2R 2R
S1 S2 S3 S8

DAC DATA LATCHES

AND DRIVERS

Figure 37. Simplified Ladder

, RFB, and I

REF

OUT

R

R

A

FB

1

I

OUT

2

I

OUT

04462-0-029

terminals of DAC A
and DAC B, making the device extremely versatile and allowing
it to be configured in several different operating modes, for
example, to provide a unipolar output, 4-quadrant multiplica­tion in bipolar mode or in single-supply modes of operation.
Note that a matching switch is used in series with the internal

feedback resistor. If users attempt to measure RFB, power

R

FB

must be applied to V

to achieve continuity.

DD

Unipolar Mode

Using a single op amp, these devices can easily be configured to
provide 2-quadrant multiplying operation or a unipolar output
voltage swing, as shown in Figure 38. When an output amplifier
is connected in unipolar mode, the output voltage is given by

OUT

REF

n

DVV 2/×−=

where D is the fractional representation of the digital word
loaded to the DAC and n is the resolution of the DAC.

D = 0 to 255 (8-bit AD5428)
= 0 to 1023 (10-bit AD5440)
= 0 to 4095 (12-bit AD5447)

Note that the output voltage polarity is opposite to the V
polarity for dc reference voltages. These DACs are designed to
operate with either negative or positive reference voltages. The
VDD power pin is only used by the internal digital logic to
drive the on and off states of the DAC switches.

These DACs are also designed to accommodate ac reference
input signals in the range of –10 V to +10 V.

With a fixed 10 V reference, the circuit in Figure 8 gives a
unipolar 0 V to –10 V output voltage swing. When V
signal, the circuit performs 2-quadrant multiplication.

The following table shows the relationship between digital
code and the expected output voltage for unipolar operation
(AD5428, 8-bit device).

Table 7. Unipolar Code Table

Digital Input Analog Output (V)

1111 1111 –V
1000 0000 –V
0000 0001 –V
0000 0000 –V

(255/256)

REF

(128/256) = –V

REF

(1/256)

REF

(0/256) = 0

REF

REF

/2

REF

is an ac

IN

Rev. 0 | Page 16 of 28

AD5428/AD5440/AD5447

(

)

AD5428/AD5440/AD5447

V

DD

DB0

DATA

INPUTS

DB7
DB9

DB11

DAC A/B

CS

R/W

DGND

NOTES:

1

R1, R2 AND R3, R4 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.

2

C1, C2 PHASE COMPENSATION (1pF–2pF) IS REQUIRED WHEN USING
HIGH SPEED AMPLIFIERS TO PREVENT RINGING OR OSCILLATION.

INPUT

BUFFER

CONTROL

LOGIC

POWER-ON

RESET

LATCH

LATCH

(±10V)

V

A

REF

8-/10-/12-BIT
R-2R DAC A

8-/10-/12-BIT

V

B

REF

(±10V)

A

V

IN

1

R1

R-2R DAC B

1

R3

VINB

A

R

FB

R

A

I

OUT

AGND

R

B

FB

R

I

B

OUT

1

R2

2

C1

A

V

OUT

AGND

1

R4

2

C2

V

B

OUT

AGND

04462-0-030

Figure 38. Unipolar Operation

Bipolar Operation

In some applications, it may be necessary to generate full
4-quadrant multiplying operation or a bipolar output swing.
This can be easily accomplished by using another external
amplifier and some external resistors, as shown in Figure 39.
In this circuit, the second amplifier, A2, provides a gain of 2.
Biasing the external amplifier with an offset from the reference
voltage results in full 4-quadrant multiplying operation. The
transfer function of this circuit shows that both negative and
positive output voltages are created as the input data (D) is
incremented from code zero (V

= 0 V) to full scale (V

(V

OUT

OUT

= −V

OUT

= +V

) to midscale

REF

). When connected in

REF

bipolar mode, the output voltage is given by

OUT

REF

2/

REF

n

−1

VDVV −×=

where D is the fractional representation of the digital word
loaded to the DAC, and n is the number of bits.

D = 0 to 255 (AD5428)
= 0 to 1023 (AD5440)
= 0 to 4095 (AD5447)

When V

is an ac signal, the circuit performs 4-quadrant

IN

multiplication. Table 8 shows the relationship between digital
code and the expected output voltage for bipolar operation
(AD5428, 8-bit device).

Table 8. Bipolar Code Table

Digital Input Analog Output (V)

1111 1111 +V

(127/128)

REF

1000 0000 0
0000 0001 –V
0000 0000 –V

(127/128)

REF

(128/128)

REF

Stability

In the I-to-V configuration, the IOUT of the DAC and the
inverting node of the op amp must be connected as close as
possible and proper PCB layout techniques must be employed.
Because every code change corresponds to a step function, gain
peaking may occur if the op amp has limited GBP and there is
excessive parasitic capacitance at the inverting node. This
parasitic capacitance introduces a pole into the open loop
response which can cause ringing or instability in the closed
loop applications circuit.

An optional compensation capacitor, C1, can be added in
parallel with R

for stability, as shown in Figure 38 and in

FB

Figure 39. Too small a value of C1 can produce ringing at the
output, while too large a value can adversely affect the settling
time. C1 should be found empirically, but 1 pF to2 pF is
generally adequate for the compensation.

Rev. 0 | Page 17 of 28

AD5428/AD5440/AD5447

2

3

V

IN

(±10V)

A

1

R1

V

A

AD5428/AD5440/AD5447

V

DD

DATA

INPUTS

NOTES:

1

DB0

DB7
DB9

DB11

DAC A/B

CS

R/W

DGND

R1, R2 AND R3, R4 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED. ADJUST R1 FOR V
ADJUST R3 FOR V
MATCHING AND TRACKING IS ESSENTIAL FOR RESISTOR PAIRS R6, R7 AND R9, R10.
C1, C2 PHASE COMPENSATION (1pF–2pF) MAY BE REQUIRED IF A1/A3 IS A HIGH SPEED AMPLIFIER.

INPUT

BUFFER

CONTROL

LOGIC

POWER-ON

RESET

B = 0V WITH CODE 10000000 IN DAC B LATCH.

OUT

LATCH

LATCH

REF

V

REF

8-/10-/12-BIT
R-2R DAC A

8-/10-/12-BIT
R-2R DAC B

B

R3

VINB

(±10V)

RR2

R

1

A = 0V WITH CODE 10000000 IN DAC A LATCH.

OUT

Figure 39. Bipolar Operation (4-Quadrant Multiplication)

R

FB

I

OUT

AGND

R

FB

I

OUT

R5

AGND

AGND

R11
5kΩ

R12
5kΩ

20kΩ

A2

R8

20kΩ

A4

V

A

OUT

V

B

OUT

04462-0-031

2

R6

20kΩ

2

R7

AGND

AGND

10kΩ

2

C1

A1

2

C2

A3

2

R9

10kΩ

2

R10

20kΩ

1

A

A

B

1

R4

B

SINGLE-SUPPLY APPLICATIONS

Voltage-Switching Mode

Figure 40 shows these DACs operating in voltage-switching
mode. The reference voltage, V

2 is connected to AGND, and the output voltage is available

I

OUT

at the V

terminal. In this configuration, a positive reference

REF

voltage results in a positive output voltage, making single­supply operation possible. The output from the DAC is voltage
at constant impedance (the DAC ladder resistance), thus an
op amp is necessary to buffer the output voltage. The reference
input no longer sees constant input impedance, but one that
varies with code. So, the voltage input should be driven from a
low impedance source.

Note that V

is limited to low voltages because the switches in

IN

the DAC ladder no longer have the same source-drain drive
voltage. As a result, their on resistance differs and this degrades
the integral linearity of the DAC. Also, V
by more than 0.3 V or an internal diode turns on, exceeding the
maximum ratings of the device. In this type of application, the
full range of multiplying capability of the DAC is lost.

, is applied to the I

IN

must not go negative

IN

OUT

1 pin,

Rev. 0 | Page 18 of 28

V

DD

V

R

DD

V

IN

NOTES:

1
2

FB

I

1

OUT

I

2

OUT

ADDITIONAL PINS OMITTED FOR CLARITY.
C1 PHASE COMPENSATION (1pF–2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.

V

GND

R

REF

R

1

2

V

OUT

04462-0-033

Figure 40. Single-Supply Voltage-Switching Mode

AD5428/AD5440/AD5447

A

Y

(

)

×

=

POSITIVE OUTPUT VOLTAGE

Note the output voltage polarity is opposite to the V
for dc reference voltages. For a positive voltage output, an
applied negative reference to the input of the DAC is preferred
over the output inversion through an inverting amplifier
because of the resistor’s tolerance errors. To generate a negative
reference, the reference can be level shifted by an op amp such
that the V

and GND pins of the reference become the virtual

OUT

ground and –2.5 V respectively, as shown in Figure 41.

V

= +5V

IN

V

DD

V

DD

8-/10-/12-BIT

REF

DAC

GND

R

FB

I

1

OUT

2

I

OUT

ADR03

V

V

OUT

GND

+5V

–2.5V

1/2 AD8552

–5V

NOTES:

1

ADDITIONAL PINS OMITTED FOR CLARITY.

2

C1 PHASE COMPENSATION (1pF–2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.

polarity

REF

C

1

0V to 2.5V

1/2 AD8552

V

=

OUT

04462-0-034

USED AS A DIVIDER OR PROGRAMMABLE GAIN ELEMENT

Current-steering DACs are very flexible and lend themselves to
many different applications. If this type of DAC is connected as
the feedback element of an op amp and R
resistor as shown in Figure 43, then the output voltage is
inversely proportional to the digital input fraction D.

OUT

n

the output voltage is

()

VDVV 21// −−=−=

ININ

n

For D = 1-2

V

V

IN

I

OUT

I

OUT

DD

R

V

FB

DD

1

2

GND

is used as the input

FB

V

REF

Figure 41. Positive Voltage Output with Minimum Components

ADDING GAIN

In applications where the output voltage is required to be
greater than V
amplifier or it can also be achieved in a single stage. It is
important to take into consideration the effect of temperature
coefficients of the thin film resistors of the DAC. Simply placing
a resistor in series with the R
temperature coefficients, resulting in larger gain temperature
coefficient errors. Instead, the circuit of Figure 42 shows the
recommended method of increasing the gain of the circuit. R

, and R3 should all have similar temperature coefficients, but

R

2

they need not match the temperature coefficients of the DAC.
This approach is recommended in circuits where gains of >1
are required.

R

2

V

IN

NOTES:

1

ADDITIONAL PINS OMITTED FOR CLARITY.

2

C1 PHASE COMPENSATION (1pF–2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.

, gain can be added with another external

IN

resistor causes mismatches in the

FB

V

DD

C

1

1
2

R

3

R

2

8-/10-/12-BIT

V

REF

V

DD

DAC

GND

R

FB

I

OUT

I

OUT

Figure 42. Increasing Gain of Current Output DAC

GAIN =

R1=

R

V

OUT

R

R

2R3

2 +R3

2

+ R
R

,

1

3

2

04462-0-035

V

OUT

NOTE:

DDITIONAL PINS OMITTED FOR CLARIT

04462-0-040

Figure 43. Current-Steering DAC Used as a Divider or

Programmable Gain Element

As D is reduced, the output voltage increases. For small values
of the digital fraction D, it is important to ensure that the
amplifier does not saturate and also that the required accuracy
is met. For example, an 8-bit DAC driven with the binary code
0 × 10 (00010000)—that is, 16 decimal—in the circuit of
Figure 43 should cause the output voltage to be 16 ×V

.

IN

However, if the DAC has a linearity specification of ± 0.5 LSB,
then D can, in fact, have the weight anywhere in the range

15.5/256 to 16.5/256 so that the possible output voltage is in the
range 15.5 V

to 16.5 VIN—an error of 3% even though the

IN

DAC itself has a maximum error of 0.2%.

DAC leakage current is also a potential error source in divider
circuits. The leakage current must be counterbalanced by an
opposite current supplied from the op amp through the DAC.
Because only a fraction, D, of the current into the V
is routed to the I

1 terminal, the output voltage must change

OUT

terminal

REF

to:

DRLeakage /

Output Error Voltage Due to DAC Leakage

where R is the DAC resistance at the VREF terminal. For a DAC
leakage current of 10 nA, R = 10 k

Ω and a gain (i.e, a/D) of 16,

the error voltage is 1.6 mV.

Rev. 0 | Page 19 of 28

AD5428/AD5440/AD5447

REFERENCE SELECTION

When selecting a reference for use with the AD54XX series of
current output DACs, pay attention to the reference’s output
voltage temperature coefficient specification. This parameter
not only affects the full-scale error, but can also affect the
linearity (INL and DNL) performance. The reference
temperature coefficient should be consistent with the system
accuracy specifications. For example, an 8-bit system required
to hold its overall specification to within 1 LSB over the
temperature range 0° to 50°C dictates that the maximum system
drift with temperature should be less than 78 ppm/°C. A 12-bit
system with the same temperature range to overall specification
within 2 LSBs requires a maximum drift of 10 ppm/°C. By
choosing a precision reference with low output temperature
coefficient this error source can be minimized. Table 9 lists
some of the references available from Analog Devices, Inc. that
are suitable for use with this range of current output DACs.

AMPLIFIER SELECTION

The primary requirement for the current-steering mode is an
amplifier with low input bias currents and low input offset
voltage. The input offset voltage of an op amp is multiplied by
the variable gain (due to the code-dependent output resistance
of the DAC) of the circuit. A change in the noise gain between
two adjacent digital fractions produces a step change in the
output voltage due to the amplifier’s input offset voltage. This
output voltage change is superimposed on the change in output
between the two codes and gives rise to a differential linearity
error, which if too large might cause the DAC to be nonmono­tonic. The input offset voltage should be <1/4 LSB to ensure
monotonic behavior when stepping through codes.

The input bias current of an op amp also generates an offset at
the voltage output as a result of the bias current flowing in the
feedback resistor, R
low enough to prevent significant errors in 12-bit applications.

In voltage-switching circuits, common-mode rejection of the op
amp is important because it produces a code-dependent error at
the voltage output of the circuit. Most op amps have adequate
common-mode rejection for use at 8-, 10-, and 12-bit resolution.

. Most op amps have input bias currents

FB

PARALLEL INTERFACE

Data is loaded to the AD5428/ AD5440/ AD5447 in the format
of an 8-, 10-, or 12-bit parallel word. Control lines CS and R/W

allow data to be written to or read from the DAC register. A
write event takes place when

and R/W are brought low, data

CS

available on the data lines fills the shift register, and the rising
edge of CS latches the data and transfers the latched data word
to the DAC register. The DAC latches are not transparent, thus a
write sequence must consist of a falling and rising edge on

CS

to

ensure data is loaded to the DAC register and its analog
equivalent reflected on the DAC output.

A read event takes place when R/

is held high and CS is

W

brought low. Data is loaded from the DAC register back to the
input register and out onto the data line where it can be read
back to the controller for verification or diagnostic purposes.
The input and DAC registers of these devices are not
transparent, so a falling and rising edge of

is required to load

CS

each data-word.

MICROPROCESSOR INTERFACING

The AD5428/AD5440/AD5447 can be interfaced to a variety of
16-bit microcontrollers or DSP processors. Figure 44 shows the
AD54xx DAC interfaced to a generic 16-bit microcontroller/
DSP processor. Microprocessor interfacing to this family of
DACs is via a data bus that uses standard protocol compatible
with microcontrollers and DSP processors. The address decoder
is used to select DAC A or DAC B and also to load parallel data
to the input latch or to read data from the DAC using an AND
gate.

A0 TO AX

MICRO/DSP*

WR

ADDRESS
DECODER

ADDRESS BUS

A

A + 1

AD54XX*

DAC A/B

CS

WR

DB0 TO DB11

Provided the DAC switches are driven from true wideband, low
impedance sources (V

and AGND), they settle quickly. Thus,

IN

the slew rate and settling time of a voltage-switching DAC
circuit is determined largely by the output op amp. To obtain
minimum settling time in this configuration, it is important to
minimize capacitance at the V

node (voltage output node in

REF

this application) of the DAC. This is done by using low input
capacitance buffer amplifiers and careful board design.

Most single-supply circuits include ground as part of the analog
signal range, which in turns requires an amplifier that can
handle rail-to-rail signals. Analog Devices, Inc. provides a large
variety of single-supply amplifiers.

Rev. 0 | Page 20 of 28

DB0 TO DB11

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 44. AD54xx to Parallel Interface

DATA BUS

04462-0-055

AD5428/AD5440/AD5447

PCB LAYOUT AND POWER SUPPLY DECOUPLING

In any circuit where accuracy is important, careful
consideration of the power supply and ground return layout
helps to ensure the rated performance. The printed circuit
board on which the AD5428/AD5440/AD5447 is mounted
should be designed so that the analog and digital sections are
separated, and confined to certain areas of the board. If the
DAC is in a system where multiple devices require an AGND­to-DGND connection, the connection should be made at one
point only. The star ground point should be established as close
as possible to the device.

These DACs should have ample supply bypassing of 10 µF in
parallel with 0.1 µF on the supply located as close to the package
as possible, ideally right up against the device. The 0.1 µF
capacitor should have low effective series resistance (ESR) and
effective series inductance (ESI), like the common ceramic types
that provide a low impedance path to ground at high
frequencies, to handle transient currents due to internal logic
switching. Low ESR 1 µF to 10 µF tantalum or electrolytic
capacitors should also be applied at the supplies to minimize
transient disturbance and filter out low frequency ripple.

Fast switching signals such as clocks should be shielded with
digital ground to avoid radiating noise to other parts of the
board, and should never be run near the reference inputs.

Avoid crossover of digital and analog signals. Traces on opposite
sides of the board should run at right angles to each other. This
reduces the effects of feedthrough on the board. A microstrip
technique is by far the best, but not always possible with a

double-sided board. In this technique, the component side of
the board is dedicated to ground plane while signal traces are
placed on the soldered side.

It is good practice to employ compact, minimum lead length
PCB layout design. Leads to the input should be as short as
possible to minimize IR drops and stray inductance.

The PCB metal traces between V

and RFB should also be

REF

matched to minimize gain error. To maximize on high
frequency performance, the I-to-V amplifier should be located
as close to the device as possible.

EVALUATION BOARD FOR THE DACS

The evaluation board consists of a DAC and a current to voltage
amplifier AD8065. Included on the evaluation board is a 10 V
reference, ADR01. An external reference may also be applied via
an SMB input.

The evaluation kit consists of a CD-ROM with self-installing
PC software to control the DAC. The software simply allows the
user to write a code to the device.

POWER SUPPLIES FOR THE EVALUATION BOARD

The board requires ±12 V, and +5 V supplies. The +12 V VDD
and Vss are used to power the output amplifier, while the +5 V
is used to power the DAC (V

Both supplies are decoupled to their respective ground plane
with 10

µF tantalum and 0.1µF ceramic capacitors.

) and transceivers (VCC).

DD1

Table 9. Suitable ADI Precision References Recommended for Use with AD5428/AD5440/AD5447 DACs

Reference Output Voltage Initial Tolerance Temperature Drift 0.1 Hz to 10 Hz noise Package

ADR01 10 V 0.1% 3 ppm/°C 20 µV p-p SC70, TSOT, SOIC
ADR02 5 V 0.1% 3 ppm/°C 10 µV p-p SC70, TSOT, SOIC
ADR03 2.5 V 0.2% 3 ppm/°C 10 µV p-p SC70, TSOT, SOIC
ADR425 5 V 0.04% 3 ppm/°C 3.4 µV p-p MSOP, SOIC

Table 10. Precision ADI Op Amps Suitable for Use with AD5428/AD5440/AD5447 DACs

Part # Max Supply Voltage V V

OP97 ±20 25 0.1 0.9 0.2
OP1177 ±18 60 2 1.3 0.7
AD8551 +6 5 0.05 1.5 0.4

(max) µVIB(max) nA IB (max) nA GBP MHz Slew Rate V/µs

OS

Table 11. High Speed ADI Op Amps Suitable for Use with AD5428/AD5440/AD5447 DACs

Part # Max Supply Voltage V BW @ ACL MHz Slew Rate V/µs V

AD8065 ±12 145 180 1500 0.01
AD8021 ±12 200 100 1000 1000
AD8038 ±5 350 425 3000 0.75

(max) µV IB (max) nA

OS

Rev. 0 | Page 21 of 28

AD5428/AD5440/AD5447

O/P B

J6

TP4

O/P A

J1

TP1

+

C24

C23

10µF

0.1µF
4

SS

2

V

C22

1.8pF

+

C6

C5

10µF

U1

0.1µF

21

DD

V

AD5547

0
B
D

8
1

0
B
D

24

23

B

B

FB

R

I

1

4

3

5

2

B

B

B

B

B

D

D

D

D

D

7
1

1
B
D

2

3

4

5

6

1

1

1

1

1

6

5

4

3

2

B

B

B

B

B

D

D

D

D

D

1

DD

V

OUT

6
B
D

+

C26

C25

10µF

6

7

V–

V+

3

DD

U7

V

TP3 TP2

3

2

A

A

FB

OUT

R

I

B

/
A

_

0

1

7

8

9

1

1
B
D

1
1

7
B
D

C

B

B

B

B

A

D

D

D

D

D

0

6

7

9

8

1

1

8

9

0

1

1

B

B

B

B

D

D

D

D

+

C9

C10

10µF

0.1µF

22

4

B

A

REF

REF

V

V

W

S

/

C

R

0

9

2

1

S

W

C

R

0.1µF
4

SS

2

V

C7

1.8pF

J5J2

EXT

EXT

1

AGND

D
N
G

D

D

N
G
D

5

+

C11

C12

10µF

6

7

V–

V+

3

U3

REF B

B
A

LK1

REF A

0.1µF

DD

V

C8

0.1µF

4

1

OUT

V

IN

+V

3

DD

V

3
J

2

U2

GND

TRIM

5

C4

0.1µF

+

C3

10µF

1

DD

D
N
G

DD

V

4
J

A

C14

10µF

C16

10µF

+

+

CC

V

V

SS

V

C18

10µF

C20

+

10µF

+

C13

C15

0.1µF

C1

0.1µF

CC

V

3

5

4

2

2

A

C

B

C

E

V

C

U4

A

A

B

B

E

E
L

O

1

2

9

0

6

1

1

6

7

B

B

1

0

A

A

4

3

1

2

1

17

18

5

4

3

B

B

B

2

3

4

A

A

A

7

6

5

314

2

2

2

1

0

1

2

B

B

B

B

B

A

A

E

E
L

O

B

D

A

N

E

7

6

5

G

C

A

A

A

1

2

098

1

1

1

74ABT543

CC

V

4

5

7

8

0

9

6

232

1

1

1

5

7B6

A

C

B

B

B

C

E

V

C2

C

U5

0.1µF

A

A

B

B

E

2

1

0

E

A

A

A

L

O

3

4

1

2

5

2

1

3

4

2

1

2

2

1

1

4

3

B

B

3

4

A

A

7

6

1

0

1

2

B

B

B

B

B

A

A

E

E
L

O

B

D

A

74ABT543

N

E

7

6

5

G

C

A

A

A

098

211

1

1

2
1

0

U6-B

4
1

6

5

7

4

0

7
–

1
P

–

–

–

–

–

1

1

1

1

1

P

P

P

P

P

U6-A

C17

0.1µF

DGND

CC

V

2

3

4

5

6

Y3Y2Y1Y

0

1

A

A

E

1

2

3

8

9

6

–

–

3

1

1

–

P

P

1
P

4

1

1

1

–

3

1

–

–

1

1

P

P

P

0.1µF

2

3

–

–

2

2

P

P

1

0

1

1

9

Y3Y2Y1Y

0

1

E

A

A

3

5

1

1

C17

C19

0.1µF

0.1µF

4

1

–

–

2

2

P

P

D
N
G
D

P1–19

P1–20

P1–21

P1–22

P1–23

P1–24

P1–25

5

6

–

–

2

2

P

P

P1–26

P1–27

P1–28

P1–29

P1–30

04464-0-023

Figure 45. Schematic of AD5428/AD5440/AD5447 Evaluation Board

Rev. 0 | Page 22 of 28

AD5428/AD5440/AD5447

04462-0-036

Figure 46. Component-Side Artwork

04462-0-038

Figure 47. Silkscreen—Component-Side View ( Top Layer)

Rev. 0 | Page 23 of 28

AD5428/AD5440/AD5447

04462-0-039

Figure 48. Solder-Side Artwork

Rev. 0 | Page 24 of 28

AD5428/AD5440/AD5447

BILL OF MATERIALS

Table 12.

Name Part Description Value Tolerance (%) Stock Code

C1 X7R Ceramic Capacitor 0.1 uF 10 FEC 499-675
C2 X7R Ceramic Capacitor 0.1 uF 10 FEC 499-675
C3 Tantalum Capacitor—Taj Series 10 uF 20 V 10 FEC 197-427
C4 X7R Ceramic Capacitor 0.1 uF 10 FEC 499-675
C5 Tantalum Capacitor—Taj Series 10 uF 10 V 10 FEC 197-130
C6 X7R Ceramic Capacitor 0.1 uF 10 FEC 499-675
C7 NPO Ceramic Capacitor 1.8 pF 10 FEC 721-876
C8 X7R Ceramic Capacitor 0.1 uF 10 FEC 499-675
C9 Tantalum Capacitor—Taj Series 10 uF 20 V 10 FEC 197-427
C10 X7R Ceramic Capacitor 0.1 uF 10 FEC 499-675
C11 Tantalum Capacitor—Taj Series 10 uF 20 V 10 FEC 197-427
C12 X7R Ceramic Capacitor 0.1 uF 10 FEC 499-675
C13 X7R Ceramic Capacitor 0.1 uF 10 FEC 499-675
C14 Tantalum Capacitor—Taj Series 10 uF 20 V 10 FEC 197-427
C15 X7R Ceramic Capacitor 0.1 uF 10 FEC 499-675
C16 Tantalum Capacitor—Taj Series 10 uF 20 V 10 FEC 197-427
C17 X7R Ceramic Capacitor 0.1 uF 10 FEC 499-675
C18 Tantalum Capacitor—Taj Series 10 uF 20 V 10 FEC 197-427
C19 X7R Ceramic Capacitor 0.1 uF 10 FEC 499-675
C20 Tantalum Capacitor—Taj Series 10 uF 20 V 10 FEC 197-427
C21 X7R Ceramic Capacitor 0.1 uF 10 FEC 499-675
C22 NPO Ceramic Capacitor 1.8 pF 10 FEC 721-876
C23 Tantalum Capacitor—Taj Series 10 uF 20 V 10 FEC 197-427
C24 X7R Ceramic Capacitor 0.1 uF 10 FEC 499-675
C25 Tantalum Capacitor—Taj Series 10 uF 20 V 10 FEC 197-427
C26 X7R Ceramic Capacitor 0.1 uF 10 FEC 499-675
CS, DB0-11 Red Testpoint FEC 240-345 (Pack)
J1-6 SMB Socket FEC 310-682
J2 SMB Socket FEC 310-682
J3 SMB Socket FEC 310-682
J4 SMB Socket FEC 310-682
J5 SMB Socket FEC 310-682
J6 SMB Socket FEC 310-682
LK1 3-Pin Header (2x2) FEC 511-791&528-456
P1 36-Pin Centronics Connector FEC 147-753
P2 6-Pin Terminal Block FEC 151-792
RW Red Testpoint FEC 240-345 (Pack)
TP1 to 4 Red Testpoint FEC 240-345 (Pack)

AD5428YRU / AD5440YRU /

U1 AD5428/AD5440/AD5447
U2 ADR01 ADR01AR
U3 AD8065 AD8065AR
U4, U5 74ABT543 Fairchild 74ABT543CMTC
U6 74139 CD74HCT139M
U7 AD8065 AD8065AR
Each Corner Rubber Stick-On Feet FEC 148-922

AD5447YRU

Rev. 0 | Page 25 of 28

AD5428/AD5440/AD5447

OVERVIEW OF AD54xx DEVICES

Table 13.

Part No. Resolution No. DACs INL(LSB) Interface Package Features

AD5424 8 1 ±0.25 Parallel RU-16, CP-20
AD5426 8 1 ±0.25 Serial RM-10 10 MHz BW, 50 MHz Serial

AD5428 8 2 ±0.25 Parallel RU-20
AD5429 8 2 ±0.25 Serial RU-10 10 MHz BW, 50 MHz Serial
AD5450 8 1 ±0.25 Serial RJ-8 10 MHz BW, 50 MHz Serial
AD5432 10 1 ±0.5 Serial RM-10 10 MHz BW, 50 MHz Serial
AD5433 10 1 ±0.5 Parallel RU-20, CP-20
AD5439 10 2 ±0.5 Serial RU-16 10 MHz BW, 50 MHz Serial
AD5440 10 2 ±0.5 Parallel RU-24
AD5451 10 1 ±0.25 Serial RJ-8 10 MHz BW, 50 MHz Serial
AD5443 12 1 ±1 Serial RM-10 10 MHz BW, 50 MHz Serial
AD5444 12 1 ±0.5 Serial RM-8 10 MHz BW, 50 MHz Serial

AD5415 12 2 ±1 Serial RU-24 10 MHz BW, 58 MHz Serial
AD5445 12 2 ±1 Parallel RU-20, CP-20

AD5447 12 2 ±1 Parallel RU-24
AD5449 12 2 ±1 Serial RU-16 10 MHz BW, 50 MHz Serial

AD5452 12 1 ±0.5 Serial RJ-8, RM-8 10 MHz BW, 50 MHz Serial
AD5446 14 1 ±1 Serial RM-8 10 MHz BW, 50 MHz Serial
AD5453 14 1 ±2 Serial UJ-8, RM-8 10 MHz BW, 50 MHz Serial
AD5553 14 1 ±1 Serial RM-8 4 MHz BW, 50 MHz Serial Clock
AD5556 14 1 ±1 Parallel RU-28
AD5555 14 2 ±1 Serial RM-8 4 MHz BW, 50 MHz Serial Clock
AD5557 14 2 ±1 Parallel RU-38

AD5543 16 1 ±2 Serial RM-8 4 MHz BW, 50 MHz Serial Clock
AD5546 16 1 ±2 Parallel RU-28

AD5545 16 2 ±2 Serial RU-16 4 MHz BW, 50 MHz Serial Clock
AD5547 16 2 ±2 Parallel RU-38

10 MHz BW, 17 ns

10 MHz BW, 17 ns

10 MHz BW, 17 ns

10 MHz BW, 17 ns

10 MHz BW, 17 ns
10 MHz BW, 17 ns

4 MHz BW, 20 ns

4 MHz BW, 20 ns

4 MHz BW, 20 ns

4 MHz BW, 20 ns

CS Pulse Width

CS Pulse Width

CS Pulse Width

CS Pulse Width

CS Pulse Width
CS Pulse Width

WR Pulse Width

WR Pulse Width

WR Pulse Width

WR Pulse Width

Rev. 0 | Page 26 of 28

AD5428/AD5440/AD5447

OUTLINE DIMENSIONS

6.60

6.50

6.40

PIN 1

0.15

0.05

COPLANARITY

0.10

24

PIN 1

0.15

0.05

0.10 COPLANARITY

20

1

0.65
BSC

0.30

0.19

COMPLIANT TO JEDEC STANDARDS MO-153AC

1.20 MAX

11

10

SEATING
PLANE

4.50

4.40

4.30

6.40 BSC

0.20

0.09

Figure 49. 20-Lead TSSOP

(RU-20)

Dimensions shown in millimeters

7.90

7.80

7.70

13

4.50

4.40

4.30

121

0.65

BSC

0.30

0.19

COMPLIANT TO JEDEC STANDARDS MO-153AD

1.20

MAX

SEATING
PLANE

6.40 BSC

0.20

0.09

8°
0°

0.75

0.60

0.45

8°
0°

0.75

0.60

0.45

Figure 50. 24-Lead TSSOP

(RU-24)

Dimensions shown in millimeters

Rev. 0 | Page 27 of 28

AD5428/AD5440/AD5447

ORDERING GUIDE

INL

Model Resolution

AD5428YRU 8 ±0.5 –40 °C to +125°C TSSOP (Thin Shrink Small Outline Package) RU-20
AD5428YRU-REEL 8 ±0.5 –40 °C to +125°C TSSOP (Thin Shrink Small Outline Package) RU-20
AD5428YRU-REEL7 8 ±0.5 –40 °C to +125°C TSSOP (Thin Shrink Small Outline Package) RU-20
AD5440YRU 10 ±0.5 –40 °C to +125°C TSSOP (Thin Shrink Small Outline Package) RU-24
AD5440YRU-REEL 10 ±0.5 –40 °C to +125°C TSSOP (Thin Shrink Small Outline Package) RU-24
AD5440YRU-REEL7 10 ±0.5 –40 °C to +125°C TSSOP (Thin Shrink Small Outline Package) RU-24
AD5447YRU 12 ±1 –40 °C to +125°C TSSOP (Thin Shrink Small Outline Package) RU-24
AD5447YRU-REEL 12 ±1 –40 °C to +125°C TSSOP (Thin Shrink Small Outline Package) RU-24
AD5447YRU-REEL7 12 ±1 –40 °C to +125°C TSSOP (Thin Shrink Small Outline Package) RU-24
EVAL-AD5428EB Evaluation Kit
EVAL-AD5440EB Evaluation Kit
EVAL-AD5447EB Evaluation Kit

(LSBs)

Temperature
Range Package Description

Package
Option

© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.

D04462–0–7/04(0)

Rev. 0 | Page 28 of 28