Datasheet AD5425 Datasheet (Analog Devices)

8-Bit, High Bandwidth

FEATURES

2.5 V to 5.5 V supply operation
50 MHz serial interface

9.5 MSPS update rate
INL of ±0.25 LSB
10 MHz multiplying bandwidth
±10 V reference input
Low glitch energy: <2 nV-s
Extended temperature range: −40°C to +125°C
10-lead MSOP package
Guaranteed monotonic
4-quadrant multiplication
Power-on reset with brownout detection

function

LDAC

0.4 µA typical power consumption

APPLICATIONS

Portable battery-powered applications
Waveform generators
Analog processing
Instrumentation applications
Programmable amplifiers and attenuators
Digitally controlled calibration
Programmable filters and oscillators
Composite video
Ultrasound
Gain, offset, and voltage trimming

Multiplying DAC with Serial Interface

GENERAL DESCRIPTION

The AD54251 is a CMOS, 8-bit, current output digital-to-analog
converter that operates from a 2.5 V to 5.5 V power supply,
making it suitable for battery-powered applications and many
other applications.

This DAC utilizes a double buffered, 3-wire serial interface that

is compatible with SPI
interface standards. An

simultaneous updates in a multi-DAC configuration. On power­up, the internal shift register and latches are filled with 0s and
the DAC outputs are 0 V.

As a result of manufacturing on a CMOS submicron process,
this DAC offers excellent 4-quadrant multiplication charac­teristics with large signal multiplying bandwidths of 10 MHz.

The applied external reference input voltage (V
the full-scale output current. An integrated feedback resistor,

, provides temperature tracking and full-scale voltage output

R

FB

when combined with an external I-to-V precision amplifier.

The AD5425 is available in a small, 10-lead MSOP package.

1

U.S. Patent No. 5,969,657

FUNCTIONAL BLOCK DIAGRAM

AD5425

V

DD

V

REF

8-BIT

R-2R DAC

R

AD5425

®, QSPI™, MICROWIRE™, and most DSP

pin is also provided, which allows

LDAC

REF

R

FB

I

1

OUT

I

2

OUT

) determines

LDAC

POWER-ON

RESET

SYNC
SCLK

SDIN

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

DAC REGISTER

INPUT LATCH

CONTROL LOGIC AND

INPUT SHIFT REGISTER

GND

Figure 1.

03161-001

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
Fax: [phone] © 2005 Analog Devices, Inc. All rights reserved.

www.analog.com

AD5425 Preliminary Technical Data

TABLE OF CONTENTS

Specifications..................................................................................... 3

Timing Characteristics..................................................................... 5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics............................................. 8

Te r m in o l o g y .................................................................................... 13

Theory of Operation ...................................................................... 14

Circuit Operation ....................................................................... 14

Single-Supply Applications........................................................ 16

Positive Output Voltage ............................................................. 16

REVISION HISTORY

3/05—Rev. 0 to Rev. A

Updated Format................................................................ Universal

Changes to Specifications Section.................................................3

Added Figure 18, Figure 20, Figure 21........................................10

Change to Table 7 ..........................................................................18

Adding Gain................................................................................ 17

DACs Used as a Divider or Programmable Gain Element... 17

Reference Selection .................................................................... 17

Amplifier Selection .................................................................... 18

Serial Interface............................................................................ 19

Microprocessor Interfacing....................................................... 19

PCB Layout and Power Supply Decoupling................................ 22

Evaluation Board ........................................................................ 22

Operating the Evaluation Board .............................................. 22

Outline Dimensions....................................................................... 27

Ordering Guide .......................................................................... 27

2/04—Revision 0: Initial Version

Rev. A | Page 2 of 28

Preliminary Technical Data AD5425

SPECIFICATIONS

VDD = 2.5 V to 5.5 V, V
otherwise noted. DC performance measured with OP177, ac performance with AD8038, unless otherwise noted.

Table 1.

Parameter Min Typ Max Unit Conditions/Comments

STATIC PERFORMANCE

Resolution 8 Bits
Relative Accuracy ±0.25 LSB
Differential Nonlinearity ±0.5 LSB Guaranteed monotonic
Gain Error ±10 mV
Gain Error Temperature Coefficient ±5 ppm FSR/°C
Output Leakage Current ±10 nA Data = 0x0000, TA = 25°C, I
±20 nA Data = 0x0000, T = −40°C to +125°C, I

REFERENCE INPUT

Reference Input Range ±10 V
V

Input Resistance 8 10 12 kΩ Input resistance TC = −50 ppm/°C

REF

RFB Resistance 8 10 12 kΩ Input resistance TC = −50 ppm/°C
Input Capacitance

Code Zero Scale 3 6 pF
Code Full Scale 5 8 pF

DIGITAL INPUT/OUTPUT1

Input High Voltage, VIH 1.7 V
Input Low Voltage, VIL 0.6 V
Output High Voltage, VOH VDD − 1 V VDD = 4.5 V to 5 V, I
V
Output Low Voltage, VOL 0.4 V VDD = 4.5 V to 5 V, I

0.4 V VDD = 2.5 V to 3.6 V, I
Input Leakage Current, IIL 1 µA
Input Capacitance 4 10 pF

DYNAMIC PERFORMANCE1

Reference Multiplying Bandwidth 10 MHz V
Output Voltage Settling Time

Measured to ±1 mV 90 160 ns
Measured to ±4 mV 55 110 ns

Measured to ±16 mV 50 100 ns
Digital Delay 40 75 ns Interface delay time
10% to 90% Settling Time 15 30 ns Rise and fall time, V
Digital-to-Analog Glitch Impulse 2 nV-s 1 LSB change around major carry V
Multiplying Feedthrough Error DAC latch loaded with all 0s. V
70 dB 1 MHz
48 dB 10 MHz
Output Capacitance

I

1 12 17 pF All 0s loaded

OUT

25 30 pF All 1s loaded
I

2 22 25 pF All 0s loaded

OUT

10 12 pF All 1s loaded

Digital Feedthrough 0.1 nV-s

Analog THD 81 dB V

= 10 V, I

REF

1

2 = 0 V. Temperature range for Y version: −40°C to +125°C. All specifications T

OUT

− 0.5 V VDD = 2.5 V to 3.6 V, I

DD

= ±3.5 V, DAC loaded all 1s

REF

= ±3.5 V, R

V

REF

LOAD

MIN

= 200 µA

SOURCE

SOURCE

= 200 µA

SINK

= 200 µA

SINK

to T

OUT

= 200 µA

, unless

MAX

1

= 100 Ω, DAC latch

OUT

1

alternately loaded with 0s and 1s

= 10 V, R

REF

Feedthrough to DAC output with

= 100 Ω

LOAD

REF

= ±3.5 V

REF

SYNC high

= 0 V

and alternate loading of all 0s and all 1s

= 3.5 V p-p; all 1s loaded, f = 1 kHz

REF

Rev. A | Page 3 of 28

AD5425 Preliminary Technical Data

Parameter Min Typ Max Unit Conditions/Comments

Digital THD Clock = 1 MHz, V

50 kHz f
20 kHz f

Output Noise Spectral Density 25

70 dB

OUT

OUT

73 dB

Hz

nV√

@ 1 kHz

SFDR Performance (Wide Band) Clock = 2 MHz , V

50 kHz f
20 kHz f

67 dB

OUT

68 dB

OUT

SFDR Performance (Narrow Band) Clock = 2 MHz, V

50 kHz f
20 kHz f

Intermodulation Distortion 79 dB

73 dB

OUT

75 dB

OUT

= 20 kHz, f2 = 25 kHz, clock = 2 MHz,

f

1

V

= 3.5 V

REF

POWER REQUIREMENTS

Power Supply Range 2.5 5.5 V
IDD 0.6 µA TA = 25°C, logic inputs = 0 V or VDD

0.4 5 µA Logic inputs = 0 V or VDD, T = −40°C to +125°C
Power Supply Sensitivity 0.001 %/% ∆V

1

Guaranteed by design and characterization, not subject to production test.

= ±5%

DD

= 3.5 V, C

REF

= 3.5 V

REF

= 3.5 V

REF

COMP

= 1.8 pF

Rev. A | Page 4 of 28

Preliminary Technical Data AD5425

TIMING CHARACTERISTICS

All input signals are specified with tr = tf = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. VDD =2.5 V to 5.5 V,

= 10 V, I

V

REF

Table 2. Timing Characteristics

Parameter

f

50 MHz max Maximum clock frequency

SCLK

t1 20 ns min SCLK cycle time
t2 8 ns min SCLK high time
t3 8 ns min SCLK low time

2

t

4

t5 5 ns min Data setup time
t6 3 ns min Data hold time
t7 5 ns min

t8 30 ns min
t9 0 ns min
t10 12 ns min
t11 10 ns min

1

Guaranteed by design and characterization, not subject to production test.

2

Falling or rising edge as determined by control bits of serial word.

2 = 0 V, temperature range for Y version: −40°C to +125°C ; all specifications T

OUT

1

VDD = 2.5 V to 5.5 V Unit Conditions/Comments

13 ns min

SYNC falling edge to SCLK falling edge setup time

SYNC rising edge to SCLK falling edge
Minimum

SYNC high time
SCLK falling edge to
LDAC pulse width
SCLK falling edge to

to T

MIN

MAX

LDAC falling edge

LDAC rising edge

, unless otherwise noted.

t

1

SCLK

t

t

8

4

SYNC

DIN

1

LDAC

2

LDAC

NOTES:

1

ASYNCHRONOUS LDAC UPDATE MODE.

2

SYNCHRONOUS LDAC UPDATE MODE.

DB7

t

2

t

6

t

5

t

3

t

7

DB0

t

t

10

9

t

11

03161-002

Figure 2. Timing Diagram

Rev. A | Page 5 of 28

AD5425 Preliminary Technical Data

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Rating

VDD to GND −0.3 V to +7 V
V

, RFB to GND −12 V to +12 V

REF

I

1, I

OUT

Logic Input and Output

2 to GND −0.3 V to VDD + 0.3 V

OUT

1

−0.3 V to VDD + 0.3 V

Operating Temperature Range

Extended Industrial (Y Version) −40°C to +125°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
10-lead MSOP

θ

Thermal Impedance

JA

Lead Temperature, Soldering

206°C/W

300°C

(10 secs)
IR Reflow, Peak Temperature

235°C

(<20 secs)

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may
affect device reliability. Only one absolute maximum rating may
be applied at any one time.

1

Overvoltages at SCLK,

Current should be limited to the maximum ratings given.

SYNC

, DIN, and

LDAC

are clamped by internal diodes.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. A | Page 6 of 28

Preliminary Technical Data AD5425

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

I

1

1

OUT

I

2

2

OUT

GND

SCLK

SDIN

AD5425

3

TOP VIEW

4

(Not to Scale)

5

Figure 3. Pin Configuration

Table 4. Pin Function Descriptions

Pin
No. Mnemonic Function

1 I

2 I

1 DAC Current Output.

OUT

2 DAC Analog Ground. This pin should normally be tied to the analog ground of the system.

OUT

3 GND Digital Ground Pin.

4 SCLK

Serial Clock Input. Data is clocked into the input shift register on each falling edge of the serial clock input.
This device can accommodate clock rates of up to 50 MHz.

5 SDIN Serial Data Input. Data is clocked into the 8-bit input register on each falling edge of the serial clock input.

6

SYNC

Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC

on the SCLK and DIN buffers and the input shift register is enabled. Data is transferred on each falling edge of the
following 8 clocks.

7

LDAC

Load DAC Input. Updates the DAC output. The DAC is updated when this signal goes low or alternatively; if this line is
held permanently low, an automatic update mode is selected whereby the DAC is updated after 8 SCLK falling edges

SYNC

with

low.

8 VDD Positive Power Supply Input. This part can be operated from a supply of 2.5 V to 5.5 V.

9 V

DAC Reference Voltage Input Terminal.

REF

10 RFB DAC Feedback Resistor Pin. Establishes voltage output for the DAC by connecting to external amplifier output.

10

R

FB

9

V

REF

8

V

DD

LDAC

7

SYNC6

03161-003

goes low, it powers

Rev. A | Page 7 of 28

AD5425 Preliminary Technical Data

TYPICAL PERFORMANCE CHARACTERISTICS

INL (LSB)

0.20

0.15

0.10

0.05

–0.05

–0.10

–0.15

TA = 25°C
V

REF

VDD = 5V

0

= 10V

0.4
TA= 25°C

VDD= 5V

0.2

MIN DNL

0

–0.2

DNL (LSB)

–0.4

MAX DNL

INL (LSB)

INL (LSB)

–0.20

0.20

0.15

0.10

0.05

–0.05

–0.10

–0.15

–0.20

0.3

0.2

0.1

–0.1

–0.2

–0.3

TA = 25°C
V
V

0

TA= 25°C
V

0

Figure 4. INL vs. Code (8-Bit DAC)

= 10V

REF

= 5V

DD

Figure 5. DNL vs. Code (8-Bit DAC)

= 5V

DD

REFERENCE VOLTAGE

Figure 6. INL vs. Reference Voltage

CODE

CODE

MAX INL

MIN INL

2500 50 100 150 200

03161-004

–0.6

REFERENCE VOLTAGE

1023456789

xxxxx-xxx

Figure 7. DNL vs. Reference Voltage

1.6

1.4

1.2

I

1 VDD 5V

I

OUT

OUT

1 VDD 3V

120–40 –20 0 20 40 60 80 100

03161-008

140–60 –40 –20 0 20 40 60 80 100 120

03161-009

1.0

0.8

0.6

LEAKAGE (nA)

OUT

I

0.4

0.2

2500 50 100 150 200

03161-005

1023456789

xxxxx-xxx

0

TEMPERATURE (°C)

Figure 8. I

5

V

= 10V

REF

4

3

2

1

0

–1

ERROR (mV)

–2

–3

–4

–5

1 Leakage Current vs. Temperature

OUT

VDD = 5V

VDD = 2.5V

TEMPERATURE (°C)

Figure 9. Gain Error vs. Temperature

Rev. A | Page 8 of 28

Preliminary Technical Data AD5425

LSBs

–0.1

–0.3

0.5

0.3

0.1

TA = 25°C
VDD = 3V
V

= 0V

REF

MAX INL

MIN INL

MAX DNL

MIN DNL

2.5
VDD = 5V

V

= 0V

REF

2.0

1.5

1.0

VOLTAGE (mV)

0.5

0

GAIN ERROR

OFFSET ERROR

–0.5

V

BIAS

Figure 10. Linearity vs. V

1.4
TA = 25°C

= 3V

V

DD

1.2

V

= 0V

REF

1.0

0.8

0.6

0.4

VOLTAGE(mV)

0.2

0

–0.2

–0.4

BIAS

V

BIAS

Figure 11. Gain and Offset Errors vs. V

(V)

Voltage Applied to I

GAIN ERROR

OFFSET ERROR

(V)

Voltage Applied to I

BIAS

OUT

1.50.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4

03161-010

2

1.50.5 1.0

03161-011

2

OUT

–0.5

V

(V)

BIAS

Figure 13. Gain and Offset Errors vs. Voltage Applied to I

10.0
TA = 25°C

= 5V

V

DD

V

= 2.5V

8.0

REF

6.0

4.0

2.0

VOLTAGE (mV)

0

–2.0

–4.0

Figure 14. Gain and Offset Errors vs. V

OFFSET ERROR

GAIN ERROR

V

(V)

BIAS

Voltage Applied to I

BIAS

OUT

2.50.5 1.0 1.5 2.0

2.50 0.5 1.0 1.5 2.0

OUT

03161-013

2

03161-014

2

0.5
VDD = 5V

V

= 0V

REF

0.3

0.1

LSBs

–0.1

–0.3

–0.5

Figure 12. Linearity vs. V

MAX INL

MIN DNL

MIN INL

V

(V)

BIAS

Voltage Applied to I

BIAS

MAX DNL

OUT

1.0
TA = 25°C

= 5V

V

DD

0.8

= 2.5V

V

REF

0.6

0.4

0.2

LSBs

–0.2

–0.4

–0.6

–0.8

2.50.5 1.0 1.5 2.0

03161-012

–1.0

2

MAX INL BIAS

0

MAX DNL BIAS

MIN DNL BIAS

Figure 15. Linearity vs. V

MIN INL BIAS

V

(V)

BIAS

Voltage Applied to I

BIAS

OUT

2.00 0.5 1.0 1.5

03161-015

2

Rev. A | Page 9 of 28

AD5425 Preliminary Technical Data

0.7

0.6

0.5

0.4

0.3

CURRENT (mA)

0.2

0.1

T

= 25°C

A

VDD = 5V

VDD = 2.5V

VDD = 3V

0

INPUT VOLTAGE (V)

Figure 16. Supply Current vs. Input Voltage

501234

03161-016

0.060

0.050

0.040

0.030

0.020

0.010

OUTPUT VOLTAGE (V)

0

–0.010

–0.020

Figure 19. Midscale Transition, V

VDD 5V, 0V REF
NRG = 2.049nVs
07xFF TO 0x800

VDD 3V, 0V REF
NRG = 0.088nVs
0x800 TO 0x7FF

VDD 5V, 0V REF
NRG = 0.119nVs,
0x800 TO 0x7FF

TIME (ns)

TA = 25°C
V

REF

AD8038 AMPLIFIER
C

COMP

VDD 3V, 0V REF
NRG = 1.877nVs
0x7FF TO 0x800

REF

= 0V

= 1.8pF

= 3.5 V

3000 50 100 150 200 250

03161-019

1.8
TA = 25°C

1.6

1.4

1.2

1.0

0.8

0.6

0.4

THRESHOLD VOLTAGE (V)

0.2

0

V

IH

V

IL

VOLTAGE (V)

5.52.5 3.0 3.5 4.0 4.5 5.0

03161-017

Figure 17. Thres hold Vol tages v s. Supp ly Voltag e

0.2

0

–0.2

–0.4

GAIN (dB)

6

= 25°C

T

A

0

LOADING

–6

ZS TO FS

–12
–18
–24
–30
–36
–42
–48
–54
–60

GAIN (dB)

–66
–72
–78
–84
–90
–96

–102

ALL ON
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0

ALL OFF

FREQUENCY (Hz)

= 25°C

T

A

= 5V

V

DD

= ±3.5V

V

REF

INPUT

= 1.8pF

C

COMP

AD8083 AMPLIFIER

100M1 10 100 1k 10k 100k 1M 10M

Figure 20. Reference Multiplying Bandwidth vs. Frequency and Code

3

V

= ±0.15V, AD8038 CC 1pF

REF

V

= ±2V, AD8038 CC 1pF

REF

0

V

= ±3.51V, AD8038 CC 1.8pF

REF

= ±2V, AD8038 CC 1.47pF

V

REF

–3

GAIN (dB)

= ±0.15V, AD8038 CC 1.47pF

V

REF

03161-020

TA = 25°C

–0.6

= 5V

V

DD

= ±3.5V

V

REF

= 1.8pF

C

COMP

AD8083 AMPLIFIER

–0.8

FREQUENCY (Hz)

Figure 18. Reference Multiplying Bandwidth—All 1s Loaded

100M1 10 100 1k 10k 100k 1M 10M

03161-018

Rev. A | Page 10 of 28

–6

TA = 25°C

= 5V

V

DD

AD8038 AMPLIFIER

–9

FREQUENCY (Hz)

100M10k 100k 1M 10M

Figure 21. Reference Multiplying Bandwidth vs. Frequency and

Compensation Capacitor

03161-021

Preliminary Technical Data AD5425

–60

TA = 25°C
V

DD

V

REF

–65

–70

–75

THD + N (dB)

–80

–85

–90

= 3V

= 3.5V p-p

FREQUENCY (Hz)

1M1 10 100 1k 10k 100k

03161-022

–10
–20
–30
–40
–50
–60

SFDR (dB)

–70
–80

–90
–100
–110

0

FREQUENCY (Hz)

TA = 25°C

= 5V

V

DD

= 3.5V

V

REF

AD8038 AMPLIFIER

1M0 200k 400k 600k 800k

03161-025

Figure 22. THD and Noise vs. Frequency

20

VDD = 3V
AMPLIFIER = AD8038

0

–20

–40

POWER SUPPLY REJECTION

–60

–80

–100

–120

FULL SCALE

ZERO SCALE

FREQUENCY (Hz)

Figure 23. Power Supply Rejection vs. Frequency

0
–10
–20
–30
–40
–50
–60

SFDR (dB)

–70
–80
–90

–100
–110

FREQUENCY (Hz)

Figure 24. Wideband SFDR, Clock = 2 MHz, f

TA = 25°C

= 5V

V

DD

= 3.5V

V

REF

AD8038 AMPLIFIER

= 50 kHz

OUT

Figure 25. Wideband SFDR, Clock = 2 MHz, f

0
–10
–20
–30
–40
–50
–60

SFDR (dB)

–70
–80
–90

–100

10M1 10 100 1k 10k 100k 1M

03161-023

–110

FREQUENCY (Hz)

Figure 26. Narrowband SFDR, Clock = 2 MHz, f

0
–10
–20
–30
–40
–50
–60

SFDR (dB)

–70
–80
–90

–100

1M0 200k 400k 600k 800k

03161-024

–110

FREQUENCY (Hz)

Figure 27. Narrowband SFDR, Clock = 2 MHz, f

= 20 kHz

OUT

TA = 25°C

= 5V

V

DD

= 3.5V

V

REF

AD8038 AMPLIFIER

= 20 kHz

OUT

TA = 25°C

= 5V

V

DD

= 3.5V

V

REF

AD8038 AMPLIFIER

= 50 kHz

OUT

30k10k 14k12k 18k 22k 26k16k 20k 24k 28k

03161-026

75k25k 35k30k 45k 55k 65k40k 50k 60k 70k

03161-027

Rev. A | Page 11 of 28

AD5425 Preliminary Technical Data

0

–10

–20

–30

–40

–50

IMD (dB)

–60

–70

–80

–90

–100

FREQUENCY (Hz)

Figure 28. Narrowband IMD (±50%) Clock = 2 MHz,

1 = 20 kHz, f

f

OUT

2 = 25 kHz

OUT

VDD = 5V

= 3.5V

V

REF

AD8038 AMPLIFIER

35k10k 15k 20k 25k 30k

03161-028

Rev. A | Page 12 of 28

Preliminary Technical Data AD5425

(

TERMINOLOGY

Relative Accuracy

Relative accuracy or endpoint nonlinearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
adjusting for zero and full scale and is normally expressed in
LSBs or as a percentage of full-scale reading.

Differential Nonlinearity

Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of −1 LSB maximum
over the operating temperature range ensures monotonicity.

Gain Error

Gain error or full-scale error is a measure of the output error
between an ideal DAC and the actual device output. For these
DACs, ideal maximum output is V

− 1 LSB. Gain error of the

REF

DACs is adjustable to 0 with external resistance.

Output Leakage Current

Output leakage current is current that flows in the DAC ladder
switches when these are turned off. For the I

1 terminal, it can

OUT

be measured by loading all 0s to the DAC and measuring the

1 current. Minimum current flows in the I

I

OUT

2 line when

OUT

the DAC is loaded with all 1s.

Output Capacitance

Capacitance from I

OUT

1 or I

2 to AGND.

OUT

Output Current Settling Time

This is the amount of time it takes for the output to settle to a
specified level for a full-scale input change. For these devices, it
is specified with a 100 Ω resistor to ground.

The settling time specification includes the digital delay from

rising edge to the full-scale output charge.

SYNC

Digital-to-Analog Glitch Impulse

The amount of charge injected from the digital inputs to the
analog output when the inputs change state. This is normally
specified as the area of the glitch in either pA-s or nV-s
depending upon whether the glitch is measured as a current or
voltage signal.

Digital Feedthrough

When the device is not selected, high frequency logic activity on
the device digital inputs can be capacitively coupled to show up
as noise on the I

pins and subsequently into the following

OUT

circuitry. This noise is digital feedthrough.

Multiplying Feedthrough Error

This is the error due to capacitive feedthrough from the DAC
reference input to the DAC I

1 terminal, when all 0s are

OUT

loaded to the DAC.

Total Harmonic Distortion (THD)

The DAC is driven by an ac reference. The ratio of the rms sum
of the harmonics of the DAC output to the fundamental value is
the THD. Usually only the lower order harmonics are included,
such as second to fifth.

2

2

2

THD

2

=

2

log20

4

3

V

1

)

VVVV

+++

5

Digital Intermodulation Distortion

Second-order intermodulation distortion (IMD) measurements
are the relative magnitude of the fa and fb tones generated
digitally by the DAC and the second-order products at 2fa − fb
and 2fb − fa.

Spurious-Free Dynamic Range (SFDR)

SFDR is the usable dynamic range of a DAC before spurious
noise interferes or distorts the fundamental signal. It is the mea­sure of the difference in amplitude between the fundamental
and the largest harmonically or nonharmonically related spur
from dc to full Nyquist bandwidth (half the DAC sampling rate,

/2). Narrow band SFDR is a measure of SFDR over an

or f

S

arbitrary window size, in this case 50% of the fundamental.
Digital SFDR is a measure of the usable dynamic range of the
DAC when the signal is a digitally generated sine wave.

Rev. A | Page 13 of 28

AD5425 Preliminary Technical Data

THEORY OF OPERATION

The AD5425 is an 8-bit current output DAC consisting of a
standard inverting R-2R ladder configuration. A simplified
diagram is shown in Figure 29. The feedback resistor, R

, has a

FB

value of R. The value of R is typically 10 kΩ (minimum 8 kΩ
and maximum 12 kΩ). If I

OUT

1 and I

2 are kept at the same

OUT

potential, a constant current flows in each ladder leg, regardless
of digital input code. Therefore, the input resistance presented

is always constant and nominally of value R. The DAC

at V

REF

output, I

, is code-dependent, producing various resistances

OUT

and capacitances. When choosing the external amplifier, take
into account the variation in impedance generated by the DAC
on the amplifiers inverting input node.

S3

REF

RRR

, RFB, I

2R 2R

S8

1, and I

OUT

R

R

FB

I

1

OUT

I

2

OUT

2 terminals of

OUT

03161-029

V

REF

2RS12RS22R

DAC DATA LATCHES

AND DRIVERS

Figure 29. Simplified Ladder

Access is provided to the V
the DAC, making the device extremely versatile and allowing it
to be configured in several different operating modes, for exam­ple, to provide a unipolar output, bipolar output, or in single­supply modes of operation in unipolar mode or 4-quadrant
multiplication in bipolar mode. Note that a matching switch is
used in series with the internal R
attempt to measure R

, power must be applied to VDD to

FB

feedback resistor. If users

FB

achieve continuity.

CIRCUIT OPERATION

Unipolar Mode

Using a single op amp, this device can easily be configured to
provide 2-quadrant multiplying operation or a unipolar output
voltage swing, as shown in Figure 30.

When an output amplifier is connected in unipolar mode, the
output voltage is given by

D

OUT

VV

REF

×−=

n

2

where D is the fractional representation of the digital word
loaded to the DAC, in this case 0 to 255, and n is the number
of bits.

Note that the output voltage polarity is opposite to the V
polarity for dc reference voltages.

This DAC is designed to operate with either negative or positive
reference voltages. The V

power pin is used by only the inter-

DD

nal digital logic to drive the DAC switches’ on and off states.

This DAC is also designed to accommodate ac reference input
signals in the range of −10 V to +10 V.

With a fixed 10 V reference, the circuit shown in Figure 30 gives
a unipolar 0 V to −10 V output voltage swing. When V
signal, the circuit performs 2-quadrant multiplication.

Table 5 shows the relationship between digital code and the
expected output voltage for unipolar operation.

Table 5. Unipolar Code Table

Digital Input Analog Output (V)

1111 1111 −V
1000 0000 −V
0000 0001 −V
0000 0000 −V

V

REF

R1

MICROCONTROLLER

NOTES:

1. R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.

2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.

V

REF

SCLK SDIN GND

SYNC

Figure 30. Unipolar Operation

(255/256)

REF

(128/256) = −V

REF

(1/256)

REF

(0/256) = 0

REF

V

DD

V

DD

AD5425

/2

REF

R2

R

FB

I

OUT

I

OUT

C1

1

2

AGND

A1

A1

V
TO –V

is an ac

IN

= 0

OUT

REF

REF

03161-030

Rev. A | Page 14 of 28

Preliminary Technical Data AD5425

V

R3

20kΩ

V

DD

V

R

FB

DD

I

V

REF

±10V

R1

MICROCONTROLLER

NOTES:

1. R1 AND R2 ARE USED ONLY IF GAIN ADJUSTMENT IS REQUIRED. ADJUST R1 FOR
V

= 0 V WITH CODE 10000000 LOADED TO DAC.

OUT

2. MATCHING AND TRACKING IS ESSENTIAL FOR RESISTOR PAIRS R3 AND R4.

3. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED IF A1/A2 IS A HIGH
SPEED AMPLIFIER.

REF

SCLK SDIN GND

SYNC

AD5425

OUT

I

OUT

Figure 31. Bipolar Operation (4-Quadrant Multiplication)

Bipolar Operation

In some applications, it may be necessary to generate full 4­quadrant multiplying operation or a bipolar output swing. This
can be easily accomplished by using another external amplifier
and some external resistors, as shown in Figure 31. In this
circuit, the second amplifier, A2, provides a gain of 2. Biasing
the external amplifier with an offset from the reference voltage,
results in full 4-quadrant multiplying operation. The transfer
function of this circuit shows that both negative and positive
output voltages are created as the input data, D, is incremented
from code zero (V
scale (V

= +V

OUT

()

OUT

REF

REF

OUT

= −V

).

) to midscale (V

REF

n

−1

VDVV −×=

2/

REF

= 0 V ) to full

OUT

Where D is the fractional representation of the digital word
loaded to the DAC and n is the resolution of the DAC.

R5

R2

C1

1

2

AGND

10kΩ

A1

A1

20kΩ

R4

A2

V

=–V

OUT

REF

TO +V

REF

03161-031

Stability

In the I-to-V configuration, the I

of the DAC and the

OUT

inverting node of the op amp must be connected as closely as
possible and proper PCB layout techniques must be employed.
Since every code change corresponds to a step function, gain
peaking can occur if the op amp has limited GBP and there is
excessive parasitic capacitance at the inverting node. This
parasitic capacitance introduces a pole into the open-loop
response, which can cause ringing or instability in closed-loop
applications.

An optional compensation capacitor, C1, can be added in
parallel with R

for stability, as shown in Figure 30 and Figure

FB

31. Too small a value of C1 can produce ringing at
the output, while too large a value can adversely affect the
settling time. C1 should be found empirically, but 1 pF to
2 pF is generally adequate for compensation.

When V

is an ac signal, the circuit performs 4-quadrant

IN

multiplication.

Table 6 shows the relationship between digital code and the
expected output voltage for bipolar operation.

Table 6. Bipolar Code Table

Digital Input Analog Output (V)

1111 1111 +V

(127/128)

REF

1000 0000 0
0000 0001 −V
0000 0000 −V

(127/128)

REF

(128/128)

REF

Rev. A | Page 15 of 28

AD5425 Preliminary Technical Data

V

SINGLE-SUPPLY APPLICATIONS

Current Mode Operation

In the current mode circuit of Figure 32, I
is biased positive by an amount applied to V
configuration, the output voltage is given by

= [D × (RFB/R

V

OUT

DAC

) × (V

− VIN)] + V

BIAS

As D varies from 0 to 255, the output voltage varies from

= V

to V

V

DD

V

DD

GND

OUT

= 2V

V

BIAS

V

OUT

BIAS

V

V

IN

REF

NOTES:

1. ADDITIONAL PINS OMITTED FOR CLARITY.

2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE
REQUIRED IF A1 IS A HIGH SPEED AMPLIFIER.

− V

BIAS

R

FB

1

I

OUT

I

2

OUT

Figure 32. Single-Supply Current Mode Operation

V

should be a low impedance source capable of sinking and

BIAS

sourcing all possible variations in current at the I
without any problems.

It is important to note that V

is limited to low voltages because

IN

the switches in the DAC ladder no longer have the same source­drain drive voltage. As a result, their on resistance differs and
this degrades the linearity of the DAC.

Voltage Switching Mode of Operation

Figure 33 shows this DAC operating in the voltage switching
mode. The reference voltage V

is applied to the I

IN

is connected to AGND, and the output voltage is available at the

terminal. In this configuration, a positive reference voltage

V

REF

results in a positive output voltage, making single-supply
operation possible. The output from the DAC is voltage at a
constant impedance (the DAC ladder resistance), thus an op
amp is necessary to buffer the output voltage. The reference
input no longer sees constant input impedance, but one that
varies with code. So, the voltage input should be driven from a
low impedance source.

IN

C1

2 and hence I

OUT

. In this

BIAS

BIAS

A1

A1

OUT

OUT

OUT

V

OUT

03161-032

2 terminal

1 pin, I

OUT

1

V

DD

R

V

FB

I

I

OUT

OUT

1

2

IN

NOTES:

1. ADDITIONAL PINS OMITTED FOR CLARITY.

2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.

DD

GND

V

REF

R2R1

A1

A1

V

OUT

03161-033

Figure 33. Single-Supply Voltage Switching Mode Operation

It is important to note that VIN is limited to low voltage because
the switches in the DAC ladder no longer have the same source
drain drive voltage. As a result, their on resistance differs, which
degrades the linearity of the DAC.

must also not go negative by more than 0.3 V, otherwise an

V

IN

internal diode turns on, exceeding the maximum ratings of the
device. In this type of application, the full range of the DAC
multiplying capability is lost.

POSITIVE OUTPUT VOLTAGE

Note that the output voltage polarity is opposite to the V
polarity for dc reference voltages. To achieve a positive voltage
output, an applied negative reference to the input of the DAC is
preferred over the output inversion through an inverting
amplifier because of the resistor tolerance errors. To generate a
negative reference, the reference can be level shifted by an
op amp such that the V

and GND pins of the reference

OUT

become the virtual ground and −2.5 V respectively, as shown
in Figure 34.

V

REF

VDD = 5V

V

DD

GND

R

FB

I

OUT

I

OUT

C1

1

2

V

OUT

ADR03

V

OUTVIN

GND

+5V

2

–5V

–2.5V

NOTES:

1

ADDITIONAL PINS OMITTED FOR CLARITY.

2

C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED,

IF A1 IS A HIGH SPEED AMPLIFIER.

Figure 34. Positive Voltage Output with Minimum of Components

REF

= 0V TO +2.5V

04588-033

Rev. A | Page 16 of 28

Preliminary Technical Data AD5425

V

V

ADDING GAIN

In applications where the output voltage is required to be
greater than V

, gain can be added with an additional external

IN

amplifier or it can be achieved in a single stage. It is important
to take into consideration the effect of temperature coefficients
of the thin film resistors of the DAC. Simply placing a resistor in
series with the R

resistor causes mismatches in the temp-

FB

erature coefficients and results in larger gain temperature
coefficient errors. Instead, the circuit of Figure 35 is a recom­mended method of increasing the gain of the circuit. R1, R2,
and R3 should all have similar temperature coefficients, but
they need not match the temperature coefficients of the DAC.
This approach is recommended in circuits where gains of
greater than 1 are required.

V

DD

R

V

R1

IN

V

REF

GND

NOTES:

1. ADDITIONAL PINS OMITTED FOR CLARITY.

2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.

FB

DD

I

I

OUT

OUT

Figure 35. Increasing the Gain of Current Output DAC

C1

1

2

A1

R3

R2

V

OUT

GAIN = R2 + R3
R2

R1 = R2R3
R2 + R3

03161-035

DACS USED AS A DIVIDER OR PROGRAMMABLE GAIN ELEMENT

Current steering DACs are very flexible and lend themselves to
many different applications. If this type of DAC is connected as
the feedback element of an op amp and R
resistor as shown in Figure 36, then the output voltage is
inversely proportional to the digital input fraction, D.

−n

For D = 1 − 2

V

OUT

, the output voltage is

= −VIN/D = −VIN/(1 − 2−n)

As D is reduced, the output voltage increases. For small values
of D, it is important to ensure that the amplifier does not satur­ate and that the required accuracy is met. For example, an 8-bit
DAC driven with the Binary Code 0x10 (00010000), that is, 16
decimal, in the circuit of Figure 36, should cause the output
voltage to be 16 × V

. However, if the DAC has a linearity

IN

specification of ±0.5 LSB, then D can in fact have a weight
anywhere in the range 15.5/256 to 16.5/256. Therefore, the
possible output voltage is in the range of 15.5 V
an error of 3%, even though the DAC itself has a maximum
error of 0.2%.

is used as the input

FB

to 16.5 VIN—

IN

V

IN

R

I

1

OUT

NOTE:

1. ADDITIONAL PINS OMITTED FOR CLARITY.

DD

V

FB

DD

V

REF

GND

V

OUT

03161-036

Figure 36. Current Steering DAC Used as a Divider or

Programmable Gain Element

DAC leakage current is also a potential error source in divider
circuits. The leakage current must be counterbalanced by an
opposite current supplied from the op amp through the DAC.
Since only a fraction, D, of the current into the V
routed to the I

1 terminal, the output voltage has to change

OUT

terminal is

REF

as follows:

Output Error Voltage Due to DAC Leakage = (Leakage × R)/D

where R is the DAC resistance at the V

terminal. For a DAC

REF

leakage current of 10 nA, R = 10 kΩ. With a gain (that is, 1/D)
of 16 the error voltage is 1.6 mV.

REFERENCE SELECTION

When selecting a reference for use with the AD5425 current
output DAC, pay attention to the reference’s output voltage
temperature coefficient specification. This parameter not only
affects the full-scale error, but can also affect the linearity (INL
and DNL) performance. The reference temperature coefficient
should be consistent with the system accuracy specifications.
For example, an 8-bit system required to hold its overall
specification to within 1 LSB over the temperature range 0°C to
50°C dictates that the maximum system drift with temperature
should be less than 78 ppm/°C. A 12-bit system with the same
temperature range to overall specification within 2 LSB requires
a maximum drift of 10 ppm/°C. By choosing a precision
reference with a low output temperature coefficient, this error
source can be minimized. Table 7 suggests some of the
references available from Analog Devices that are suitable for
use with this range of current output DACs.

Rev. A | Page 17 of 28

AD5425 Preliminary Technical Data

AMPLIFIER SELECTION

The primary requirement for the current-steering mode is an
amplifier with low input bias currents and low input offset vol­tage. The input offset voltage of an op amp is multiplied by the
variable gain (due to the code dependent output resistance of
the DAC) of the circuit. A change in this noise gain between two
adjacent digital fractions produces a step change in the output
voltage due to the amplifier’s input offset voltage. This output
voltage change is superimposed on the desired change in output
between the two codes and gives rise to a differential linearity
error, which if large enough, could cause the DAC to be
nonmonotonic.

Common-mode rejection of the op amp is important in voltage
switching circuits, since it produces a code dependent error at
the voltage output of the circuit. Most op amps have adequate
common-mode rejection for use at an 8-bit resolution.

Provided the DAC switches are driven from true wideband low
impedance sources (V

and AGND), they settle quickly. Conse-

IN

quently, the slew rate and settling time of a voltage switching
DAC circuit is determined largely by the output op amp. To
obtain minimum settling time in this configuration, it is impor­tant to minimize capacitance at the V

node (voltage output

REF

node in this application) of the DAC. This is done by using low
inputs capacitance buffer amplifiers and careful board design.

The input bias current of an op amp also generates an offset at
the voltage output as a result of the bias current flowing in the
feedback resistor, R

. Most op amps have input bias currents

FB

low enough to prevent any significant errors.

Most single-supply circuits include ground as part of the analog
signal range, which in turns requires an amplifier that can
handle rail-to-rail signals. There is a large range of single-supply
amplifiers available from Analog Devices.

Table 7. Suitable ADI Precision References

Part No. Output Voltage (V) Initial Tolerance (%) Temp Drift (ppm/°C) ISS (mA) Output Noise (µV p-p) Package

ADR01 10 0.05 3 1 20 SOIC-8
ADR01 10 0.05 9 1 20 TSOT-23, SC70
ADR02 5 0.06 3 1 10 SOIC-8
ADR02 5 0.06 9 1 10 TSOT-23, SC70
ADR03 2.5 0.10 3 1 6 SOIC-8
ADR03 2.5 0.10 9 1 6 TSOT-23, SC70
ADR06 3 0.10 3 1 10 SOIC-8
ADR06 3 0.10 9 1 10 TSOT-23, SC70
ADR431 2.5 0.04 3 0.8 3.5 SOIC-8
ADR435 5 0.04 3 0.8 8 SOIC-8
ADR391 2.5 0.16 9 0.12 5 TSOT-23
ADR395 5 0.10 9 0.12 8 TSOT-23

Table 8. Suitable Precision ADI Op Amps

0.1 Hz to 10 Hz

Part No. Supply Voltage (V) VOS (Max) (µV) IB (Max) (nA)

OP97 ±2 to ±20 25 0.1 0.5 600 SOIC-8
OP1177 ±2.5 to ±15 60 2 0.4 500 MSOP, SOIC-8
AD8551 2.7 to 5 5 0.05 1 975 MSOP, SOIC-8
AD8603 1.8 to 6 50 0.001 2.3 50 TSOT
AD8628 2.7 to 6 5 0.1 0.5 850 TSOT, SOIC-8

Noise (µV p-p)

Supply Current (µA) Package

Table 9. Suitable High Speed ADI Op Amps

Part No. Supply Voltage (V) BW @ ACL (MHz) Slew Rate (V/µs) VOS (Max) (µV) IB (Max) (nA) Package

AD8065 5 to 24 145 180 1500 6000 SOIC-8, SOT-23,MSOP
AD8021 ±2.5 to ±12 490 120 1000 10500 SOIC-8, MSOP
AD8038 3 to 12 350 425 3000 750 SOIC-8, SC70-5
AD9631 ±3 to ±6 320 1300 10000 7000 SOIC-8

Rev. A | Page 18 of 28

Preliminary Technical Data AD5425

SERIAL INTERFACE

The AD5425 has a simple 3-wire interface that is compatible
with SPI, QSPI, MICROWIRE, and DSP interface standards.
Data is written to the device in 8-bit words. This 8-bit word
consists of 8 data bits, as shown in Figure 37.

DB7 (MSB)

DB7 DB6 DB5 DB4 DB3 DB2 DB0DB1

DATA BITS

Figure 37. 8-Bit Input Shift Register Contents

is an edge-triggered input that acts as a frame synchro-

SYNC
nization signal and chip enable. Data can be transferred into the

device only while

should be taken low, observing the minimum

SYNC

is low. To start the serial data transfer,

SYNC

falling to SCLK falling edge setup time, t

After loading eight data bits to the shift register, the

is brought high. The contents of the DAC register and the
output are updated by bringing

LDAC

8-bit data transfer is complete, as seen in the timing diagram of
Figure 2.

can be tied permanently low if required. For

LDAC

another serial transfer to take place, the interface must be
enabled by another falling edge of

DB0 (LSB)

03161-037

.

4

SYNC

low any time after the

.

SYNC

SYNC

line

ADSP-2191

1

ADDITIONAL PINS OMITTED FOR CLARITY.

1

SPIxSEL

Figure 38. ADSP-2191 SPI-to-AD5425 Interface

SYNC

SDINMOSI

SCLKSCK

A serial interface between the DAC and DSP SPORT is shown
in Figure 39. In this interface example, SPORT0 is used to
transfer data to the DAC shift register. Transmission is initiated
by writing a word to the Tx register after the SPORT has been
enabled. In a write sequence, data is clocked out on each rising
edge of the DSP’s serial clock and clocked into the DAC input
shift register on the falling edge of its SCLK. The update of the
DAC output takes place on the rising edge of the

ADSP-2101/
ADSP-2103/
ADSP-2191

1

SYNCTFS

SDINDT

SCLKSCLK

AD5425

SYNC

AD5425

1

03161-038

signal.

1

Low Power Serial Interface

To minimize the power consumption of the device, the interface
fully powers up only when the device is being written to, that is,
on the falling edge of

are powered down on the rising edge of

. The SCLK and SDIN input buffers

SYNC

.

SYNC

MICROPROCESSOR INTERFACING

Microprocessor interfacing to this DAC is via a serial bus that
uses standard protocol compatible with microcontrollers and
DSP processors. The communications channel is a 3-wire inter­face consisting of a clock signal, a data signal, and a synchro­nization signal. An

requires an 8-bit word with the default being data valid on the
falling edge of SCLK, but this is changeable via the control bits
in the data-word.

ADSP-21xx-to AD5425 Interface

The ADSP-21xx family of DSPs is easily interfaced to this family
of DACs without extra glue logic. Figure 38 shows an example
of an SPI interface between the DAC and the ADSP-2191. SCK
of the DSP drives the serial data line, DIN. SYNC is driven from
one of the port lines, in this case

pin is also included. The AD5425

LDAC

SPIxSEL

.

1

ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 39. ADSP-2101/ADSP-2103/ADSP-2191 SPORT-to-AD5425 Interface

Communication between two devices at a given clock speed is
possible when the following specifications from one device to
the other are compatible: frame sync delay and frame sync setup
and hold, data delay and data setup and hold, and SCLK width.
The DAC interface expects a t

(SYNC falling edge to SCLK

4

falling edge setup time) of 13 ns minimum. Consult the ADSP­21xx user manual for information on clock and frame sync
frequencies for the SPORT register.

Table 10. SPORT Control Register Setup

Name Setting Description

TFSW 1 Alternate framing
INVTFS 1 Active low frame signal
DTYPE 00 Right-justify data
ISCLK 1 Internal serial clock
TFSR 1 Frame every word
ITFS 1 Internal framing signal
SLEN 0111 8-bit data-word

03161-039

Rev. A | Page 19 of 28

AD5425 Preliminary Technical Data

ADSP-BF5xx-to-AD5425 Interface

The ADSP-BF5xx family of processors has an SPI-compatible
port that enables the processor to communicate with SPI­compatible devices. A serial interface between the ADSP-BF5xx
and the AD5425 DAC is shown in Figure 40. In this configura­tion, data is transferred through the MOSI (master output/slave
input) pin.

is driven by the SPI chip select pin, which is a

SYNC

reconfigured programmable flag pin.

ADSP-BF5xx

1

SYNCSPIxSEL

SDINMOSI

SCLKSCK

AD5425

1

80C51/80L51-to-AD5425 Interface

A serial interface between the DAC and the 8051 is shown in
Figure 42. TxD of the 8051 drives SCLK of the DAC serial
interface, while RxD drives the serial data line, D
programmable pin on the serial port that drives

. P3.3 is a bit-

IN

. When

SYNC

data is transmitted to the switch, P3.3 is taken low. The 80C51/
80L51 transmits data in 8-bit bytes, which fits the AD5425 since
it only requires an 8-bit word. Data on RxD is clocked out of the
microcontroller on the rising edge of TxD and is valid on the
falling edge. As a result, no glue logic is required between the
DAC and microcontroller interface. P3.3 is taken high at the
completion of this cycle. The 8051 provides the LSB of its SBUF
register as the first bit in the data stream. The DAC input reg­ister requires that the MSB is the first bit received. The transmit
routine should take this into account.

1

ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 40. ADSP-BF5xx-to-AD5425 Interface

The ADSP-BF5xx processor incorporates channel synchronous
serial ports (SPORT). A serial interface between the DAC and
the DSP SPORT is shown in Figure 41. When the SPORT is
enabled, initiate transmission by writing a word to the Tx
register. The data is clocked out on each rising edge of the DSP’s
serial clock and clocked into the DAC’s input shift register on
the falling edge of its SCLK. The DAC output is updated by
using the transmit frame synchronization (TFS) line to provide

signal.

a

SYNC

ADSP-BF5xx

1

ADDITIONAL PINS OMITTED FOR CLARITY.

1

Figure 41. ADSP-BF5xx-to-AD5425 Interface

SYNCTFS

SDINDT

SCLKSCLK

AD5425

1

03161-040

03161-041

1

8051

1

ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 42. 80C51/80L51-to-AD5425 Inter face

SCLKTxD

SDINRxD

SYNCP1.1

AD5425

1

03161-042

MC68HC11 Interface-to-AD5425 Interface

Figure 43 shows an example of a serial interface between the
DAC and the MC68HC11 microcontroller. The serial peripheral
interface (SPI) on the MC68HC11 is configured for master
mode (MSTR = 1), clock polarity bit (CPOL) = 0, and the clock
phase bit (CPHA) = 1. The SPI is configured by writing to the
SPI control register (SPCR) (see the MC68HC11 user manual).
SCK of the MC68HC11 drives the SCLK of the DAC interface,
the MOSI output drives the serial data line, D
The

being transmitted to the AD5425, the

signal is derived from a port line, PC7. When data is

SYNC

SYNC

, of the AD5425.

IN

line is taken low

(PC7). Data appearing on the MOSI output is valid on the
falling edge of SCK. Serial data from the MC68HC11 is
transmitted in 8-bit bytes with only 8 falling clock edges
occurring in the transmit cycle. Data is transmitted MSB first.
PC7 is taken high at the end of the write.

1

ADDITIONAL PINS OMITTED FOR CLARITY.

Rev. A | Page 20 of 28

MC68HC11

1

PC7

SCK

MOSI

Figure 43. 68HC11/68L11-to-AD5425 Interface

SYNC

SCLK

SDIN

AD5425

1

03161-043

Preliminary Technical Data AD5425

MICROWIRE-to-AD5425 Interface PIC16C6x/7x-to-AD5425

Figure 44 shows an interface between the DAC and any

MICROWIRE

™-compatible device. Serial data is shifted out on

the falling edge of the serial clock, SK, and is clocked into the
DAC input shift register on the rising edge of SK, which
corresponds to the falling edge of the DAC’s SCLK.

MICROWIRE

1

ADDITIONAL PINS OMITTED FOR CLARITY.

1

SK

SO

CS

Figure 44. MICROWIRE-to-AD5425 Interface

SYNC

SCLK

SDIN

AD5425

1

03161-044

The PIC16C6x/7x synchronous serial port (SSP) is configured
as an SPI master with the clock polarity bit (CKP) = 0. This is
done by writing to the synchronous serial port control register
(SSPCON) (see the PIC16/17 microcontroller user manual). In
this example, I/O Port RA1 is being used to provide a

SYNC

signal and enable the DAC serial port. This microcontroller
transfers eight bits of data during each serial transfer operation.
Figure 45 shows the connection diagram.

PIC16C6x/7x

1

ADDITIONAL PINS OMITTED FOR CLARITY.

1

RA1

Figure 45. PIC16C6x/7x-to-AD5425 Interface

SCLKSCK/RC3

SDINSDI/RC4

SYNC

AD5425

1

03161-045

Rev. A | Page 21 of 28

AD5425 Preliminary Technical Data

PCB LAYOUT AND POWER SUPPLY DECOUPLING

In any circuit where accuracy is important, careful consider­ation of the power supply and ground return layout helps to
ensure the rated performance. The printed circuit board on
which the AD5425 is mounted should be designed so that the
analog and digital sections are separated and confined to
certain areas of the board. If the DAC is in a system where
multiple devices require an AGND-to-DGND connection, the
connection should be made at one point only. The star ground
point should be established as close as possible to the device.

These DACs should have an ample supply bypassing of 10 µF in
parallel with 0.1 µF on the supply and located as close to the
package as possible—ideally up against the device. The 0.1 µF
capacitor should have low effective series resistance (ESR) and
effective series inductance (ESI), such as found in the common
ceramic types that provide a low impedance path to ground at
high frequencies, to handle transient currents due to internal
logic switching. Low ESR, 1 µF to 10 µF tantalum or electrolytic
capacitors should also be applied at the supplies to minimize
transient disturbance and to filter out low frequency ripple.

Fast switching signals such as clocks should be shielded with
digital ground to avoid radiating noise to other parts of the
board and should never be run near the reference inputs.

It is good practice to employ compact, minimum lead length
PCB layout design. Leads to the input should be as short as
possible to minimize IR drops and stray inductance.

The PCB metal traces between V
matched to minimize gain error. To maximize high frequency
performance, the I-to-V amplifier should be located as close to
the device as possible.

and RFB should also be

REF

EVALUATION BOARD

The board consists of an 8-bit AD5425 and a current-to-voltage
amplifier, the AD8065. Included on the evaluation board is a
10 V reference, the ADR01. An external reference can also be
applied via an SMB input.

The evaluation kit consists of a CD-ROM with self-installing
PC software to control the DAC. The software simply allows the
user to write a code to the device.

OPERATING THE EVALUATION BOARD

Power Supplies

The board requires ±12 V and 5 V supplies. The 12 V VDD and

are used to power the output amplifier, while the 5 V is used

V

SS

to power the DAC (V

) and transceivers (VCC).

DD1

Avoid crossover of digital and analog signals. Traces on opposite
sides of the board should run at right angles to each other. This
reduces the effects of feedthrough through the board. A
microstrip technique is by far the best, but not always possible
with a double-sided board. In this technique, the component
side of the board is dedicated to ground plane while signal
traces are placed on the solder side.

Both supplies are decoupled to their respective ground plane
with 10 µF tantalum and 0.1 µF ceramic capacitors.

Link1 (LK1) is provided to allow selection between the on­board reference (ADR01) or an external reference applied
through J2. Link2 should be connected to the

LDAC

position.

Rev. A | Page 22 of 28

Preliminary Technical Data AD5425

V

DD1

R1 = 0Ω

+

C2

C1

0.1µF

2

5

10µF

V

REF

+VINV

U2

ADR01AR

TRIM

GND

4

OUT

4.7pF

V

6

C5

REF

J2

U3

C5

0.1µF

LK1

V

SS

2

AD8065AR

3

V

DD

C7
10µF

+

C8

0.1µF

4

V–

6

7

V+

C9
10µF

+

C10

0.1µF

TP1

V

OUT

J1

P1–3

P1–2

P1–4

P1–5

P1–13

P1–19
P1–20
P1–21
P1–22
P1–23
P1–24
P1–25
P1–26
P1–27
P1–28
P1–29
P1–30

SCLK

SDIN

SYNC

LDAC

SDO

LK2

A
B

P2–3

P2–2

J3

J4

J5

J6

SCLK

SDIN

SYNC

SDO/LDAC

C11

0.1µF

C13

0.1µF

4

5

6

7

U1

SCLK

SDIN

SYNC

SDO/LDAC

AD5425/AD5426/

AD5432/AD5443

V

DD

+

C12
10µF

C14
10µF

AGND

+

8

V

DD

10

R

FB

1

1

I

OUT

2

2

I

OUT

3

GND

9

V

REF

V

DD

C3

10µFC40.1µF

P2–1

V

DD1

V

SS

P2–4

0.1µF

C15

+

C16
10µF

03161-046

Figure 46. Schematic of the AD5425 Evaluation Board

Rev. A | Page 23 of 28

AD5425 Preliminary Technical Data

EVAL–AD5425EB

03161-047

Figure 47. Component-Side Artwork

P1

SCLK

SDO

SDO/LDAC

LK2

LDAC

SDIN

SYNC

J3

J4

SDO/LDAC

J5

J6

SCLK

SDIN

SYNC

U1

C1
C2

C15

J2

C16

VDD1

U3

C8

VREF

C11

C6

R1

LK1

VREF

C10 C13

VDD

AGND

TP1

U2

C14C9

VSS

P2

J1
VOUT

C4

C3

03161-048

Figure 48. Silkscreen—Component-Side View ( Top Layer)

Rev. A | Page 24 of 28

Preliminary Technical Data AD5425

Figure 49. Solder-Side Artwork

03161-049

Rev. A | Page 25 of 28

AD5425 Preliminary Technical Data

Table 11. Overview of the AD54xx and AD55xx Devices

Part No. Resolution No. DACs INL (LSB) Interface Package Features

AD5424 8 1 ±0.25 Parallel RU-16, CP-20
AD5426 8 1 ±0.25 Serial RM-10 10 MHz BW, 50 MHz serial

AD5428 8 2 ±0.25 Parallel RU-20
AD5429 8 2 ±0.25 Serial RU-10 10 MHz BW, 50 MHz serial
AD5450 8 1 ±0.25 Serial RJ-8 10 MHz BW, 50 MHz serial
AD5432 10 1 ±0.5 Serial RM-10 10 MHz BW, 50 MHz serial
AD5433 10 1 ±0.5 Parallel RU-20, CP-20
AD5439 10 2 ±0.5 Serial RU-16 10 MHz BW, 50 MHz serial
AD5440 10 2 ±0.5 Parallel RU-24
AD5451 10 1 ±0.25 Serial RJ-8 10 MHz BW, 50 MHz serial
AD5443 12 1 ±1 Serial RM-10 10 MHz BW, 50 MHz serial
AD5444 12 1 ±0.5 Serial RM-8 10 MHz BW, 50 MHz serial interface

AD5415 12 2 ±1 Serial RU-24 10 MHz BW, 50 MHz serial
AD5405 12 2 ±1 Parallel CP-40

AD5445 12 2 ±1 Parallel RU-20, CP-20
AD5447 12 2 ±1 Parallel RU-24
AD5449 12 2 ±1 Serial RU-16 10 MHz BW, 50 MHz serial

AD5452 12 1 ±0.5 Serial RJ-8, RM-8 10 MHz BW, 50 MHz serial
AD5446 14 1 ±1 Serial RM-8 10 MHz BW, 50 MHz serial
AD5453 14 1 ±2 Serial UJ-8, RM-8 10 MHz BW, 50 MHz serial
AD5553 14 1 ±1 Serial RM-8 4 MHz BW, 50 MHz serial clock
AD5556 14 1 ±1 Parallel RU-28

AD5555 14 2 ±1 Serial RM-8 4 MHz BW, 50 MHz serial clock
AD5557 14 2 ±1 Parallel RU-38

AD5543 16 1 ±2 Serial RM-8 4 MHz BW, 50 MHz serial clock
AD5546 16 1 ±2 Parallel RU-28
AD5545 16 2 ±2 Serial RU-16 4 MHz BW, 50 MHz serial clock
AD5547 16 2 ±2 Parallel RU-38

10 MHz BW, 17 ns

10 MHz BW, 17 ns

10 MHz BW, 17 ns

10 MHz BW, 17 ns

10 MHz BW, 17 ns
10 MHz BW, 17 ns
10 MHz BW, 17 ns

4 MHz BW, 20 ns

4 MHz BW, 20 ns

4 MHz BW, 20 ns

4 MHz BW, 20 ns

CS pulse width

CS pulse width

CS pulse width

CS pulse width

CS pulse width
CS pulse width
CS pulse width

WR pulse width

WR pulse width

WR pulse width

WR pulse width

Rev. A | Page 26 of 28

Preliminary Technical Data AD5425

OUTLINE DIMENSIONS

3.00 BSC

6

10

3.00 BSC

1

PIN 1

0.50 BSC

0.95

0.85

0.75

0.15

0.00

0.27

0.17

COPLANARITY

0.10
COMPLIANT TO JEDEC STANDARDS MO-187BA

Figure 50. 10-Lead Mini Small Outline Package [MSOP]

4.90 BSC

5

1.10 MAX

SEATING
PLANE

0.23

0.08

8°
0°

(RM-10)

Dimensions shown in millimeters

0.80

0.60

0.40

ORDERING GUIDE

Resolution

Model

(Bits)

AD5425YRM 8 ±0.25 −40°C to +125°C MSOP D1P RM-10
AD5425YRM-REEL 8 ±0.25 −40°C to +125°C MSOP D1P RM-10
AD5425YRM-REEL7 8 ±0.25 −40°C to +125°C MSOP D1P RM-10
EVAL-AD5425EB Evaluation Kit

INL
(LSBs) Temperature Range

Package
Description Branding

Package
Option

Rev. A | Page 27 of 28

AD5425 Preliminary Technical Data

NOTES

© 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered
trademarks are the property of their respective owners.
D03161-0-3/05(A)

Rev. A | Page 28 of 28