Datasheet AD5420 Datasheet (ANALOG DEVICES)

Single-Channel, 12-/16-Bit, Serial Input,

R

FEATURES

12-/16-bit resolution and monotonicity
Current output ranges: 4 mA to 20 mA, 0 mA to 20 mA, or

0 mA to 24 mA
±0.01% FSR typical total unadjusted error (TUE)

±3 ppm/°C typical output drift
Flexible serial digital interface
On-chip output fault detection
On-chip reference (10 ppm/°C maximum)
Asynchronous clear function
Power supply (AV

10.8 V to 40 V; AD5410AREZ/AD5420AREZ

10.8 V to 60 V; AD5410ACPZ/AD5420ACPZ
Output loop compliance to AV
Temperature range: −40°C to +85°C
24-lead TSSOP and 40-Lead LFCSP packages

APPLICATIONS

Process control
Actuator control
PLC

) range

DD

− 2.5 V

DD

4 mA to 20 mA, Current Source DAC

AD5410/AD5420

GENERAL DESCRIPTION

The AD5410/AD5420 are low cost, precision, fully integrated
12-/16-bit converters offering a programmable current source
output designed to meet the requirements of industrial process
control applications. The output current range is programmable
at 4 mA to 20 mA, 0 mA to 20 mA, or an overrange function of
0 mA to 24 mA. The output is open-circuit protected. The
device operates with a power supply (AV
to 60 V. Output loop compliance is 0 V to AV

The flexible serial interface is SPI, MICROWIRE™, QSPI™, and
DSP compatible and can be operated in 3-wire mode to
minimize the digital isolation required in isolated applications.

The device also includes a power-on reset function, ensuring
that the device powers up in a known state, and an asynchronous
CLEAR pin that sets the output to the low end of the selected
current range.

The total unadjusted error is typically ±0.01% FSR.

) range from 10.8 V

DD

− 2.5 V.

DD

FUNCTIONAL BLOCK DIAGRAM

DV

CC

SELECT

DV

CC

CAP1

CAP2

AD5410/AD5420

CLEA

LATCH

SCLK

SDIN

SDO

INPUT SHIFT

REGISTER

AND CONTROL

LOGIC

POWER-

ON

RESET

12/16

VREF

12-/16-BIT

DAC

REFIN

Figure 1.

R2 R3

R

SET

AV

DD

R3

SENSE

BOOST

I

OUT

FAULT

R

SET

GNDREFOUT

07027-001

Rev. B

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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2009—2010 Analog Devices, Inc. All rights reserved.

AD5410/AD5420

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

General Description ......................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

AC Performance Characteristics ................................................ 5

Timing Characteristics ................................................................ 5

Absolute Maximum Ratings ............................................................ 7

ESD Caution .................................................................................. 7

Pin Configuration and Function Descriptions ............................. 8

Typical Performance Characteristics ........................................... 10

Terminolog y .................................................................................... 15

Theory of Operation ...................................................................... 16

Architecture ................................................................................. 16

Serial Interface ............................................................................ 16

Power-On State ........................................................................... 18

Transfer Function ....................................................................... 18

Data Register ............................................................................... 18

Control Register .......................................................................... 18

Reset Register .............................................................................. 19

Status Register ............................................................................. 19

AD5410/AD5420 Features ............................................................ 20

Fault Alert .................................................................................... 20

Asynchronous Clear (CLEAR) ................................................. 20

Internal Reference ...................................................................... 20

External Current Setting Resistor ............................................ 20

Digital Power Supply .................................................................. 20

External Boost Function ........................................................... 20

Digital Slew Rate Control .......................................................... 21

I

Filtering Capacitors ............................................................ 22

OUT

Feedback/Monitoring of Output Current ............................... 23

Applications Information .............................................................. 25

Driving Inductive Loads ............................................................ 25

Transient Voltage Protection .................................................... 25

Layout Guidelines....................................................................... 25

Galvanically Isolated Interface ................................................. 25

Microprocessor Interfacing ....................................................... 26

Thermal and Supply Considerations ....................................... 26

Industrial Analog Output Application .................................... 27

Outline Dimensions ....................................................................... 28

Ordering Guide .......................................................................... 28

REVISION HISTORY

2/10—Rev. A to Rev. B

Changes to Figure 46 ..................................................................... 23

8/09—Rev. 0 to Rev. A

Changes to Features and General Description ............................ 1

Changes to Table 1 ............................................................................ 3

Changes to Table 2 ............................................................................ 5

Changes to Introduction to Table 4 and to Table 4 ...................... 7

Added Figure 6, Changes to Figure 5 and Table 5 ........................ 8

Added Feedback/Monitoring of Output Current Section,
Including Figure 45 to Figure 47; Renumbered Subsequent

Figures .............................................................................................. 23

Changes to Thermal and Supply Considerations Section and

Table 21 ............................................................................................ 26

Updated Outline Dimensions ....................................................... 28

Changes to Ordering Guide .......................................................... 28

3/09—Revision 0: Initial Version

Rev. B | Page 2 of 28

AD5410/AD5420

SPECIFICATIONS

AVDD = 10.8 V to 26.4 V, GND = 0 V, REFIN = 5 V external; DVCC = 2.7 V to 5.5 V, R
unless otherwise noted.

Table 1.

Parameter1 Min Typ Max Unit Test Conditions/Comments

OUTPUT CURRENT RANGES 0 24 mA

0 20 mA
4 20 mA

ACCURACY, INTERNAL R

Resolution 16 Bits AD5420
12 Bits AD5410
Total Unadjusted Error (TUE) −0.3 +0.3 % FSR AD5420

−0.13 ±0.08 +0.13 % FSR AD5420, TA = 25°C

−0.5 +0.5 % FSR AD5410

−0.3 ±0.15 +0.3 % FSR AD5410, TA = 25°C

Relative Accuracy (INL)2 −0.024 +0.024 % FSR AD5420

−0.032 +0.032 % FSR AD5410

Differential Nonlinearity (DNL) −1 +1 LSB Guaranteed monotonic
Offset Error −0.27 +0.27 % FSR

−0.12 ±0.08 +0.12 % FSR TA = 25°C

Offset Error Temperature Coefficient (TC)3 ±16 ppm FSR/°C
Gain Error −0.18 +0.18 % FSR AD5420

−0.03 ±0.006 +0.03 % FSR AD5420, TA = 25°C

−0.22 +0.22 AD5410

−0.06 ±0.012 +0.06 AD5410, TA = 25°C

Gain Error Temperature Coefficient (TC)3
Full-Scale Error −0.2 +0.2 % FSR

−0.1 ±0.08 +0.1 % FSR TA = 25°C

Full-Scale Error Temperature Coefficient (TC)3

ACCURACY, EXTERNAL R

Resolution 16 Bits AD5420
12 Bits AD5410
Total Unadjusted Error (TUE) −0.15 +0.15 % FSR AD5420

−0.06 ±0.01 +0.06 % FSR AD5420, TA = 25°C

−0.3 +0.3 % FSR AD5410

−0.1 ±0.02 +0.1 % FSR

Relative Accuracy (INL)2

−0.032 +0.032 % FSR AD5410

Differential Nonlinearity (DNL) −1 +1 LSB Guaranteed monotonic
Offset Error −0.1 +0.1 % FSR

−0.03 ±0.006 +0.03 % FSR TA = 25°C

Offset Error Temperature Coefficient (TC)3
Gain Error −0.08 +0.08 % FSR

−0.05 ±0.003 +0.05 % FSR TA = 25°C

Gain Error Temperature Coefficient (TC)3
Full-Scale Error −0.15 +0.15 % FSR

−0.06 ±0.01 +0.06 % FSR TA = 25°C

Full-Scale Error Temperature Coefficient (TC)3

OUTPUT CHARACTERISTICS3

Current Loop Compliance Voltage 0 AVDD − 2.5 V
Output Current Drift vs. Time 50 ppm FSR Internal R
20 ppm FSR External R
Resistive Load 1200 Ω
Inductive Load 50 mH TA = 25°C
DC Power Supply Rejection Ratio (PSRR) 1 μA/V

SET

±10 ppm FSR/°C

±12 ppm FSR/°C

Assumes an ideal 15 kΩ resistor

SET

−0.012 +0.012 % FSR AD5420

±3 ppm FSR/°C

±4 ppm FSR/°C

±7 ppm FSR/°C

Rev. B | Page 3 of 28

= 300 Ω; all specifications T

LOAD

AD5410, T

A

SET

SET

MIN

to T

MAX

,

= 25°C

, drift after 1000 hours at 125°C

, drift after 1000 hours at 125°C

AD5410/AD5420

Parameter1 Min Typ Max Unit Test Conditions/Comments

Output Impedance 50 MΩ
Output Current Leakage 60 pA Output disabled
R3 Resistor Value 36 40 44 Ω TA = 25°C
R3 Resistor Temperature Coefficient (TC) 30 ppm/°C
I

Current 399 444 489 μA

BIAS

I

Current Temperature Coefficient (TC) 30 ppm/°C

BIAS

REFERENCE INPUT/OUTPUT

Reference Input3

Reference Input Voltage 4.95 5 5.05 V For specified performance
DC Input Impedance 25 30 kΩ

Reference Output

Output Voltage 4.995 5.000 5.005 V TA = 25°C
Reference TC

3, 4

Output Noise (0.1 Hz to 10 Hz)3
Noise Spectral Density3
Output Voltage Drift vs. Time3
Capacitive Load3
Load Current3
Short-Circuit Current3
Load Regulation3

DIGITAL INPUTS3

Input High Voltage, VIH 2 V
Input Low Voltage, VIL 0.8 V
Input Current −1 +1 μA Per pin
Pin Capacitance 10 pF Per pin

DIGITAL OUTPUTS3

SDO

Output Low Voltage, VOL 0.4 V Sinking 200 μA
Output High Voltage, VOH DVCC − 0.5 V Sourcing 200 μA
High Impedance Leakage Current −1 +1 μA
High Impedance Output Capacitance 5 pF

FAULT

Output Low Voltage, VOL 0.4 V 10 kΩ pull-up resistor to DVCC
Output Low Voltage, VOL 0.6 V 2.5 mA load current
Output High Voltage, VOH 3.6 V 10 kΩ pull-up resistor to DVCC

POWER REQUIREMENTS

AVDD 10.8 40 V TSSOP package

10.8 60 V LFCSP package
DVCC

Input Voltage 2.7 5.5 V Internal supply disabled
Output Voltage 4.5 V DVCC can be overdriven up to 5.5 V
Output Load Current3
Short-Circuit Current3

AIDD 3 mA Output disabled
4 mA Output enabled
DICC 1 mA VIH = DVCC, VIL = GND
Power Dissipation 144 mW AVDD = 40 V, I
50 mW AVDD = 15 V, I

1

Temperature range: −40°C to +85°C; typical at +25°C.

2

For 0 mA to 20 mA and 0 mA to 24 mA ranges, INL is measured from Code 256 for the AD5420 and Code 16 for the AD5410.

3

Guaranteed by design and characterization but not production tested.

4

The on-chip reference is production trimmed and tested at 25°C and 85°C. It is characterized from −40°C to +85°C.

1.8 10 ppm/°C
18 μV p-p
100 nV/√Hz @ 10 kHz
50 ppm Drift after 1000 hours, T
600 nF
5 mA
7 mA
95 ppm/mA
JEDEC compliant

5 mA
20 mA

= 0 mA

OUT

= 0 mA

OUT

= 125°C

A

Rev. B | Page 4 of 28

AD5410/AD5420

AC PERFORMANCE CHARACTERISTICS

AVDD = 10.8 V to 26.4 V, GND = 0 V, REFIN = 5 V external; DVCC = 2.7 V to 5.5 V, R
otherwise noted.

Table 2.

Parameter1 Min Typ Max Unit Test Conditions/Comments

DYNAMIC PERFORMANCE

Output Current Settling Time2 10 μs 16 mA step, to 0.1% FSR

40 μs 16 mA step, to 0.1% FSR, L = 1 mH

AC PSRR −75 dB 200 mV, 50 Hz/60 Hz sine wave superimposed on power supply voltage

1

Guaranteed by design and characterization; not production tested.

2

Digital slew rate control feature disabled and CAP1 = CAP2 = open circuit.

TIMING CHARACTERISTICS

AVDD = 10.8 V to 26.4 V, GND = 0 V, REFIN = 5 V external; DVCC = 2.7 V to 5.5 V, R
otherwise noted.

Table 3.

Parameter

WRITE MODE

t1 33 ns min SCLK cycle time
t2 13 ns min SCLK low time
t3 13 ns min SCLK high time
t4 13 ns min LATCH delay time
t5 40 ns min LATCH high time
t5 5 μs min LATCH high time after a write to the control register
t6 5 ns min Data setup time
t7 5 ns min Data hold time
t8 40 ns min LATCH low time
t9 20 ns min CLEAR pulse width
t10 5 μs max CLEAR activation time

READBACK MODE

t11 90 ns min SCLK cycle time
t12 40 ns min SCLK low time
t13 40 ns min SCLK high time
t14 13 ns min LATCH delay time
t15 40 ns min LATCH high time
t16 5 ns min Data setup time
t17 5 ns min Data hold time
t18 40 ns min LATCH low time
t19 35 ns max Serial output delay time (C
t20 35 ns max LATCH rising edge to SDO tristate

DAISY-CHAIN MODE

t21 90 ns min SCLK cycle time
t22 40 ns min SCLK low time
t23 40 ns min SCLK high time
t24 13 ns min LATCH delay time
t25 40 ns min LATCH high time
t26 5 ns min Data setup time
t27 5 ns min Data hold time
t28 40 ns min LATCH low time
t29 35 ns max Serial output delay time (C

1

Guaranteed by characterization but not production tested.

2

All input signals are specified with tR = tF = 5 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V.

3

See Figure 2, Figure 3, and Figure 4.

4

C

LSDO

1, 2, 3

Limit at T

= capacitive load on SDO output.

, T

Unit Description

MIN

MAX

= 300 Ω; all specifications T

LOAD

= 300 Ω; all specifications T

LOAD

= 50 pF)4

L SDO

= 50 pF)4

L SDO

MIN

MIN

to T

to T

MAX

MAX

, unless

, unless

Rev. B | Page 5 of 28

AD5410/AD5420

SCLK

t

2

LATCH

t

7

t

9

t

10

SDIN

CLEAR

I

OUT

t

DB23

6

t

1

2421

t

3

DB0

t

t

4

5

t

8

07027-002

Figure 2. Write Mode Timing Diagram

t

11

SCLK

2421

t

12

t

13

t

t

14

15

2

1

923

8

22

24

LATCH

t

18

DB0DB23

DB23

FIRST 8 BITS ARE
DON’T CARE BITS

NOP CONDITION

DB15XXXX

t

19

SELECTED REGISTER
DATA CLOCKED OUT

DB0

DB0

t

20

07027-003

SDIN

SDO

t

16

INPUT WORD SPECIFIES
REGISTE R T O BE READ

UNDEFINED DATA

t

17

Figure 3. Readback Mode Timing Diagram

t

21

DB0

DB0

4826

t

t

24

25

t

28

07027-004

SCLK

LATCH

SDIN

SDO

DB23

DB23

INPUT WORD FOR DAC N

UNDEFINED

t

DB0

29

DB0

25

2421

t

t

26

DB23

INPUT W ORD FOR DAC N – 1

DB23

INPUT WORD FOR DAC N

22

t

23

t

27

Figure 4. Daisy-Chain Mode Timing Diagram

Rev. B | Page 6 of 28

AD5410/AD5420

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted. Transient currents of up to
80 mA do not cause SCR latch-up.

Table 4.

Parameter Rating

AVDD to GND −0.3 V to +60 V
DVCC to GND −0.3 V to +7 V
Digital Inputs to GND

Digital Outputs to GND

REFIN, REFOUT to GND −0.3 V to +7 V
I

to GND −0.3 V to AVDD

OUT

Operating Temperature Range

Industrial −40°C to +85°C1
Storage Temperature Range −65°C to +150°C
Junction Temperature (TJ max) 125°C
24-Lead TSSOP Package

Thermal Impedance, θJA 42°C/W

Thermal Impedance, θJC 9°C/W
40-Lead LFCSP Package

Thermal Impedance, θJA 28°C/W

Thermal Impedance, θJC 4°C/W
Power Dissipation (TJ max − TA)/θJA
Lead Temperature JEDEC industry standard

Soldering J-STD-020
ESD (Human Body Model) 2 kV

1

Power dissipated on chip must be derated to keep junction temperature

below 125°C. The assumption is that the maximum power dissipation
condition is sourcing 24 mA into ground from AVDD with a 4 mA on-chip
current.

−0.3 V to DV
(whichever is less)

−0.3 V to DV
(whichever is less)

+ 0.3 V or +7 V

CC

+ 0.3 V or +7 V

CC

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. B | Page 7 of 28

AD5410/AD5420

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

GND

2

DV

CC

3

FAULT

4

GND

GND
CLEAR
LATCH

SCLK

SDIN

SDO
GND
GND

NOTES

1. NC = NO CONNEC T.

2. GROUND REF E RE NCE CONNECTION. IT IS RECOMMENDED THAT THE
EXPOSED PAD BE THERMALLY CONNECTED TO A COPPER PLANE FOR
ENHANCED THERMAL PERFORMANCE.

AD5410/

AD5420

5

TOP VIEW

6

(Not to Scale)

7
8

9

10
11

12

Figure 5. TSSOP Pin Configuration

24

23

22

21

20

19

18

17

16

15

14

13

AV

DD

NC
CAP2
CAP1
BOOST
I

OUT

R3

SENSE

NC
DV

CC

REFIN
REFOUT
R

SET

SELECT

FAULT

NOTES

1. NC = NO CONNECT.

2. GROUND REFE RE NCE CONNECTION. IT IS RECO MMENDED THAT THE
EXPOSED PAD BE THERMALLY CONNECTED TO A COPPER PLANE FOR

07027-005

ENHANCED THERMAL PE RFORMANCE.

CC

DD

NC
40

PIN 1

1NC

INDICATOR

2
3GND
4GND

AD5410/AD5420

5CLEAR
6LATCH
7SCLK
8SDIN
9SDO

10NC

1

1
NC

GND

NC

DV

37

38

39

TOP VIEW

(Not to Scale)

12

13

14

GND

GND

GND

C
N

NC

NC

NC

AV

NC
32

31

33

34

35

36

18

19

20

15

17

16

C

NC

N

SET

GND

R

REFIN

REFOUT

Figure 6. LFCSP Pin Configuration

30 NC
29 CAP2
28 CAP1
27 BOOST

I

26

OUT

25

R3

SENSE

24

NC

23 DV

CC

22

NC

21 NC

SELECT

07027-053

Table 5. Pin Function Descriptions

TSSOP Pin No. LFCSP Pin No. Mnemonic Description

1, 4, 5, 12 3, 4, 14, 15, 37 GND These pins must be connected to ground.
2 39 DVCC Digital Supply Pin. Voltage ranges from 2.7 V to 5.5 V.
3 2

Fault Alert. This pin is asserted low when an open circuit is detected between I

FAU LT

GND or an overtemperature is detected. The FAULT pin is an open-drain output and
must be connected to DV

6 5 CLEAR

Active High Input. Asserting this pin sets the output current to the zero-scale value,

through a pull-up resistor (typically 10 kΩ).

CC

which is either 0 mA or 4 mA, depending on the output range programmed, that is, 0 mA
to 20 mA, 0 mA to 24 mA, or 4 mA to 20 mA.

7 6 LATCH

Positive Edge Sensitive Latch. A rising edge parallel loads the input shift register data
into the relevant register. In the case of the data register, the output current is also
updated.

8 7 SCLK

Serial Clock Input. Data is clocked into the input shift register on the rising edge of

SCLK. This operates at clock speeds of up to 30 MHz.
9 8 SDIN Serial Data Input. Data must be valid on the rising edge of SCLK.
10 9 SDO

Serial Data Output. This pin is used to clock data from the device in daisy-chain or

readback mode. Data is clocked out on the falling edge of SCLK. See Figure 3 and

Figure 4.
11 12, 13 GND Ground Reference Pin.
13 16 R

SET

An external, precision, low drift 15 kΩ current setting resistor can be connected to this

pin to improve the overall performance of the device. See the Specifications and

AD5410/AD5420 Features sections.
14 17 REFOUT

Internal Reference Voltage Output. V

= 5 V ± 5 mV at TA = 25°C. Typical temperature

REFOUT

drift is 1.8 ppm/°C.
15 18 REFIN External Reference Voltage Input. V
16 23

DV

CC

SELECT

This pin, when connected to GND, disables the internal supply, and an external supply

must be connected to the DV

CC

= 5 V ± 50 mV for specified performance.

REFIN

pin. Leave this pin unconnected to enable the internal

supply. See the AD5410/AD5420 Features section.
17, 23

1, 10, 11, 19, 20,

NC Do not connect to these pins.
21, 22, 24, 30,
31, 32, 33, 34,
35, 38, 40

OUT

and

Rev. B | Page 8 of 28

AD5410/AD5420

TSSOP Pin No. LFCSP Pin No. Mnemonic Description

18 25 R3

19 26 I
20 27 BOOST

21 28 CAP1

22 29 CAP2

24 36 AVDD Positive Analog Supply Pin. Voltage ranges from 10.8 V to 40 V.
25 (EPAD) 41 (EPAD)

SENSE

The voltage measured between this pin and the BOOST pin is directly proportional to
the output current and can be used as a monitor/feedback feature. This should be used
as a voltage sense output only; current should not be sourced from this pin. See the
AD5410/AD5420 Features section.

Current Output Pin.

OUT

Optional External Transistor Connection. Connecting an external transistor reduces the
power dissipated in the AD5410/AD5420. See the AD5410/AD5420 Features section.

Connection for Optional Output Filtering Capacitor. See the AD5410/AD5420 Features
section.

Connection for Optional Output Filtering Capacitor. See the AD5410/AD5420 Features
section.

Exposed
pad

Ground Reference Connection. It is recommended that the exposed pad be thermally
connected to a copper plane for enhanced thermal performance.

Rev. B | Page 9 of 28

AD5410/AD5420

TYPICAL PERFORMANCE CHARACTERISTICS

0.004

0.002

–0.002

EXTERNAL R
INTERNAL R
EXTERNAL R
INTERNAL R

0

SET

SET

, BOOST TRANSISTOR

SET

, BOOST TRANSISTOR

SET

0.004

0.002

–0.002

= 24V

AV

DD

0mA TO 24mA RANGE

0

–0.004

INL ERROR (% FSR)

–0.006

–0.008

–0.010

AVDD = 2.4V

= 25°C

T

A

= 250Ω

R

LOAD

0 10,000 20,000 30,000 40,000 50,000 60,000

CODE

Figure 7. Integral Nonlinearity Error vs. Code

1.0
AVDD = 2.4V

T

= 25°C

0.8

A

R

= 250Ω

LOAD

0.6

0.4

0.2

0

–0.2

DNL ERROR (LSB)

–0.4

–0.6

–0.8

–1.0

EXTERNAL R
INTERNAL R
EXTERNAL R
INTERNAL R

0 10,000 20,000 30,000 40,000 50,000 60,000

SET

SET

, BOOST TRANSISTOR

SET

, BOOST TRANSISTOR

SET

CODE

Figure 8. Differential Nonlinearity Error vs. Code

0.05

0.03

0.01

–0.01

–0.03

–0.05

AVDD = 24V
T

= 25°C

A

–0.07

R

= 250Ω

LOAD

–0.09

–0.11

TOTAL UNADJUSTED ERROR (% FS R)

–0.13

–0.15

EXTERNAL R
INTERNAL R
EXTERNAL R
INTERNAL R

0 10,000 20,000 30,000 40,000 50,000 60,000

SET

SET

, BOOST TRANSISTOR

SET

, BOOST TRANSISTO R

SET

CODE

Figure 9. Total Unadjusted Error vs. Code

–0.004

INL ERROR (% FSR)

–0.006

–0.008

07027-006

–0.010

–40 –20 0 20 40 60 80

TEMPERATURE (°C)

Figure 10. Integral Nonlinearity Error vs. Temperature, Internal R

0.003

0.002

0.001

0

–0.001

INL ERROR (% FSR)

–0.002

07027-007

–0.003

–40 –20 0 20 40 60 80

= 24V

AV

DD

0mA TO 24mA RANGE

TEMPERATURE (°C)

Figure 11. Integral Nonlinearity Error vs. Temperature, External R

1.0
AVDD = 24V
ALL RANGES

0.8
INTERNAL AND EXTERNAL R

0.6

0.4

0.2

0

–0.2

DNL ERROR (LSB)

–0.4

–0.6

–0.8

07027-008

–1.0

–40 –20 0 20 40 60 80

TEMPERATURE (°C)

SET

07027-009

SET

07027-109

SET

07027-010

Figure 12. Differential Nonlinearity Error vs. Temperature

Rev. B | Page 10 of 28

AD5410/AD5420

R

0.10

0.05

0

–0.05

–0.10

–0.15

–0.20

TOTAL UNADJUST E D ERROR (%FSR)

–0.25

–40 –20 0 20 40 60 80

AVDD = 24V

4mA TO 20mA INTERNAL R
0mA TO 20mA INTERNAL R
0mA TO 24mA INTERNAL R
4mA TO 20mA EXTERNAL R
0mA TO 20mA EXTERNAL R
0mA TO 24mA EXTERNAL R

TEMPERATURE (°C)

SET
SET
SET

SET
SET
SET

Figure 13. Total Unadjusted Error vs. Temperature

0.10

0.05

0

–0.05

–0.10

–0.15

OFFSET ERROR (% FSR)

–0.20

–0.25

–40–20 0 20406080

AVDD = 24V

4mA TO 20mA INTERNAL R
0mA TO 20mA INTERNAL R
0mA TO 24mA INTERNAL R
4mA TO 20mA EXTERNAL R
0mA TO 20mA EXTERNAL R
0mA TO 24mA EXTERNAL R

TEMPERATURE (°C)

SET
SET
SET

SET
SET
SET

Figure 14. Offset Error vs. Temperature

0.06

0.04

0.02

0

–0.02

–0.04

GAIN ERROR (% F S R)

–0.06

–0.08

–0.10

–40–20 0 20406080

AVDD = 24V

4mA TO 20mA INTE RNAL R
0mA TO 20mA INTE RNAL R
0mA TO 24mA INTE RNAL R
4mA TO 20mA EXTE RNAL R
0mA TO 20mA EXTE RNAL R
0mA TO 24mA EXTE RNAL R

TEMPERATURE (°C)

Figure 15. Gain Error vs. Temperature

07027-013

07027-017

SET
SET
SET

SET
SET
SET

07027-018

0.015
TA = 25°C
0mA TO 24mA RANGE

0.010

0.005

0

–0.005

INL ERROR (% F S R)

–0.010

–0.015

10 15 20 25 30 35 40

AVDD (V)

Figure 16. Integral Nonlinearity Error vs. AVDD, External R

0.020

–0.005

INL ERROR (%F S R)

–0.010

–0.015

–0.020

0.015

0.010

0.005

TA = 25°C
0mA TO 24mA RANGE

0

10 15 20 25 30 35 40

AVDD (V)

Figure 17. Integral Nonlinearity Error vs. AVDD, Internal R

1.0
TA = 25°C

0.8
0mA TO 24mA RANGE

0.6

0.4

0.2

(LSB)

0

–0.2

DNL ERRO

–0.4

–0.6

–0.8

–1.0

10 15 20 25 30 35 40

AVDD(V)

Figure 18. Differential Nonlinearity Error vs. AVDD, External R

07027-011

SET

07027-014

SET

07027-012

SET

Rev. B | Page 11 of 28

AD5410/AD5420

R

%

R
A

1.0

0.8
TA = 25°C

0.6

0mA TO 24mA RANGE

0.4

0.2

0

–0.2

DNL ERROR (LSB)

–0.4

–0.6

–0.8

–1.0

10 15 20 25 30 35 40

Figure 19. Differential Nonlinearity Error vs. AVDD, Internal R

0.025
TA = 25°C

0mA TO 24mA RANGE

0

10 15 20 25 30 35 40

–0.005

TOTAL UNADJUS TED ERROR (% FSR)

–0.010

–0.015

0.020

0.015

0.010

0.005

Figure 20. Total Unadjusted Error vs. AVDD, External R

0.05

0.03

0.01

FSR)
(

–0.01

–0.03

TA = 25°C
0mA TO 24mA RANGE

10 15 20 25 30 35 40

TOTAL UNADJUS TED ERRO

–0.05

–0.07

–0.09

–0.11

–0.13

–0.15

Figure 21. Total Unadjusted Error vs. AVDD, Internal R

AVDD (V)

AVDD (V)

AVDD(V)

2.5
AVDD = 15V

I

= 24mA

OUT

R

= 500Ω

LOAD

2.0

1.5

1.0

HEADROOM VOLTAGE (V)

0.5

07027-015

SET

07027-016

SET

07027-032

SET

0

–40–20 0 2040 6080

TEMPERATURE (°C)

Figure 22. Compliance Voltage Headroom vs. Temperature

3.5
AVDD = 24V

T

3.0

2.5

)

2.0

ENT (µ

1.5

1.0

OUTPUT CUR

0.5

0

0 100 200 300 400 500 600

R

A
LOAD

= 25°C

= 250Ω

TIME (µs)

Figure 23. Output Current vs. Time on Power-Up

20

10

AVDD = 24V

0

T

= 25°C

A

R

= 250Ω

–10

–20

–30

OUTPUT CURRENT ( µ A)

–40

–50

LOAD

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

TIME (µs)

Figure 24. Output Current vs. Time on Output Enable

07027-019

07027-020

07027-021

Rev. B | Page 12 of 28

AD5410/AD5420

A

m

A

V

900

TA = 25°C

800

700

600

500

(µA)

CC

400

DI

300

200

100

DVCC = 5V

= 3V

DV

CC

0

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

LOGIC VOLTAGE (V)

Figure 25. DICC vs. Logic Input Voltage

5.0
TA = 25°C

4.5

I

= 0mA

OUT

4.0

3.5

3.0

)
(

2.5

DD

I

2.0

1.5

1.0

0.5

0

10 15 20 25 30 35 40

AVDD (V)

Figure 26. AIDD vs. AVDD

9

TA = 25°C

8

7

6

OLTAGE (V)

5

4

OUTPUT

3

CC

DV

2

1

0

–21 –19 –17 –15 –13 –11 –9 –7 –5 –3 –1 1

LOAD CURRENT (mA)

Figure 27. DVCC Output Voltage vs. Load Current

3

1

07027-022

07027-023

CH1 2.00V

CH3 5.00V

1

CH1 2µV M2.00s LINE 1.8V

Figure 29. Reference Noise (0.1 Hz to 10 Hz Bandwidth)

1

07027-024

CH1 20µV M2.00s LINE 0V

Figure 30. Reference Noise (100 kHz Bandwidth)

AV

DD

REFERE NC E OUTP UT

M200µs CH3 2.1V

Figure 28. Reference Turn-on Transient

07027-025

07027-026

07027-027

Rev. B | Page 13 of 28

AD5410/AD5420

%

70

60

50

40

30

20

LEAKAGE CURRENT (pA)

5.003

5.002

TA = 25°C

= 40V

AV

10

–10

DD

OUTPUT DIS ABLED

0

0 5 10 15 20 25 30 35 40 45

COMPLIANCE VO LTAGE (V)

Figure 31. Output Leakage Current vs. Compliance Voltage

50 DEVICES SHO WN
AV

= 24V

DD

5.0005

5.0000

4.9995

4.9990

4.9985

4.9980

4.9975

4.9970

4.9965

REFERENCE OUT P UT VOLTAGE (V)

4.9960

07027-028

4.9955
0123456789

LOAD CURRENT (mA)

TA = 25°C
AV

= 24V

DD

07027-031

Figure 34. Reference Output Voltage vs. Load Current

30

20

AVDD = 24V
T

= 25°C

A

R

= 250Ω

LOAD

0x8000 TO 0x7FFF
0x7FFF TO 0x8000

5.001

5.000

4.999

4.998

REFERENCE OUTPUT VOLTAGE (V)

4.997
–40 –20 0 20

TEMPERATURE ( °C)

40 60 80

Figure 32. Reference Output Voltage vs. Temperature

45

40

35

)

30

25

20

POPULATION (

15

10

5

0

10 2345678910

AVDD = 24V

TEMPERATURE CO EFFICIENT ( p p m/ ° C)

Figure 33. Reference Temperature Coefficient Histogram

10

0

–10

OUTPUT CURRENT ( µ A)

–20

07027-029

–30

02468101214161820

TIME (µs)

07027-049

Figure 35. Digital-to-Analog Glitch

25

TA = 25°C
AV
R

DD

LOAD

= 24V

= 300Ω

07027-134

TIME (µs)

20

15

10

OUTPUT CURRENT (mA)

5

07027-030

0

–1012345678

Figure 36. 4 mA to 20 mA Output Current Step

Rev. B | Page 14 of 28

AD5410/AD5420

TERMINOLOGY

Relative Accuracy or Integral Nonlinearity (INL)

For the DAC, relative accuracy, or integral nonlinearity (INL), is
a measure of the maximum deviation, in % FSR, from a straight
line passing through the endpoints of the DAC transfer
function. A typical INL vs. code plot is shown in Figure 7.

Differential Nonlinearity (DNL)

Differential nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A specified differential nonlinearity of ±1 LSB
maximum ensures monotonicity. This DAC is guaranteed
monotonic by design. A typical DNL vs. code plot can be seen
in Figure 8.

Tot a l U n ad ju s te d E rr o r ( TU E )

Total unadjusted error (TUE) is a measure of the output error
taking all the various errors into account, namely INL error,
offset error, gain error, and output drift over supplies and
temperature. TUE is expressed in % FSR. A typical TUE vs.
code plot can be seen in Figure 9.

Monotonicity

A DAC is monotonic if the output either increases or remains
constant for increasing digital input code. The AD5410/AD5420
are monotonic over their full operating temperature range.

Full-Scale Error

Full-scale error is a measure of the output error when full-scale
code is loaded to the data register. Ideally, the output should be
full-scale − 1 LSB. Full-scale error is expressed as a percentage
of the full-scale range (% FSR).

Full-Scale Error Temperature Coefficient (TC)

This is a measure of the change in full-scale error with changes
in temperature. Full-scale error TC is expressed in ppm FSR/°C.

Gain Error

This is a measure of the span error of the DAC. It is the devia­tion in slope of the DAC transfer characteristic from the ideal
expressed in % FSR. A plot of gain error vs. temperature can be
seen in Figure 15.

Gain Error Temperature Coefficient (TC)

This is a measure of the change in gain error with changes in
temperature. Gain error TC is expressed in ppm FSR/°C.

Current Loop Compliance Voltage

This is the maximum voltage at the I

pin for which the

OUT

output current is equal to the programmed value.

Power Supply Rejection Ratio (PSRR)

PSRR indicates how the output of the DAC is affected by
changes in the power supply voltage.

Voltage Reference Temperature Coefficient (TC)

Voltage reference TC is a measure of the change in the reference
output voltage with a change in temperature. The voltage
reference TC is calculated using the box method, which defines
the TC as the maximum change in the reference output over a
given temperature range, expressed in ppm/°C as follows:

TC

⎡

=

⎢

REFnom

⎣

−

VV

REFminREFmax

×

TempRangeV

⎤

6

10×

⎥
⎦

where:

is the maximum reference output measured over the

V

REFmax

total temperature range.

V

is the minimum reference output measured over the total

REFmin

temperature range.

V

is the nominal reference output voltage, 5 V.

REFnom

Te mp R an g e is the specified temperature range, −40°C to +85°C.

Reference Load Regulation

Load regulation is the change in reference output voltage due to
a specified change in load current. It is expressed in ppm/mA.

Rev. B | Page 15 of 28

AD5410/AD5420

V

A

V

THEORY OF OPERATION

The AD5410/AD5420 are precision digital-to-current loop output
converters designed to meet the requirements of industrial
process control applications. They provide a high precision,
fully integrated, low cost single-chip solution for generating
current loop outputs. The current ranges available are 0 mA
to 20 mA, 0 mA to 24 mA, and 4 mA to 20 mA. The desired
output configuration is user selectable via the control register.

ARCHITECTURE

The DAC core architecture of the AD5410/AD5420 consists of
two matched DAC sections. A simplified circuit diagram is shown
in Figure 37. The four MSBs of the 12-bit or 16-bit data-word
are decoded to drive 15 switches, E1 to E15. Each of these switches
connects one of 15 matched resistors to either ground or the
reference buffer output. The remaining 8/12 bits of the data­word drive Switch S0 to Switch S7 or Switch S0 to Switch S11 of an
8-/12-bit voltage mode R-2R ladder network.

OUT

2R
E15

V

REFIN

2R

2R

2R

2R

S1

S0

2R
S7/S11

2R

E2

E1

SCLK. The input shift register consists of eight address bits and
16 data bits, as shown in Tabl e 6. The 24-bit word is uncondition­ally latched on the rising edge of LATCH. Data continues to be
clocked in irrespective of the state of LATCH. On the rising edge
of LATCH, the data that is present in the input shift register is
latched; that is, the last 24 bits to be clocked in before the rising
edge of LATCH is the data that is latched. The timing diagram
for this operation is shown in Figure 2.

Standalone Operation

The serial interface works with both a continuous and noncon­tinuous SCLK. A continuous SCLK source can be used only if
LATCH is taken high after the correct number of data bits has
been clocked in. In gated clock mode, a burst clock containing
the exact number of clock cycles must be used, and LATCH
must be taken high after the final clock to latch the data. The
first rising edge of SCLK that clocks in the MSB of the data­word marks the beginning of the write cycle. Exactly 24 rising
clock edges must be applied to SCLK before LATCH is brought
high. If LATCH is brought high before the 24

th

rising SCLK
edge, the data written is invalid. If more than 24 rising SCLK
edges are applied before LATCH is brought high, the input data
is also invalid.

8-/12-BIT R- 2R LADDER FO UR M S Bs DECODED INTO

Figure 37. DAC Ladder Structure

15 EQUAL SEGMENTS

07027-033

The voltage output from the DAC core is converted to a current
(see Figure 38) that is then mirrored to the supply rail so that
the application simply sees a current source output with respect
to ground.

DD

R2

A2

12-/16-BIT

DAC

Figure 38. Voltage-to-Current Conversion Circuitry

T1

A1

R

SET

R3

T2

I

OUT

07027-034

SERIAL INTERFACE

The AD5410/AD5420 are controlled over a versatile 3-wire
serial interface that operates at clock rates of up to 30 MHz. They
are compatible with SPI, QSPI, MICROWIRE, and DSP
standards.

Input Shift Register

The input shift register is 24 bits wide. Data is loaded into the
device MSB first as a 24-bit word under the control of a serial
clock input, SCLK. Data is clocked in on the rising edge of

Rev. B | Page 16 of 28

Table 6. Input Shift Register Format

MSB LSB

DB23 to DB16 DB15 to DB0

Address byte Data-word

Table 7. Address Byte Functions

Address Byte Function

00000000 No operation (NOP)
00000001 Data register
00000010

Readback register value as per read address
(see Table 8)

01010101

Control register

01010110 Reset register

Daisy-Chain Operation

For systems that contain several devices, the SDO pin can be used
to daisy-chain several devices together, as shown in Figure 39.
This daisy-chain mode can be useful in system diagnostics and
in reducing the number of serial interface lines. Daisy-chain
mode is enabled by setting the DCEN bit of the control register.
The first rising edge of SCLK that clocks in the MSB of the data­word marks the beginning of the write cycle. SCLK is continuously
applied to the input shift register. If more than 24 clock pulses
are applied, the data ripples out of the input shift register and
appears on the SDO line. This data, having been clocked out on
the previous falling SCLK edge, is valid on the rising edge of
SCLK. By connecting the SDO of the first device to the SDIN
input of the next device in the chain, a multidevice interface is
constructed. Each device in the system requires 24 clock pulses.
Therefore, the total number of clock cycles must equal 24 × N,

AD5410/AD5420

where N is the total number of AD5410/AD5420 devices in the
chain. When the serial transfer to all devices is complete,
LATCH is taken high. This latches the input data in each device
in the daisy chain. The serial clock can be a continuous or a
gated clock.

A continuous SCLK source can be used only if LATCH is taken
high after the correct number of clock cycles. In gated clock
mode, a burst clock containing the exact number of clock cycles
must be used, and LATCH must be taken high after the final
clock to latch the data. See Figure 4 for a timing diagram.

CONTROLLER

DATA OUT

SERIAL CLOCK

CONTROL OUT

DATA IN

AD5410/
AD5420*

SDIN
SCLK

LATCH

SDO

SDIN

AD5410/
AD5420*

SCLK
LATCH

SDO

SDIN

AD5410/
AD5420*

SCLK
LATCH

Readback Operation

Readback mode is invoked by setting the address byte and read
address as shown in Tabl e 9 and Tab l e 8 when writing to the
input shift register. The next write to the AD5410/AD5420
should be a NOP command, which clocks out the data from the
previously addressed register, as shown in Figure 3. By default,
the SDO pin is disabled. After having addressed the AD5410/
AD5420 for a read operation, a rising edge on LATCH enables
the SDO pin in anticipation of data being clocked out. After the
data has been clocked out on SDO, a rising edge on LATCH
disables (tristate) the SDO pin once again. To read back the
data register, for example, the following sequence should be
implemented:

1. Write 0x020001 to the AD5410/AD5420 input shift

register. This configures the part for read mode with the
data register selected.

2. Follow this with a second write, a NOP condition, 0x000000.

During this write, the data from the data register is clocked
out on the SDO line.

Table 8. Read Address Decoding

Read Address Function

00 Read status register
01 Read data register
10 Read control register

SDO

*ADDITIONAL PINS OMITTED FOR CLARI TY.

Figure 39. Daisy Chaining the AD5410/AD5420

07027-035

Table 9. Input Shift Register Contents for a Read Operation

MSB LSB
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 to DB2 DB1 DB0

0 0 0 0 0 0 1 0 X1 Read address

1

X = don’t care.

Rev. B | Page 17 of 28

AD5410/AD5420

POWER-ON STATE

Upon power-on of the AD5410/AD5420, the power-on reset
circuit ensures that all registers are loaded with zero code. As
such, the output is disabled (tristate). Also upon power-on,
internal calibration registers are read, and the data is applied to
internal calibration circuitry. For a reliable read operation, there
must be sufficient voltage on the AV
is triggered by the DV
up the DV
and AV

supply after the AVDD supply ensures this. If DVCC

CC

are powered up simultaneously or if the internal DVCC

DD

power supply powering up. Powering

CC

is enabled, the supplies should be powered up at a rate greater
than, typically, 500 V/sec or 24 V per 50 ms. If this cannot be
achieved, simply issue a reset command to the AD5410/AD5420
after power-on. This performs a power-on reset event, reading
the calibration registers and ensuring specified operation of the
AD5410/AD5420.

TRANSFER FUNCTION

For the 0 mA to 20 mA, 0 mA to 24 mA, and 4 mA to 20 mA
current output ranges, the output current is respectively
expressed as

mA20

⎡

=

OUT

⎢
⎣

⎡

=

OUT

⎢
⎣

⎡

= DI

OUT

⎢
⎣

where:

D is the decimal equivalent of the code loaded to the DAC.
N is the bit resolution of the DAC.

⎤

DI

×

N

2

mA24

N

2

mA16

N

2

⎥
⎦

⎤

DI

×

⎥
⎦

⎤

+×

⎥
⎦

supply when the read event

DD

mA4

DATA REGISTER

The data register is addressed by setting the address byte of the
input shift register to 0x01. The data to be written to the data
register is entered in Position DB15 to Position DB4 for the
AD5410 and in Position DB15 to Position DB0 for the AD5420,
as shown in Tabl e 12 and Ta bl e 1 3, respectively

CONTROL REGISTER

The control register is addressed by setting the address byte of
the input shift register to 0x55. The data to be written to the
control register is entered in Position DB15 to Position DB0,
as shown in Tab l e 14 . The control register bit functions are
described in Ta ble 1 0.

Table 10. Control Register Bit Functions

Bit Description

REXT

OUTEN

SR Clock

SR Step

SREN Digital slew rate control enable.
DCEN
R2, R1, R0 Output range select. See Table 11.

Table 11. Output Range Options

R2 R1 R0 Output Range Selected

1 0 1 4 mA to 20 mA current range
1 1 0 0 mA to 20 mA current range
1 1 1 0 mA to 24 mA current range

Setting this bit selects the external current setting
resistor. See the AD5410/AD5420 Features section
for further details.

Output enable. This bit must be set to enable the
output.

Digital slew rate control. See the AD5410/AD5420
Features section.

Digital slew rate control. See the AD5410/AD5420
Features section.

Daisy-chain enable.

Table 12. Programming the AD5410 Data Register

MSB LSB
DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

12-bit data-word X1 X1 X1 X1

1

X = don’t care.

Table 13. Programming the AD5420 Data Register

MSB LSB
DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

16-bit data-word

Table 14. Programming the Control Register

MSB LSB
DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

0 0 REXT OUTEN SR clock SR step SREN DCEN R2 R1 R0

Rev. B | Page 18 of 28

AD5410/AD5420

RESET REGISTER

The reset register is addressed by setting the address byte of the
input shift register to 0x56. The reset register contains a single
reset bit at Position DB0, as shown in Tabl e 16 . Writing a logic
high to this bit performs a reset operation, restoring the part to
its power-on state.

STATUS REGISTER

The status register is a read-only register. The status register bit
functionality is shown in Ta b le 1 5 and Tab l e 17 .

Table 16. Programming the Reset Register

MSB LSB
DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Reserved Reset

Table 17. Decoding the Status Register

MSB LSB
DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

Reserved I

Table 15. Status Register Bit Functions

Bit Description

I

Fault This bit is set if a fault is detected on the I

OUT

Slew Active

Overtemp

This bit is set while the output value is slewing
(slew rate control enabled).

This bit is set if the AD5410/AD5420 core
temperature exceeds approximately 150°C.

fault Slew active Overtemp

OUT

OUT

pin.

Rev. B | Page 19 of 28

AD5410/AD5420

AD5410/AD5420 FEATURES

FAULT ALERT

The AD5410/AD5420 are equipped with a
an open-drain output allowing several AD5410/AD5420
devices to be connected together to one pull-up resistor for
global fault detection. The

FAU LT

pin is forced active by any

one of the following fault scenarios:

• The voltage at I

attempts to rise above the compliance

OUT

range, due to an open-loop circuit or insufficient power
supply voltage. The I

current is controlled by a PMOS

OUT

transistor and internal amplifier, as shown in Figure 38.
The internal circuitry that develops the fault output avoids
using a comparator with window limits because this requires
an actual output error before the
active. Instead, the signal is generated when the internal
amplifier in the output stage has less than approximately
1 V of remaining drive capability (when the gate of the
output PMOS transistor nearly reaches ground). Thus, the
FAU LT

output activates slightly before the compliance limit is
reached. Because the comparison is made within the feed­back loop of the output amplifier, the output accuracy is
maintained by its open-loop gain and an output error does
not occur before the

FAU LT

output becomes active.

• If the core temperature of the AD5410/AD5420 exceeds

approximately 150°C.

The I
in conjunction with the
fault condition caused the

fault and overtemp bits of the status register are used

OUT

FAU LT

pin to inform the user which

FAU LT

pin to be asserted. See Table 17

and Table 15.

ASYNCHRONOUS CLEAR (CLEAR)

CLEAR is an active high clear that clears the current output to
the bottom of its programmed range. It is necessary to maintain
CLEAR high for a minimum amount of time (see Figure 2) to
complete the operation. When the CLEAR signal is returned
low, the output remains at the cleared value. The preclear value
can be restored by pulsing the LATCH signal low without
clocking any data. A new value cannot be programmed until the
CLEAR pin is returned low.

INTERNAL REFERENCE

The AD5410/AD5420 contain an integrated +5 V voltage
reference with initial accuracy of ±5 mV maximum and a
temperature drift coefficient of 10 ppm/°C maximum. The
reference voltage is buffered and externally available for use
elsewhere within the system. See Figure 34 for a load regulation
graph of the integrated reference.

FAU LT

FAU LT

output becomes

pin, which is

EXTERNAL CURRENT SETTING RESISTOR

In Figure 38, R
voltage-to-current conversion circuitry. The stability of the
output current over temperature is dependent on the stability of
the value of R
can be connected from the R
ground; this improves the overall performance of the AD5410/
AD5420. The external resistor is selected via the control
register. See Table 14.

is an internal sense resistor as part of the

SET

. An external precision 15 kΩ low drift resistor

SET

pin of the AD5410/AD5420 to

SET

DIGITAL POWER SUPPLY

By default, the DVCC pin accepts a power supply of 2.7 V to

5.5 V. Alternatively, via the DV
power supply can be output on the DV

SELECT pin, an internal 4.5 V

CC

pin for use as a digital

CC

power supply for other devices in the system or as a termination
for pull-up resistors. This facility offers the advantage of not
having to bring a digital supply across an isolation barrier. The
internal power supply is enabled by leaving the DV
pin unconnected. To disable the internal supply, DV
should be tied to 0 V. DV

is capable of supplying up to 5 mA

CC

SELECT

CC

SELECT

CC

of current. See Figure 27 for a load regulation graph.

EXTERNAL BOOST FUNCTION

The addition of an external boost transistor, as shown in Figure 40,
reduces the power dissipated in the AD5410/AD5420 by reducing
the current flowing in the on-chip output transistor (dividing it
by the current gain of the external circuit). A discrete NPN
transistor with a breakdown voltage, BV
can be used.

The external boost capability allows the AD5410/AD5420 to be
used at the extremes of the supply voltage, load current, and
temperature range. The boost transistor can also be used to
reduce the amount of temperature-induced drift in the part.
This minimizes the temperature-induced drift of the on-chip
voltage reference, which improves drift and linearity.

BOOST

AD5410/
AD5420

Figure 40. External Boost Configuration

I

OUT

0.022µF

, greater than 40 V

CEO

MJD31C

OR

2N3053

1kΩ

R

L

07027-036

Rev. B | Page 20 of 28

AD5410/AD5420

=

DIGITAL SLEW RATE CONTROL

The slew rate control feature of the AD5410/AD5420 allows the
user to control the rate at which the output current changes.
With the slew rate control feature disabled, the output current
changes at a rate of approximately 16 mA in 10 µs (see Figure 36).
This varies with load conditions. To reduce the slew rate, enable
the slew rate control feature. With the feature enabled via the
SREN bit of the control register (see Tabl e 14), the output, instead
of slewing directly between two values, steps digitally at a rate
defined by two parameters accessible via the control register, as
shown in Tab l e 14 . The parameters are SR clock and SR step.
SR clock defines the rate at which the digital slew is updated,
SR step defines by how much the output value changes at each
update. Both parameters together define the rate of change of
the output current. Tab l e 1 8 and Tab l e 1 9 outline the range of
values for both the SR clock and SR step parameters. Figure 41
shows the output current changing for ramp times of 10 ms,
50 ms, and 100 ms.

Table 18. Slew Rate Update Clock Values

SR Clock Update Clock Frequency (Hz)

0000 257,730
0001 198,410
0010 152,440
0011 131,580
0100 115,740
0101 69,440
0110 37,590
0111 25,770
1000 20,160
1001 16,030
1010 10,290
1011 8280
1100 6900
1101 5530
1110 4240
1111 3300

Table 19. Slew Rate Step Size Options

SR Step AD5410 Step Size (LSB) AD5420 Step Size (LSB)

000 1/16 1
001 1/8 2
010 1/4 4
011 1/2 8
100 1 16
101 2 32
110 4 64
111 8 128

25

TA = 25°C

= 24V

AV

DD

R

= 300Ω

LOAD

20

15

10

OUTPUT CURRENT ( mA)

5

0
–10 0 10 20 30 40 50 60 70 80 90 100 110

Figure 41. Output Current Slewing Under Control of the Digital Slew Rate

10ms RAMP, SR CLOCK = 0x1, SR S TEP = 0x5
50ms RAMP, SR CLOCK = 0xA, SR STEP = 0x7
100ms RAMP, SR CL OCK = 0x8, SR ST EP = 0x5

TIME (ms)

Control Feature

07027-139

The time it takes for the output current to slew over a given
output range can be expressed as follows:

TimeSlew

ChangeOutput

××

(1)

SizeLSBFrequencyClockUpdateSizeStep

where:

Slew Time is expressed in seconds.
Output Change is expressed in amps.

When the slew rate control feature is enabled, all output
changes change at the programmed slew rate. If the CLEAR
pin is asserted, the output slews to the zero-scale value at the
programmed slew rate. The output can be halted at its current
value with a write to the control register. To avoid halting the
output slew, the slew active bit can be read to check that the
slew has completed before writing to any of the AD5410/
AD5420 registers (see Tab le 17 ). The update clock frequency for
any given value is the same for all output ranges. The step size,
however, varies across output ranges for a given value of step
size because the LSB size is different for each output range.
Tabl e 20 shows the range of programmable slew times for a full­scale change on any of the output ranges. The values in Table 2 0
were obtained using Equation 1. The digital slew rate control
feature results in a staircase formation on the current output, as
shown in Figure 45. Figure 45 also shows how the staircase can
be removed by connecting capacitors to the CAP1 and CAP2
pins, as described in the I

Filtering Capacitors section.

OUT

Rev. B | Page 21 of 28

AD5410/AD5420

A

V

Table 20. Programmable Slew Time Values in Seconds for a Full-Scale Change on Any Output Range

Step Size (LSBs)
Update Clock Frequency (Hz) 1 2 4 8 16 32 64 128

257,730 0.25 0.13 0.06 0.03 0.016 0.008 0.004 0.0020
198,410 0.33 0.17 0.08 0.04 0.021 0.010 0.005 0.0026
152,440 0.43 0.21 0.11 0.05 0.027 0.013 0.007
131,580 0.50 0.25 0.12 0.06 0.031 0.016 0.008
115,740 0.57 0.28 0.14 0.07 0.035 0.018 0.009
69,440 0.9 0.47 0.24 0.12 0.06 0.03 0.015
37,590 1.7 0.87 0.44 0.22 0.11 0.05 0.03
25,770 2.5 1.3 0.64 0.32 0.16 0.08 0.04
20,160 3.3 1.6 0.81 0.41 0.20 0.10 0.05
16,030 4.1 2.0 1.0 0.51 0.26 0.13 0.06
10,290 6.4 3.2 1.6 0.80 0.40 0.20 0.10
8280 7.9 4.0 2.0 1.0 0.49 0.25 0.12
6900 9.5 4.8 2.4 1.2 0.59 0.30 0.15
5530 12 5.9 3.0 1.5 0.74 0.37 0.19
4240 15 7.7 3.9 1.9 0.97 0.48 0.24
3300 20 9.9 5.0 2.5 1.24 0.62 0.31 0.16

I

FILTERING CAPACITORS

OUT

Capacitors can be placed between CAP1 and AVDD, and CAP2
and AV

, as shown in Figure 42.

DD

AV

AD5410/
AD5420

GND

Figure 42. I

DD

C1 C2

DD

CAP1

CAP2

I

OUT

Filtering Capacitors

OUT

07027-037

The capacitors form a filter on the current output circuitry, as
shown in Figure 43, reducing the bandwidth and the slew rate
of the output current. Figure 44 shows the effect the capacitors

DAC

CAP1

CAP2

4kΩ

12.5kΩ

R

SET

Figure 43. I

Filter Circuitry

OUT

25

C1

C2

have on the slew rate of the output current. To achieve
significant reductions in the rate of change, very large capacitor

20

values are required, which may not be suitable in some
applications. In this case, the digital slew rate control feature
should be used. The capacitors can be used in conjunction with
the digital slew rate control feature as a means of smoothing out
the steps caused by the digital code increments, as shown in
Figure 45.

15

10

OUTPUT CURRENT ( mA)

5

0
–0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

NO CAPACITOR
10nF ON CAP1
10nF ON CAP2
47nF ON CAP1
47nF ON CAP2

TIME (ms)

Figure 44. Slew Controlled 4 mA to 20 mA Output Current Step Using

External Capacitors on the CAP1 and CAP2 Pins

TA = 25°C
AV
R

LOAD

DD

40Ω

= 24V

= 300Ω

0.0034

0.0039

0.0044

0.007

0.014

0.020

0.025

0.03

0.05

0.06

0.07

0.09

0.12

AV

DD

BOOST

I

OUT

07027-142

07027-038

Rev. B | Page 22 of 28

AD5410/AD5420

R

A

V

6.8
TA = 25°C

AV

6.7

6.6

6.5

6.4

6.3

OUTPUT CURRENT ( mA)

6.2

6.1

–1012345678

R

DD

LOAD

= 24V

= 300Ω

TIME (ms)

NO EXTERNAL CAPS
10nF ON CAP1
10nF ON CAP2

07027-043

Figure 45. Smoothing Out the Steps Caused by the Digital Slew Rate Control

Feature

FEEDBACK/MONITORING OF OUTPUT CURRENT

For feedback or monitoring of the output current value, a sense
resistor can be placed in series with the I
voltage drop across it measured. As well as being an additional
component, the resistor increases the compliance voltage
required. An alternative method is to use a resistor that is
already in place. R3 is such a resistor and is internal to the
AD5410/AD5420, as shown in Figure 46. By measuring the
voltage between the R3

and BOOST pins, the value of the

SENSE

output current can be calculated as follows:

V

R

I −=

OUT

3

3

(2)

I

BIAS

where:

V

is the voltage drop across R3 measured between the R3

R3

and BOOST pins

I

is a constant bias current flowing through R3 with a typical

BIAS

value of 444 µA.

R3 is the resistance value of resistor R3 with a typical value of 40 .

DD

R

METAL

R3
40Ω

I

444µA

BIAS

Figure 46. Structure of Current Output Circuit

output pin and the

OUT

R3

SENSE

BOOST

I

OUT

07027-050

SENSE

R3 and I
coefficient of 30 ppm/°C. Connecting to R3
AV

DD

both have a tolerance of ±10% and a temperature

BIAS

rather than

SENSE

avoids incorporating into R3 internal metal connections
that have large temperature coefficients and result in large
errors. See Figure 47 for a plot of R3 vs. ambient temperature
and Figure 48 for a plot of R3 vs. output current.

40.98
I

= 12mA

OUT

40.96

R3 = V

/(12mA + 444µA)

R3

40.94

40.92

40.90

40.88

40.86

R3 RESISTANCE (Ω)

40.84

40.82

40.80

40.78

–40 –20 0 20 40 60 80 100

AMBIENT TEMPERATURE (°C)

Figure 47. R3 Resistor Value vs. Temperature

42.0

TA = 25°C
R3 = V

/(I

41.8

41.6

41.4

41.2

41.0

R3 (Ω)

40.8

40.6

40.4

40.2

40.0

0 5 10 15 20 25

To eliminate errors due to the tolerances of R3 and I

+ 444µA)

R3

OUT

(mA)

I

OUT

Figure 48. R3 Resistor Value vs. I

OUT

BIAS

, a two­measurement calibration can be performed as the following
example illustrates:

1.

Progam code 0x1000 and measure I

and VR3. In this

OUT

example, the measured values are

= 1.47965 mA

I

OUT

= 79.55446 mV

V

R3

Program Code 0xF000 and measure I

2.

and VR3 again.

OUT

The measured values this time are

= 22.46754 mA

I

OUT

= 946.39628 mV

V

R3

07027-051

07027-052

Rev. B | Page 23 of 28

AD5410/AD5420

Using this information and Equation 2, two simultaneous
equations can be generated from which the values of R3 and
I

can be calculated as follows:

BIAS

V

R

3

I

OUT

I

BIAS

Simultaneous Equation 1

I

BIAS

I

−=

BIAS

R

3

V

R

3

R

3

07955446.0

R

I

−=⇒

OUT

−=

3

00147965.0

Simultaneous Equation 2

I

BIAS

94639628.0

R

3

From these two equations,

 and A

302.413=R

And Equation 2 becomes

V

R

I

OUT

3

−=

302.41

−=

02246754.0

I

BIAS

µA

5.446

5.446=

Rev. B | Page 24 of 28

AD5410/AD5420

A

V

R

*

APPLICATIONS INFORMATION

DRIVING INDUCTIVE LOADS

When driving inductive or poorly defined loads, connect a 0.01 µF
capacitor between I

and GND. This ensures stability with

OUT

loads beyond 50 mH. There is no maximum capacitance limit.
The capacitive component of the load may cause slower settling.
Alternatively, the capacitor can be connected from CAP1 and/or
CAP2 to AV

to reduce the slew rate of the current. The digital

DD

slew rate control feature may also prove useful in this situation.

TRANSIENT VOLTAGE PROTECTION

The AD5410/AD5420 contain ESD protection diodes that prevent
damage from normal handling. The industrial control environ­ment can, however, subject I/O circuits to much higher transients.
To protect the AD5410/AD5420 from excessively high voltage
transients, external power diodes and a surge current limiting
resistor may be required, as shown in Figure 49. The constraint
on the resistor value is that during normal operation, the output
level at I
AV

DD

must remain within its voltage compliance limit of

OUT

− 2.5 V, and the two protection diodes and resistor must
have appropriate power ratings. Further protection can be pro­vided with transient voltage suppressors (TVS), or transorbs.
These are available as both unidirectional suppressors (protect
against positive high voltage transients) and bidirectional
suppressors (protect against both positive and negative high
voltage transients) and are available in a wide range of standoff
and breakdown voltage ratings. It is recommended that all field
connected nodes be protected.

DD

AV

DD

AD5410/
AD5420

GND

I

OUT

Figure 49. Output Transient Voltage Protection

R

P

R

L

7027-039

LAYOUT GUIDELINES

In any circuit where accuracy is important, careful consideration
of the power supply and ground return layout helps to ensure
the rated performance. The printed circuit board (PCB) on
which the AD5410/AD5420 are mounted should be designed so
that the analog and digital sections are separated and confined
to certain areas of the board. If the AD5410/AD5420 are in a
system where multiple devices require an AGND-to-DGND
connection, the connection should be made at one point only.
The star ground point should be established as close as possible
to the device.

The AD5410/AD5420 should have ample supply bypassing of
10 µF in parallel with 0.1 µF on each supply, located as close to
the package as possible, ideally right up against the device.
The 10 µF capacitors are the tantalum bead type. The 0.1 µF

Rev. B | Page 25 of 28

capacitor should have low effective series resistance (ESR)
and low effective series inductance (ESI), such as the common
ceramic types, which provide a low impedance path to ground
at high frequencies to handle transient currents due to internal
logic switching.

The power supply lines of the AD5410/AD5420 should use as
large a trace as possible to provide low impedance paths and to
reduce the effects of glitches on the power supply line. Fast­switching signals such as clocks should be shielded with digital
ground to avoid radiating noise to other parts of the board and
should never be run near the reference inputs. A ground line
routed between the SDIN and SCLK lines helps reduce crosstalk
between them (not required on a multilayer board that has a
separate ground plane, but separating the lines helps). It is
essential to minimize noise on the REFIN line because noise
can couple through to the DAC output.

Avoid crossover of digital and analog signals. Traces on
opposite sides of the board should run at right angles to each
other. This reduces the effects of feedthrough on the board.
A microstrip technique is by far the best method but is not
always possible with a double-sided board. In this technique,
the component side of the board is dedicated to the ground
plane, and signal traces are placed on the solder side.

GALVANICALLY ISOLATED INTERFACE

In many process control applications, it is necessary to provide
an isolation barrier between the controller and the unit being
controlled to protect and isolate the controlling circuitry from
any hazardous common-mode voltages that may occur. The

iCoupler® family of products from Analog Devices, Inc.,

provides voltage isolation in excess of 2.5 kV. The serial loading
structure of the AD5410/AD5420 is ideal for isolated interfaces
because the number of interface lines is kept to a minimum.
Figure 50 shows a 4-channel isolated interface to the AD5410/
AD5420 using an ADuM1400. For further information, visit

www.analog.com/icouplers.

CONTROLLE

SERIAL

CLOCK

SERIAL

CONTROL

ADDITIONAL PINS OMI T TED FOR CLARITY.

OUT

DATA

OUT

SYNC

OUT

OUT

V

IA

V

IB

V

IC

V

ID

ADuM1400*

ENCODE

ENCODE

ENCODE

ENCODE

DECODE

DECODE

DECODE

DECODE

Figure 50. Isolated Interface

V

OA

TO
SCLK

V

OB

TO
SDIN

V

OC

TO
LATCH

V

OD

TO
CLEAR

07027-040

AD5410/AD5420

MICROPROCESSOR INTERFACING

Microprocessor interfacing to the AD5410/AD5420 is via a serial
bus that uses a protocol compatible with microcontrollers and
DSP processors. The communication channel is a 3-wire (mini­mum) interface consisting of a clock signal, a data signal, and a
latch signal. The AD5410/AD5420 require a 24-bit data-word
with data valid on the rising edge of SCLK.

For all interfaces, the DAC output update is initiated on the
rising edge of LATCH. The contents of the registers can be read
using the readback function.

THERMAL AND SUPPLY CONSIDERATIONS

The AD5410/AD5420 are designed to operate at a maximum
junction temperature of 125°C. It is important that the device
not be operated under conditions that cause the junction tempera­ture to exceed this value. Excessive junction temperature can
occur if the AD5410/AD5420 are operated from the maximum

, while driving the maximum current (24 mA) directly to

AV

DD

ground. In this case, the ambient temperature should be controlled
or AV

At the maximum ambient temperature of 85°C, the 24-lead
TSSOP can dissipate 950 mW, and the 40-Lead LFCSP can
dissipate 1.42 W.

To ensure that the junction temperature does not exceed 125°C
while driving the maximum current of 24 mA directly into
ground (also adding an on-chip current of 4 mA), AV
be reduced from the maximum rating to ensure that the
package is not required to dissipate more power than previously
stated (see Tab l e 2 1 , Figure 51, and

should be reduced.

DD

Figure 52).

should

DD

2.5

2.0

1.5

1.0

POWER DISS IPATION ( W)

0.5

0

40 45 50 55 60 65 70 75 80 85

Figure 51. Maximum Power Dissipation vs. Ambient Temperature

65

60

55

50

45

40

SUPPLY VOLTAGE (V )

35

30

25

25 35 45 55 65

Figure 52. Maximum Supply Voltage vs. Ambient Temperature

AMBIENT TEMPERATURE (°C)

AMBIENT TEM P E RATURE (°C)

LFCSP

TSSOP

LFCSP

TSSOP

75 85

07027-055

07027-054

Table 21. Thermal and Supply Considerations

Consideration TSSOP LFCSP

Maximum Allowed Power
Dissipation When Operating at
an Ambient Temperature of 85°C

T

J

max

Θ

JA

T

−

A

=

85125

−

42

mW

950

=

W

T

J

max

Θ

JA

T

−

A

85125

−

=

28

Maximum Allowed Ambient
Temperature When Operating
from a Supply of 40 V/60 V and

JADJ

( )

CPT

°=××−=Θ×− 7842028.040125max

JADJ

Driving 24 mA Directly to Ground
Maximum Allowed Supply

Voltage When Operating at an
Ambient Temperature of 85°C
and Driving 24 mA Directly to

−

AJ

AI

=

Θ×

JADD

85125

−

×

V

34

=

42028.0

V

AI

max

TT

−

AJ

=

Θ×

JADD

85125

−

28028.0

×

TT

max

Ground

Rev. B | Page 26 of 28

42.1

=

()

CPT

°=××−=Θ×− 7828028.060125max

51

=

AD5410/AD5420

V

INDUSTRIAL ANALOG OUTPUT APPLICATION

Many industrial control applications have requirements for
accurately controlled current output signals, and the AD5410/
AD5420 are ideal for such applications. Figure 53 shows the
AD5410/AD5420 in a circuit design for an output module
specifically for use in an industrial control application. The
design provides for a current output. The module is powered
from a field supply of 24 V. This supplies AV
transient overvoltage protection, transient voltage suppressors
(TVS) are placed on both the I
A 24 V TVS is placed on the I

and field supply connections.

OUT

connection, and a 36 V TVS is

OUT

placed on the field supply input. For added protection, clamping
diodes are connected from the I

pin to the AVDD and GND

OUT

power supply pins. Isolation between the AD5410/AD5420 and
the backplane circuitry is provided with the ADuM1400 and

BACKPLANE SUPPLY

0.1µF

MICROCONTROLLER

DIGITAL

OUTPUTS

BACKPLANE INTERF ACE

DIGITAL

INTPUTS

directly. For

DD

0.1µF

ADuM1400

V

V
NC
V
V
V
V
GND
GND

V
V
V
GND

DD1

IA
IB
IC
ID

DD2
OA
OB

DD2

V

E2

V

OA

V

OB

V

OC

V

OD

GND

2

1

GND

2

1

V

DD1

V

IA

V

IB

GND

2

1

ADUM1200

Figure 53. AD5410/AD5420 in an Industrial Analog Output Application

ADuM1200

iCoupler products is available at www.analog.com/icouplers.

The internally generated digital power supply of the AD5410/
AD5420 powers the field side of the digital isolators, removing
the need to generate a digital power supply on the field side of
the isolation barrier. The AD5410/AD5420 digital supply out­put supplies up to 5 mA, which is more than enough to supply
the 2.8 mA requirement of the ADuM1400 and ADuM1200
operating at a logic signal frequency of up to 1 MHz. To reduce
the number of isolators required, nonessential signals such as
CLEAR can be connected to GND and
left unconnected, reducing the isolation requirements to just
three signals. Doing so, however, disables the fault alert features
of the part.

10kΩ

DV

CC

SELECT

CLEAR
LATCH
SCLK

SDIN

FAULT
SDO

iCoupler digital isolators; further information on

FAU LT

+

10µF

SMAJ36CA
36V

0.1µF

C1
C2

CAP2

REFIN

AV

DD

I

OUT

0.1µF

18Ω

24V
SMAJ24CA

CAP1

DV

CC

AD5410/AD5420

GND

REFOUT

, and SDO can be

24
FIELD
SUPPLY

FIELD
GROUND

I

OUT

07027-048

Rev. B | Page 27 of 28

AD5410/AD5420

OUTLINE DIMENSIONS

7.90

7.80

7.70

5.02

5.00

4.95

24

1.20 MAX

0.15
SEATING

0.05

0.10 COPLANARITY

PLANE

TOP VIEW

0.65
BSC

13

4.50

4.40

4.30

6.40 BSC

1.05

1.00

0.80

COMPLIANT TO JEDEC STANDARDS MO-153-ADT

8°
0°

0.20

0.09

0.30

0.19

121

EXPOSED

PAD

(Pins Up)

BOTTOM VIEW

3.25

3.20

3.15

FOR PROPER CONNE CT I O N O F
THE EXPOSED PAD, REFER TO
THE PIN CONF IGURATIO N AND
FUNCTION DES CRIPTIONS
SECTION OF THIS DATA SHEET.

0.75

0.60

0.45

061708-A

Figure 54. 24-Lead Thin Shrink Small Outline Package, Exposed Pad [TSSOP_EP]

(RE-24)

Dimensions shown in millimeters

PIN 1

INDICATOR

1.00

0.85

0.80

12° MAX

SEATING
PLANE

6.00

BSC SQ

TOP

VIEW

0.80 MAX

0.65 TYP

0.30

0.23

0.18

COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2

5.75

BSC SQ

0.20 REF

0.05 MAX

0.02 NOM

COPLANARITY

0.60 MAX

0.50
BSC

0.50

0.40

0.30

0.08

0.60 MAX

31

30

EXPOSED

(BOTTOM VIEW)

21

20

40

1

PAD

10

11

4.50
REF

FOR PROPE R CONNECTION O F
THE EXPOSED PAD, REFER TO
THE PIN CONF IGURATIO N AND
FUNCTION DES CRIPTIONS
SECTION O F THIS DATA S HE E T.

PIN 1
INDICATOR

4.25

4.10 SQ

3.95

0.25 MIN

072108-A

Figure 55. 40-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

6 mm × 6 mm Body, Very Thin Quad

(CP-40-1)

Dimensions shown in millimeters

ORDERING GUIDE

Model1 Temperature Range Resolution TUE Package Description Package Option

AD5410AREZ −40°C to +85°C 12 Bits 0.3% Max 24-Lead TSSOP_EP RE-24
AD5410AREZ-REEL7 −40°C to +85°C 12 Bits 0.3% Max 24-Lead TSSOP_EP RE-24
AD5410ACPZ-REEL −40°C to +85°C 12 Bits 0.3% Max 40-Lead LFCSP_VQ
AD5410ACPZ-REEL7 −40°C to +85°C 12 Bits 0.3% Max 40-Lead LFCSP_VQ
AD5420AREZ −40°C to +85°C 16 Bits 0.15% Max 24-Lead TSSOP_EP RE-24
AD5420AREZ-REEL7 −40°C to +85°C 16 Bits 0.15% Max 24-Lead TSSOP_EP RE-24
AD5420ACPZ-REEL −40°C to +85°C 16 Bits 0.15% Max 40-Lead LFCSP_VQ
AD5420ACPZ-REEL7 −40°C to +85°C 16 Bits 0.15% Max 40-Lead LFCSP_VQ
EVAL-AD5420EBZ Evaluation Board

1

Z = RoHS Compliant Part.

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D07027-0-2/10(B)

CP-40-1
CP-40-1

CP-40-1
CP-40-1

Rev. B | Page 28 of 28