Page 1
Dual 12-Bit, High Bandwidth, Multiplying DAC
with 4-Quadrant Resistors and Serial Interface
FEATURES
On-chip 4-quadrant resistors allow flexible output ranges
10 MHz multiplying bandwidth
50 MHz serial interface
2.5 V to 5.5 V supply operation
±10 V reference input
Extended temperature range: −40°C to +125°C
24-lead TSSOP package
Guaranteed monotonic
Power-on reset
Daisy-chain mode
Readback function
0.5 µA typical current consumption
APPLICATIONS
Portable battery-powered applications
Waveform generators
Analog processing
Instrumentation applications
Programmable amplifiers and attenuators
Digitally controlled calibration
Programmable filters and oscillators
Composite video
Ultrasound
Gain, offset, and voltage trimming
FUNCTIONAL BLOCK DIAGRAM
V
SYNC
SCLK
SDIN
SDO
LDAC
DD
AD5415
SHIFT
REGISTER
REGISTER
GENERAL DESCRIPTION
The AD54151 is a CMOS 12-bit, dual-channel, current output
digital-to-analog converter. This device operates from a 2.5 V to
5.5 V power supply, making it suited to battery-powered applications as well as many other applications.
The applied external reference input voltage (V
the full-scale output current. An integrated feedback resistor
) provides temperature tracking and full-scale voltage
(R
FB
output when combined with an external current-to-voltage
precision amplifier. In addition, this device contains all the
4-quadrant resistors necessary for bipolar operation and other
configuration modes.
This DAC utilizes a double-buffered 3-wire serial interface that
is compatible with SPI®, QSPI™, MICROWIRE™, and most DSP
interface standards. In addition, a serial data out pin (SDO)
allows for daisy-chaining when multiple packages are used.
Data readback allows the user to read the contents of the DAC
register via the SDO pin. On power-up, the internal shift
register and latches are filled with zeros, and the DAC outputs
are at zero scale. As a result of manufacture on a CMOS submicron process, this part offers excellent 4-quadrant multiplication
characteristics, with large-signal multiplying bandwidths of
10 MHz.
1
US Patent Number 5,689,257.
R3A R2_3A R2A V
R32RR2
2R
INPUT
DAC
REGISTER
A R1A
REF
12-BIT
R-2R DAC A
AD5415
) determines
REF
R
R1
FB
2R
2R
R
I
I
OUT
OUT
A
FB
1A
2A
INPUT
REGISTER
R3B R2_3B R2B V
CLR
GND
POWER-ON
RESET
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
R3
2R
Figure 1.
I
1B
DAC
REGISTER
R2
2R
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved.
12-BIT
R-2R DAC B
R12RR
2R
B R1B
REF
www.analog.com
OUT
I
2B
OUT
R
B
FB
FB
04461-0-001
Page 2
AD5415
TABLE OF CONTENTS
Specifications..................................................................................... 3
Divider or Programmable Gain Element................................ 17
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Te r m in o l o g y ...................................................................................... 9
Typical Performance Characteristics ........................................... 10
General Description ....................................................................... 15
DAC Section................................................................................ 15
Unipolar Mode............................................................................ 15
Bipolar Operation....................................................................... 16
Stability ........................................................................................ 16
Single-Supply Applications............................................................ 17
Voltage Switching Mode of Operation .................................... 17
Positive Output Voltage ............................................................. 17
Adding Gain................................................................................ 17
Reference Selection .................................................................... 18
Amplifier Selection .................................................................... 18
Serial Interface ................................................................................ 20
Low Power Serial Interface ....................................................... 20
Control Register ......................................................................... 20
SYNC
Function........................................................................... 21
Daisy-Chain Mode..................................................................... 21
Standalone Mode........................................................................ 21
LDAC
Function .......................................................................... 21
Microprocessor Interfacing....................................................... 22
PCB Layout and Power Supply Decoupling................................ 24
Evaluation Board for the DAC ................................................. 24
Power Supplies for the Evaluation Board................................ 24
Outline Dimensions....................................................................... 28
Ordering Guide .......................................................................... 28
REVISION HISTORY
7/04—Revision 0: Initial Version
Rev. 0 | Page 2 of 28
Page 3
AD5415
SPECIFICATIONS
Temperature range for Y Version: −40°C to +125°C.
= 2.5 V to 5.5 V, V
V
DD
DC performance measured with OP1177, ac performance with AD8038, unless otherwise noted.
Table 1.
Parameter Min Typ Max Unit Conditions
STATIC PERFORMANCE
Resolution 12 Bits
Relative Accuracy ±1 LSB
Differential Nonlinearity −1/+2 LSB Guaranteed monotonic
Gain Error ±25 mV
Gain Error Temperature Coefficient1 ±5 ppm FSR/°C
Bipolar Zero Code Error ±25 mV
Output Leakage Current ±1 nA Data = 0x0000, TA = 25°C, I
±10 nA Data = 0x0000, I
REFERENCE INPUT1 Typical Resistor TC = −50 ppm/°C
Reference Input Range ±10 V
V
A, V
REF
V
REF
B Input Resistance 8 10 12 kΩ DAC input resistance
REF
A to V
B Input Resistance
REF
Mismatch
R1, RFB Resistance 16 20 24 kΩ
R2, R3 Resistance 16 20 24 kΩ
R2 to R3 Resistance Mismatch 0.06 0.18 % Typ = 25°C, Max = 125°C
DIGITAL INPUTS/OUTPUT1
Input High Voltage, V
Input Low Voltage, V
0.7 V VDD = 2.5 V to 2.7 V
Input Leakage Current, IIL 1 µA
Input Capacitance 10 pF
VDD = 4.5 V to 5.5 V
Output Low Voltage, V
Output High Voltage, V
VDD = 2.5 V to 3.6 V
Output Low Voltage, V
Output High Voltage, VOH V
DYNAMIC PERFORMANCE1
Reference Multiplying Bandwidth 10 MHz V
Output Voltage Settling Time 90 160 ns
Digital Delay 20 40 ns
Digital-to-Analog Glitch Impulse 3 nV-s 1 LSB change around major carry, V
Multiplying Feedthrough Error −75 dB DAC latch loaded with all 0s, reference = 10 kHz
Output Capacitance 2 pF DAC latches loaded with all 0s
4 pF DAC latches loaded with all 1s
Digital Feedthrough 5 nV-s
Total Harmonic Distortion −75 dB V
−75 dB V
Output Noise Spectral Density 25 nV/√Hz @ 1 kHz
= 10 V, I
REF
IH
IL
2A, I
OUT
2B = 0 V; all specifications T
OUT
MIN
to T
, unless otherwise noted.
MAX
OUT
1
OUT
1
1.6 2.5 % Typ = 25°C, Max = 125°C
1.7 V VDD = 2.5 V to 5.5 V
0.8 V VDD = 2.7 V to 5.5 V
OL
OH
OL
0.4 V I
V
− 1 V I
DD
0.4 V I
− 0.5 V I
DD
= 200 µA
SINK
= 200 µA
SOURCE
= 200 µA
SINK
= 200 µA
SOURCE
= 5 V p-p, DAC loaded all 1s
REF
Measured to ±4 mV of FS; R
= 100 Ω, C
LOAD
LOAD
=
0s, 15 pF, DAC latch alternately loaded with 0s
and 1s
= 0 V
REF
Feedthrough to DAC output with
CS high and
alternate loading of all 0s and all 1s
= 5 V p-p, all 1s loaded, f = 1 kHz
REF
= 5 V, sine wave generated from digital code
REF
Rev. 0 | Page 3 of 28
Page 4
AD5415
Parameter Min Typ Max Unit Conditions
SFDR Performance (Wideband)
Clock = 10 MHz
500 kHz f
100 kHz f
50 kHz f
OUT
OUT
OUT
Clock = 25 MHz
500 kHz f
100 kHz f
50 kHz f
OUT
OUT
OUT
SFDR Performance (Narrow-Band)
Clock = 10 MHz
500 kHz f
100 kHz f
50k Hz f
OUT
OUT
OUT
Clock = 25 MHz
500 kHz f
100 kHz f
50k Hz f
OUT
OUT
OUT
Intermodulation Distortion
Clock = 10 MHz
f1 = 400 kHz, f2 = 500 kHz 65 dB
f1 = 40 kHz, f2 = 50 kHz 72 dB
Clock = 25 MHz
f1 = 400 kHz, f2 = 500 kHz 51 dB
f1 = 40 kHz, f2 = 50 kHz 65 dB
POWER REQUIREMENTS
Power Supply Range 2.5 5.5 V
I
DD
Power Supply Sensitivity1 0.001 %/% ∆VDD = ±5%
55 dB
63 dB
65 dB
50 dB
60 dB
62 dB
73 dB
80 dB
87 dB
70 dB
75 dB
80 dB
10 µA Logic inputs = 0 V or VDD
1
Guaranteed by design and characterization, not subject to production test.
Rev. 0 | Page 4 of 28
Page 5
AD5415
TIMING CHARACTERISTICS
Temperature range for Y Version: −40°C to +125°C. See Figure 2 and Figure 3.
Guaranteed by design and characterization, not subject to production test.
All input signals are specified with tr = tf = 1 ns (10% to 90% of V
V
= 2.5 V to 5.5 V, V
DD
= 5 V, I
REF
2 = 0 V. All specifications T
OUT
Table 2.
Parameter Limit at T
f
50 MHz max Maximum clock frequency
SCLK
MIN
, T
Unit Conditions/Comments
MAX
t1 20 ns min SCLK cycle time
t2 8 ns min SCLK high time
t3 8 ns min SCLK low time
t4 13 ns min
t5 5 ns min Data setup time
t6 4 ns min Data hold time
t7 5 ns min
t8 30 ns min
t9 0 ns min
t10 12 ns min
t11 10 ns min
2
t
12
25 ns min SCLK active edge to SDO valid, strong SDO driver
60 ns min SCLK active edge to SDO valid, weak SDO driver
) and timed from a voltage level of (VIL + VIH)/2.
DD
MIN
to T
, unless otherwise noted.
MAX
1
SYNC falling edge to SCLK falling edge setup time
SYNC rising edge to SCLK falling edge
Minimum
SCLK falling edge to
SYNC high time
LDAC falling edge
LDAC pulse width
SCLK falling edge to
LDAC rising edge
1
Falling or rising edge as determined by the control bits of serial word. Strong or weak SDO driver selected via the control register.
2
Daisy-chain and readback modes cannot operate at maximum clock frequency. SDO timing specifications measured with a load circuit, as shown in . Figure 4
t
1
SCLK
SYNC
LDAC
LDAC
DIN
t
t
4
t
8
t
6
t
5
DB15
1
2
NOTES
1
ASYNCHRONOUS LDAC UPDATE MODE
2
SYNCHRONOUS LDAC UPDATE MODE
ALTERNATIVELY, DATA CAN BE CLOCKED INTO INPUT SHIFT REGISTER ON RISING EDGE OF SCLK AS
DETERMINED BY CONTROL BITS. TIMING AS ABOVE, WITH SCLK INVERTED.
2
Figure 2. Standalone Mode Timing Diagram
t
3
t
7
DB0
t
10
t
9
t
11
04461-0-002
Rev. 0 | Page 5 of 28
Page 6
AD5415
t
1
SCLK
t
t
SYNC
SDIN
SDO
ALTERNATIVELY, DATA CAN BE CLOCKED INTO INPUT SHIFT REGISTER ON RISING EDGE OF SCLK AS
DETERMINED BY CONTROL BITS. IN THIS CASE, DATA WOULD BE CLOCKED OUT OF SDO ON FALLING
EDGE OF SCLK. TIMING AS ABOVE, WITH SCLK INVERTED.
4
DB15
(N)
t
6
t
5
2
t
3
DB15
DB0
(N+1)
(N)
t
12
DB15
(N)
DB0
(N+1)
DB0
(N)
t
7
t
8
04461-0-003
Figure 3. Daisy-Chain and Readback Modes Timing Diagram
200µAI
TO OUTPUT
PIN
C
L
50pF
200µAI
Figure 4. Load Circuit for SDO Timing Specifications
OL
VOH (MIN) + VOL (MAX)
OH
2
04461-0-004
Rev. 0 | Page 6 of 28
Page 7
AD5415
ABSOLUTE MAXIMUM RATINGS
Transient currents of up to 100 mA do not cause SCR latch-up.
= 25°C, unless otherwise noted.
T
A
Table 3.
Parameter Rating
VDD to GND −0.3 V to +7 V
V
, RFB to GND −12 V to +12 V
REF
I
1, I
OUT
2 to GND −0.3 V to +7 V
OUT
Input Current to Any Pin except Supplies ±10 mA
Logic Inputs and Output
Operating Temperature Range
Extended (Y Version)
1
−0.3 V to VDD + 0.3 V
−40°C to +125°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
24-Lead TSSOP θJA Thermal Impedance 128°C/W
Lead Temperature, Soldering
(10 seconds)
IR Reflow, Peak Temperature
(<20 seconds)
300°C
235°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
1
Overvoltages at SCLK,
Current should be limited to the maximum ratings given.
, and DIN are clamped by internal diodes.
SYNC
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 7 of 28
Page 8
AD5415
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
I
OUT
I
OUT
R
FB
R1A
R2A
R2_3A
R3A
V
REF
GND
LDAC
SCLK
SDIN
1A
2A
A
A
1
2
3
4
5
AD5415
6
TOP VIEW
(Not to Scale)
7
8
9
10
11
12
24
1B
I
OUT
23
I
2B
OUT
22
R
B
FB
21
R1B
20
R2B
19
R2_3B
18
R3B
17
V
B
REF
16
V
DD
15
CLR
14
SYNC
13
SDO
04461-0-005
Figure 5. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Function
1 I
2 I
1A DAC A Current Output.
OUT
OUT
2A
DAC A Analog Ground. This pin should normally be tied to the analog ground of the system, but can be biased to
achieve single-supply operation.
3 RFBA
DAC Feedback Resistor Pin. This pin establishes voltage output for the DAC by connecting to the external
amplifier output.
4–7 R1A–R3A
DAC A 4-Quadrant Resistors. These pins allow a number of configuration modes, including bipolar operation, with
minimum external components.
8 V
A DAC A Reference Voltage Input Pin.
REF
9 GND Ground Pin.
10
LDAC Load DAC Input. This pin allows asynchronous or synchronous updates to the DAC output. The DAC is
asynchronously updated when this signal goes low. Alternatively, if this line is held permanently low, an
automatic or synchronous update mode is selected whereby the DAC is updated on the 16th clock falling edge
11 SCLK
when the device is in standalone mode or on the rising edge of
Serial Clock Input. By default, data is clocked into the input shift register on the falling edge of the serial clock
SYNC when in daisy-chain mode.
input. Alternatively, by means of the serial control bits, the device can be configured such that data is clocked into
the shift register on the rising edge of SCLK.
12 SDIN
Serial Data Input. Data is clocked into the 16-bit input register on the active edge of the serial clock input. By
default, on power-up, data is clocked into the shift register on the falling edge of SCLK. The control bits allow the
user to change the active edge to the rising edge.
13 SDO
Serial Data Output. This pin allows a number of parts to be daisy-chained. By default, data is clocked into the shift
register on the falling edge and out via SDO on the rising edge of SCLK. Data is always clocked out on the
alternate edge to loading data to the shift register. Writing the readback control word to the shift register makes
the DAC register contents available for readback on the SDO pin, clocked out on the next 16 opposite clock edges
to the active clock edge.
14
SYNC
Active Low Control Input. The frame synchronization signal for the input data. When
the SCLK and DIN buffers, and the input shift register is enabled. Data is loaded to the shift register on the active
edge of the following clocks. In standalone mode, the serial interface counts clocks, and data is latched to the shift
register on the 16th active clock edge.
15
CLR Active Low Control Input. This pin clears the DAC output, input, and DAC registers. Configuration mode allows the
user to enable the hardware
CLR pin as a clear to zero scale or midscale, as required.
16 VDD Positive Power Supply Input. This part can be operated from a supply of 2.5 V to 5.5 V.
17 V
18–21 R1B–R3B
B DAC B Reference Voltage Input Pin.
REF
DAC B 4-Quadrant Resistors. These pins allow a number of configuration modes, including bipolar operation, with
minimum of external components.
22 RFBB
DAC B Feedback Resistor Pin. This pin establishes voltage output for the DAC by connecting to the external
amplifier output.
23 I
OUT
2B
DAC B Analog Ground. This pin should normally be tied to the analog ground of the system, but can be biased to
achieve single-supply operation.
24 I
1B DAC B Current Output.
OUT
SYNC goes low, it powers on
Rev. 0 | Page 8 of 28
Page 9
AD5415
(
(
)
TERMINOLOGY
Relative Accuracy
Relative accuracy or endpoint nonlinearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
adjusting for zero scale and full scale, and is normally expressed
in LSB or as a percentage of full-scale reading.
Differential Nonlinearity
Differential nonlinearity is the difference in the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ±1 LSB maximum
over the operating temperature range ensures monotonicity.
Gain Error
Gain error or full-scale error is a measure of the output error
between an ideal DAC and the actual device output. For these
DACs, ideal maximum output is V
− 1 LSB. Gain error of the
REF
DACs is adjustable to zero with external resistance.
Output Leakage Current
Output leakage current is current that flows in the DAC ladder
switches when they are turned off. For the I
1 terminal, it can
OUT
be measured by loading all 0s to the DAC and measuring the
1 current. Minimum current flows in the I
I
OUT
2 line when
OUT
the DAC is loaded with all 1s.
Digital Crosstalk
The glitch impulse transferred to the outputs of one DAC in
response to a full-scale code change (all 0s to all 1s and vice
versa) in the input register of the other DAC. It is expressed
in nV-s.
Analog Crosstalk
The glitch impulse transferred to the output of one DAC due to
a change in the output of another DAC. It is measured by
loading one of the input registers with a full-scale code change
LDAC
(all 0s to all 1s and vice versa), while keeping
LDAC
pulse
low and monitor the output of the DAC whose
high. Then
digital code was not changed. The area of the glitch is expressed
in nV-s.
Channel-to-Channel Isolation
The proportion of input signal from one DAC reference input
that appears at the output of the other DAC and is expressed
in dB.
Harmonic Distortion
The DAC is driven by an ac reference. The ratio of the rms sum
of the harmonics of the DAC output to the fundamental value is
the total harmonic distortion (THD). Usually only the lowerorder harmonics are included, such as second to fifth.
Output Capacitance
Capacitance from I
OUT
1 or I
2 to AGND.
OUT
Output Current Settling Time
The amount of time it takes for the output to settle to a specified level for a full-scale input change. For these devices, it is
specified with a 100 Ω resistor to ground.
Digital-to-Analog Glitch Impulse
The amount of charge injected from the digital inputs to the
analog output when the inputs change state. This is normally
specified as the area of the glitch in either pA-s or nV-s depending upon whether the glitch is measured as a current or
voltage signal.
Digital Feedthrough
When the device is not selected, high frequency logic activity on
the device’s digital inputs is capacitively coupled through the
device to show up as noise on the I
pins and subsequently
OUT
into the following circuitry. This noise is digital feedthrough.
Multiplying Feedthrough Error
The error due to capacitive feedthrough from the DAC
reference input to the DAC I
1 terminal when all 0s are
OUT
loaded to the DAC.
THD
2
2
log20
=
4
3
V
1
)
VVVV
+++
5
2
2
2
Intermodulation Distortion
The DAC is driven by two combined sine wave references of
frequencies fa and fb. Distortion products are produced at sum
and difference frequencies of mfa ± nfb, where m, n = 0, 1, 2, 3 ...
Intermodulation terms are those for which m or n is not equal
to zero. The second-order terms include (fa + fb) and (fa − fb)
and the third-order terms are (2fa + fb), (2fa − fb), (f + 2fa +
2fb) and (fa − 2fb). IMD is defined as
IMD log20=
productsdistortiondiffandsumtheofsumrms
lfundamentatheofamplituderms
Compliance Voltage Range
The maximum range of (output) terminal voltage for which the
device provides the specified characteristics.
Rev. 0 | Page 9 of 28
Page 10
AD5415
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
TA = 25°C
0.8
V
= 10V
REF
V
= 5V
DD
0.6
0.4
0.2
0
INL (LSB)
–0.2
–0.4
–0.6
–0.8
–1.0
Figure 6. INL vs. Code (12-Bit DAC)
1.0
TA = 25°C
0.8
V
= 10V
REF
= 5V
V
DD
0.6
0.4
0.2
0
DNL (LSB)
–0.2
–0.4
–0.6
–0.8
–1.0
20001500500 10000 2500 3000 3500 4000
CODE
20001500500 10000 2500 3000 3500 4000
CODE
04461-0-006
04461-0-007
–0.40
TA = 25°C
V
= 10V
REF
V
= 5V
DD
–0.45
–0.50
–0.55
DNL (LSB)
–0.60
–0.65
–0.70
MIN DNL
6534278
REFERENCE VOLTAGE
Figure 9. DNL vs. Reference Voltage
5
4
3
2
1
0
–1
ERROR (mV)
–2
–3
–4
–5
–60 –40 –20 0 20 40 60 80 100 120 140
V
REF
VDD = 5V
V
DD
= 10V
= 2.5V
TEMPERATURE (°C)
910
04461-0-009
04461-0-010
INL (LSB)
0.6
0.5
0.4
0.3
0.2
0.1
–0.1
–0.2
–0.3
Figure 7. DNL vs. Code (12-Bit DAC)
8
7
MAX INL
TA = 25°C
V
= 10V
REF
V
= 5V
0
MIN INL
6534278
REFERENCE VOLTAGE
DD
910
04461-0-008
6
5
4
3
CURRENT (mA)
2
1
0
Figure 8. INL vs. Reference Voltage
Figure 10. Gain Error vs. Temperature
TA = 25°C
VDD = 5V
VDD = 3V
VDD = 2.5V
1.00.50
INPUT VOLTAGE (V)
Figure 11. Supply Current vs. Logic Input Voltage
5.0
4.54.03.53.02.52.01.5
04461-0-011
Rev. 0 | Page 10 of 28
Page 11
AD5415
LEAKAGE (nA)
OUT
I
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
I
1 VDD 5V
OUT
1 VDD 3V
I
OUT
0
4020–20 0–40 60 80 100 120
TEMPERATURE (°C)
04461-0-012
6
TA = 25°C
0
LOADING
–6
ZS TO FS
–12
–18
–24
–30
–36
–42
–48
–54
GAIN (dB)
–60
–66
–72
–78
–84
–90
–96
–102
1 100 1k 10k 100k 1M 10M 100M
ALL ON
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
V
ALL OFF
10
FREQUENCY (Hz)
C
COMP
AD8038 AMPLIFIER
TA = 25°C
V
DD
= ±3.5V
REF
INPUT
= 1.8pF
= 5V
04461-0-015
Figure 12. I
0.50
0.45
0.40
0.35
0.30
0.25
0.20
CURRENT (µA)
0.15
0.10
0.05
0
–60 –40 –20 0 20 40 60 80 100 120 140
1 Leakage Current vs. Temperature
out
TA = 25°C
VDD = 5V
ALL 0s
ALL 1s
VDD = 2.5V
ALL 0sALL 1s
TEMPERATURE (°C)
Figure 13. Supply Current vs. Temperature
14
TA = 25°C
LOADING ZS TO FS
12
V
= 5V
10
DD
04461-0-013
Figure 15. Reference Multiplying Bandwidth vs. Frequency and Code
0.2
0
–0.2
GAIN (dB)
–0.4
TA = 25°C
–0.6
–0.8
= 5V
V
DD
= ±3.5V
V
REF
= 1.8pF
C
COMP
AD8038 AMPLIFIER
10k1k10 1001 100k 1M 10M 100M
FREQUENCY (Hz)
Figure 16. Reference Multiplying Bandwidth–All Ones Loaded
3
TA = 25°C
V
= 5V
DD
0
04461-0-016
(mA)
DD
I
8
6
4
2
0
10k1k10 1001 100k 1M 10M 100M
FREQUENCY (Hz)
V
= 3V
DD
V
= 2.5V
DD
04461-0-014
Figure 14. Supply Current vs. Update Rate
–3
GAIN (dB)
V
= ±2V, AD8038 CC 1.47pF
REF
–6
V
= ±2V, AD8038 CC 1pF
REF
= ±0.15V, AD8038 CC 1pF
V
REF
= ±0.15V, AD8038 CC 1.47pF
V
REF
V
= ±3.51V, AD8038 CC 1.8pF
REF
–9
10k 100k 1M 10M 100M
FREQUENCY (Hz)
Figure 17. Reference Multiplying Bandwidth vs. Frequency and
Compensation Capacitor
04461-0-017
Rev. 0 | Page 11 of 28
Page 12
AD5415
–
–
0.045
7FF TO 800H
0.040
0.035
0.030
0.025
0.020
0.015
0.010
OUTPUT VOLTAGE (V)
0.005
0
–0.005
–0.010
0 20 40 60 80 100 120 140 160 180 200
1.68
–1.69
–1.70
–1.71
–1.72
–1.73
–1.74
OUTPUT VOLTAGE (V)
–1.75
–1.76
800 TO 7FFH
–1.77
0 20 40 60 80 100 120 140 160 180 200
20
TA = 25°C
V
DD
AMP = AD8038
0
–20
–40
–60
PSRR (dB)
–80
–100
–120
1 100 1k 10k 100k 1M 10M
Figure 20. Power Supply Rejection vs. Frequency
VDD = 5V
VDD = 3V
800 TO 7FFH
VDD = 3V
VDD = 5V
TIME (ns)
Figure 18. Midscale Transition, V
7FF TO 800H
VDD = 5V
VDD = 3V
VDD = 5V
VDD = 3V
TIME (ns)
Figure 19. Midscale Transition, V
= 3V
FULL SCALE
10
FREQUENCY (Hz)
TA = 25°C
V
= 0V
REF
AD8038 AMPLIFIER
C
= 1.8pF
COMP
= 0 V
REF
TA = 25°C
= 3.5V
V
REF
AD8038 AMPLIFIER
= 1.8pF
C
COMP
= 3.5 V
REF
ZERO SCALE
04461-0-018
04461-0-019
04461-0-020
60
TA = 25°C
= 3V
V
DD
= 3.5V p-p
V
REF
–65
–70
–75
THD + N (dB)
–80
–85
–90
100 1k1 10 10k 100k 1M
FREQUENCY (Hz)
Figure 21. THD and Noise vs. Frequency
100
MCLK = 1MHz
80
MCLK = 200kHz
60
MCLK = 0.5MHz
SFDR (dB)
40
20
0
0 20 40 60 80 100 120 140 160 180 200
f
(kHz)
OUT
Figure 22. Wideband SFDR vs. f
TA = 25°C
V
= 3.5V
REF
AD8038 AMPLIFIER
Frequency
OUT
90
80
70
60
50
40
SFDR (dB)
30
20
10
MCLK = 5MHz
MCLK = 10MHz
MCLK = 25MHz
TA = 25°C
= 3.5V
V
REF
0
0 100 200 300 400 500 600 700 800 900 1000
f
(kHz)
OUT
Figure 23. Wideband SFDR vs. f
AD8038 AMPLIFIER
Frequency
OUT
04461-0-021
04461-0-022
04461-0-023
Rev. 0 | Page 12 of 28
Page 13
AD5415
0
–10
–20
–30
–40
–50
SFDR (dB)
–60
–70
–80
–90
0
24681012
Figure 24. Wideband SFDR, f
0
–10
–20
–30
–40
–50
SFDR (dB)
–60
–70
–80
–90
–100
0.5 1.5 3.0 3.5 4.01.0 2.0 2.5 4.5 5.0
0
Figure 25. Wideband SFDR, f
0
–10
–20
–30
–40
–50
SFDR (dB)
–60
–70
–80
–90
0.5 1.5 3.0 3.5 4.01.0 2.0 2.5 4.5 5.0
0
Figure 26. Wideband SFDR, f
FREQUENCY (MHz)
= 100 kHz, Clock = 25 MHz
OUT
FREQUENCY (MHz)
= 500 kHz, Clock = 10 MHz
OUT
FREQUENCY (MHz)
= 50 kHz, Clock = 10 MHz
OUT
TA = 25°C
V
= 5V
DD
AMP = AD8038
65k CODES
TA = 25°C
= 5V
V
DD
AMP = AD8038
65k CODES
TA = 25°C
VDD = 5V
AMP = AD8038
65k CODES
04461-0-024
04461-0-025
04461-0-026
0
–10
–20
–30
–40
–50
–60
SFDR (dB)
–70
–80
–90
–100
250 750300 350 400 650 700
Figure 27. Narrow-Band Spectral Response, f
450 500 550 600
FREQUENCY (MHz)
OUT
= 500 kHz, Clock = 25 MHz
20
0
–20
–40
–60
SFDR (dB)
–80
–100
–120
50 150
60 70 80 130 140
Figure 28. Narrow-Band SFDR, f
90 100 110 120
FREQUENCY (MHz)
= 100 kHz, MCLK = 25 MHz
OUT
0
–10
–20
–30
–40
–50
(dB)
–60
–70
–80
–90
–100
70 12075 80 85 115
Figure 29. Narrow-Band IMD, f
90 100 105 110
95
FREQUENCY (MHz)
= 90 kHz, 100 kHz, Clock = 10 MHz
OUT
TA = 25°C
V
= 3V
DD
AMP = AD8038
65k CODES
TA = 25°C
= 3V
V
DD
AMP = AD8038
65k CODES
TA = 25°C
V
= 3V
DD
AMP = AD8038
65k CODES
04461-0-027
04461-0-028
04461-0-029
Rev. 0 | Page 13 of 28
Page 14
AD5415
0
–10
–20
–30
–40
–50
(dB)
–60
–70
–80
–90
–100
0 400
50 300 350100 150 200 250
Figure 30. Wideband IMD, f
TA = 25°C
V
= 5V
DD
AMP = AD8038
65k CODES
FREQUENCY (kHz)
= 90 kHz, 100 kHz, Clock = 25 MHz
OUT
04461-0-030
300
ZERO SCALE LOADED TO DAC
250
200
150
100
OUTPUT NOISE (nV/ Hz)
50
0
MIDSCALE LOADED TO DAC
FULL SCALE LOADED TO DAC
100 1k 10k 100k
FREQUENCY (Hz)
TA = 25°C
AMP = AD8038
Figure 31. Output Noise Spectral Density
04461-0-031
Rev. 0 | Page 14 of 28
Page 15
AD5415
V
A
GENERAL DESCRIPTION
DAC SECTION
The AD5415 is a 12-bit, dual-channel, current output DAC
consisting of standard inverting R to 2R ladder configuration. A
simplified diagram of one DAC channel for the AD5415 is
shown in Figure 32. The feedback resistor R
has a value of 2R.
FB
The value of R is typically 10 kΩ (minimum 8 kΩ and
maximum 12 kΩ). If I
OUT
1 and I
2 are kept at the same
OUT
potential, a constant current flows in each ladder leg, regardless
of the digital input code. Therefore, the input resistance
presented at V
A
REF
Access is provided to the V
is always constant.
REF
RR R
2R
2R
S1
DAC DATA LATCHES
2R
S2
S3
AND DRIVERS
Figure 32. Simplified Ladder
, RFB, I
REF
OUT
2R
S12
1, and I
2R
2R
2 terminals of
OUT
R
I
I
OUT
OUT
A
FB
1A
2A
04461-0-032
the DAC, making the device extremely versatile and allowing it
to be configured in several different operating modes, for
example, to provide a unipolar output, bipolar output, or in
single-supply modes of operation in unipolar mode or
4-quadrant multiplication in bipolar mode.
UNIPOLAR MODE
Using a single op amp, these devices can easily be configured to
provide 2-quadrant multiplying operation or a unipolar output
voltage swing, as shown in Figure 33. When an output amplifier
is connected in unipolar mode, the output voltage is given by
V
DD
R1A
R1
2R
R2A
GND
R2_3A
R3A
R2
2R
R3
2R
A SCLKSYNC
REF
AD5415
12-BIT DAC A
R
V
= −V
OUT
REF
where:
D is the fractional representation of the digital word loaded to
the DAC, in the range of 0 to 4095.
n is the number of bits.
Note that the output voltage polarity is opposite the V
polarity for dc reference voltages.
These DACs are designed to operate with either negative or
positive reference voltages. The V
the internal digital logic to drive the DAC switches’ on and off
states.
These DACs are also designed to accommodate ac reference
input signals in the range of −10 V to +10 V.
With a fixed 10 V reference, the circuit in Figure 32 gives a
unipolar 0 V to −10 V output voltage swing. When V
signal, the circuit performs 2-quadrant multiplication.
Table 5 shows the relationship between digital code and
expected output voltage for unipolar operation.
Table 5. Unipolar Code Table
Digital Input Analog Output (V)
1111 1111 −V
1000 0000 −V
0000 0001 −V
0000 0000 −V
R
FB
2R
GNDSDINV
I
I
OUT
OUT
RFBA
1A
C1
A1
2A
AGND
× D/2
V
OUT
n
= 0V TO –V
power pin is used only by
DD
(4095/4096)
REF
(2048/4096) = −V
REF
(1/4096)
REF
(0/4096) = 0
REF
IN
REF
is an ac
IN
REF
/2
uCONTROLLER
NOTES:
1
DAC B OMITTED FOR CLARITY.
2
C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED,
IF A1 IS A HIGH SPEED AMPLIFIER.
AGND
04461-0-033
Figure 33. Unipolar Operation
Rev. 0 | Page 15 of 28
Page 16
AD5415
A
BIPOLAR OPERATION
In some applications, it might be necessary to generate full
4-quadrant multiplying operation or a bipolar output swing.
This can be easily accomplished by using another external
amplifier and the on chip 4-quadrant resistors, as shown in
Figure 34.
When in bipolar mode, the output voltage is given by
V
= V
OUT
REF
where D is the fractional representation of the digital word
loaded to the DAC, in the range of 0 to 4095.
n is the number of bits.
When V
is an ac signal, the circuit performs 4-quadrant
IN
multiplication.
Table 6 shows the relationship between digital code and the
expected output voltage for bipolar operation.
Table 6. Bipolar Code Table
Digital Input Analog Output (V)
1111 1111 +V
1000 0000 0
0000 0001 −V
0000 0000 V
× D/2
n − 1
−V
REF
REF
(2047/2048)
REF
(2047/2048)
REF
(2048/2048)
STABILITY
In the I-to-V configuration, the I
inverting node of the op amp must be connected as close as
possible, and proper PCB layout techniques must be employed.
Because every code change corresponds to a step function, gain
peaking can occur if the op amp has limited GBP and there is
excessive parasitic capacitance at the inverting node. This
parasitic capacitance introduces a pole into the open loop
response that can cause ringing or instability in the closed loop
application’s circuit.
An optional compensation capacitor, C1, can be added in
parallel with R
for stability, as shown in Figure 33 and
FB
Figure 34. Too small a value of C1 can produce ringing at the
output, while too large a value can adversely affect the settling
time. C1 should be found empirically, but 1 pF to 2 pF is
generally adequate for the compensation.
of the DAC and the
OUT
V
DD
GND
R1A
R1
2R
V
R2A
IN
R2_3A
R3A
A1
R2
2R
R3
2R
A SCLKSYNC
REF
NOTES:
1
DAC B OMITTED FOR CLARITY.
2
C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED,
IF A1 IS A HIGH SPEED AMPLIFIER.
R
FB
2R
AD5415
12-BIT DAC A
R
uCONTROLLER
R
I
OUT
I
OUT
GNDSDINV
AGND
A
FB
C1
1A
A1
2A
AGND
V
OUT
=–VIN TO +V
IN
04461-0-034
Figure 34. Bipolar Operation
Rev. 0 | Page 16 of 28
Page 17
AD5415
V
V
V
SINGLE-SUPPLY APPLICATIONS
VOLTAGE SWITCHING MODE OF OPERATION
Figure 35 shows these DACs operating in the voltage switching
mode. The reference voltage, V
I
2 is connected to AGND, and the output voltage is available
OUT
at the V
terminal. In this configuration, a positive reference
REF
, is applied to the I
IN
OUT
1 pin,
voltage results in a positive output voltage, making singlesupply operation possible. The output from the DAC is voltage
at a constant impedance (the DAC ladder resistance). Therefore,
an op amp is necessary to buffer the output voltage. The
reference input no longer sees a constant input impedance, but
one that varies with code. So, the voltage input should be driven
from a low impedance source.
V
DD
R
V
FB
I
IN
NOTES
1. SIMILAR CONFIGURATION FOR DACB
2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
I
OUT
OUT
DD
1
2
GND
V
REF
R
R
1
2
V
OUT
04461-0-035
Figure 35. Single-Supply Voltage Switching Mode
Note that VIN is limited to low voltages, because the switches in
the DAC ladder no longer have the same source-drain drive
voltage. As a result, their on resistance differs and this degrades
the integral linearity of the DAC. Also, V
must not go negative
IN
by more than 0.3 V or an internal diode is turned on, exceeding
the maximum ratings of the device. In this type of application,
the full range of multiplying capability of the DAC is lost.
POSITIVE OUTPUT VOLTAGE
The output voltage polarity is opposite to the V
dc reference voltages. To achieve a positive voltage output, an
applied negative reference to the input of the DAC is preferred
over the output inversion through an inverting amplifier
because of the resistors’ tolerance errors. To generate a negative
reference, the reference can be level-shifted by an op amp such
that the V
and GND pins of the reference become the virtual
OUT
ground and −2.5 V, respectively, as shown in Figure 36.
polarity for
REF
ADR03
V
OUTVIN
GND
+5V
–2.5V
1/2 AD8552
–5V
NOTES:
1
ADDITIONAL PINS OMITTED FOR CLARITY.
2
C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED,
IF A1 IS A HIGH SPEED AMPLIFIER.
Figure 36. Positive Voltage Output with Minimum of Components
ADDING GAIN
In applications where the output voltage is required to be
greater than V
amplifier, or it can also be achieved in a single stage. It is
important to take into consideration the effect of temperature
coefficients of the thin film resistors of the DAC. Simply placing
a resistor in series with the R
temperature coefficients, resulting in larger gain temperature
coefficient errors. Instead, the circuit in Figure 37 is a recommended method of increasing the gain of the circuit. R
R
should all have similar temperature coefficients, but they
3
need not match the temperature coefficients of the DAC. This
approach is recommended in circuits where gains of greater
than 1 are required.
R2
IN
V
NOTES:
1
ADDITIONAL PINS OMITTED FOR CLARITY.
2
C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED,
IF A1 IS A HIGH SPEED AMPLIFIER.
Figure 37. Increasing the Gain of the Current Output DAC
DIVIDER OR PROGRAMMABLE GAIN ELEMENT
Current-steering DACs are very flexible and lend themselves to
many different applications. If this type of DAC is connected as
the feedback element of an op amp and R
resistor, as shown in Figure 38, then the output voltage is
inversely proportional to the digital input fraction, D. For D
equal to 1 − 2
VDD = 5V
V
R
DD
FB
I
12-BIT DAC
V
REF
GND
, gain can be added with an additional external
IN
DD
V
DD
12-BIT DAC
REF
GND
n
, the output voltage is
OUT
I
OUT
resistor causes mismatches in the
FB
R
FB
I
1
OUT
2
I
OUT
C1
1
2
1/2 AD8552
C1
R3
R2
is used as the input
FB
V
= 0 TO +2.5V
OUT
GAIN =
R1 =
, R2, and
1
V
OUT
R2R3
R2 + R3
R2 + R3
R2
04461-0-036
04461-0-037
= −VIN/D = −VIN/(1 −2−n)
V
OUT
Rev. 0 | Page 17 of 28
Page 18
AD5415
V
IN
I
1
OUT
2
I
OUT
NOTE:
1
ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 38. Current-Steering DAC Used as a Divider or
Programmable Gain Element
V
DD
V
R
DD
FB
V
REF
GND
V
OUT
04461-0-038
As D is reduced, the output voltage increases. For small values
of the digital fraction, D, it is important to ensure that the
amplifier does not saturate and also that the required accuracy
is met. For example, an 8-bit DAC driven with the binary code
0x10 (0001 0000), that is, 16 decimal, in the circuit of Figure 37
should cause the output voltage to be 16 times V
. However, if
IN
the DAC has a linearity specification of ±0.5 LSB, then D can, in
fact, have a weight anywhere in the range 15.5/256 to 16.5/256,
so that the possible output voltage is in the range 15.5 V
16.5 V
, an error of 3% even though the DAC itself has a
IN
to
IN
maximum error of 0.2%.
DAC leakage current is also a potential error source in divider
circuits. The leakage current must be counterbalanced by an
opposite current supplied from the op amp through the DAC.
Because only a fraction D of the current into the V
is routed to the I
1 terminal, the output voltage has to change
OUT
terminal
REF
as follows:
Output Error Voltage Due to DAC Leakage = (Leakage × R)/D
where R is the DAC resistance at the V
terminal.
REF
For a DAC leakage current of 10 nA, R = 10 kΩ, and a gain
(that is, 1/D) of 16, the error voltage is 1.6 mV.
REFERENCE SELECTION
When selecting a reference for use with the AD54xx series of
current output DACs, pay attention to the reference’s output
voltage temperature coefficient specification. This parameter
affects not only the full-scale error, but can also affect the
linearity (INL and DNL) performance. The reference temperature coefficient should be consistent with the system accuracy
specifications. For example, an 8-bit system required to hold its
overall specification to within 1 LSB over the temperature range
0°C to 50°C dictates that the maximum system drift with
temperature should be less than 78 ppm/°C. A 12-bit system
with the same temperature range to overall specification within
2 LSB requires a maximum drift of 10 ppm/°C. By choosing a
precision reference with a low output temperature coefficient,
this error source can be minimized. Table 7 suggests some of
the references available from Analog Devices that are suitable
for use with this range of current output DACs.
AMPLIFIER SELECTION
The primary requirement for the current-steering mode is an
amplifier with low input bias currents and low input offset
voltage. The input offset voltage of an op amp is multiplied by
the variable gain (due to the code-dependent output resistance
of the DAC) of the circuit. A change in this noise gain between
two adjacent digital fractions produces a step change in the
output voltage due to the amplifier’s input offset voltage. This
output voltage change is superimposed upon the desired change
in output between the two codes and gives rise to a differential
linearity error, which, if large enough, could cause the DAC to
be nonmonotonic.
The input bias current of an op amp also generates an offset at
the voltage output as a result of the bias current flowing in the
feedback resistor, R
low enough to prevent any significant errors in 12-bit
applications.
Common-mode rejection of the op amp is important in voltage
switching circuits, because it produces a code-dependent error
at the voltage output of the circuit. Most op amps have adequate
common-mode rejection for use at 12-bit resolution.
Provided that the DAC switches are driven from true wideband
low impedance sources (V
Consequently, the slew rate and settling time of a voltage
switching DAC circuit is determined largely by the output op
amp. To obtain minimum settling time in this configuration, it
is important to minimize capacitance at the V
output node in this application) of the DAC. This is done by
using low inputs, capacitance buffer amplifiers, and careful
board design.
Most single-supply circuits include ground as part of the analog
signal range, which in turn requires an amplifier that can handle
rail-to-rail signals. A large range of single-supply amplifiers is
available from Analog Devices.
. Most op amps have input bias currents
FB
and AGND), they settle quickly.
IN
node (voltage
REF
Rev. 0 | Page 18 of 28
Page 19
AD5415
Table 7. ADI Precision References for Use with AD54xx DACs
Reference Output Voltage (V) Initial Tolerance (%) Temp. Drift (ppm/°C) 0.1 Hz to 10 Hz Noise Package
ADR01 10 0.1 3 20 µV p-p SC70, TSOT, SOIC
ADR02 5 0.1 3 10 µV p-p SC70, TSOT, SOIC
ADR03 2.5 0.2 3 10 µV p-p SC70, TSOT, SOIC
ADR425 5 0.04 3 3.4 µV p-p MSOP, SOIC
Table 8. Precision ADI Op Amps for Use with AD54xx DACs
Part No. Max Supply Voltage (V) VOS (max) µV IB (max) nA GBP MHz Slew Rate (V/µs)
OP97 ±20 25 0.1 0.9 0.2
OP1177 ±18 60 2 1.3 0.7
AD8551 ±6 5 0.05 1.5 0.4
Table 9. High Speed ADI Op Amps for Use with AD54xx DACs
Part No. Max Supply Voltage (V) VOS (max) µV IB (max) nA BW @ ACL MHz Slew Rate (V/µs)
AD8065 ±12 1500 0.01 145 180
AD8021 ±12 1000 1000 200 100
AD8038 ±5 3000 0.75 350 425
Rev. 0 | Page 19 of 28
Page 20
AD5415
SERIAL INTERFACE
The AD5415 has an easy-to-use 3-wire interface, which is
compatible with SPI, QSPI, MICROWIRE, and DSP interface
standards. Data is written to the device in 16-bit words. Each
16-bit word consists of four control bits and 12 data bits, as
shown in Figure 39.
LOW POWER SERIAL INTERFACE
To minimize the power consumption of the device, the interface
powers up fully only when the device is being written to, that is,
on the falling edge of
are powered down on the rising edge of
DAC Control Bits C3 to C0
Control bits C3 to C0 allow control of various functions of the
DAC, as shown in Table 11. Default settings of the DAC at
power-on are as follows. Data is clocked into the shift register
on falling clock edges; daisy-chain mode is enabled. The device
powers on with zero-scale load to the DAC register and I
lines. The DAC control bits allow the user to adjust certain
features at power-on. For example, daisy-chaining can be
disabled when not in use, active clock edge can be changed to
rising edge, and DAC output can be cleared to either zero scale
or midscale. The user can also initiate a readback of the DAC
register contents for verification purposes.
CONTROL REGISTER
(Control Bits = 1101)
While maintaining software compatibility with the singlechannel current output DACs (AD5426/AD5433/AD5443), this
DAC also features some additional interface functionality.
Simply set the control bits to 1101 to enter control register
mode. Figure 40 shows the contents of the control register, the
functions of which are described in the following sections.
SYNC
. The SCLK and DIN input buffers
SYNC
.
OUT
SDO Control (SDO1 and SDO2)
The SDO bits enable the user to control the SDO output driver
strength, disable the SDO output, or configure it as an opendrain driver. The strength of the SDO driver affects the timing
of t
and, when stronger, allows a faster clock cycle to be used.
12
Table 10. SDO Control Bits
SDO2 SDO1 Function
0 0 Full SDO Driver
0 1 SDO Configured as Open Drain
1 0 Weak SDO Driver
1 1 Disable SDO Output
Daisy-Chain Control (DSY)
DSY enables or disables daisy-chain mode. A 1 enables daisychain mode; a 0 disables it. When disabled, a readback request is
accepted, SDO is automatically enabled, the DAC register
contents of the relevant DAC are clocked out on SDO, and,
when complete, SDO is disabled again.
Hardware
The default setting for the hardware
CLR
Bit (HCLR)
CLR
pin is to clear the
registers and DAC output to zero code. A 1 in the HCLR bit
clears the DAC outputs to midscale; a 0 clears them to
zero scale.
Active Clock Edge (SCLK)
The default active clock edge is the falling edge. Write a 1 to this
bit to clock data in on the rising edge; write a 0 to clock it on the
falling edge.
DB0 (LSB)DB15 (MSB)
C3 C2
C0 DB11 DB10 DB9 DB8 DB7
C1
Figure 39. AD5415 12-Bit Input Shift Register Contents
DB6 DB5 DB4 DB3 DB2 DB1 DB0
DATA BITSCONTROL BITS
04461-0-039
DB0 (LSB)DB15 (MSB)
11
CONTROL BITS
1 SDO1 SDO2 DSY HCLR SCLK
0
Figure 40. Control Register Loading Sequence
XXXXXXX
04461-0-040
Rev. 0 | Page 20 of 28
Page 21
AD5415
Table 11. DAC Control Bits
C3 C2 C1 C0 DAC Function
0 0 0 0 A and B No Operation (Power-On Default)
0 0 0 1 A Load and Update
0 0 1 0 A Initiate Readback
0 0 1 1 A Load Input Register
0 1 0 0 B Load and Update
0 1 0 1 B Initiate Readback
0 1 1 0 B Load Input Register
0 1 1 1 A and B Update DAC Outputs
1 0 0 0 A and B Load Input Registers
1 0 0 1 – Daisy-Chain Disable
1 0 1 0 – Clock Data to Shift Register on Rising Edge
1 0 1 1 – Clear DAC Output to Zero
1 1 0 0 – Clear DAC Output to Midscale
1 1 0 1 – Control Word
1 1 1 0 – Reserved
1 1 1 1 – No Operation
SYNC FUNCTION
SYNC
is an edge-triggered input that acts as a frame synchroni-
zation signal and chip enable. Data can be transferred into the
SYNC
device only while
SYNC
should be taken low, observing the minimum
falling to SCLK falling edge setup time, t
is low. To start the serial data transfer,
SYNC
.
4
DAISY-CHAIN MODE
Daisy-chain mode is the default mode at power-on. To disable
the daisy-chain function, write 1001 to the control word. In
daisy-chain mode, the internal gating on SCLK is disabled. The
SCLK is continuously applied to the input shift register when
SYNC
is low. If more than 16 clock pulses are applied, the data
ripples out of the shift register and appears on the SDO line.
This data is clocked out on the rising edge of SCLK and is valid
for the next device on the falling edge (default). By connecting
this line to the DIN input on the next device in the chain, a
multidevice interface is constructed. Sixteen clock pulses are
required for each device in the system. Therefore, the total
number of clock cycles must equal 16N, where N is the total
number of devices in the chain. (See the timing diagram in
Figure 4.)
When the serial transfer to all devices is complete,
be taken high. This prevents any further data from being
clocked into the input shift register. A burst clock containing the
exact number of clock cycles can be used and
some time later. After the rising edge of
SYNC
cally transferred from each device’s input shift register to the
addressed DAC.
SYNC
should
SYNC
taken high
, data is automati-
When control bits are 0000, the device is in no-operation mode.
This might be useful in daisy-chain applications, where the user
does not want to change the settings of a particular DAC in the
chain. Simply write 0000 to the control bits for that DAC, and
the following data bits are ignored.
STANDALONE MODE
After power-on, writing 1001 to the control word disables daisychain mode. The first falling edge of
SYNC
resets a counter that
counts the number of serial clocks to ensure that the correct
number of bits is shifted in and out of the serial shift registers. A
SYNC
edge during the 16-bit write cycle causes the device to
abort the current write cycle.
After the falling edge of the 16th SCLK pulse, data is automatically transferred from the input shift register to the DAC. In
order for another serial transfer to take place, the counter must
be reset by the falling edge of
SYNC
.
LDAC FUNCTION
LDAC
The
updates to the DAC output. The DAC is asynchronously
updated when this signal goes low. Alternatively, if this line is
held permanently low, an automatic or synchronous update
mode is selected, whereby the DAC is updated on the 16th clock
falling edge when the device is in standalone mode or on the
rising edge of
Software
Load and update mode also functions as a software update
function, irrespective of the voltage level on the
function allows asynchronous or synchronous
SYNC
when in daisy-chain mode.
LDAC
Function
LDAC
pin.
Rev. 0 | Page 21 of 28
Page 22
AD5415
MICROPROCESSOR INTERFACING
Microprocessor interfacing to the AD5415 DAC is through a
serial bus that uses standard protocol compatible with microcontrollers and DSP processors. The communications channel is
a 3-wire interface consisting of a clock signal, a data signal, and
a synchronization signal. The AD5415 requires a 16-bit word,
with the default being data valid on the falling edge of SCLK,
but this is changeable using the control bits in the data-word.
ADSP-21xx to AD5415 Interface
The ADSP-21xx family of DSPs is easily interfaced to the
AD5415 DAC without the need for extra glue logic. Figure 40
is an example of an SPI interface between the DAC and the
ADSP-2191M. SCK of the DSP drives the serial data line, DIN.
SYNC is driven from one of the port lines, in this case SPIxSEL.
ADSP-2191*
SPIxSEL
MOSI
SCK
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 41. ADSP-2191 SPI to AD5415 Interface
A serial interface between the DAC and DSP SPORT is shown
in Figure 42. In this interface example, SPORT0 is used to
transfer data to the DAC shift register. Transmission is initiated
by writing a word to the Tx register after the SPORT has been
enabled. In a write sequence, data is clocked out on each rising
edge of the DSP’s serial clock and clocked into the DAC input
shift register on the falling edge of its SCLK. The update of the
DAC output takes place on the rising edge of the SYNC signal.
ADSP-2101/
ADSP-2103/
ADSP-2191*
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 42. ADSP-2101/ADSP-2103/ADSP-2191 SPORT to AD5415 Interface
TFS
DT
SCLK
Communication between two devices at a given clock speed is
possible when the following specifications are compatible:
frame sync delay and frame sync setup-and-hold, data delay and
data setup-and-hold, and SCLK width. The DAC interface
expects a t
(SYNC falling edge to SCLK falling edge setup time)
4
of 13 ns minimum. See the ADSP-21xx User Manual for
information on clock and frame sync frequencies for the
SPORT register.
Table 12 shows the set up for the SPORT control register.
AD5415*
SYNC
SDIN
SCLK
AD5415*
SYNC
SDIN
SCLK
Table 12. SPORT Control Register Setup
Name Setting Description
TFSW 1 Alternate framing
INVTFS 1 Active low frame signal
DTYPE 00 Right-justify data
ISCLK 1 Internal serial clock
TFSR 1 Frame every word
ITFS 1 Internal framing signal
SLEN 1111 16-bit data-word
80C51/80L51 to AD5415 Interface
A serial interface between the DAC and the 80C51 is shown in
Figure 43. TXD of the 80C51 drives SCLK of the DAC serial
interface, while RXD drives the serial data line, DIN. P3.3 is a
bit-programmable pin on the serial port and is used to drive
SYNC. When data is to be transmitted to the switch, P3.3 is
taken low. The 80C51/80L51 transmits data only in 8-bit bytes;
therefore, only eight falling clock edges occur in the transmit
cycle. To load data correctly to the DAC, P3.3 is left low after the
first eight bits are transmitted, and a second write cycle is
initiated to transmit the second byte of data. Data on RXD is
04461-0-041
clocked out of the microcontroller on the rising edge of TXD
and is valid on the falling edge. As a result, no glue logic is
required between the DAC and microcontroller interface. P3.3
is taken high following the completion of this cycle. The 80C51
provides the LSB of its SBUF register as the first bit in the data
stream. The DAC input register requires its data with the MSB
as the first bit received. The transmit routine should take this
into account.
8051*
TxD
RxD
P1.1
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 43. 80C51/80L51 to AD5415 Interface
SCLK
SDIN
SYNC
AD5415*
04461-0-043
MC68HC11 Interface to AD5415 Interface
04461-0-042
Figure 44 is an example of a serial interface between the DAC
and the MC68HC11 microcontroller. The serial peripheral
interface (SPI) on the MC68HC11 is configured for master
mode (MSTR) = 1, Clock polarity bit (CPOL) = 0, and the clock
phase bit (CPHA) = 1. The SPI is configured by writing to the
SPI control register (SPCR); see the 68HC11 User Manual. SCK
of the 68HC11 drives the SCLK of the DAC interface, the MOSI
output drives the serial data line (DIN) of the AD5516.
The SYNC signal is derived from a port line (PC7). When data
is being transmitted to the AD5516, the SYNC line is taken low
(PC7). Data appearing on the MOSI output is valid on the
falling edge of SCK. Serial data from the 68HC11 is transmitted
in 8-bit bytes with only eight falling clock edges occurring in
Rev. 0 | Page 22 of 28
Page 23
AD5415
the transmit cycle. Data is transmitted MSB first. To load data to
the DAC, PC7 is left low after the first eight bits are transferred,
and a second serial write operation is performed to the DAC.
PC7 is taken high at the end of this procedure.
MICROWIRE*
SK
SO
CS
AD5415*
SCLK
SDIN
SYNC
MC68HC11*
PC7
SCK
MOSI
*ADDITIONAL PINS OMITTED FOR CLARITY
AD5415*
SYNC
SCLK
SDIN
Figure 44. 68HC11/68L11 to AD5415 Interface
If the user wants to verify the data previously written to the
input shift register, the SDO line can be connected to MISO of
the MC68HC11, and, with SYNC low, the shift register clocks
data out on the rising edges of SCLK.
MICROWIRE to AD5415 Interface
Figure 45 shows an interface between the DAC and any
MICROWIRE-compatible device. Serial data is shifted out on
the falling edge of the serial clock, SK, and is clocked into the
DAC input shift register on the rising edge of SK, which
corresponds to the falling edge of the DAC’s SCLK.
*ADDITIONAL PINS OMITTED FOR CLARITY
04461-0-045
Figure 45. MICROWIRE to AD5415 Interface
PIC16C6x/7x to AD5415 Interface
The PIC16C6x/7x synchronous serial port (SSP) is configured
04461-0-044
as an SPI master with the clock polarity bit (CKP) = 0. This is
done by writing to the synchronous serial port control register
(SSPCON); see the PIC16/17 Microcontroller User Manual. In
this example, I/O port RA1 is used to provide a SYNC signal
and enable the serial port of the DAC. This microcontroller
transfers only eight bits of data during each serial transfer
operation; therefore, two consecutive write operations are
required. Figure 46 shows the connection diagram.
PIC16C6x/7x*
SCK/RC3
SDI/RC4
RA1
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 46. PIC16C6x/7x to AD5415 Inter face
SCLK
SDIN
SYNC
AD5415*
04461-0-046
Rev. 0 | Page 23 of 28
Page 24
AD5415
PCB LAYOUT AND POWER SUPPLY DECOUPLING
In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to
ensure the rated performance. The printed circuit board on
which the AD5415 is mounted should be designed so that the
analog and digital sections are separated, and confined to
certain areas of the board. If the DAC is in a system where
multiple devices require an AGND-to-DGND connection, the
connection should be made at one point only. The star ground
point should be established as close as possible to the device.
The DAC should have ample supply bypassing of 10 µF in
parallel with 0.1 µF on the supply located as close to the package
as possible, ideally right up against the device. The 0.1 µF
capacitor should have low effective series resistance (ESR) and
effective series inductance (ESI), like the common ceramic types
that provide a low impedance path to ground at high
frequencies, to handle transient currents due to internal logic
switching. Low ESR 1 µF to 10 µF tantalum or electrolytic
capacitors should also be applied at the supplies to minimize
transient disturbance and filter out low frequency ripple.
Fast switching signals such as clocks should be shielded with
digital ground to avoid radiating noise to other parts of the
board, and should never be run near the reference inputs.
Avoid crossover of digital and analog signals. Traces on opposite
sides of the board should run at right angles to each other. This
reduces the effects of feedthrough on the board. A microstrip
technique is by far the best, but not always possible with a
double-sided board. In this technique, the component side of
the board is dedicated to the ground plane while signal traces
are placed on the soldered side.
It is good practice to employ compact, minimum lead length
PCB layout design. Leads to the input should be as short as
possible to minimize IR drops and stray inductance.
The PCB metal traces between V
matched to minimize gain error. To maximize on high frequency performance, the I-to-V amplifier should be located
as close to the device as possible.
EVALUATION BOARD FOR THE DAC
The evaluation board consists of an AD5415 DAC and a
current-to-voltage amplifier, AD8065. Included on the
evaluation board is a 10 V reference, ADR01. An external
reference can also be applied via an SMB input.
The evaluation kit consists of a CD-ROM with self-installing
PC software to control the DAC. The software allows the user to
write a code to the device.
POWER SUPPLIES FOR THE EVALUATION BOARD
The board requires ±12 V and +5 V supplies. The +12 V VDD
and V
used to power the DAC (V
Both supplies are decoupled to their respective ground plane
with 10 µF tantalum and 0.1 µF ceramic capacitors.
and RFB should also be
REF
are used to power the output amplifier, while the +5 V is
SS
) and transceivers (VCC).
DD1
Rev. 0 | Page 24 of 28
Page 25
AD5415
TP2
OUT
V
B
J2
C3
DD
V
10µF
C4
0.1µF
+V
V
IN
OUT
A
V
U2
C4
LK3
REF
21
5
TRIM
ADR01AR
1
0.1µF
B
IN
V
J10
20
R2B
R1B
GND
22
10µF
+
0.1µF
4
C18
C17
C19
SS
V
1.8pF
10µF
C22
6
4
V–
2
+
0.1µF
C23
SS
V
+
10µF
0.1µF
C20
C21
7
V+
3
DD
V
U4
0.1µF
10µF
U5
3
2
V–
V+
7
4
6
+
C24
C25
DD
V
AD8065AR
24
23
19
18
17
R2–3B
B
R3B
REF
V
B
2B
1B
FB
R
OUT
OUT
I
I
3
A
OUT
J1
V
TP1
10µF
+
0.1µF
C8
SS
V
1.8pF
FB
6
4
V–
2
4
1
1A
R1A
OUT
I
C7
C8
3
A
R
+
10µF
0.1µF
C9
C10
7
V+
3
DD
V
U3
2
5
6
2A
R2A
OUT
R2–3A
I
4
A
LK2
REF
V
J8
7
8
A
R3A
REF
V
U1
1
DD
V
1
DD
V
1
DD
V
AD5415
R1
10kΩ
R2
10kΩ
R3
10kΩ
SCLK
CLR
SDO
LDAC
SYNC
SDIN
SCLK
11
12
14
10
13
15
P1–19
P1–20
P1–21
P1–22
P1–23
P1–24
P1–25
P1–26
P1–27
P1–28
P1–29
P1–30
J3
J4
AGND
C14
+
1
DD
V
SS
V
C16
10µF
10µF
+
J5
J6
J7
CLR
SDIN
SDO
LDAC
SYNC
DD
V
C12
10µF
+
AB
SCLK
LK1
CLR
SDO
LDAC
SYNC
SDIN
C11
C13
0.1µF
0.1µF
P2–3
P2–2
P2–1
C15
0.1µF
P2–4
DD
V
16
1
DD
+
V
GND
9
C1
0.1µF
C2
10µF
P1–2
P1–3
P1–4
P1–5
P1–13
P1–6
04461-0-047
Figure 47. Schematic of the AD5415 Evaluation Board
Rev. 0 | Page 25 of 28
Page 26
AD5415
Figure 48. Component-Side Artwork
04461-0-048
Figure 49. Silkscreen—Component-Side View ( Top)
Rev. 0 | Page 26 of 28
04461-0-049
Page 27
AD5415
04461-0-050
Figure 50. Solder-Side Artwork
Table 13. Overview of AD54xx Devices
Part No. Resolution No. DACs INL(LSB) Interface Package Features
AD5424 8 1 ±0.25 Parallel RU-16, CP-20
10 MHz BW, 17 ns
AD5426 8 1 ±0.25 Serial RM-10 10 MHz BW, 50 MHz Serial
AD5428 8 2 ±0.25 Parallel RU-20
10 MHz BW, 17 ns
AD5429 8 2 ±0.25 Serial RU-10 10 MHz BW, 50 MHz Serial
AD5450 8 1 ±0.25 Serial RJ-8 10 MHz BW, 50 MHz Serial
AD5432 10 1 ±0.5 Serial RM-10 10 MHz BW, 50 MHz Serial
AD5433 10 1 ±0.5 Parallel RU-20, CP-20
10 MHz BW, 17 ns
AD5439 10 2 ±0.5 Serial RU-16 10 MHz BW, 50 MHz Serial
AD5440 10 2 ±0.5 Parallel RU-24
10 MHz BW, 17 ns
AD5451 10 1 ±0.25 Serial RJ-8 10 MHz BW, 50 MHz Serial
AD5443 12 1 ±1 Serial RM-10 10 MHz BW, 50 MHz Serial
AD5444 12 1 ±0.5 Serial RM-8 10 MHz BW, 50 MHz Serial
AD5415 12 2 ±1 Serial RU-24 10 MHz BW, 58 MHz Serial
AD5445 12 2 ±1 Parallel RU-20, CP-20
AD5447 12 2 ±1 Parallel RU-24
10 MHz BW, 17 ns
10 MHz BW, 17 ns
AD5449 12 2 ±1 Serial RU-16 10 MHz BW, 50 MHz Serial
AD5452 12 1 ±0.5 Serial RJ-8, RM-8 10 MHz BW, 50 MHz Serial
AD5446 14 1 ±1 Serial RM-8 10 MHz BW, 50 MHz Serial
AD5453 14 1 ±2 Serial UJ-8, RM-8 10 MHz BW, 50 MHz Serial
AD5553 14 1 ±1 Serial RM-8 4 MHz BW, 50 MHz Serial Clock
AD5556 14 1 ±1 Parallel RU-28
4 MHz BW, 20 ns
AD5555 14 2 ±1 Serial RM-8 4 MHz BW, 50 MHz Serial Clock
AD5557 14 2 ±1 Parallel RU-38
4 MHz BW, 20 ns
AD5543 16 1 ±2 Serial RM-8 4 MHz BW, 50 MHz Serial Clock
AD5546 16 1 ±2 Parallel RU-28
4 MHz BW, 20 ns
AD5545 16 2 ±2 Serial RU-16 4 MHz BW, 50 MHz Serial Clock
AD5547 16 2 ±2 Parallel RU-38
4 MHz BW, 20 ns
CS Pulse Width
CS Pulse Width
CS Pulse Width
CS Pulse Width
CS Pulse Width
CS Pulse Width
WR Pulse Width
WR Pulse Width
WR Pulse Width
WR Pulse Width
Rev. 0 | Page 27 of 28
Page 28
AD5415
OUTLINE DIMENSIONS
7.90
7.80
7.70
24
PIN 1
0.15
0.05
0.10 COPLANARITY
0.65
BSC
0.30
0.19
COMPLIANT TO JEDEC STANDARDS MO-153AD
13
121
1.20
MAX
SEATING
PLANE
4.50
4.40
4.30
6.40 BSC
0.20
0.09
8°
0°
0.75
0.60
0.45
Figure 51. 24-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-24)
Dimensions shown in millimeters
ORDERING GUIDE
Model Resolution INL (LSBs) Temperature Range Package Description Package Option
AD5415YRU 12 ±1 −40°C to +125°C TSSOP RU-24
AD5415YRU-REEL 12 ±1 −40°C to +125°C TSSOP RU-24
AD5415YRU-REEL7 12 ±1 −40°C to +125°C TSSOP RU-24
EVAL-AD5415EB Evaluation Kit
© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04461–0–7/04(0)
Rev. 0 | Page 28 of 28
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