On chip 4-quadrant resistors allow flexible output ranges
10 MHz multiplying bandwidth
Fast parallel interface write cycle: 58 MSPS
2.5 V to 5.5 V supply operation
±10 V reference input
Extended temperature range: −40°C to 125°C
40-lead LFCSP package
Guaranteed monotonic
4-quadrant multiplication
Power-on reset
Readback function
.5 µA typical current consumption
APPLICATIONS
Portable battery-powered applications
Waveform generators
Analog processing
Instrumentation applications
Programmable amplifiers and attenuators
Digitally-controlled calibration
Programmable filters and oscillators
Composite video
Ultrasound
Gain, offset, and voltage trimming
R3AR2AR2_3A
AD5405
V
DD
DATA
DB0
INPUTS
DB11
INPUT
BUFFER
AD5405
GENERAL DESCRIPTION
The AD54051 is a dual CMOS, 12-bit, cur rent output dig italto-analog converter (DAC).This device operates from a 2.5 V to
5.5 V power supply, making it suited to battery-powered and
other applications.
The applied external reference input voltage (V
the full-scale output current. An integrated feedback resistor
) provides temperature tracking and full-scale voltage
(R
FB
output when combined with an external I-to-V precision
amplifier. This device also contains all the 4-quadrant resistors
necessary for bipolar operation and other configuration modes.
This DAC utilizes data readback, allowing the user to read the
contents of the DAC register via the DB pins. On power-up, the
internal register and latches are filled with zeros and the DAC
outputs are at zero scale.
As a result of manufacture with a CMOS submicron process, the
device offers excellent 4-quadrant multiplication characteristics,
with large signal multiplying bandwidths of up to 10 MHz.
The AD5405 has a 6 mm × 6 mm, 40-lead LFCSP package.
1
US Patent Number 5,689,257.
V
A
REF
R1A
R2
R3
2R
2R
LATCH
R1
2R
12-BIT
R-2R DAC A
RFB
2R
R
I
I
OUT
OUT
A
FB
1A
2A
) determines
REF
DAC A/B
CS
R/W
LDAC
GND
CONTROL
LOGIC
POWER-ON
RESET
R3
2R
R3BR2BR2_3B
Figure 1. AD5405 Functional Block Diagram
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Anal og Devices. Trademarks and
registered trademarks are the property of their respective owners.
VDD = 2.5 V to 5.5 V, V
with OP1177, AC performance with AD9631, unless otherwise noted.
Table 1.
Parameter Min Typ Max Unit Conditions
STATIC PERFORMANCE
Resolution 12 Bits
Relative Accuracy ±1 LSB
Differential Nonlinearity −1/+2 LSB Guaranteed monotonic
Gain Error ±25 mV
Gain Error Temp Coefficient
Bipolar Zero-Code Error ±25 mV
Output Leakage Current ±1 nA Data = 0x0000, TA = 25°C, I
±10 nA Data = 0x0000H, I
REFERENCE INPUT2
Reference Input Range ±10 V
V
A, V
REF
V
REF
Mismatch
R1, RFB Resistance 16 20 24 kΩ
R2, R3 Resistance 16 20 24 kΩ
R2 to R3 Resistance Mismatch .06 .18 % Typ = 25°C, Max = 125°C
DIGITAL INPUTS/OUTPUT2
Input High Voltage, V
Input Low Voltage, V
0.7 V VDD = 2.5 V to 2.7 V
Input Leakage Current, I
Input Capacitance 10 pF
VDD = 4.5 V to 5.5 V
VDD = 2.5 V to 3.6 V
DYNAMIC PERFORMANCE2
Reference Multiplying BW 10 MHz V
Output Voltage Settling Time 80 120 ns Measured to ±1 mV of FS. R
Digital Delay 20 40 ns
Digital-to-Analog Glitch Impulse 3 nV-s 1 LSB change around major carry, V
Multiplying Feedthrough Error −75 dB DAC latch loaded with all 0s. Reference = 10 kHz
Output Capacitance 2 pF DAC latches loaded with all 0s
4 pF DAC latches loaded with all 1s
Digital Feedthrough 5 nV-s
Total Harmonic Distortion −75 dB V
−75 dB V
Output Noise Spectral Density 25 nV/√Hz @ 1 kHz
B Input Resistance 8 10 12 kΩ DAC input resistance
REF
A to V
B Input Resistance
REF
Output Low Voltage, V
Output High Voltage, V
Output Low Voltage, V
Output High Voltage, V
Rev. 0 | Page 3 of 24
Page 4
AD5405
Parameter Min Typ Max Unit Conditions
SFDR Performance (Wideband)
Clock = 10 MHz
500 kHz f
100 kHz f
50 kHz f
OUT
OUT
OUT
Clock = 25 MHz
500 kHz f
100 kHz f
50 kHz f
OUT
OUT
OUT
SFDR Performance (Narrow Band)
Clock = 10 MHz
500 kHz f
100 kHz f
50k Hz f
OUT
OUT
OUT
Clock = 25 MHz
500 kHz f
100 kHz f
50k Hz f
OUT
OUT
OUT
Intermodulation Distortion
Clock = 10 MHz
f1 = 400 kHz, f2 = 500 kHz 65 dB
f1 = 40 kHz, f2 = 50 kHz 72 dB
Clock = 25 MHz
f1 = 400 kHz, f2 = 500 kHz 51 dB
f1 = 40 kHz, f2 = 50 kHz 65 dB
POWER REQUIREMENTS
Power Supply Range 2.5 5.5 V
I
DD
Power Supply Sensitivity2 0.001 %/% ∆VDD = ±5%
1
Temperature range for Y version is −40°C to +125°C.
2
Guaranteed by design, not subject to production test.
55 dB
63 dB
65 dB
50 dB
60 dB
62 dB
73 dB
80 dB
87 dB
70 dB
75 dB
80 dB
10 µA Logic inputs = 0 V or V
DD
Rev. 0 | Page 4 of 24
Page 5
AD5405
TIMING CHARACTERISTICS
VDD = 2.5 V to 5.5 V, V
Table 2.
Parameter
1, 2
Write Mode
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
Data Readback Mode
t
10
t
11
t
12
35 ns max
t
13
10 ns max
1
See Temperature range for Y version is −40°C to +125°C. Guaranteed by design and characterization, not subject to production test. Figure 2.
2
All input signals are specified with tr = tf = 5ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. Digital output timing measured
with load circuit in . Figure 3
= 5 V, I
REF
Limit at T
0 ns min
0 ns min
10 ns min
2 = 0 V. All specifications T
OUT
MIN
, T
Unit Conditions/Comments
MAX
to T
MIN
W to CS setup time
R/
W to CS hold time
R/
unless otherwise noted.
MAX,
CS low time
10 ns min Address setup time
0 ns min Address hold time
6 ns min Data setup time
0 ns min Data hold time
5 ns min
7 ns min
W high to CS low
R/
CS min high time
0 ns typ Address setup time
0 ns typ Address hold time
5 ns typ Data access time
5 ns typ Bus relinquish time
t
R/W
t
1
t
2
8
t
2
t
9
t
10
t
t
7
12
t
11
DATA VALID
t
13
04463-0-002
DACA/DACB
DATA
CS
t
3
t
4
t
6
DATA VALID
t
5
Figure 2. Timing Diagram
I
OL
V
+ V
OH (MIN)
I
OH
OL (MAX)
2
04463-0-003
TO
OUTPUT
PIN
C
L
50pF
200µA
200µA
Figure 3. Load Circuit for Data Timing Specifications
Rev. 0 | Page 5 of 24
Page 6
AD5405
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter Rating
VDD to GND
V
A, V
REF
I
OUT
B, RFBA, RFBB to GND
REF
1, I
2 to GND
OUT
Logic Inputs and Output
1
−0.3 V to +7 V
−12 V to +12 V
−0.3 V to +7 V
−0.3V to VDD + 0.3 V
Operating Temperature Range
Automotive (Y Version)
Storage Temperature Range
−40°C to +125°C
−65°C to +150°C
Junction Temperature 150°C
40-lead LFCSP, θJA Thermal Impedance 30°C/W
Lead Temperature, Soldering (10 sec.) 300°C
IR Reflow, Peak Temperature (< 20 sec.) 235°C
1
Over voltages at DBx,
Current should be limited to the maximum ratings given.
LDAC, CS
, and W/R are clamped by internal diodes.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may
affect device reliability.
Rev. 0 | Page 6 of 24
Page 7
AD5405
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
R1A
R2A
R2_3A
R3A
V
REF
DGND
LDAC
DAC A/B
NC
DB11
A
2
1A
A
FB
OUT
OUT
40 R
39 I
38 I
1
2
3
4
A
5
6
7
8
9
10
PIN 1
INDICATOR
AD5405
TOP VIEW
B
B
1
2
B
FB
OUT
37 NC
36 NC
OUT
35 NC
34 NC
33 I
32 I
31 R
30 R1B
29 R2B
28 R2_3B
27 R3B
B
26 V
REF
25 V
DD
24 CLR
23 R/W
22 CS
21 DB0
NC = NO CONNECT
DB10 11
DB5 16
DB9 12
DB8 13
DB7 14
DB6 15
DB4 17
DB2 19
DB1 20
DB3 18
Figure 4. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Function
1 to 4 R1A to R3A
DAC A 4-Quadrant Resistors. Allow a number of configuration modes, including bipolar operation with
minimum of external components.
5, 26 V
REF
A, V
B DAC Reference Voltage Input Terminals.
REF
6 DGND Digital Ground Pin.
7
LDACLoad DAC Input. Allows asynchronous or synchronous updates to the DAC output. The DAC is asynchronously
updated when this signal goes low. Alternatively, if this line is held permanently low, an automatic or
synchronous update mode is selected whereby the DAC is updated on the rising edge of
8 DAC A/B Selects DAC A or B. Low selects DAC A, while high selects DAC B.
9, 34, 35,
NC Not internally connected.
36, 37
10 to 21 DB11 to DB0 Parallel Data Bits 11 through 0.
22
CSChip Select Input. Active low. Used in conjunction with R/W to load parallel data to the input latch or to read
data from the DAC register. Edge sensitive; when pulled high, the DAC data is latched.
23
WRead/Write. When low, used in conjunction with CS to load parallel data. When high, used in conjunction with
R/
CS to read back contents of DAC register.
24
25 V
CLR
DD
26 to 30 R3B to R1B
Active Low Control Input. Clears DAC output and input and DAC registers.
Positive Power Supply Input. These parts can be operated from a supply of 2.5 V to 5.5 V.
DAC B 4-Quadrant Resistors. Allow a number of configuration modes, including bipolar operation with a
minimum of external components.
32 I
OUT
2B
DAC A Analog Ground. This pin typically should be tied to the analog ground of the system, but may be biased
to achieve single-supply operation.
33 I
38 I
39 I
1B DAC B Current Outputs.
OUT
1A DAC A Current Outputs.
OUT
OUT
2A
DAC A Analog Ground. This pin typically should be tied to the analog ground of the system, but may be biased
Figure 16. Reference Multiplying Bandwidth vs. Frequency and Compensation
Capacitor
Rev. 0 | Page 9 of 24
Page 10
AD5405
0.045
7FF TO 800H
0.040
0.035
0.030
0.025
0.020
0.015
0.010
OUTPUT VOLTAGE (V)
0.005
0
–0.005
–0.010
020406080100 120 140 160 180 200
–1.68
–1.69
–1.70
–1.71
–1.72
–1.73
–1.74
OUTPUT VOLTAGE (V)
–1.75
–1.76
–1.77
020406080100 120 140 160 180 200
20
TA = 25°C
V
AMP = AD8038
0
–20
–40
–60
PSRR (dB)
–80
–100
–120
11001k10k100k1M10M
TA = 25°C
= 0V
V
VDD = 5V
VDD = 3V
VDD = 5V
TIME (ns)
Figure 17. Midscale Transition, V
REF
AD8038 AMPLIFIER
C
COMP
800 TO 7FFH
VDD = 3V
REF
= 1.8pF
= 0 V
7FF TO 800H
VDD = 5V
VDD = 3V
VDD = 5V
800 TO 7FFH
TIME (ns)
Figure 18. Midscale Transition, V
TA = 25°C
V
REF
AD8038 AMPLIFIER
C
COMP
VDD = 3V
REF
= 3.5V
= 1.8pF
= 3.5 V
= 3V
DD
FULL SCALE
ZERO SCALE
10
FREQUENCY (Hz)
Figure 19. Power Supply Rejection vs. Frequency
04463-0-039
04463-0-040
04463-0-026
–60
TA = 25°C
V
= 3V
DD
= 3.5V p-p
V
REF
–65
–70
–75
THD + N (dB)
–80
–85
–90
1001k11010k100k1M
FREQUENCY (Hz)
Figure 20. THD and Noise vs. Frequency
100
MCLK = 1MHz
80
MCLK = 200kHz
60
MCLK = 0.5MHz
SFDR (dB)
40
20
0
020406080100 120 140 160 180 200
f
(kHz)
OUT
Figure 21. Wideband SFDR vs. f
TA = 25°C
V
= 3.5V
REF
AD8038 AMPLIFIER
AD5405
Frequenc y
OUT
90
80
70
60
50
40
SFDR (dB)
30
20
10
MCLK = 5MHz
MCLK = 10MHz
MCLK = 25MHz
TA = 25°C
V
= 3.5V
REF
AD8038 AMPLIFIER
0
0100 200 300 400 500 600 700 800 900 1000
f
(kHz)
OUT
Figure 22. Wideband SFDR vs. f
AD5405
Frequency
OUT
04463-0-041
04463-0-027
04463-0-028
Rev. 0 | Page 10 of 24
Page 11
AD5405
0
–10
–20
–30
–40
–50
SFDR (dB)
–60
–70
–80
–90
0
24681012
Figure 23. Wideband SFDR, f
0
–10
–20
–30
–40
–50
SFDR (dB)
–60
–70
–80
–90
–100
0.51.53.03.54.01.02.0 2.54.55.0
0
Figure 24. Wideband SFDR, f
0
–10
–20
–30
–40
–50
SFDR (dB)
–60
–70
–80
–90
0.51.53.03.54.01.02.0 2.54.55.0
0
Figure 25. Wideband SFDR, f
FREQUENCY (MHz)
= 100 kHz, Clock = 25 MHz
OUT
FREQUENCY (MHz)
=500 kHz, Clock = 10 MHz
OUT
FREQUENCY (MHz)
= 50 kHz, Clock = 10 MHz
OUT
TA = 25°C
V
= 5V
DD
AMP = AD8038
AD5405
65k CODES
TA = 25°C
= 5V
V
DD
AMP = AD8038
AD5405
65k CODES
TA = 25°C
VDD = 5V
AMP = AD8038
AD5405
65k CODES
04463-0-018
04463-0-019
04463-0-020
0
–10
–20
–30
–40
–50
–60
SFDR (dB)
–70
–80
–90
–100
250750300 350 400650 700
Figure 26. Narrow-Band Spectral Response, f
450 500 550 600
FREQUENCY (MHz)
OUT
= 500 kHz, Clock = 25 MHz
20
0
–20
–40
–60
SFDR (dB)
–80
–100
–120
50150
607080130 140
Figure 27. Narrow-Band SFDR, f
90100 110 120
FREQUENCY (MHz)
= 100 kHz, Clock = 25 MHz
OUT
0
–10
–20
–30
–40
–50
(dB)
–60
–70
–80
–90
–100
70120758085115
Figure 28. Narrow-Band IMD, f
95
90100 105 110
FREQUENCY (MHz)
= 90 kHz, 100 kHz, Clock = 10 MHz
OUT
TA = 25°C
V
= 3V
DD
AMP = AD8038
AD5405
65k CODES
TA = 25°C
V
= 3V
DD
AMP = AD8038
AD5405
65k CODES
TA = 25°C
= 3V
V
DD
AMP = AD8038
AD5405
65k CODES
04463-0-021
04463-0-022
04463-0-023
Rev. 0 | Page 11 of 24
Page 12
AD5405
0
–10
–20
–30
–40
–50
(dB)
–60
–70
–80
–90
–100
0400
50300350100150200250
Figure 29. Wideband IMD, f
FREQUENCY (kHz)
= 90 kHz, 100 kHz, Clock = 25 MHz
OUT
TA = 25°C
= 5V
V
DD
AMP = AD8038
AD5405
65k CODES
04463-0-024
300
ZERO SCALE LOADED TO DAC
250
200
150
100
OUTPUT NOISE (nV/ Hz)
50
0
1001k10k100k
MIDSCALE LOADED TO DAC
FULL SCALE LOADED TO DAC
FREQUENCY (Hz)
TA = 25°C
AMP = AD8038
Figure 30. Output Noise Spectral Density
04463-0-025
Rev. 0 | Page 12 of 24
Page 13
AD5405
(
)
(
)
TERMINOLOGY
Relative Accuracy
Relative accuracy or endpoint nonlinearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
adjusting for zero and full scale and is normally expressed in
LSBs or as a percentage of full-scale reading.
Differential Nonlinearity
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ±1 LSB max over
the operating temperature range ensures monotonicity.
Gain Error
Gain error or full-scale error is a measure of the output error
between an ideal DAC and the actual device output. For this
DAC, ideal maximum output is V
− 1 LSB. Gain error of the
REF
DACs is adjustable to zero with external resistance.
Output Leakage Current
Output leakage current is current that flows in the DAC ladder
switches when these are turned off. For the I
1 terminal, it can
OUT
be measured by loading all 0s to the DAC and measuring the
1 current. Minimum current flows in the I
I
OUT
2 line when
OUT
the DAC is loaded with all 1s.
Output Capacitance
Capacitance from I
OUT
1 or I
2 to AGND.
OUT
Output Current Settling Time
This is the amount of time it takes for the output to settle to a
specified level for a full-scale input change. For this device, it is
specified with a 100 Ω resistor to ground.
Digital to Analog Glitch lmpulse
The amount of charge injected from the digital inputs to the
analog output when the inputs change state. This is typically
specified as the area of the glitch in either pA-secs or nV-secs
depending upon whether the glitch is measured as a current or
voltage signal.
Digital Feedthrough
When the device is not selected, high frequency logic activity on
the device’ s digital inputs is capacitively coupled through the
device to show up as noise on the I
pins and subsequently
OUT
into the following circuitry. This noise is digital feedthrough.
Multiplying Feedthrough Error
This is the error due to capacitive feedthrough from the DAC
reference input to the DAC I
1 terminal, when all 0s are
OUT
loaded to the DAC.
Digital Crosstalk
This is the glitch impulse transferred to the outputs of one
DAC in response to a full-scale code change (all 0s to all 1s,
and vice versa) in the input register of the other DAC. It is
expressed in nV-s.
Analog Crosstalk
This is the glitch impulse transferred to the output of one DAC
due to a change in the output of another DAC. It is measured by
loading one of the input registers with a full-scale code change
(all 0s to all 1s, and vice versa), while keeping LDAC high. Then
pulse LDAC low and monitor the output of the DAC whose
digital code was not changed. The area of the glitch is expressed
in nV-s.
Channel to Channel Isolation
This refers to the proportion of input signal from one DAC’s
reference input which appears at the output of the other DAC,
and is expressed in dBs.
Total Harmonic Distortion (THD)
The DAC is driven by an ac reference. The ratio of the rms sum
of the harmonics of the DAC output to the fundamental value is
the THD. Usually only the lower-order harmonics are included,
such as the second to the fifth.
2
2
2
THD
2
3
2
log20
=
V
VVVV
+++
5
4
1
Intermodulation Distortion
The DAC is driven by two combined sine wave references
of frequencies fa and fb. Distortion products are produced
at sum and difference frequencies of mfa ± nfb where m, n = 0,
1, 2, 3,... Intermodulation terms are those for which m or n is
not equal to zero. The second-order terms include (fa + fb)
and (fa − fb) and the third-order terms are (2fa + fb), (2fa − fb),
(f + 2fa + 2fb) and (fa − 2fb). IMD is defined as
IMDlog20=
productsdistortiondiffandsumtheofsumrms
lfundamentatheofamplituderms
Compliance Voltage Range
The maximum range of (output) terminal voltage for which the
device provides the specified characteristics.
Rev. 0 | Page 13 of 24
Page 14
AD5405
GENERAL DESCRIPTION
DAC SECTION
The AD5405 is a 12-bit, dual-channel, current-output DAC
consisting of a standard inverting R-2R ladder configuration.
Figure 31 shows a simplified diagram for a single channel of the
AD5405. The feedback resistor R
of R is typically 10 kΩ (minimum 8 kΩ and maximum 12 kΩ).
If I
1A and I
OUT
2A are kept at the same potential, a constant
OUT
current flows in each ladder leg, regardless of digital input code.
Thus, the input resistance presented at V
V
REFA
2RS12RS22R
DAC DATA LATCHES
AND DRIVERS
Figure 31. Simplified Ladder Configuration
Access is provided to the V
each DAC, making the device extremely versatile and allowing
it to be configured in several different operating modes, such as
for unipolar output, bipolar output, or single-supply mode.
CIRCUIT OPERATION
Unipolar Mode
Using a single op amp, this DAC can easily be configured to
provide 2-quadrant multiplying operation or a unipolar output
voltage swing, as shown in Figure 32.
V
DD
R1A
R1
2R
R2A
R2
R2_3A
AGND
2R
R3
2R
R3A
V
A
REF
NOTES
1. SIMILAR CONFIGURATION FOR DAC B
2. C1 PHASE COMPENSATION (1pF–2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
When an output amplifier is connected in unipolar mode, the
output voltage is given by
OUT
where D is the fractional representation of the digital word
loaded to the DAC, and n is the resolution of the DAC.
40950 toD =
AD5405
12-Bit DAC A
R
Figure 32. Unipolar Operation
n
VDV×−=2
REF
has a value of 2R. The value
FB
is always constant.
REF
RRR
2R
2R
S3
R
REF
2R
FB
, RFB, I
GND
AGND
S12
OUT
I
OUT
I
OUT
2R
1, and I
RFBA
C1
1A
2A
AGND
RFB A
I
OUT1A
I
OUT 2A
2 terminals of
OUT
A1
= 0V TO –V
V
OUT
04463-0-005
IN
With a fixed 10 V reference, the circuit shown in Figure 32 gives
a unipolar 0 V to −10 V output voltage swing. When V
is an ac
IN
signal, the circuit performs 2-quadrant multiplication.
Table 5 shows the relationship between digital code and
expected output voltage for unipolar operation.
In some applications, it may be necessary to generate full
4-quadrant multiplying operation or a bipolar output swing.
This can be easily accomplished by using another external
amplifier, as shown in Figure 33.
V
DD
AGND
R1A
R2A
V
IN
A1
R2
2R
R2_3A
R3
2R
R3A
V
A
REF
NOTES
1. SIMILAR CONFIGURATION FOR DAC B
2. C1 PHASE COMPENSATION (1pF–2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
When in bipolar mode, the output voltage is given by
OUT
REF
2
REF
−1
n
VDVV××=
where D is the fractional representation of the digital word
loaded to the DAC, in the range of 0 to 4095, and n is the
number of bits. When V
is an ac signal, the circuit performs
IN
4-quadrant multiplication.
Table 6 shows the relationship between the digital code and the
04463-0-006
expected output voltage for bipolar operation.
Table 6. Bipolar Code Table
Digital Input Analog Output (V)
1111 1111 +V
(2047/2048)
REF
1000 0000 0
0000 0001 −V
0000 0000 −V
(2047/2048)
REF
(2048/2048)
REF
Rev. 0 | Page 14 of 24
Page 15
AD5405
Stability
In the I-to-V configuration, the I
of the DAC and the
OUT
inverting node of the op amp must be connected as close as
possible, and proper PCB layout techniques must be employed.
Because every code change corresponds to a step function, gain
peaking may occur if the op amp has limited GBP and there is
excessive parasitic capacitance at the inverting node. This
parasitic capacitance introduces a pole into the open loop
response which can cause ringing or instability in the closedloop applications circuit.
An optional compensation capacitor, C1, can be added in
parallel with R
for stability, as shown in Figure 32 and
FB
Figure 33. Too small a value of C1 can produce ringing at the
output, while too large a value can adversely affect the settling
time. C1 should be found empirically, but 1 pF to 2 pF is
generally adequate for the compensation.
SINGLE-SUPPLY APPLICATIONS
Voltage Switching Mode of Operation
Figure 34 shows these DACs operating in the voltage switching
mode. The reference voltage, V
I
2 is connected to AGND, and the output voltage is available
OUT
at the V
terminal. In this configuration, a positive reference
REF
voltage results in a positive output voltage, making singlesupply operation possible. The output from the DAC is voltage
at a constant impedance (the DAC ladder resistance). Thus an
op amp is necessary to buffer the output voltage. The reference
input no longer sees a constant input impedance, but one that
varies with code. So, the voltage input should be driven from a
low impedance source.
V
DD
R
V
FB
V
IN
I
I
OUT
OUT
DD
1
2
GND
, is applied to the I
IN
R
1
V
REF
1 pin,
OUT
R
2
V
OUT
POSITIVE OUTPUT VOLTAGE
Note that the output voltage polarity is opposite to the V
polarity for dc reference voltages. In order to achieve a positive
voltage output, an applied negative reference to the input of
the DAC is preferred over the output inversion through an
inverting amplifier because of the resistor’s tolerance errors. To
generate a negative reference, the reference can be level shifted
by an op amp such that the V
and GND pins of the reference
OUT
become the virtual ground and −2.5 V respectively, as shown in
Figure 35.
VDD = +5V
ADR03
V
V
IN
OUT
GND
+
5V
–2.5V
V
12-BIT DAC
1/2 AD8552
–5V
REF
NOTES
1. SIMILAR CONFIGURATION FOR DAC B
2. C1 PHASE COMPENSATION (1pF–2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
V
GND
R
FB
DD
I
OUT
I
OUT
Figure 35. Positive Voltage Output with Minimum Components
C
1
1
2
1/2 AD8552
V
= 0V TO +2.5V
OUT
REF
ADDING GAIN
In applications where the output voltage is required to be
greater than VIN, gain can be added with an additional external
amplifier or it can also be achieved in a single stage. Consider
the effect of temperature coefficients of the thin film resistors
of the DAC. Simply placing a resistor in series with the R
resistor causes mismatches in the temperature coefficients
resulting in larger gain temperature coefficient errors. Instead,
the circuit of Figure 36 is a recommended method of increasing
the gain of the circuit. R
, R2, and R3 should all have similar
1
temperature coefficients, but they need not match the temperature coefficients of the DAC. This approach is recommended
in circuits where gains of > 1 are required.
V
DD
FB
04463-0-010
NOTES
1. SIMILAR CONFIGURATION FOR DAC B
2. C1 PHASE COMPENSATION (1pF–2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
Figure 34. Single-Supply Voltage Switching Mode
Note that VIN is limited to low voltages because the switches in
the DAC ladder no longer have the same source-drain drive
voltage. As a result, their on resistance differs and degrades the
integral linearity of the DAC. Also, V
must not go negative by
IN
more than 0.3 V or an internal diode turns on, exceeding the
max ratings of the device. In this type of application, the full
range of multiplying capability of the DAC is lost.
Rev. 0 | Page 15 of 24
04463-0-009
C
DD
DAC
R
V
R2
V
IN
NOTES
1. SIMILAR CONFIGURATION FOR DAC B
2. C1 PHASE COMPENSATION (1pF–2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
12-BIT
V
REF
GND
I
I
FB
OUT
OUT
1
1
2
Figure 36. Increasing Gain of Current Output DAC
R
3
GAIN = R2 + R3
R2
R2
R1 = R2R3
R2 + R3
V
OUT
04463-0-011
Page 16
AD5405
(
)
A
Y
USED AS A DIVIDER OR PROGRAMMABLE GAIN
ELEMENT
Used as a divider or programmable gain element, currentsteering DACs are very flexible and lend themselves to many
different applications. If this type of DAC is connected as the
feedback element of an op amp, and R
resistor, as shown in Figure 37, then the output voltage is
inversely proportional to the digital input fraction D.
For
D = 1−2
n
the output voltage is
VDVV
−−=−=21
OUT
V
IN
NOTE
DDITIONAL PINS OMITTED FOR CLARIT
Figure 37. Current-Steering DAC Used as a Divider or
ININ
V
DD
R
V
FB
DD
1
I
OUT
I
2
OUT
GND
Programmable Gain Element
As D is reduced, the output voltage increases. For small values
of the digital fraction D
, it is important to ensure that the
amplifier does not saturate and also that the required accuracy
is met. For example, an 8-bit DAC driven with the binary code
0 × 10 (00010000), that is, 16 decimal, in the circuit of Figure 37
should cause the output voltage to be 16 × V
DAC has a linearity specification of ±0.5 LSB, then D can, in
fact, have the weight anywhere in the range 15.5/256 to 16.5/256
so that the possible output voltage is in the range 15.5 V
—an error of 3% even though the DAC itself has a
16.5 V
IN
maximum error of 0.2%.
DAC leakage current is also a potential error source in divider
circuits. The leakage current must be counterbalanced by an
opposite current supplied from the op amp through the DAC.
Because only a fraction D of the current into the V
is routed to the I
1 terminal, the output voltage has to change
OUT
as follows:
Output Error Voltage Due to DAC Leakage = (Leakage × R)/D
where R is the DAC resistance at the V
For a DAC leakage current of 10 nA, R = 10 kΩ and a gain (that
is, 1/D) of 16, the error voltage is 1.6 mV.
is used as the input
FB
n
−
V
REF
IN
terminal.
REF
V
OUT
04463-0-012
. However, if the
to
IN
terminal
REF
REFERENCE SELECTION
When selecting a reference for use with the AD5405 series of
current output DACs, pay attention to the reference output
voltage temperature coefficient specification. This parameter
not only affects the full-scale error, but can also affect the
linearity (INL and DNL) performance. The reference temperature coefficient should be consistent with the system accuracy
specifications. For example, an 8-bit system required to hold
its overall specification to within 1 LSB over the temperature
range 0°C to 50°C dictates that the maximum system drift with
temperature should be less than 78 ppm/°C. A 12-bit system
with the same temperature range to overall specification within
2 LSBs requires a maximum drift of 10 ppm/°C. By choosing a
precision reference with low output temperature coefficient, this
error source can be minimized. Table 7 lists some references
available from Analog Devices that are suitable for use with this
range of current output DACs.
AMPLIFIER SELECTION
The primary requirement for the current-steering mode is an
amplifier with low input bias currents and low input offset
voltage. The input offset voltage of an op amp is multiplied by
the variable gain (due to the code-dependent output resistance
of the DAC) of the circuit. A change in this noise gain between
two adjacent digital fractions produces a step change in the
output voltage due to the amplifier’s input offset voltage. This
output voltage change is superimposed upon the desired change
in output between the two codes and gives rise to a differential
linearity error, which, if large enough, could cause the DAC to
be nonmonotonic.
The input bias current of an op amp also generates an offset at
the voltage output as a result of the bias current flowing in the
feedback resistor R
enough to prevent any significant errors in 12-bit applications.
Common-mode rejection of the op amp is important in
voltage-switching circuits, because it produces a codedependent error at the voltage output of the circuit. Most
op amps have adequate common-mode rejection for use at
12-bit resolution.
Provided the DAC switches are driven from true wide band,
low impedance sources (V
Consequently, the slew rate and settling time of a voltageswitching DAC circuit is determined largely by the output op
amp. To obtain minimum settling time in this configuration,
minimize capacitance at the V
this application) of the DAC. This is done by using low input
capacitance buffer amplifiers and careful board design.
Most single-supply circuits include ground as part of the analog
signal range, which in turn requires an amplifier that can handle
rail-to-rail signals. Analog Devices offers a large range of singlesupply amplifiers, as listed in Table 8.
. Most op amps have input bias currents low
FB
and AGND) they settle quickly.
IN
node (voltage output node in
REF
Rev. 0 | Page 16 of 24
Page 17
AD5405
Table 7. Suitable ADI Precision References Recommended for Use with AD5405 DACs
Reference Output Voltage Initial Tolerance Temperature Drift 0.1 Hz to 10 Hz noise Package
Data is loaded to the AD5405 in the format of a 12-bit parallel
word. Control lines CS and R/W allow data to be written to or
read from the DAC register. A write event takes place when
and R/
the shift register, and the rising edge of
are brought low, data available on the data lines fills
W
latches the data and
CS
transfers the latched data word to the DAC register. The DAC
latches are not transparent, thus a write sequence must consist
of a falling and rising edge on
to ensure data is loaded to the
CS
DAC register and its analog equivalent reflected on the DAC
output. A read event takes place when R/
is held high and CS
W
is brought low. Data is loaded from the DAC register back to the
input register and out onto the data line where it can be read
back to the controller for verification or diagnostic purposes.
The input and DAC registers of these devices are not trans-
parent, so a falling and rising edge of
is required to load
CS
each data-word.
MICROPROCESSOR INTERFACING
The AD5405 can be interfaced to a variety of 16-bit microcontrollers or DSP processors. Figure 38 shows the AD5405
DAC interfaced to a generic 16-bit microcontroller/DSP
processor. Microprocessor interfacing to this family of DAC is
via a data bus that uses a standard protocol compatible with
microcontrollers and DSP processors. The address decoder
selects DAC A or DAC B and also to loads parallel data to the
input latch or to read data from the DAC using an AND gate.
(max) µV IB (max) nA GBP MHz Slew Rate V/µs
OS
(max) µV IB (max) nA BW @ ACL MHz Slew Rate V/µs
OS
CS
A0 TO AX
MICRO/DSP*
DB0 TO DB11
*ADDITIONAL PINS OMITTED FOR CLARITY
ADDRESS
DECODER
WR
Figure 38. AD54xx to Parallel Interface
ADDRESS BUS
A
A + 1
DATA BUS
AD54xx*
DAC A/B
CS
WR
DB0 TO DB11
PCB LAYOUT AND POWER SUPPLY DECOUPLING
In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to
ensure the rated performance. The printed circuit board on
which the AD5405 is mounted should be designed so that the
analog and digital sections are separated, and confined to
certain areas of the board. If the DAC is in a system where
multiple devices require an AGND-to-DGND connection, the
connection should be made at one point only. The star ground
point should be established as close as possible to the device.
04462-0-055
Rev. 0 | Page 17 of 24
Page 18
AD5405
These DACs should have ample supply bypassing of 10 µF in
parallel with 0.1 µF on the supply located as close to the package as possible, ideally right up against the device. The 0.1 µF
capacitor should have low effective series resistance (ESR)
and effective series inductance (ESI), like the common ceramic
types that provide a low impedance path to ground at high
frequencies, to handle transient currents due to internal logic
switching. Low ESR 1 µF to 10 µF tantalum or electrolytic
capacitors should also be applied at the supplies to minimize
transient disturbance and filter out low frequency ripple.
Fast switching signals such as clocks should be shielded with
digital ground to avoid radiating noise to other parts of the
board, and should never be run near the reference inputs.
It is good practice to employ compact, minimum lead length
PCB layout design. Leads to the input should be as short as
possible to minimize IR drops and stray inductance.
The PCB metal traces between V
and RFB should also be
REF
matched to minimize gain error. To maximize high frequency
performance, the I-to-V amplifier should be located as close to
the device as possible.
EVALUATION BOARD FOR THE DACS
The evaluation board consists of a DAC and a current-tovoltage amplifier, the AD8065. Included on the evaluation
board is a 10 V reference, the ADR01. An external reference
may also be applied via an SMB input.
Avoid crossover of digital and analog signals. Traces on opposite
sides of the board should run at right angles to each other. This
reduces the effects of feedthrough on the board. A microstrip
technique is by far the best, but not always possible with a
double-sided board. In this technique, the component side of
the board is dedicated to the ground plane while signal traces
are placed on the soldered side.
The evaluation kit consists of a CD-ROM with self-installing
PC software to control the DAC. The software simply allows the
user to write a code to the device.
POWER SUPPLIES FOR THE EVALUATION BOARD
The board requires ±12 V and 5 V supplies. The 12 V V
are used to power the output amplifier, while the 5 V is used
V
SS
to power the DAC (V
) and transceivers (VCC).
DD1
Both supplies are decoupled to their respective ground plane
with 10
µF tantalum and 0.1 µF ceramic capacitors.
DD
and
Rev. 0 | Page 18 of 24
Page 19
AD5405
Figure 39. Schematic of AD5405 Evaluation Board
Rev. 0 | Page 19 of 24
04463-0-045
Page 20
AD5405
Figure 40. Component-Side Artwork
04463-0-046
04463-0-047
Figure 41. Silkscreen—Component-Side View ( Top Layer)
Rev. 0 | Page 20 of 24
Page 21
AD5405
04463-0-048
Figure 42. Solder-Side Artwork
Rev. 0 | Page 21 of 24
Page 22
AD5405
OVERVIEW OF AD54xx DEVICES
Table 10.
Part No. Resolution No. DACs INL(LSB) Interface Package Features
AD5424 8 1 ±0.25 Parallel RU-16, CP-20
AD5426 8 1 ±0.25 Serial RM-10 10 MHz BW, 50 MHz Serial
AD5428 8 2 ±0.25 Parallel RU-20
AD5429 8 2 ±0.25 Serial RU-10 10 MHz BW, 50 MHz Serial
AD5450 8 1 ±0.25 Serial RJ-8 10 MHz BW, 50 MHz Serial
AD5432 10 1 ±0.5 Serial RM-10 10 MHz BW, 50 MHz Serial
AD5433 10 1 ±0.5 Parallel RU-20, CP-20
AD5439 10 2 ±0.5 Serial RU-16 10 MHz BW, 50 MHz Serial
AD5440 10 2 ±0.5 Parallel RU-24
AD5451 10 1 ±0.25 Serial RJ-8 10 MHz BW, 50 MHz Serial
AD5443 12 1 ±1 Serial RM-10 10 MHz BW, 50 MHz Serial
AD5444 12 1 ±0.5 Serial RM-8 10 MHz BW, 50 MHz Serial
AD5415 12 2 ±1 Serial RU-24 10 MHz BW, 58 MHz Serial
AD5445 12 2 ±1 Parallel RU-20, CP-20
AD5447 12 2 ±1 Parallel RU-24
AD5449 12 2 ±1 Serial RU-16 10 MHz BW, 50 MHz Serial
AD5452 12 1 ±0.5 Serial RJ-8, RM-8 10 MHz BW, 50 MHz Serial
AD5446 14 1 ±1 Serial RM-8 10 MHz BW, 50 MHz Serial
AD5453 14 1 ±2 Serial UJ-8, RM-8 10 MHz BW, 50 MHz Serial
AD5553 14 1 ±1 Serial RM-8 4 MHz BW, 50 MHz Serial Clock
AD5556 14 1 ±1 Parallel RU-28
AD5555 14 2 ±1 Serial RM-8 4 MHz BW, 50 MHz Serial Clock
AD5557 14 2 ±1 Parallel RU-38
AD5543 16 1 ±2 Serial RM-8 4 MHz BW, 50 MHz Serial Clock
AD5546 16 1 ±2 Parallel RU-28
AD5545 16 2 ±2 Serial RU-16 4 MHz BW, 50 MHz Serial Clock
AD5547 16 2 ±2 Parallel RU-38
10 MHz BW, 17 ns
10 MHz BW, 17 ns
10 MHz BW, 17 ns
10 MHz BW, 17 ns
10 MHz BW, 17 ns
10 MHz BW, 17 ns
4 MHz BW, 20 ns
4 MHz BW, 20 ns
4 MHz BW, 20 ns
4 MHz BW, 20 ns
CS Pulse Width
CS Pulse Width
CS Pulse Width
CS Pulse Width
CS Pulse Width
CS Pulse Width
WR Pulse Width
WR Pulse Width
WR Pulse Width
WR Pulse Width
Rev. 0 | Page 22 of 24
Page 23
AD5405
OUTLINE DIMENSIONS
PIN 1
INDICATOR
1.00
0.85
0.80
126° MAX
SEATING
PLANE
6.00
BSC SQ
TOP
VIEW
0.80 MAX
0.65 TYP
0.30
0.23
0.18
COMPLIANT TO JEDEC STANDARDS MO-220-VJJD-2
5.75
BCS SQ
0.20 REF
0.05 MAX
0.02 NOM
COPLANARITY
0.60 MAX
0.50
BSC
0.50
0.40
0.30
0.08
0.60 MAX
31
30
EXPOSED
(BOTTOM VIEW)
21
20
PAD
4.50
REF
PIN 1
40
11
INDICATOR
1
4.25
4.10 SQ
3.95
10
0.25 MIN
Figure 43. 40 Lead LFCSP
(CP-40)
Dimensions shown in inches and (mm)
ORDERING GUIDE
Model Resolution INL (LSBs) Temperature Range Package Description Package Option
AD5405YCP 12 ±1 −40°C to +125°C LFCSP CP-40
AD5405YCP–REEL 12 ±1 −40°C to +125°C LFCSP CP-40
AD5405YCP–REEL7 12 ±1 −40°C to +125°C LFCSP CP-40
EVAL-AD5405EB Evaluation Kit