Datasheet AD5398 Datasheet (Analog Devices)

120 mA, Current Sinking, 10-Bit, I2C DAC

FEATURES

120 mA current sink
Available in 8-lead LFCSP package
2-wire (I
10-bit resolution
Integrated current sense resistor

2.7 V to 5.5 V power supply
Guaranteed monotonic over all codes
Power-down to 0.5 µA typical
Internal reference
Ultralow noise preamplifier
Power-down function
Power-on reset

CONSUMER/COMMUNICATIONS APPLICATIONS

Lens autofocus
Image stabilization
Optical zoom
Shutters
Iris/exposure
Neutral density filter NDFs
Lens covers
Camera phones
Digital still cameras
Camera modules
Digital video cameras (DVCs)/camcorders
Camera-enabled devices
Security cameras
Web/PC cameras

INDUSTRIAL APPLICATIONS

Heater control
Fan control
Cooler (Peltier) control
Solenoid control
Valve control
Linear actuator control
Light control
Current loop control

2

C®-compatible) serial interface

AD5398

FUNCTIONAL BLOCK DIAGRAM

V

DD
6

REFERENCE

10-BIT

CURRENT

OUTPUT DAC

2

DGND

Figure 1.

SDA

SCL

PD

3

4

1

AD5398

I2C SERIAL

INTERFACE

5

DGND

GENERAL DESCRIPTION

The AD5398 is a single 10-bit DAC with 120 mA output
current sink capability. It features an internal reference, and
operates from a single 2.7 V to 5.5 V supply. The DAC is
controlled via a 2-wire (I
operates at clock rates up to 400 kHz.

The AD5398 incorporates a power-on reset circuit, which
ensures that the DAC output powers up to 0 V and remains
there until a valid write takes place. It has a power-down
feature that reduces the current consumption of the device to
1 µA max.

The AD5398 is designed for autofocus, image stabilization,
and optical zoom applications in camera phones, digital still
cameras, and camcorders.

The AD5398 also has many industrial applications, such as
controlling temperature, light, and movement, over the range

−40°C to +85°C without derating.

2

C address range for the AD5398 is 0x18 to 0x1F

The I
inclusive.

2

C-compatible) serial interface that

POWER-ON

RESET

8

R

R

SENSE

3.3Ω

7

AGND

I

SINK

05034-001

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and

5

registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

www.analog.com

AD5398

TABLE OF CONTENTS

Specifications..................................................................................... 3

Theory of Operation ...................................................................... 10

AC Characteristics ............................................................................ 4

Timing Characteristics..................................................................... 4

Absolute Maximum Ratings............................................................ 5

ESD Caution.................................................................................. 5

Pin Configuration and Function Descriptions............................. 6

Typical Performance Characteristics............................................. 7

Te r mi n ol o g y ...................................................................................... 9

REVISION HISTORY

12/04—Revision 0: Initial Version

Serial Interface............................................................................ 10

2

I

C Bus Operation ...................................................................... 10

Data Format ................................................................................ 10

Power Supply Bypassing and Grounding................................ 11

Applications..................................................................................... 13

Outline Dimensions ....................................................................... 14

Ordering Guide .......................................................................... 14

Rev. 0 | Page 2 of 16

AD5398

SPECIFICATIONS

VDD = 2.7 V to 5.5 V, AGND = DGND = 0 V, load resistance RL = 25 Ω connected to VDD; all specifications T
unless otherwise noted.

Table 1.

B Version

1

Parameter Min Typ Max Unit Test Conditions/Comments

DC PERFORMANCE

= 3.6 V to 4.5 V. Device operates over 2.7 V to 5.5 V

V

DD

with reduced performance.
Resolution 10 Bits 117 µA/LSB
Relative Accuracy
Differential Nonlinearity
Zero Code Error
Offset Error @ Code 16
Gain Error
Offset Error Drift
Gain Error Drift

2

2, 4

2

4, 5

2, 5

±1.5 ±4 LSB

2, 3

±1 LSB Guaranteed monotonic over all codes.

0 1 5 mA All 0s loaded to DAC.

2

0.5 mA
±0.6 % of FSR @ 25°C
10 µA/ºC
±0.2 ±0.5 LSB/ºC

OUTPUT CHARACTERISTICS

Minimum Sink Current
Maximum Sink Current 120 mA

4

3 mA

= 3.6 V to 4.5 V. Device operates over 2.7 V to 5.5 V, but

V

DD

specified maximum sink current might not be achieved.

Output Current During PD 80 nA PD = 1.
Output Compliance

5

0.6 V

DD

V

Output voltage range over which max sink current is

available.

Power-Up Time 20 µs To 10% of FS, coming out of power-down mode. VDD = 5 V.

LOGIC INPUTS (PD)

5

Input Current ±1 µA
Input Low Voltage, V
Input High Voltage, V

INL

INH

0.8 V VDD = 2.7 V to 5.5 V

0.7 V

V V

DD

= 2.7 V to 5.5 V

DD

Pin Capacitance 3 pF

HYST

5

INL

INH

IN

−0.3 0.3 V

0.7 V

DD

VDD + 0.3

±1 µA V

V

DD

V

= 0 V to V

IN

DD

0.05 VDD V

LOGIC INPUTS (SCL, SDA)

Input Low Voltage, V
Input High Voltage, V
Input Leakage Current I
Input Hysteresis, V
Digital Input Capacitance, CIN 6 pF
Glitch Rejection

6

50 ns Pulse width of spike suppressed.

POWER REQUIREMENTS

V

DD

2.7 5.5 V
IDD (Normal Mode) IDD specification is valid for all DAC codes.
VDD = 2.7 V to 5.5 V
V

= 2.7 V to 4.5 V

DD

2.5

2.3

4
3

mA
mA

= VDD, and VIL = GND, VDD = 5.5 V

V

IH

V

= VDD, and VIL = GND, VDD = 4.5 V

IH

IDD (Power-Down Mode) 0.5 1 µA VIH = VDD, and VIL = GND

1

Temperature range is as follows: B Version: –40°C to +85°C.

2

See the Terminology section.

3

Linearity is tested using a reduced code range: Codes 32 to 1023.

4

To achieve near zero output current, use the power-down feature.

5

Guaranteed by design and characterization; not production tested.

6

Input filtering on both the SCL and SDA inputs suppresses noise spikes that are less than 50 ns.

MIN

to T

MAX

,

Rev. 0 | Page 3 of 16

AD5398

AC CHARACTERISTICS

VDD = 2.7 V to 5.5 V, AGND = DGND = 0 V, load resistance RL = 25 Ω connected to VDD, unless otherwise noted.

Table 2.

B Version

1, 2

Parameter Min Typ Max Unit Test Conditions/Comments

Output Current Settling Time 250 µs

= 5 V, RL = 25 Ω, LL = 680 µH

V

DD

¼ scale to ¾ scale change (0x100 to 0x300)
Slew Rate 0.3 mA/µs
Major Code Change Glitch Impulse 0.15 nA-s 1 LSB change around major carry
Digital Feedthrough

3

0.06 nA-s

1

Temperature range is as follows: B Version: –40°C to +85°C.

2

Guaranteed by design and characterization; not production tested.

3

See the section. Terminology

TIMING CHARACTERISTICS

VDD = 2.7 V to 5.5 V. All specifications T

Table 3.

Parameter

f

SCL

t

1

t

2

t

3

t

4

t

5

2

t

6

Limit at T

1

(B Version) Unit Conditions/Comments

400 kHz max SCL clock frequency

2.5 µs min SCL cycle time

0.6 µs min t

1.3 µs min t

0.6 µs min t
100 ns min t

0.9 µs max t

MIN

, T

MAX

0 µs min
t

7

t

8

t

9

t

10

0.6 µs min t

0.6 µs min t

1.3 µs min t

300 ns max tR, rise time of both SCL and SDA when receiving
0 ns min May be CMOS driven
t

11

250 ns max tF, fall time of SDA when receiving
300 ns max tF, fall time of Both SCL and SDA when transmitting
20 + 0.1 C
C

b

400 pF max Capacitive load for each bus line

3

b

1

Guaranteed by design and characterization; not production tested.

2

A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the VIH MIN of the SCL signal) in order to bridge the undefined region of SCL’s

falling edge.

3

C

is the total capacitance of one bus line in pF. t

b

MIN

to T

, unless otherwise noted.

MAX

, SCL high time

HIGH

, SCL low time

LOW

, start/repeated start condition hold time

HD,STA

, data setup time

SU,DAT

, data hold time

HD,DAT

, setup time for repeated start

SU,STA

, stop condition setup time

SU,STO

, bus free time between a stop condition and a start condition

BUF

ns min

and tF are measured between 0.3 VDD and 0.7 V

R

DD.

SDA

t

9

SCL

START

CONDITION

t

3

t

4

t

10

t

6

t

11

t

2

t

5

Figure 2. 2-Wire Serial Interface Timing Diagram

t

7

REPEATED

START

CONDITION

t

4

t

1

t

8

STOP

CONDITION

05034-002

Rev. 0 | Page 4 of 16

AD5398

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 4.

Parameter Rating

VDD to AGND –0.3 V to +7 V
VDD to DGND –0.3 V to VDD + 0.3 V
AGND to DGND –0.3 V to +0.3 V
SCL, SDA to DGND –0.3 V to VDD + 0.3 V
PD to DGND –0.3 V to VDD + 0.3 V
I

to AGND –0.3 V to VDD + 0.3 V

SINK

Operating Temperature Range

Industrial (B Version) –40°C to +85°C
Storage Temperature Range –65°C to +150°C
Junction Temperature (TJ max) 150°C
LFCSP Power Dissipation (TJ max – TA)/θ
θJA Thermal Impedance

2

Mounted on 2-Layer Board 84°C/W

Mounted on 4-Layer Board 48°C/W
Lead Temperature, Soldering

Vapor Phase (60 sec) 215°C

Infrared (15 sec) 220°C

____________________

1

Transient currents of up to 100 mA do not cause SCR latch-up.

2

To achieve the optimum θJA, it is recommended that the AD5398 is soldered on a

4-layer board. The AD5398 comes in an 8-lead LFCSP package with an exposed
paddle that should be connected to the same potential as the AD5398 DGND pin.

1

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability. Only one absolute maximum rating may be
applied at any one time.

JA

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. 0 | Page 5 of 16

AD5398

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

PD

DGND

SDA

SCL

1

AD5398

2

TOP VIEW

3

(Not to Scale)

4

8
7
6
5

I

SINK

AGND
V

DD

DGND

05034-003

Figure 3. 8-Lead LFCSP

Table 5.

Pin No. Mnemonic Description

1 PD Power Down. Asynchronous power down signal.
2 DGND Digital Ground Pin.
3 SDA I2C Interface Signal.
4 SCL I2C Interface Signal.
5 DGND Digital Ground Pin.
6 V

DD

Digital Supply Voltage.
7 AGND Analog Ground Pin.
8 I

SINK

Output Current Sink.

Rev. 0 | Page 6 of 16

AD5398

TYPICAL PERFORMANCE CHARACTERISTICS

INL (LSB)

2.0

1.5

1.0

0.5

INL V

= 3.8V

DD

TEMP = 25°C

0

VERT = 50µs/DIV

3

–0.5

0

56

112

168

224

280

336

Figure 4. Typical INL Plot

0.6

0.5

0.4

0.3

0.2

0.1

DNL (LSB)

0

–0.1

–0.2

–0.3

0

56

112

168

224

280

336

Figure 5. Typical DNL Plot

92.0

91.5

91.0

90.5

90.0

89.5

OUTPUT CURRENT (mA)

89.0

88.5

88.0

53.5

–6

100.0

–6

150.0

Figure 6. ¼ to ¾ Scale Settling Time (V

560

504

HORIZ = 468µA/DIV

= 3.6 V)

DD

4.8µA p-p

HORIZ = 2s/DIV

= 3.6 V)

DD

I

@ +25°C

OUT

@ –40°C

I

OUT

I

OUT

840

784

728

672

616

DD

392

448

CODE

504

560

616

672

728

784

840

896

952

1008

1023

05034-004

CH3 M50.0µs

Figure 7. Settling Time for a 4-LSB Step (V

392

448

CODE

504

560

616

672

DNL VDD = 3.8V
TEMP = 25°C

896

840

784

728

952

1008

1023

05034-005

VERT = 2µA/DIV

1

CH1 M2.0s

Figure 8. 0.1 Hz to 10 Hz Noise Plot ( V

0.14

0.12

0.10

0.08

(A)

OUT

0.06

I

0.04

0.02

05034-006

–6

200.0

TIME

–6

–6

250.0

–6

= 3.6 V)

DD

300.0

333.1

–6

0

0

56

224

168

112

280

336

392

448

CODE

Figure 9. Sink Current vs. Code vs. Temperature (V

@ +85°C

952

896

= 3.6 V)

05034-007

05034-008

1008

1023

05034-009

Rev. 0 | Page 7 of 16

AD5398

2000

1800

1600

1400

1200

1000

µA/V

800

600

400

200

0

10 100 1k 100k10k

3.5

3.0

2.5

2.0

1.5

1.0

INL (LSB)

0.5

0

–0.5

–1.0

1.0

0.8

0.6

0.4

0.2

0

DNL (LSB)

–0.2

–0.4

–0.6

–0.8

–1.0

FREQUENCY

Figure 10. AC Power Supply Rejection (V

POSITIVE INL (V

POSITIVE INL (VDD = 3.6V)

NEGATIVE INL (VDD = 3.6V)

NEGATIVE INL (V

NEGATIVE INL (V

TEMPERATURE (°C)

DD

DD

= 3.8V)

= 4.5V)

Figure 11. INL vs. Temperature vs. Supply

POSITIVE DNL (VDD = 3.6V)

POSITIVE DNL (V

NEGATIVE DNL (V

NEGATIVE DNL (V

= 4.5V)

DD

= 3.8V)

DD

NEGATIVE DNL (V

= 3.6V)

DD

TEMPERATURE (°C)

POSITIVE DNL (V

= 4.5V)

DD

Figure 12. DNL vs. Temperature vs. Supply

= 3.6 V)

DD

DD

= 3.8V)

DD

05034-010

0.45

0.40

0.35

0.30

0.25

0.20

0.15

ZERO CODE ERROR (mA)

0.10

0.05

0

V

DD

= 4.5V

VDD = 3.6V

= 3.8V

V

DD

TEMPERATURE (°C)

05034-013

85–40–30–20–100 15253545556575

Figure 13. Zero Code Error vs. Supply Voltage vs. Temperature

1.5
= 4.5V

V

= 4.5V)POSITIVE INL (VDD = 3.8V)

05034-011

85–40–30–20–100 15253545556575

1.0

0.5

0

–0.5

FS ERROR (mA)

–1.0

–1.5

–2.0

V

DD

= 3.8V

DD

TEMPERATURE (°C)

VDD = 3.6V

05034-096

85–40–30–20–100 15253545556575

Figure 14. Full-Scale Error vs. Temperature vs. Supply

05034-012

85–40–30–20–100 15253545556575

Rev. 0 | Page 8 of 16

AD5398

TERMINOLOGY

Relative Accuracy

For the DAC, relative accuracy or integral nonlinearity is a
measurement of the maximum deviation, in LSBs, from a
straight line passing through the endpoints of the DAC transfer
function. A typical INL vs. code plot is shown in Figure 4.

Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ±1 LSB maximum
ensures monotonicity. This DAC is guaranteed monotonic by
design. A typical DNL vs. code plot is shown in Figure 5.

Zero-Code Error

Zero-code error is a measurement of the output error when
zero code (0x0000) is loaded to the DAC register. Ideally the
output is 0 mA. The zero-code error is always positive in the
AD5398 because the output of the DAC cannot go below 0 mA.
This is due to a combination of the offset errors in the DAC and
output amplifier. Zero-code error is expressed in mA.

Gain Error

This is a measurement of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from the
ideal, expressed as a percent of the full-scale range.

Gain Error Drift
This is a measurement of the change in gain error with changes
in temperature. It is expressed in LSB/°C.

Digital-to-Analog Glitch Impulse

Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nA-s
and is measured when the digital input code is changed by
1 LSB at the major carry transition.

Digital Feedthrough

Digital feedthrough is a measurement of the impulse injected
into the analog output of the DAC from the digital inputs of the
DAC, but is measured when the DAC output is not updated. It
is specified in nA-s and measured with a full-scale code change
on the data bus, that is, from all 0s to all 1s and vice versa.

Offset Error

Offset error is a measurement of the difference between I
(actual) and I
function, expressed in mA. Offset error is measured on the
AD5398 with Code 16 loaded into the DAC register.

Offset Error Drift

This is a measurement of the change in offset error with a
change in temperature. It is expressed in µV/°C.

(ideal) in the linear region of the transfer

OUT

SINK

Rev. 0 | Page 9 of 16

AD5398

A

V

V

THEORY OF OPERATION

The AD5398 is a fully integrated 10-bit DAC with 120 mA
output current sink capability, and is intended for driving voice
coil actuators in applications such as lens autofocus, image sta­bilization, and optical zoom. The circuit diagram is shown in
Figure 15. A 10-bit current output DAC coupled with Resistor R
generates the voltage that drives the noninverting input of the
operational amplifier. This voltage also appears across the R
resistor, and generates the sink current required to drive the
voice coil.

Resistors R and R

are interleaved and matched, and there-

SENSE

fore the temperature coefficient and any nonlinearities over
temperature are matched and the output drift over temperature
is minimized. Diode D1 is an output protection diode.

V

DD
6

R

POWER-ON

RESET

R

SENSE

3.3Ω

D1

7

AGND

SD

SCL

AD5398

3

I2C SERIAL

INTERFACE

4

1

PD

5

DGND

REFERENCE

10-BIT

CURRENT

OUTPUT DAC

2

DGND

Figure 15. Block Diagram Showing Connection to Voice Coil

SERIAL INTERFACE

The AD5398 is controlled using the industry-standard I2C
2-wire serial protocol. Data can be written to the DAC, or read
back from it, at data rates up to 400 kHz. After a read operation
the contents of the input register are reset to all zeros.

I2C BUS OPERATION

An I2C bus operates with one or more master devices that
generate the serial clock (SCL), and read/write data on the serial
data line (SDA) to/from slave devices such as the AD5398. All
devices on an I
line, and their SCL pin connected to the SCL line. I
can only pull the bus lines low; pulling high is achieved by pull­up resistors R
capacitance, and the maximum load current that the I
can sink (3 mA for a standard device).

DD

P

2

C bus have their SCL pin connected to the SDA

. The value of RP depends on the data rate, bus

P

RPR

I2C MASTER

DEVICE

SDA
SCL

AD5398

Figure 16. Typical I

I2C SLAVE

DEVICE

2

C Bus

2

C devices

I2C SLAVE

DEVICE

BAT

VOICE
COIL
ACTUATOR

8

I

SINK

2

C device

SENSE

05034-015

05034-016

When the bus is idle, SCL and SDA are both high. The master
device initiates a serial bus operation by generating a start
condition, which is defined as a high-to-low transition on the
SDA low while SCL is high. The slave device connected to the
bus responds to the start condition, and shifts in the next 8 data
bits under control of the serial clock. These 8 data bits consist of
a 7-bit address, plus a read/write bit, which is 0 if data is to be
written to a device, and 1 if data is to be read from a device. Each

2

slave device on an I

C bus must have a unique address. The
address of the AD5398 is 0001 100, however, 0001101, 0001110,
and 0001111 address the part because the last two bits are
unused/don’t care (see Figure 17 and Figure 18). Since the address
plus R/W bit always equals 8 bits of data, another way of looking
at it is that the write address of the AD5398 is 0001 1000 (0x18)
and the read address is 0001 1001 (0x19). Again, Bit 6 and Bit 7
of the address are unused, and therefore the write addresses can
also be 0x1A, 0x1C, and 0x1E, and the read address can be 0x1B,
0x1D, and 0x1F (see Figure 17 and Figure 18).

At the end of the address data, after the R/W bit, the slave
device that recognizes its own address responds by generating
an acknowledge (ACK) condition. This is defined as the slave
device pulling SDA low while SCL is low before the ninth clock
pulse, and keeping it low during the ninth clock pulse. Upon
receiving ACK, the master device can clock data into the
AD5398 in a write operation, or it can clock it out in a read
operation. Data must change only during the low period of the
clock, because SDA transitions during the high period define a
start condition as described previously, or a stop condition as
described in the Data Format section.

2

C data is divided into blocks of 8 bits, and the slave generates

I
an ACK at the end of each block. Since the AD5398 requires
10 bits of data, two data-words must be written to it when a
write operation, or read back from it when a read operation. At
the end of a read or write operation, the AD5398 acknowledges
the second data byte. The master generates a stop condition,
defined as a low-to-high transition on SDA while SCL is high,
to end the transaction.

DATA FORMAT

Data is written to the AD5398 high byte first, MSB first, and is
shifted into the 16-bit input register. After all data is shifted in,
data from the input register is transferred to the DAC register.

Because the DAC requires only 10 bits of data, not all bits of the
input register data are used. The MSB is reserved for an active­high, software-controlled, power-down function. Bit 14 is
unused; Bits 13 to 4 are DAC data; Bits 9 to 0 and Bits 3 to 0 are
unused.

During a read operation, data is read back in the same bit order.

Rev. 0 | Page 10 of 16

AD5398

A

A

1191

SCL

9

SD

START BY

MASTER

00

0 1 1 X X R/W

FRAME 1

SERIAL BUS

ADDRESS BYTE

PD X D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X

ACK BY
AD5398

FRAME 2

MOST SIGNIFICANT

DATA BYTE

ACK BY

AD5398

FRAME 3

LEAST SIGNIFICANT

DATA BYTE

ACK BY

AD5398

Figure 17. AD5398 Write Operation

SCL

SD

START BY

MASTER

1191

00

0 1 1 X X R/W

FRAME 1

SERIAL BUS

ADDRESS BYTE

PD X D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X

ACK BY
AD5398

FRAME 2

MOST SIGNIFICANT

DATA BYTE

ACK BY

AD5398

FRAME 3

LEAST SIGNIFICANT

DATA BYTE

9

ACK BY

AD5398

Figure 18. AD5398 Read Operation

Table 6. Data Format

Serial Data Words High Byte Low Byte

Serial Data Bits SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0
Input Register R15 R14 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 R0
Function PD X D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X

PD = soft power-down; X = unused/don’t care; D9 to D0 = DAC data

POWER SUPPLY BYPASSING AND GROUNDING

V

When accuracy is important in an application, it is beneficial to
consider power supply and ground return layout on the PCB.
The PCB for the AD5398 should have separate analog and
digital power supply sections. Where shared AGND and DGND
is necessary, the connection of grounds should be made at only
one point, as close as possible to the AD5398.

Special attention should be paid to the layout of the AGND
return path and track between the voice coil motor and I

SINK

to
minimize any series resistance. Figure 19 shows the output
current sink of the AD5398, and illustrates the importance of
reducing the effective series impedance of AGND, and the track
resistance between the motor and I
modeled as inductor L

and resistor RC. The current through

C

. The voice coil is

SINK

the voice coil is effectively a dc current which results in a
voltage drop, V

, when the AD5398 is sinking current; the effect

C

of any series inductance is minimal. The maximum voltage
drop allowed across R

is 400 mV, and the minimum drain

SENSE

to source voltage of Q1 is 200 mV. This means that the AD5398
output has a compliance voltage of 600 mV. If V

falls below

DROP

600 mV, the output transistor, Q1, can no longer operate
properly and I

might not be maintained as a constant.

SINK

VOICE

COIL

ACTUATOR

Q1

R

SENSE

3.3Ω

7

AGND

GROUND

RESISTANCE

GROUND

INDUCTANCE

R

G

V

L

G

Figure 19. Effect of PCB Trace Resistance and Inductance

BAT

L

C

V

C

T

C

TRACE
RESISTANCE

V

T

V

DROP

05034-019

R

R

8

I

SINK

G

STOP BY
MASTER

STOP BY
MASTER

05034-017

05034-018

Rev. 0 | Page 11 of 16

AD5398

K

As the current increases through the voice coil, VC increases
and V
specified compliance voltage of 600 mV. The ground return
path is modeled by the components R
resistance between the voice coil and the AD5398 is modeled as
R

T

and, because the current is maintained as a constant, it is not as
critical as the purely resistive component of the ground return
path. When the maximum sink current is flowing through the
motor the resistive elements, R
on the voltage headroom of Q1, and could, in turn, limit the
maximum value of R

For example,

V

BAT

R

G

R

T

I

SINK

V

DROP

Then the largest value of resistance of the voice coil, R

decreases and eventually approaches the minimum

DROP

and LG, and the track

G

. The inductive effects of LG influence R

and RG, might have an impact

T

because of voltage compliance.

C

SENSE

= 3.6 V

= 0.5 Ω

= 0.5 Ω

= 120 mA

= 600 mV (the compliance voltage)

SINKDROP

BAT

=

R

C

T

I

SIN

××+−

mA120

and RC equally

, is

C

×+×+−

RIRIVV

)]()([

GSINK

=

Ω)]0.5mA(1202mV[600V3.6

=

Ω24

For this reason it is important to minimize any series impedance
on both the ground return path and interconnect between the
AD5398 and the motor.

The power supply of the AD5398 should be decoupled with

0.1 µF and 10 µF capacitors. These capacitors should be kept as
physically close as possible, with the 0.1 µF capacitor serving as
a local bypass capacitor, and therefore should be located as close
as possible to the V

pin. The 10 µF capacitor should be a

DD

tantalum bead-type; the 0.1 µF capacitor should be a ceramic
type with a low effective series resistance and effective series
inductance. The 0.1 µF capacitor provides a low impedance path
to ground for high transient currents.

The power supply line itself should have as large a trace as
possible to provide a low impedance path and reduce glitch
effects on the supply line. Clocks and other fast switching digital
signals should be shielded from other parts of the board by
digital ground. Avoid crossover of digital and analog signals if
possible. When traces cross on opposite sides of the board,
ensure that they run at right angles to each other to reduce
feedthrough effects through the board. The best board layout
technique is to use a multilayer board with ground and power
planes, where the component side of the board is dedicated to
the ground plane only and the signal traces are placed on the
solder side. However, this is not always possible with a 2-layer
board.

The exposed paddle on the AD5398 should be soldered to
ground to ensure the best possible thermal performance. The
thermal impedance of the AD5398 LFCSP package is 48°C/W
when soldered in a 4-layer board. It is defined in the Absolute
Maximum Ratings.

Rev. 0 | Page 12 of 16

AD5398

APPLICATIONS

The AD5398 is designed to drive both spring preloaded and
nonspring linear motors used in applications such as lens auto­focus, image stabilization, or optical zoom. The operation
principle of the spring preloaded motor is that the lens position
is controlled by the balancing of a voice coil and spring. Figure 20
shows the transfer curve of a typical spring preloaded linear
motor for autofocus. The key points of this transfer function are
displacement or stroke, which is the actual distance the lens
moves in mm, and the current through the motor in mA.

0.5

0.4

Figure 21 shows the transfer curve for a linear motor, which
does not include a spring. The primary difference between this
type of motor and the spring preload motor is the absence of the
start current. Because no spring is used, displacement occurs
when current is applied.

The AD5398 is designed to sink up to 120 mA, which is more
than adequate for available commercial linear motors or voice
coils. Another factor that makes the AD5398 the ideal solution
for these applications is the monotonicity of the device, which
ensures that lens positioning is repeatable for the application of
a given digital word.

0.5

0.3

STROKE (mm)

0.2

START

0.1

CURRENT

0

10 20 30 40

50 60 70 80 90 100 110 1200

SINK CURRENT (mA)

Figure 20. Spring Preloaded Voice Coil Stroke vs. Sink Current

A start current is associated with spring preloaded linear
motors, which is effectively a threshold current that must be
exceeded for any displacement in the lens to occur. The start
current is usually 20 mA or greater; the rated stroke or
displacement is usually 0.25 mm to 0.4 mm; and the slope of
the transfer curve is approximately 10 µm/mA or less.

POWER-DOWN

RESET

V

DD

R

PRP

SDA
SCL

1

3

4

05034-020

AD5398

I2C SERIAL

INTERFACE

0.4

0.3

0.2

STROKE (mm)

0.1

0

10 20 30 40 50 60 70 80 90 100 110 1200

SINK CURRENT (mA)

Figure 21. Nonspring Voice Coil Stroke vs. Sink Current

Figure 22 shows a typical application circuit for the AD5398.

0.1µF 10µF

6

V

+

REFERENCE

10-BIT

CURRENT

OUTPUT DAC

DD

V

CC

POWER-ON

RESET

+

0.1µF10µF

VOICE
COIL
ACTUATOR

8

05034-021

I2C MASTER

DEVICE

I2C SLAVE

DEVICE

I2C SLAVE

DEVICE

5

Figure 22. Typical Application Circuit

Rev. 0 | Page 13 of 16

R

R

SENSE

3.3Ω

72

05034-022

AD5398

R

OUTLINE DIMENSIONS

INDICATO

PIN 1

3.00

BSC SQ

TOP

VIEW

2.75

BSC SQ

0.45

0.50

BSC

0.60 MAX

0.50

0.40

0.30

8

5

1

4

1.50
REF

PIN 1
INDICATOR

1.90

1.75

1.60

0.90

0.85

0.80

SEATING

PLANE

12° MAX

0.30

0.23

0.18

0.80 MAX

0.65 TYP

0.05 MAX

0.02 NOM

0.20 REF

0.25
MIN

1.60

1.45

1.30

Figure 23. 8-Lead Lead Frame Chip Scale Package [VD_LFCSP]

3 mm × 3 mm Body, Very Thin, Dual Lead

(CP-8-2)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD5398BCPZ-REEL
AD5398BCPZ-REEL7
AD5398BCPZ-WP

1

Z = Pb-free part.

1

1

1

–40°C to +85°C 8-lead VD_LFCSP CP-8-2
–40°C to +85°C 8-lead VD_LFCSP CP-8-2
–40°C to +85°C 8-lead VD_LFCSP CP-8-2

Rev. 0 | Page 14 of 16

AD5398

NOTES

Rev. 0 | Page 15 of 16

AD5398

NOTES

Purchase of licensed I
Rights to use these components in an I

© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.

D05304–0–12/04(0)

2

C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent

2

C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.

Rev. 0 | Page 16 of 16