Datasheet AD5383 Datasheet (Analog Devices)

Page 1

32-Channel, 3 V/5 V, Single-Supply,

FEATURES

Guaranteed monotonic INL error: ±1 LSB max On-chip 1.25 V/2.5 V, 10 ppm/°C reference Temperature range: –40°C to +85°C Rail-to-rail output amplifier Power-down mode Package type: 100-lead LQFP (14 mm × 14 mm) User Interfaces

Parallel Serial (SPI®-/QSPI™-/MICROWIRE™-/DSP-compatible,

featuring data readback)

C®-compatible

FUNCTIONAL BLOCK DIAGRAM

SER/PAR

FIFO EN

CS/(SYNC/AD0)

WR/(DCEN/AD1)

SDO

DB11/(DIN/SDA)

DB10/(SCLK/SCL)

DB9/(SPI/I

REG 0

REG 1

RESET

MON_IN1 MON_IN2 MON_IN3 MON_IN4

DB8

DB0

BUSY

CLR

A4 A0

(×3)

DGND (×3)

AD5383

MACHINE

CONTROL

OUT

FIFO

STATE

LOGIC

INTERFACE

CONTROL

LOGIC

POWER-ON

RESET

0………V

OUT

36-TO-1

MUX

AVDD (×4)

INPUT REG 0

12 12

INPUT REG 1

12 12

INPUT REG 6

12 12

INPUT REG 7

12 12

12-Bit, Voltage Output DAC

AD5383

INTEGRATED FUNCTIONS

Channel monitor Simultaneous output update via

Clear function to user-programmable code Amplifier boost mode to optimize slew rate User programmable offset and gain adjust Toggle mode enables square wave generation Thermal monitor

APPLICATIONS

Variable optical attenuators (VOA) Level setting (ATE) Optical microelectro-mechanical systems (MEMS) Control systems Instrumentation

AGND (×4) DAC GND (×4) REFGND REFOUT/REFIN SIGNAL GND (×4)

1.25V/2.5V

REFERENCE

1212 1212

m REG 0

c REG 0

m REG 1

c REG 1

m REG 6

c REG 6

m REG 7

c REG 7

×4

DAC

REG 0

DAC

REG 1

DAC

REG 6

DAC

REG 7

DAC 0

1212 1212

DAC 1

1212 1212

DAC 6

1212 1212

DAC 7

LDAC

OUT

MON_OUT LDAC

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

Figure 1.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700

www.analog.com

03734-001

Page 2

AD5383

TABLE OF CONTENTS

General Description......................................................................... 3

Asynchronous Clear Function.................................................. 25

Specifications..................................................................................... 4

AD5383-5 Specifications............................................................. 4

AD5383-3 Specifications............................................................. 6

AC Characteristics........................................................................ 7

Timing Characteristics..................................................................... 8

Serial Interface Timing................................................................ 8

C Serial Interface Timing........................................................ 10

Parallel Interface Timing........................................................... 11

Absolute Maximum Ratings.......................................................... 13

ESD CAUTION ..........................................................................13

Pin Configuration and Function Descriptions........................... 14

Terminology ....................................................................................17

Typical Performance Characteristics ...........................................18

Functional Description.................................................................. 21

DAC Architecture—General..................................................... 21

BUSY

FIFO Operation in Parallel Mode............................................ 25

Power-On Reset.......................................................................... 25

Power-Down ............................................................................... 25

Interfaces.......................................................................................... 26

DSP-, SPI-, MICROWIRE-Compatible Serial Interfaces ..... 26

C Serial Interface ..................................................................... 28

Parallel Interface......................................................................... 30

Microprocessor Interfacing....................................................... 31

Application Information................................................................ 33

Power Supply Decoupling......................................................... 33

Typical Configuration Circuit ..................................................33

Channel Monitor Function....................................................... 34

Toggle Mode Function............................................................... 34

Thermal Monitor Function....................................................... 34

and

LDAC

Functions...................................................... 25

Data Decoding............................................................................ 21

On-Chip Special Function Registers (SFR) ............................22

SFR Commands.......................................................................... 22

Hardware Functions....................................................................... 25

Reset Function ............................................................................25

REVISION HISTORY

3/05 — Rev. 0 to Rev. A

Changes to Table 1............................................................................ 3

Changes to Table 3............................................................................ 6

Change to Table 5 .............................................................................7

Change to Table 18......................................................................... 24

5/04 — Revision 0: Initial Version

Optical Attenuators.................................................................... 35

Utilizing the FIFO...................................................................... 36

Outline Dimensions....................................................................... 37

Ordering Guide .......................................................................... 37

Rev. A | Page 2 of 40

Page 3

AD5383

GENERAL DESCRIPTION

The AD5383 is a complete, single-supply, 32-channel, 12-bit DAC available in a 100-lead LQFP package. All 32 channels have an on-chip output amplifier with rail-to-rail operation. The AD5383 includes a programmable internal 1.25 V/2.5 V, 10 ppm/°C reference; an on-chip channel monitor function that multiplexes the analog outputs to a common MON_OUT pin for external monitoring; and an output amplifier boost mode that allows optimization of the amplifier slew rate. The AD5383 features

• Double-buffered parallel interface with a 20 ns

width.

pulse

• SPI-/QSPI-/MICROWIRE-/DSP-compatible serial

interface with interface speeds in excess of 30 MHz.

• I

C-compatible interface that supports a 400 kHz data

transfer rate.

An input register followed by a DAC register provides double buffering, allowing the DAC outputs to be updated independently or simultaneously using the

Each channel has a programmable gain and offset adjust register that allows the user to fully calibrate any DAC channel. With boost off, power consumption is typically 0.25 mA/channel.

Table 1 and Table 2 show additional products featuring high channel count, low voltage, single-supply operation, and bipolar voltage output operation.

LDAC

input.

Table 1. Other H l n olt D liigh Channe

AD5380BST-5 14 Bits 4.5 V to 5.5 V 40 ±4 100-Lead LQFP ST-100 AD5380BST-3 14 Bits 2.7 V to 3.6 V 40 ±4 100-Lead LQFP ST-100 AD5384BBC-5 14 Bits 4.5 V to 5.5 V 40 ±4 100-Lead CSPBGA BC-100 AD5384BBC-3 14 Bits 2.7 V to 3.6 V 40 ±4 100-Lead CSPBGA BC-100 AD5381BST-5 12 Bits 4.5 V to 5.5 V 40 ±1 100-Lead LQFP ST-100 AD5381BST-3 12 Bits 2.7 V to 3.6 V 40 ±1 100-Lead LQFP ST-100 AD5382BST-5 14 Bits 4.5 V to 5.5 V 32 ±4 100-Lead LQFP ST-100 AD5382BST-3 14 Bits 2.7 V to 3.6 V 32 ±4 100-Lead LQFP ST-100 AD5390BST-5 14 Bits 4.5 V to 5.5 V 16 ±3 52-Lead LQFP ST-52 AD5390BCP-5 14 Bits 4.5 V to 5.5 V 16 ±3 64-Lead LFCSP CP-64 AD5390BST-3 14 Bits 2.7 V to 3.6 V 16 ±4 52-Lead LQFP ST-52 AD5390BCP-3 14 Bits 2.7 V to 3.6 V 16 ±4 64-Lead LFCSP CP-64 AD5391BST-5 12 Bits 4.5 V to 5.5 V 16 ±1 52-Lead LQFP ST-52 AD5391BCP-5 12 Bits 4.5 V to 5.5 V 16 ±1 64-Lead LFCSP CP-64 AD5391BST-3 12 Bits 2.7 V to 3.6 V 16 ±1 52-Lead LQFP ST-52 AD5391BCP-3 12 Bits 2.7 V to 3.6 V 16 ±1 64-Lead LFCSP CP-64 AD5392BST-5 14 Bits 4.5 V to 5.5 V 8 ±3 52-Lead LQFP ST-52 AD5392BCP-5 14 Bits 4.5 V to 5.5 V 8 ±3 64-Lead LFCSP CP-64 AD5392BST-3 14 Bits 2.7 V to 3.6 V 8 ±4 52-Lead LQFP ST-52 AD5392BCP-3 14 Bits 2.7 V to 3.6 V 8 ±4 64-Lead LFCSP CP-64

Cou t, Low V age, Single-Supply AC Products in Portfo

ion

arity Error (LSB)

ption Model Resolut AVDD Range Output Channels Line Package Descri Package Option

Table 2. 40-Ch ar Aannel, Bipol

AD5379ABC 14 Bits ±11.4 V to ±16.5 V 40 ±3 108-Lead CSPBGA BC-108

Voltage Output D C

ion

ls Model Resolut Analog Supplies Output Channe Linearity Error (LSB) Package Package Option

Rev. A | Page 3 of 40

Page 4

AD5383

SPECIFICATIONS

AD5383-5 SPECIFICATIONS

AVDD = 4.5 V to 5.5 V; DVDD = 2.7 V to 5.5 V, AGND = DGND = 0 V; external REFIN = 2.5 V; all specifications T otherwise noted.

Table 3.

Parameter AD5383-51 Unit Test Conditions/Comments

ACCURACY

Resolution 12 Bits Relative Accuracy2 (INL) ±1 LSB max Differential Nonlinearity (DNL) ±1 LSB max Guaranteed monotonic over temperature Zero-Scale Error ±4 mV max Offset Error ±4 mV max Measured at Code 32 in the linear region Offset Error TC ±5 µV/°C typ Gain Error ±0.024 % FSR max At 25°C ±0.06 % FSR max T

MIN

to T

MAX

Gain Temperature Coefficient3 2 ppm FSR/°C typ DC Crosstalk3 0.5 LSB max

REFERENCE INPUT/OUTPUT

Reference Input3

Reference Input Voltage 2.5 V ±1% for specified performance, AVDD = 2 × REFIN + 50 mV DC Input Impedance 1 MΩ min Typically 100 MΩ Input Current ±10 µA max Typically ±30 nA Reference Range 1 to VDD/2 V min/max

Reference Output4

Enabled via CR8 in the AD5383 control register, CR10 selects the reference voltage

Output Voltage 2.495/2.505 V min/max At ambient; optimized for 2.5 V operation; CR10 = 1

1.22/1.28 V min/max 1.25 V reference selected; CR10 = 0 Reference TC ±10 ppm/°C max Temperature range: +25°C to +85°C ±15 ppm/°C max Temperature range: −40°C to +85°C

OUTPUT CHARACTERISTICS3

Output Voltage Range2 0/AVDD V min/max Short-Circuit Current 40 mA max Load Current ±1 mA max Capacitive Load Stability

RL = ∞ 200 pF max RL = 5 kΩ 1000 pF max

DC Output Impedance 0.5 Ω max

MONITOR PIN

Output Impedance 500 Ω typ Three-State Leakage Current 100 nA typ

LOGIC INPUTS (EXCEPT SDA/SCL)3 DVDD = 2.7 V to 5.5 V

VIH, Input High Voltage 2 V min VIL, Input Low Voltage 0.8 V max Input Current ±10 µA max Total for all pins; TA = T

MIN

to T

Pin Capacitance 10 pF max

LOGIC INPUTS (SDA, SCL ONLY)

VIH, Input High Voltage 0.7 DVDD V min SMBus compatible at DVDD < 3.6 V VIL, Input Low Voltage 0.3 DVDD V max SMBus compatible at DVDD < 3.6 V IIN, Input Leakage Current ±1 µA max V

, Input Hysteresis 0.05 DVDD V min

HYST

CIN, Input Capacitance 8 pF typ Glitch Rejection 50 ns max Input filtering suppresses noise spikes of less than 50 ns

MAX

MIN

to T

MAX

, unless

Rev. A | Page 4 of 40

Page 5

AD5383

Parameter AD5383-51 Unit Test Conditions/Comments

LOGIC OUTPUTS (

BUSY

, SDO)3 VOL, Output Low Voltage 0.4 V max DVDD = 5 V ± 10%, sinking 200 µA VOH, Output High Voltage DVDD – 1 V min DVDD = 5 V ± 10%, sourcing 200 µA VOL, Output Low Voltage 0.4 V max DVDD = 2.7 V to 3.6 V, sinking 200 µA VOH, Output High Voltage DVDD – 0.5 V min DVDD = 2.7 V to 3.6 V, sourcing 200 µA High Impedance Leakage Current ±1 µA max SDO only High Impedance Output Capacitance 5 pF typ SDO only

LOGIC OUTPUT (SDA)3

VOL, Output Low Voltage 0.4 V max I

0.6 V max I Three-State Leakage Current ±1 µA max Three-State Output Capacitance 8 pF typ

POWER REQUIREMENTS

AVDD 4.5/5.5 V min/max DVDD 2.7/5.5 V min/max Power Supply Sensitivity3

∆Midscale/∆ΑVDD –85 dB typ

AIDD 0.375 mA/channel max Outputs unloaded, boost off; 0.25 mA/channel typ

0.475 mA/channel max Outputs unloaded, boost on; 0.325 mA/channel typ DIDD 1 mA max VIH = DVDD, VIL = DGND AIDD (Power-Down) 2 µA max Typically 200 nA DIDD (Power-Down) 20 µA max Typically 3 µA Power Dissipation 65 mW max Outputs unloaded, boost off, AVDD = DVDD = 5 V

AD5383-5 is calibrated using an external 2.5 V reference. Temperature range for all versions: –40°C to +85°C.

Accuracy guaranteed from V

Guaranteed by characterization, not production tested.

Default on the AD5383-5 is 2.5 V. Programmable to 1.25 V via CR10 in the AD5383 control register; operating the AD5383-5 with a 1.25 V reference leads to degraded

accuracy specifications.

= 10 mV to AVDD – 50 mV.

OUT

= 3 mA

SINK

= 6 mA

SINK

Rev. A | Page 5 of 40

Page 6

AD5383

AD5383-3 SPECIFICATIONS

AVDD = 2.7 V to 3.6 V; DVDD = 2.7 V to 5.5 V, AGND = DGND = 0 V; external REFIN = 1.25 V; all specifications T otherwise noted.

Table 4.

Parameter AD5383-31 Unit Test Conditions/Comments

ACCURACY

Resolution 12 Bits Relative Accuracy2 (INL) ±1 LSB max Differential Nonlinearity (DNL) ±1 LSB max Guaranteed monotonic over temperature Zero-Scale Error 4 mV max Offset Error ±4 mV max Measured at Code 64 in the linear region Offset Error TC ±5 µV/°C typ Gain Error ±0.024 % FSR max At 25°C ±0.1 % FSR max T

MIN

to T

MAX

Gain Temperature Coefficient3 2 ppm FSR/°C typ DC Crosstalk3 0.5 LSB max

REFERENCE INPUT/OUTPUT

Reference Input3

Reference Input Voltage 1.25 V ±1% for specified performance DC Input Impedance 1 MΩ min Typically 100 MΩ Input Current ±10 µA max Typically ±30 nA Reference Range 1 to AVDD/2 V min/max

Reference Output4

Enabled via CR8 in the AD5383 control register, CR10 selects the reference voltage

Output Voltage 1.245/1.255 V min/max At ambient; optimized for 1.25 V operation; CR10 = 0

2.47/2.53 V min/max 2.5 V reference enabled; CR10 = 1 Reference TC ±10 ppm/°C typ Temperature range: +25°C to +85°C ±15 ppm/°C typ

Temperature range: −40°C to +85°C

OUTPUT CHARACTERISTICS3

Output Voltage Range2 0/AVDD V min/max Short-Circuit Current 40 mA max Load Current ±1 mA max Capacitive Load Stability

RL = ∞ 200 pF max RL = 5 kΩ 1000 pF max

DC Output Impedance 0.5 Ω max

MONITOR PIN

Output Impedance 500 Ω typ Three-State Leakage Current 100 nA typ

LOGIC INPUTS (EXCEPT SDA/SCL)3 DVDD = 2.7 V to 3.6 V

VIH, Input High Voltage 2 V min V

Input Low Voltage 0.8 V max

IL,

Input Current ±10 µA max Total for all pins; TA = T

MIN

to T

MAX

Pin Capacitance 10 pF max

LOGIC INPUTS (SDA, SCL ONLY)

VIH, Input High Voltage 0.7 DVDD V min SMBus-compatible at DVDD < 3.6 V VIL, Input Low Voltage 0.3 DVDD V max SMBus-compatible at DVDD < 3.6 V IIN, Input Leakage Current ±1 µA max V

, Input Hysteresis 0.05 DVDD V min

HYST

CIN, Input Capacitance 8 pF typ Glitch Rejection 50 ns max Input filtering suppresses noise spikes of less than 50 ns

MIN

to T

MAX

, unless

Rev. A | Page 6 of 40

Page 7

AD5383

Parameter AD5383-31 Unit Test Conditions/Comments

LOGIC OUTPUTS (BUSY, SDO)3

VOL, Output Low Voltage 0.4 V max Sinking 200 µA VOH, Output High Voltage DVDD – 0.5 V min Sourcing 200 µA High Impedance Leakage Current ±1 µA max SDO only High Impedance Output Capacitance 5 pF typ SDO only

LOGIC OUTPUT (SDA)3

VOL, Output Low Voltage 0.4 V max I

0.6 V max I Three-State Leakage Current ±1 µA max Three-State Output Capacitance 8 pF typ

POWER REQUIREMENTS

AVDD 2.7/3.6 V min/max DVDD 2.7/5.5 V min/max Power Supply Sensitivity3

∆Midscale/∆ΑVDD –85 dB typ

AIDD 0.375 mA/channel max Outputs unloaded, boost off; 0.25 mA/channel typ

0.475 mA/channel max Outputs unloaded, boost on; 0.325 mA/channel typ DIDD 1 mA max VIH = DVDD, VIL = DGND. AIDD (Power-Down) 2 µA max Typically 200 nA DIDD (Power-Down) 20 µA max Typically 1 µA Power Dissipation 39 mW max Outputs unloaded, boost off; AVDD = DVDD = 3 V

AD5383-3 is calibrated using an external 1.25 V reference. Temperature range is –40°C to +85°C.

Accuracy guaranteed from V

Guaranteed by characterization, not production tested.

Default on the AD5383-3 is 1.25 V. Programmable to 2.5 V via CR10 in the AD5383 control register; operating the AD5383-3 with a 2.5 V reference leads to degraded

accuracy specifications and limited input code range.

= 10 mV to AVDD – 50 mV.

OUT

= 3 mA

SINK

= 6 mA

SINK

AC CHARACTERISTICS1

AVDD = 4.5 V to 5.5 V or 2.7 V to 3.6 V; DVDD = 2.7 V to 5.5 V; AGND = DGND = 0 V.

Table 5.

Parameter All Unit Test Conditions/Comments

DYNAMIC PERFORMANCE

Output Voltage Settling Time2 ¼ scale to ¾ scale change settling to ±1 LSB 6 µs typ 8 µs max Slew Rate2 2 V/µs typ Boost mode off, CR9 = 0 3 V/µs typ Boost mode on, CR9 = 1 Digital-to-Analog Glitch Energy 12 nV-s typ Glitch Impulse Peak Amplitude 15 mV typ DAC-to-DAC Crosstalk 1 nV-s typ See Terminology section Digital Crosstalk 0.8 nV-s typ Digital Feedthrough 0.1 nV-s typ Effect of input bus activity on DAC output under test Output Noise 0.1 Hz to 10 Hz 15 µV p-p typ External reference, midscale loaded to DAC 40 µV p-p typ Internal reference, midscale loaded to DAC Output Noise Spectral Density

@ 1 kHz 150 nV/√Hz typ @ 10 kHz 100 nV/√Hz typ

Guaranteed by design and characterization, not production tested.

The slew rate can be programmed via the current boost control bit (CR9) in the AD5383 control register.

Rev. A | Page 7 of 40

Page 8

AD5383

TIMING CHARACTERISTICS

SERIAL INTERFACE TIMING

DVDD = 2.7 V to 5.5 V; AVDD = 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V; all specifications T noted.

MIN

to T

, unless otherwise

MAX

Table 6.

Parameter

1, 2, 3

Limit at T

MIN

, T

Unit Description

MAX

t1 33 ns min SCLK cycle time t2 13 ns min SCLK high time t3 13 ns min SCLK low time t4 13 ns min

13 ns min

33 ns min

t7 10 ns min t7A 50 ns min

SYNC

falling edge to SCLK falling edge setup time

SYNC

24th SCLK falling edge to Minimum

Minimum Minimum

SYNC low time SYNC high time SYNC high time in readback mode

falling edge

t8 5 ns min Data setup time t9 4.5 ns min Data hold time

30 ns max

t11 670 ns max

20 ns min

t13 20 ns min t14 100 ns max t15 0 ns min t16 100 ns min

24th SCLK falling edge to BUSY

pulse width low (single channel update) 24th SCLK falling edge to LDAC

pulse width low BUSY

rising edge to DAC output response time BUSY

rising edge to LDAC

falling edge to DAC output response time

BUSY

LDAC

falling edge

t17 8 µs typ DAC output settling time, boost mode off t18 20 ns min

35 µs max

20 ns max SCLK rising edge to SDO valid

5 ns min

8 ns min

t23 20 ns min

Guaranteed by design and characterization, not production tested.

All input signals are specified with t

See , F , and . Figure 2 igure 3 Figure 4, Figure 5

Standalone mode only.

Daisy-chain mode only.

= t

= 5 ns (10% to 90% of VCC) and are timed from a voltage level of 1.2 V.

CLR

pulse width low

CLR

pulse activation time

SCLK falling edge to SYNC

rising edge to SCLK rising edge SYNC

rising edge to

SYNC

LDAC

rising edge

falling edge

O OUTPUT PIN

50pF

200µA

(MIN) OR

(MAX)

03734-002

Figure 2. Load Circuit for SDO Timing Diagram

(Serial Interface, Daisy- Chain Mode)

Rev. A | Page 8 of 40

Page 9

AD5383

SCLK

SYNC

BUSY

LDAC

OUT

LDAC

OUT

CLR

DIN

1 1

OUT

LDAC ACTIVE DURING BUSY

LDAC ACTIVE AFTER BUSY

Figure 3. Serial Interface Timing Diagram (Standalone Mode)

t8t

DB23

DB0

2424

03734-003

SYNC

DIN

SDO

SCLK

SYNC

DIN

SDO

24 48SCLK

DB23 DB0 DB23 DB0

INPUT WORD SPECIFIES

UNDEFINED

DB23 DB0

NOP CONDITION

SELECTED REGISTER

DATA CLOCKED OUT

Figure 4. Serial Interface Timing Diagram (Data Readback Mode)

t8t

DB23 DB0 DB0DB23

INPUT WORD FOR DAC N INPUT WORD FOR DAC N+1

DB23 DB0

03734-004

4824

UNDEFINED INPUT WORD FOR DAC N

LDAC

Figure 5. Serial Interface Timing Diagram (Daisy-Chain Mode)

03734-005

Rev. A | Page 9 of 40

Page 10

AD5383

I2C SERIAL INTERFACE TIMING

DVDD = 2.7 V to 5.5 V; AVDD = 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V; all specifications T noted.

MIN

to T

, unless otherwise

MAX

Table 7.

Parameter

SCL

1, 2

Limit at T

, T

Unit Description

MIN

MAX

400 kHz max SCL clock frequency t1 2.5 µs min SCL cycle time t2 0.6 µs min t t3 1.3 µs min t t4 0.6 µs min t t5 100 ns min t

0.9 µs max t

0 µs min t t7 0.6 µs min t t8 0.6 µs min t t9 1.3 µs min t

, SCL high time

HIGH

, SCL low time

LOW

, start/repeated start condition hold time

HD,STA

, data setup time

SU,DAT

, data hold time

HD,DAT

, data hold time

HD,DAT

, setup time for repeated start

SU,STA

, stop condition setup time

SU,STO

, bus free time between a STOP and a START condition

BUF

t10 300 ns max tR, rise time of SCL and SDA when receiving 0 ns min tR, rise time of SCL and SDA when receiving (CMOS-compatible) t11 300 ns max tF, fall time of SDA when transmitting 0 ns min tF, fall time of SDA when receiving (CMOS-compatible) 300 ns max tF, fall time of SCL and SDA when receiving 20 + 0.1 C

ns min tF, fall time of SCL and SDA when transmitting

Cb 400 pF max Capacitive load for each bus line

Guaranteed by design and characterization, not production tested.

See . Figure 6

A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the V

falling edge.

Cb is the total capacitance, in pF, of one bus line. tR and tF are measured between 0.3 DVDD and 0.7 DVDD.

min of the SCL signal) in order to bridge the undefined region of SCL’s

SDA

SCL

START

CONDITION

Figure 6. I

C-Compatible Serial Interface Timing Diagram

REPEATED

CONDITION

START

STOP

CONDITION

03734-006

Rev. A | Page 10 of 40

Page 11

AD5383

PARALLEL INTERFACE TIMING

DVDD = 2.7 V to 5.5 V; AVDD = 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V; all specifications T noted.

MIN

to T

, unless otherwise

MAX

Table 8.

Parameter

t0 4.5 ns min t1 4.5 ns min t2 20 ns min t3 20 ns min t4 0 ns min t5 0 ns min t6 4.5 ns min t7 4.5 ns min t8 20 ns min

700 ns min

30 ns max

4, 5

t12 30 ns min t13 20 ns min t14 100 ns max t15 20 ns min t16 0 ns min t17 100 ns min

1, 2, 3

Limit at T

MIN

, T

Unit Description

MAX

670 ns max

REG0, REG1, address to REG0, REG1, address to CS

pulse width low

to WR falling edge setup time

to CS rising edge hold time

Data to WR rising edge setup time

Data to WR

Minimum WR

BUSY WR LDAC BUSY LDAC BUSY LDAC

rising edge hold time

pulse width high

cycle time (single-channel write)

rising edge to

BUSY

pulse width low (single-channel update)

rising edge to

LDAC

pulse width low

rising edge to DAC output response time

rising edge to WR rising edge

rising edge to

LDAC

falling edge to DAC output response time t18 8 µs max DAC output settling time t19 20 ns min

t20 35 µs max

Guaranteed by design and characterization, not production tested.

All input signals are specified with tR = tR = 5 ns (10% to 90% of DVDD) and timed from a voltage level of 1.2 V.

See . Figure 7

See . Figure 29

Measured with the load circuit of . Figure 2

CLR

pulse width low

CLR

pulse activation time

rising edge setup time

rising edge hold time

falling edge

Rev. A | Page 11 of 40

Page 12

AD5383

REG0, REG1, A4..A0

DB11..DB0

BUSY

LDAC

OUT

LDAC

OUT

CLR

OUT

LDAC ACTIVE DURING BUSY

LDAC ACTIVE AFTER BUSY

03734-007

Figure 7. Parallel Interface Timing Diagram

Rev. A | Page 12 of 40

Page 13

AD5383

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted1.

Table 9.

Parameter Rating AVDD to AGND –0.3 V to +7 V DVDD to DGND –0.3 V to +7 V Digital Inputs to DGND –0.3 V to DVDD + 0.3 V SDA/SCL to DGND –0.3 V to +7 V Digital Outputs to DGND –0.3 V to DVDD + 0.3 V REFIN/REFOUT to AGND –0.3 V to AVDD + 0.3 V AGND to DGND –0.3 V to +0.3 V V

x to AGND –0.3 V to AVDD + 0.3 V

OUT

Analog Inputs to AGND –0.3 V to AVDD + 0.3 V MON_IN Inputs to AGND –0.3 V to AVDD + 0.3 V MON_OUT to AGND –0.3 V to AVDD + 0.3 V Operating Temperature Range

Commercial (B Version) –40°C to +85°C Storage Temperature Range –65°C to +150°C JunctionTemperature (TJ Max) 150°C 100-Lead LQFP Package

θJA Thermal Impedance 44°C/W Reflow Soldering

Peak Temperature 230°C

Transient currents of up to 100 mA will not cause SCR latch-up.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Rev. A | Page 13 of 40

Page 14

AD5383

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

FIFO EN

CLR

OUT

SIGNAL_GND4

DAC_GND4

AGND4

OUT

REF GND

REFOUT/REFIN

SIGNAL_GND1

DAC_GND1

OUT

AGND1

DB7

OUT

DB6

OUT

SDO(A/B)

DGND

DGNDNCA4A3A2A1A0

AD5383

TOP VIEW

(Not to Scale)

363137383940424344

MON_IN1

MON_IN2

MON_IN3

DVDDDVDDDGND

SER/PARPDWR (DCEN/AD1)

8793868584828180797877

MON_IN4

OUT

45414647484950

OUT

DAC_GND2

MON_OUT

SIGNAL_GND2

OUT

LDAC

BUSY

OUT

RESET

DB5

DB4

DB3

DB2

DB1

DB0

REG0

REG1

OUT

AGND3

DAC_GND3

SIGNAL_GND3

OUT

AGND2

03734-008

CS/(SYNC/AD0)

100

1 2 3

7 8 9

15 16 17 18 19

262827293032333435

NCNCNC

DB8

DB11/(DIN/SDA)

DB10/(SCLK/SCL)

DB9/(SPI/I

9899979695949291908988

PIN 1 IDENTIFIER

OUT

Figure 8. 100-Lead LQFP Pin Configuration

Table 10. Pin Function Descriptions

Mnemonic Function

OUT

Buffered Analog Outputs for Channel x. Each analog output is driven by a rail-to-rail output amplifier operating at a gain of 2. Each output is capable of driving an output load of 5 kΩ to ground. Typical output impedance is 0.5 Ω.

SIGNAL_GND(1 to 4)

Analog Ground Reference Points for Each Group of Eight Output Channels. All SIGNAL_GND pins are tied together internally and should be connected to the AGND plane as close as possible to the AD5383.

DAC_GND(1 to 4)

Each Group of Eight Channels Contains a DAC_GND Pin. This is the ground reference point for the internal 12-bit DAC. These pins shound be connected to the AGND plane.

AGND(1 to 4)

Analog Ground Reference Point. Each group of eight channels contains an AGND pin. All AGND pins should be connected externally to the AGND plane.

AVDD(1 to 4)

Analog Supply Pins. Each group of eight channels has a separate AV internally and should be decoupled with a 0.1 µF ceramic capacitor and a 10 µF tantalum capacitor. Operating

range for the AD5383-5 is 4.5 V to 5.5 V; operating range for the AD5383-3 is 2.7 V to 3.6 V. DGND Ground for All Digital Circuitry. DVDD

Logic Power Supply. Guaranteed operating range is 2.7 V to 5.5 V. It is recommended that these pins be decoupled

with 0.1 µF ceramic and 10 µF tantalum capacitors to DGND. REF GND Ground Reference Point for the Internal Reference. REFOUT/REFIN

The AD5383 Contains a Common REFOUT/REFIN Pin. When the internal reference is selected, this pin is the

reference output. If the application requires an external reference, it can be applied to this pin and the internal

reference can be disabled via the control register. The default for this pin is a reference input.

Rev. A | Page 14 of 40

pin. These pins are connected together

Page 15

AD5383

Mnemonic Function

MON_OUT

MON_INx

PA R

SER/

CS/(SYNC

/AD0)

/(DCEN/AD1)

DB11 to DB0 Parallel Data Bus. DB11 is the MSB and DB0 is the LSB of the input data-word on the AD5383. A4 to A0

REG1, REG0

SDO/(A/B)

BUSY

LDAC Load DAC Logic Input (Active Low). If LDAC is taken low while BUSY is inactive (high), the contents of the input

CLR Asynchronous Clear Input. The CLR input is falling edge sensitive. When CLR is activated, all channels are updated

RESET Asynchronous Digital Reset Input (Falling Edge Sensitive). The function of this pin is equivalent to that of the power-

MON_OUT Monitor Output Pin. When the monitor function is enabled, this output acts as the output of a 36-to-1 channel multiplexer that can be programmed to multiplex one of Channels 0 to 31or any of the monitor input pins (MON_IN1 to MON_IN4) to the MON_OUT pin. The MON_OUT pin’s output impedance is typically 500 Ω, and is intended to drive a high input impedance like that exhibited by SAR ADC inputs.

MON_IN Monitor Input Pins. The AD5383 contains four monitor input pins that allow the user to connect input signals within the maximum ratings of the device to these pins for monitoring purposes. Any of the signals applied to the MON_IN pins along with the 32 output channels can be switched to the MON_OUT pin via software. An external ADC, for example, can be used to monitor these signals.

Interface Select Input. This pin allows the user to select whether the serial or parallel interface is used. If it is tied

SPI

high, the serial interface mode is selected and Pin 97 ( Parallel interface mode is selected when SER/

PA R

/I2C) is used to determine if the interface mode is SPI or I2C.

is low.

Parallel Interface Mode. This pin acts as chip select input (level sensitive, active low). When low, the AD5383 is selected.

Serial Interface Mode. This is the frame synchronization input signal for the serial clocks before the addressed register is updated.

C Mode. This pin acts as a hardware address pin used in conjunction with AD1 to determine the software address

I for the device on the I

Multifunction Pin. In parallel interface mode, this pin acts as write enable. In serial interface mode, this pin acts as a daisy-chain enable in SPI mode, and as a hardware address pin in I

Parallel Interface Write Input (Edge Sensitive). The rising edge of

C bus.

C mode.

is used in conjunction with CS low and the

address bus inputs to write to the selected device registers. Serial Interface. Daisy-chain select input (level sensitive, active high). When high, this signal is used in conjunction

PA R

with SER/

C Mode. This pin acts as a hardware address pin used in conjunction with AD0 to determine the software address

I for this device on the I

high to enable the SPI serial interface daisy-chain mode.

C bus.

Parallel Address Inputs. A4 to A0 are decoded to address one of the AD5383’s 40 input channels. Used in conjunction with the REG1 and REG0 pins to determine the destination register for the input data.

Register Pins. In parallel interface mode, REG1 and REG0 are used in decoding the destination registers for the input data. REG1 and REG0 are decoded to address the input data register, offset register, or gain register for the selected channel and are also used to decide the special function registers.

Serial Data Output in Serial Interface Mode. Three-stateable CMOS output. SDO can be used for daisy-chaining a number of devices together. Data is clocked out on SDO on the rising edge of SCLK, and is valid on the falling edge of SCLK.

When operating in parallel interface mode, this pin acts as the A or B data register select when writing data to the AD5383’s data registers with toggle mode selected (see the Toggle Mode Function section). In toggle mode, the LDAC

is used to switch the output between the data contained in the A and B data registers. All DAC channels

contain two data registers. In normal mode, Data Register A is the default for data transfers. Digital CMOS Output.

BUSY

goes low during internal calculations of the data (x2) loaded to the DAC data register.

During this time, the user can continue writing new data to the x1, c, and m registers in parallel mode (these are

LDAC

BUSY

is taken low pin is low.

stored in a FIFO), but no further updates to the DAC registers and DAC outputs can take place. If

BUSY

while

is low, this event is stored.

During this time, the interface is disabled and any events on

BUSY

also goes low during power-on reset, and when the

LDAC are ignored. A CLR operation also brings BUSY

low.

registers are transferred to the DAC registers and the DAC outputs are updated. If active and internal calculations are taking place, the

BUSY

goes inactive. However any events on

with the data contained in the updated with the

CLR code.

CLR code register.

LDAC

event is stored and the DAC registers are updated when

during power-on reset or on

BUSY

is low for a duration of 35 µs while all channels are being

LDAC

RESET

is taken low while BUSY is

are ignored.

on reset generator. When this pin is taken low, the state machine initiates a reset sequence to digitally reset the x1, m, c, and x2 registers to their default power-on values. This sequence typically takes 270 µs. The falling edge of RESET

initiates the BUSY

While resumes normal operation and the status of the

RESET

process and

BUSY

goes low for the duration, returning high when

is low, all interfaces are disabled and all

RESET pin is ignored until the next falling edge is detected.

LDAC

pulses are ignored. When

RESET

is complete.

BUSY

returns high, the part

Rev. A | Page 15 of 40

Page 16

AD5383

Mnemonic Function

FIFO EN

SPI

DB9/(

/I2C)

In this mode, DB12 is the serial clock (SCL) input and DB11 is the serial data (SDA) input. DB10/(SCLK/SCL)

DB11/(DIN/SDA) Multifunction Data Input Pin. In parallel interface mode, this pin acts as DB11 of the parallel input data-word.

I NC No Connect. The user is advised not to connect any signal to these pins.

Power Down (Level Sensitive, Active High). PD is used to place the device in low power mode where the device

consumes 2 µA analog supply current and 20 µA digital supply current. In power-down mode, all internal analog

circuitry is placed in low power mode, and the analog output is configured as a high impedance output or will

provide a 100 kΩ load to ground, depending on how the power-down mode is configured. The serial interface

remains active during power-down.

FIFO Enable (Level Sensitive, Active High). When connected to DV

, the internal FIFO is enabled, allowing the user

to write to the device at full speed. FIFO is only available in parallel interface mode. The status of the FIFO EN pin is

sampled on power-up, and also following a CLEAR or RESET, to determine if the FIFO is enabled. In either serial or I

interface modes, the FIFO EN pin should be tied low.

Multifunction Input Pin. In parallel interface mode, this pin acts as DB9 of the parallel input data-word. In serial

interface mode, this pin acts as serial interface mode select. When serial interface mode is selected (SER/

PA R

and this input is low, SPI mode is selected. In SPI mode, DB12 is the serial clock (SCLK) input and DB11 is the serial

data (DIN) input.

When serial interface mode is selected (SER/

PA R = 1) and this input is high I2C mode is selected.

Multifunction Input Pin. In parallel interface mode, this pin acts as DB10 of the parallel input data-word. In serial

interface mode, this pin acts as a serial clock input.

Serial Interface Mode. In serial interface mode, data is clocked into the shift register on the falling edge of SCLK. This

operates at clock speeds up to 50 MHz.

C Mode. In I2C mode, this pin performs the SCL function, clocking data into the device. The data transfer rate in I2C

mode is compatible with both 100 kHz and 400 kHz operating modes.

Serial Interface Mode. In serial interface mode, this pin acts as the serial data input. Data must be valid on the falling

edge of SCLK.

C Mode. In I2C mode, this pin is the serial data pin (SDA) operating as an open-drain input/output.

= 1)

Rev. A | Page 16 of 40

Page 17

AD5383

TERMINOLOGY

Relative Accuracy

Relative accuracy, or endpoint linearity, is a measure of the maximum deviation from a straight line passing through the endpoints of the DAC transfer function. It is measured after adjusting for zero-scale error and full-scale error, and is expressed in LSB.

Differential Nonlinearity

Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of 1 LSB maximum ensures monotonicity.

Zero-Scale Error

Zero-scale error is the error in the DAC output voltage when all 0s are loaded into the DAC register. Ideally, with all 0s loaded to the DAC and m = all 1s, c = 2

OUT(Zero-Scale)

= 0 V

Zero-scale error is a measure of the difference between V (actual) and V

(ideal), expressed in mV. It is mainly due to

OUT

n – 1

OUT

offsets in the output amplifier.

Offset Error

Offset error is a measure of the difference between V and V

(ideal) in the linear region of the transfer function,

OUT

(actual)

OUT

expressed in mV. Offset error is measured on the AD5383-5 with Code 32 loaded into the DAC register, and on the AD5383-3 with Code 64.

Gain Error

Gain Error is specified in the linear region of the output range between V

= 10 mV and V

OUT

= AVDD – 50 mV. It is the

OUT

deviation in slope of the DAC transfer characteristic from the ideal and is expressed in %FSR with the DAC output unloaded.

DC Crosstalk

DC crosstalk is the dc change in the output level of one DAC at midscale in response to a full-scale code (all 0s to all 1s, and vice versa) and output change of all other DACs. It is expressed in LSB.

DC Output Impedance

DC output impedance is the effective output source resistance. It is dominated by package lead resistance.

Output Voltage Settling Time

Output voltage settling time is the amount of time it takes for the output of a DAC to settle to a specified level for a ¼ to ¾

BUSY

full-scale input change, and is measured from the

rising

edge.

Digital-to-Analog Glitch Energy

Digital-to-analog glitch energy is the amount of energy injected into the analog output at the major code transition. It is specified as the area of the glitch in nV-s. It is measured by toggling the DAC register data between 0x1FFF and 0x2000.

DAC-to-DAC Crosstalk

DAC-to-DAC crosstalk is the glitch impulse that appears at the output of one DAC due to both the digital change and to the subsequent analog output change at another DAC. The victim channel is loaded with midscale. DAC-to-DAC crosstalk is specified in nV-s.

Digital Crosstalk

The glitch impulse transferred to the output of one converter due to a change in the DAC register code of another converter is defined as the digital crosstalk and is specified in nV-s.

Digital Feedthrough

When the device is not selected, high frequency logic activity on the device’s digital inputs can be capacitively coupled both across and through the device to show up as noise on the V

OUT

pins. It can also be coupled along the supply and ground lines. This noise is digital feedthrough.

Output Noise Spectral Density

Output noise spectral density is a measure of internally generated random noise. Random noise is characterized as a spectral density (voltage per √Hertz). It is measured by loading all DACs to midscale and measuring noise at the output. It is measured in nV/√Hz in a 1 Hz bandwidth at 10 kHz.

Rev. A | Page 17 of 40

Page 18

AD5383

TYPICAL PERFORMANCE CHARACTERISTICS

1.00

0.75

0.50

= 5V

REFIN = 2.5V

= 25°C

1.00

0.75

0.50

AVDD = 3V

REFIN = 1.25V

= 25°C

–0.25

INL ERROR (LSB)

–0.50

–0.75

–1.00

2.539

2.538

2.537

2.536

2.535

2.534

2.533

2.532

2.531

2.530

2.529

AMPLITUDE (V)

2.528

2.527

2.526

2.525

2.524

2.523

0.25

INPUT CODE

40960 512 1024 1536 2048 2560 3072 3584

03734-009

Figure 9. Typical AD5383-5 INL Plot

AVDD = DVDD = 5V

= 2.5V

REF

= 25°C

14ns/SAMPLE NUMBER 1 LSB CHANGE AROUND MIDSCALE GLITCH IMPULSE = 10nV-s

SAMPLE NUMBER

5500 100 150 200 250 30050 350 400 500450

03734-010

Figure 10. AD5383-5 Glitch Impulse

–0.25

INL ERROR (LSB)

–0.50

–0.75

–1.00

1.254

1.253

1.252

1.251

1.250

1.249

1.248

AMPLITUDE (V)

1.247

1.246

1.245

INPUT CODE

40960 512 1024 1536 2048 2560 3072 3584

03734-012

Figure 12. Typical AD5383-3 INL Plot

AVDD = DVDD = 3V

= 1.25V

REF

= 25°C

14ns/SAMPLE NUMBER 1 LSB CHANGE AROUND MIDSCALE GLITCH IMPULSE = 5nV-s

SAMPLE NUMBER

5500 100 150 200 250 30050 350 400 500450

03734-013

Figure 13. AD5383-3 Glitch Impulse

AVDD = DVDD = 5V

= 2.5V

REF

= 25°C

OUT

Figure 11. Slew Rate with Boost Off

03734-011

Rev. A | Page 18 of 40

AVDD = DVDD = 5V

= 2.5V

REF

= 25°C

Figure 14. Slew Rate with Boost On

OUT

03734-014

Page 19

AD5383

AVDD = 5.5V

= 2.5V

REF

= 25°C

AVDD = DVDD = 5V

= 2.5V

REF

= 25°C

POWER SUPPLY RAMP RATE = 10ms

OUT

PERCENTAGE OF UNITS (%)

NUMBER OF UNITS

Figure 15. AI

Figure 16. DI

AIDD (mA)

Histogram

DIDD (mA)

Histogram

DVDD = 5.5V V

VIL = DGND T

0.8 0.90.4 0.5 0.6 0.7

118910

= DV

= 25°C

03734-015

03734-018

Figure 18. Power-Up Transient

03734-016

FREQUENCY

0 –5.0

–4.0

–1.0 3.0–3.0 1.00 4.0 5.0

–2.0 2.0

–1.5 2.5–3.5–4.5

REFERENCE DRIFT (ppm/°C)

0.5–0.5 3.5–2.5 1.5

4.5

03734-019

Figure 19. REFOUT Temperature Coefficient

BUSY

AVDD = DVDD = 5V

= 2.5V

REF

= 25°C

EXITS SOFT PD TO MIDSCALE

Figure 17. Exiting Soft Power-Down

OUT

03734-017

OUT

AVDD = DVDD = 5V

= 2.5V

REF

= 25°C

EXITS HARDWARE PD

TO MIDSCALE

03734-020

Figure 20. Exiting Hardware Power-Down

Rev. A | Page 19 of 40

Page 20

AD5383

FULL-SCALE

(V)

OUT

–1

–40 –20 –10 –5 –2 0 2 5 10 20 40

3/4 SCALE

MIDSCALE

1/4 SCALE

ZERO-SCALE

CURRENT (mA)

Figure 21. AD5383-5 Output Amplifier Source and Sink Capability

AVDD = DVDD= 5V

= 2.5V

REF

= 25°C

03734-021

AVDD = DVDD= 3V

= 1.25V

REF

= 25°C

MIDSCALE

(V)

OUT

–1

–40 –20 –10 –5 –2 0 2 5 10 20 40

3/4 SCALE

ZERO-SCALE

FULL-SCALE

1/4 SCALE

CURRENT (mA)

Figure 24. AD5383-3 Output Amplifier Source and Sink Capability

03734-024

0.20

0.15

–0.05

ERROR VOLTAGE (V)

–0.10

–0.15

–0.20

0.10

0.05

ERROR AT ZERO SINKING CURRENT

(VDD–V

) AT FULL-SCALE SOURCING CURRENT

OUT

SOURCE/ISINK

(mA)

Figure 22. Headroom at Rails vs. Source/Sink Current

600

500

400

300

AVDD = 5V T

= 25°C

REFOUT DECOUPLED WITH 100nF CAPACITOR

AVDD = 5V

= 2.5V

REF

= 25°C

2.456

2.455

2.454

2.453

2.452

AMPLITUDE (V)

2.451

2.450

2.000 0.25 0.50 0.75 1.00 1.25 1.50 1.75

03734-022

2.449

SAMPLE NUMBER

AVDD = DVDD = 5V V

= 2.5V

REF

= 25°C

14ns/SAMPLE NUMBER

5500 100 150 200 250 30050 350 400 500450

03734-025

Figure 25. Adjacent Channel DAC-to-DAC Crosstalk

AVDD = DVDD = 5V

= 25°C

DAC LOADED WITH MIDSCALE EXTERNAL REFERENCE Y AXIS = 5µV/DIV X AXIS = 100ms/DIV

REFOUT = 2.5V

FREQUENCY (Hz)

AVDD = DVDD = 5V

= 2.5V

REF

= 25°C

EXITS SOFT PD

TO MIDSCALE

100k100 1k 10k

03734-023

03734-026

Figure 26. 0.1 Hz to 10 Hz Noise Plot

OUTPUT NOISE (nV/ Hz)

200

100

REFOUT = 1.25V

Figure 23. REFOUT Noise Spectral Density

Rev. A | Page 20 of 40

Page 21

AD5383

FUNCTIONAL DESCRIPTION

DAC ARCHITECTURE—GENERAL

The AD5383 is a complete, single-supply, 32-channel voltage output DAC that offers 12-bit resolution. The part is available in a 100-lead LQFP package and features both a parallel and a serial interface. This product includes an internal, software selectable, 1.25 V/2.5 V, 10 ppm/°C reference that can be used to drive the buffered reference inputs; alternatively, an external reference can be used to drive these inputs. Internal/external reference selection is via the CR8 bit in the control register; CR10 selects the reference magnitude if the internal reference is selected. All channels have an on-chip output amplifier with rail-to-rail output capable of driving 5 kΩ in parallel with a 200 pF load.

REF

×1 INPUT

REG

m REG

c REG

DAC

×2INPUT DAT

REG

Figure 27. Single-Channel Architecture

12-BIT

DAC

OUT

03734-027

The complete transfer function for these devices can be represented as

= 2 × V

OUT

× x2/2n

REF

where x2 is the data-word loaded to the resistor string DAC.

is the internal reference voltage or the reference voltage

REF

externally applied to the DAC REFOUT/REFIN pin. For specified performance, an external reference voltage of 2.5 V is recommended for the AD5380-5 and 1.25 V for the AD5380-3.

DATA DECODING

The AD5383 contains a 12-bit data bus, DB11 to DB0. Depending on the value of REG1 and REG0 (see Table 11), this data is loaded into the addressed DAC input registers, offset (c) registers, or gain (m) registers. The format data, offset (c), and gain (m) register contents are shown in Table 12 to Table 14.

Table 11. Register Selection

REG1 REG0 Register Selected

1 1 Input Data Register (x1) 1 0 Offset Register (c) 0 1 Gain Register (m) 0 0 Special Function Registers (SFRs)

The architecture of a single DAC channel consists of a 12-bit resistor-string DAC followed by an output buffer amplifier operating at a gain of 2. This resistor-string architecture guarantees DAC monotonicity. The 12-bit binary digital code loaded to the DAC register determines at which node on the string the voltage is tapped off before being fed to the output amplifier. Each channel on these devices contains independent offset and gain control registers that allow the user to digitally trim offset and gain. These registers give the user the ability to calibrate out errors in the complete signal chain, including the DAC, using the internal m and c registers, which hold the correction factors. All channels are double buffered, allowing

LDAC

synchronous updating of all channels using the

pin. Figure 27 shows a block diagram of a single channel on the AD5383. The digital input transfer function for each DAC can be represented as

x2 = [(m + 2)/ 2

× x1] + (c – 2

n – 1

)

where:

x2 = the data-word loaded to the resistor string DAC. x1 = the 12-bit data-word written to the DAC input register. m = the gain coefficient (default is 0xFFE). The gain coefficient

is written to the 11 most significant bits (DB11 to DB1) and the LSB (DB0) is 0.

n = DAC resolution (n = 12 for AD5383). c = the12-bit offset coefficient (default is 0x800).

Table 12. DAC Data Format (REG1 = 1, REG0 = 1)

DB11 to DB0 DAC Output (V)

1111 1111 1111 2 V 1111 1111 1110 2 V 1000 0000 0001 2 V 1000 0000 0000 2 V 0111 1111 1111 2 V 0000 0000 0001 2 V

× (4095/4096)

REF

× (4094/4096)

REF

× (2049/4096)

REF

× (2048/4096)

REF

× (2047/4096)

REF

× (1/4096)

REF

0000 0000 0000 0

Table 13. Offset Data Format (REG1 = 1, REG0 = 0)

DB11 to DB0 Offset (LSB)

1111 1111 1111 +2048 1111 1111 1110 +2047 1000 0000 0001 +1 1000 0000 0000 0 0111 1111 1111 –1 0000 0000 0001 –2047 0000 0000 0000 –2048

Table 14. Gain Data Format (REG1 = 0, REG0 = 1)

DB11 to DB1 Gain Factor

1111 1111 1110 1 1011 1111 1110 0.75 0111 1111 1110 0.5 0011 1111 1110 0.25 0000 0000 0000 0

Rev. A | Page 21 of 40

Page 22

AD5383

ON-CHIP SPECIAL FUNCTION REGISTERS (SFR)

The AD5383 contains a number of special function registers (SFRs), as outlined in Table 15. SFRs are addressed with REG1 = REG0 = 0 and are decoded using Address Bit A4 to Address Bit A0.

Table 15. SFR Register Functions (REG1 = 0, REG0 = 0)

A4 A3 A2 A1 A0 Function

X 0 0 0 0 0 NOP (No Operation) 0 0 0 0 0 1 Write CLR Code 0 0 0 0 1 0 Soft CLR 0 0 1 0 0 0 Soft Power-Down 0 0 1 0 0 1 Soft Power-Up 0 0 1 1 0 0 Control Register Write 1 0 1 1 0 0 Control Register Read 0 0 1 0 1 0 Channel Monitor 0 0 1 1 1 1 Soft Reset

SFR COMMANDS

NOP (No Operation)

REG1 = REG0 = 0, A4 to A0 = 00000

Performs no operation but is useful in serial readback mode to clock out data on D

for diagnostic purposes.

OUT

low during a NOP operation.

BUSY

pulses

Soft CLR

REG1 = REG0 = 0, A4 to A0 = 00010 DB11 to DB0 = don’t care

Executing this instruction performs the CLR, which is functionally

CLR

the same as that provided by the external

pin. The DAC outputs are loaded with the data in the CLR code register. It takes 35 µs to fully execute the SOFT CLR, as indicated by the BUSY

low time.

Soft Power-Down

REG1 = REG0 = 0, A4 to A0 = 01000 DB11 to DB0 = don’t care

Executing this instruction performs a global power-down feature that puts all channels into a low power mode that reduces the analog supply current to 2 µA max, and the digital current to 20 µA. In power-down mode, the output amplifier can be configured as a high impedance output or provide a 100 kΩ load to ground. The contents of all internal registers are retained in power-down mode. No register can be written to while in power-down.

Soft Power-Up

REG1 = REG0 = 0, A4 to A0 = 01001 DB11 to DB0 = don’t care

Write CLR Code

REG1 = REG0 = 0, A4 to A0 = 00001 DB11 to DB0 = contain the CLR data

CLR

Bringing the

line low or exercising the soft clear function loads the contents of the DAC registers with the data con-tained in the user configurable

CLR

OUT

0 to V

OUT

31 accordingly. This can be very useful for setting up a specific output voltage in a clear condition. It is also beneficial for calibration purposes; the user can load full scale or zero scale to the clear code register and then issue a hardware or software clear to load this code to all DACs, removing the need for individual writes to each DAC. Default on power-up is all zeros.

This instruction is used to power up the output amplifiers and the internal reference. The time to exit power-down is 8 µs. The hardware power-down and software function are internally combined in a digital OR function.

Soft RESET

REG1 = REG0 = 0, A4 to A0 = 01111 DB11 to DB0 = don’t care

This instruction is used to implement a software reset. All internal registers are reset to their default values, which correspond to m at full scale and c at zero scale. The contents of the DAC registers are cleared, setting all analog outputs to 0 V. The soft reset activation time is 135 µs.

Rev. A | Page 22 of 40

Page 23

AD5383

Table 16. Control Register Contents

MSB LSB

CR11 CR10 CR9 CR8 CR7 CR6 CR5 CR4 CR3 CR2 CR1 CR0

Control Register Write/Read

REG1 = REG0 = 0, A4 to A0 = 01100, R/

the operation is a write (R/

= 0) or a read (R/W = 1). DB11 to

DB0 contains the control register data.

Control Register Contents

status determines if

CR7 = 0: Monitor Disabled (default on power-up). When the monitor is disabled, the MON_OUT pin is three-stated.

CR6: Thermal Monitor Function. This function is used to monitor the AD5383’s internal die temperature when enabled. The thermal monitor powers down the output amplifiers when

CR11: Power-Down Status. This bit is used to configure the output amplifier state in power down.

CR11 = 1. Amplifier output is high impedance (default on power-up).

CR11 = 0. Amplifier output is 100 kΩ to ground.

CR10: REF Select. This bit selects the operating internal reference for the AD5383. CR12 is programmed as follows:

CR10 = 1: Internal reference is 2.5 V (AD5383-5 default), the recommended operating reference for AD5383-5.

CR10 = 0: Internal reference is 1.25 V (AD5383-3 default), the recommended operating reference for AD5383-3.

CR9: Current Boost Control. This bit is used to boost the current in the output amplifier, thereby altering its slew rate. This bit is configured as follows:

the temperature exceeds 130°C. This function can be used to protect the device in cases where power dissipation may be exceeded if a number of output channels are simultaneously short-circuited. A soft power-up will re-enable the output amplifiers if the die temperature has dropped below 130°C.

CR6 = 1: Thermal Monitor Enabled.

CR6 = 0: Thermal Monitor Disabled (default on power-up).

CR5 and CR4: Don’t Care.

CR3 to CR0: Toggle Function Enable. This function allows the

user to toggle the output between two codes loaded to the A and B registers for each DAC. Control Register Bits CR3 to CR0 are used to enable individual groups of eight channels for operation in toggle mode. A Logic 1 written to any bit enables a group of channels; a Logic 0 disables a group.

LDAC

toggle between the two registers. Logic 1 enables a group of channels; Logic 0 disables a group of channels.

CR9 = 1: Boost Mode On. This maximizes the bias current in the output amplifier, optimizing its slew rate but increasing the power dissipation.

CR9 = 0: Boost Mode Off (default on power-up). This reduces the bias current in the output amplifier and reduces the overall power consumption.

Table 17.

CR Bit Group Channels

CR3 3 24 to 31 CR2 2 16 to 23 CR1 1 8 to 15 CR0 0 0 to 7

CR8: Internal/External Reference. This bit determines if the DAC uses its internal reference or an externally applied reference.

Channel Monitor Function

REG1 = REG0 = 0, A4 to A0 = 01010

is used to

CR8 = 1: Internal Reference Enabled. The reference output depends on data loaded to CR10.

CR8 = 0: External Reference Selected (default on power up).

CR7: Channel Monitor Enable (see Channel Monitor Function).

CR7= 1: Monitor Enabled. This enables the channel monitor function. After a write to the monitor channel in the SFR register, the selected channel output is routed to the MON_OUT pin.

DB11 to DB6 = Contain data to address the monitored channel.

A channel monitor function is provided on the AD5383. This feature, which consists of a multiplexer addressed via the interface, allows any channel output or signals connected to the MON_IN pins to be routed to the MON_OUT pin for monitoring using an external ADC. The channel monitor function must be enabled in the control register before any channels are routed to MON_OUT. On the AD5383, DB11 to DB6 contain the channel address for the monitored channel. Selecting Channel Address 63 three-states MON_OUT.

Rev. A | Page 23 of 40

Page 24

AD5383

Table 18. Channel Monitor Decoding

REG1 REG0 A4 A3 A2 A1 A0 DB11 DB10 DB9 DB8 DB7 DB6 DB5 to DB0 MON_OUT

0 0 0 1 0 1 0 0 0 0 0 0 0 X V 0 0 0 1 0 1 0 0 0 0 0 0 1 X V 0 0 0 1 0 1 0 0 0 0 0 1 0 X V 0 0 0 1 0 1 0 0 0 0 0 1 1 X V 0 0 0 1 0 1 0 0 0 0 1 0 0 X V 0 0 0 1 0 1 0 0 0 0 1 0 1 X V 0 0 0 1 0 1 0 0 0 0 1 1 0 X V 0 0 0 1 0 1 0 0 0 0 1 1 1 X V 0 0 0 1 0 1 0 0 0 1 0 0 0 X V 0 0 0 1 0 1 0 0 0 1 0 0 1 X V 0 0 0 1 0 1 0 0 0 1 0 1 0 X V 0 0 0 1 0 1 0 0 0 1 0 1 1 X V 0 0 0 1 0 1 0 0 0 1 1 0 0 X V 0 0 0 1 0 1 0 0 0 1 1 0 1 X V 0 0 0 1 0 1 0 0 0 1 1 1 0 X V 0 0 0 1 0 1 0 0 0 1 1 1 1 X V 0 0 0 1 0 1 0 0 1 0 0 0 0 X V 0 0 0 1 0 1 0 0 1 0 0 0 1 X V 0 0 0 1 0 1 0 0 1 0 0 1 0 X V 0 0 0 1 0 1 0 0 1 0 0 1 1 X V 0 0 0 1 0 1 0 0 1 0 1 0 0 X V 0 0 0 1 0 1 0 0 1 0 1 0 1 X V 0 0 0 1 0 1 0 0 1 0 1 1 0 X V 0 0 0 1 0 1 0 0 1 0 1 1 1 X V 0 0 0 1 0 1 0 0 1 1 0 0 0 X V 0 0 0 1 0 1 0 0 1 1 0 0 1 X V 0 0 0 1 0 1 0 0 1 1 0 1 0 X V 0 0 0 1 0 1 0 0 1 1 0 1 1 X V 0 0 0 1 0 1 0 0 1 1 1 0 0 X V 0 0 0 1 0 1 0 0 1 1 1 0 1 X V 0 0 0 1 0 1 0 0 1 1 1 1 0 X V 0 0 0 1 0 1 0 0 1 1 1 1 1 X V 0 0 0 1 0 1 0 1 0 0 0 0 0 X MON_IN1 0 0 0 1 0 1 0 1 0 0 0 0 1 X MON_IN2 0 0 0 1 0 1 0 1 0 0 0 1 0 X MON_IN3 0 0 0 1 0 0 1 0 0 0 1 1 X MON_IN4 0 0 0 1 0 1 0 1 0 0 1 0 0 X Undefined 0 0 0 1 0 1 0 1 0 0 1 0 1 X Undefined

• • • • • • • • • • • • • • •

0 0 0 1 0 1 0 1 1 1 1 1 0 X Undefined 0 0 0 1 0 1 0 1 1 1 1 1 1 X Three-State

OUT

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

REG1 REG0 A4 A3 A2 A1 A0

OUT

MON_IN1 MON_IN2 MON_IN3 MON_IN4

0001010

0 1

30 31

CHANNEL ADDRESS

AD5383

CHANNEL

MONITOR

DECODING

DB11–DB6

Figure 28. Channel Monitor Decoding

Rev. A | Page 24 of 40

MON_OUT

03734-028

Page 25

AD5383

HARDWARE FUNCTIONS

RESET FUNCTION

Bringing the registers to their power-on reset state. sensitive input. The default corresponds to m at full scale and to c at zero scale. The contents of the DAC registers are cleared,

setting V The falling edge of low for the duration, returning high when While pulses are ignored. When normal operation and the status of the until the next falling edge is detected.

RESET

line low resets the contents of all internal

RESET

0 to V

OUT

BUSY

is low, all interfaces are disabled and all

31 to 0 V. This sequence takes 270 µs max.

OUT

RESET

initiates the reset process;

BUSY

returns high, the part resumes

is a negative edge-

RESET

pin is ignored

BUSY

goes

is complete.

LDAC

ASYNCHRONOUS CLEAR FUNCTION

Bringing the registers to the data contained in the user-configurable CLR register and sets V be used in system calibration to load zero scale and full scale to all channels. The execution time for a CLR is 32 µs.

CLR

line low clears the contents of the DAC

OUT

0 to V

31 accordingly. This function can

OUT

FIFO OPERATION IN PARALLEL MODE

The AD5383 contains a FIFO to optimize operation when operating in parallel interface mode. The FIFO Enable (level sensitive, active high) is used to enable the internal FIFO. When connected to DV user to write to the device at full speed. FIFO is only available in parallel interface mode. The status of the FIFO EN pin is sampled on power-up, and after a if the FIFO is enabled. In either serial or I FIFO EN should be tied low. Up to 128 successive instructions can be written to the FIFO at maximum speed in parallel mode. When the FIFO is full, any further writes to the device are ignored. Figure 29 shows a comparison between FIFO mode and non-FIFO mode in terms of channel update time. Figure 29 also outlines digital loading time.

, the internal FIFO is enabled, allowing the

CLR

WITHOUT FIFO

(CHANNEL UPDATE TIME)

RESET

, to determine

C interface modes,

BUSY AND LDAC FUNCTIONS

BUSY

is a digital CMOS output that indicates the status of the AD5383. The value of x2, the internal data loaded to the DAC data register, is calculated each time the user writes new data to the corresponding x1, c, or m registers. During the calculation of x2, the

BUSY

output goes low. While can continue writing new data to the x1, m, or c registers, but no DAC output updates can take place. The DAC outputs are

LDAC

updated by taking the BUSY

is active, the

LDAC

update immediately after

LDAC

the

input permanently low, in which case the DAC

input low. If

event is stored and the DAC outputs

BUSY

goes high. The user may hold

outputs update immediately after goes low during power-on reset and when a falling edge is detected on the disabled and any events on

RESET

pin. During this time, all interfaces are

LDAC

contains an extra feature whereby a DAC register is not updated unless its x2 register has been written to since the last time LDAC

was brought low. Normally, when the DAC registers are filled with the contents of the x2 registers. However, the AD5383 will only update the DAC register if the x2 data has changed, thereby removing unnecessary digital crosstalk.

BUSY

is low, the user

LDAC

goes low while

BUSY

goes high.

BUSY

also

are ignored. The AD5383

LDAC

is brought low,

TIME (µs)

(DIGITAL LOADING TIME)

1 4 7 10 13 16 19 22 25 28 31 34 37

Figure 29. Channel Update Rate (FIFO vs. Non-FIFO)

NUMBER OF WRITES

WITH FIFO

(CHANNEL UPDATE TIME)

WITH FIFO

03734-029

POWER-ON RESET

The AD5383 contains a power-on reset generator and state machine. The power-on reset resets all registers to a predefined state and configures the analog outputs as high impedance. The BUSY

pin goes low during the power-on reset sequencing,

preventing data writes to the device.

POWER-DOWN

The AD5383 contains a global power-down feature that puts all channels into a low power mode and reduces the analog power consumption to 2 µA maximum and digital power consumption to 20 µA maximum. In power-down mode, the output amplifier can be configured as high impedance output or provide a 100 kΩ load to ground. The contents of all internal registers are retained in power-down mode. When exiting power-down, the settling time of the amplifier will elapse before the outputs settle to their correct values.

Rev. A | Page 25 of 40

Page 26

AD5383

INTERFACES

The AD5383 contains both parallel and serial interfaces. Furthermore, the serial interface can be programmed to be SPI-, DSP-, MICROWIRE-, or I pin selects parallel and serial interface modes. In serial mode,

SPI

the

/I2C pin is used to select DSP, SPI, MICROWIRE, or I2C

interface mode.

The devices use an internal FIFO memory to allow high speed successive writes in parallel interface mode. The user can continue writing new data to the device while write instructions are being executed. The

BUSY

the device, going low while instructions in the FIFO are being executed. In parallel mode, up to 128 successive instructions can be written to the FIFO at maximum speed. When the FIFO is full, any further writes to the device are ignored.

To minimize both the power consumption of the device and the on-chip digital noise, the active interface only powers up fully when the device is being written to, that is, on the falling edge

or the falling edge of

DSP-, SPI-, MICROWIRE-COMPATIBLE SERIAL INTERFACES

The serial interface can be operated with a minimum of three wires in standalone mode or four wires in daisy-chain mode. Daisy-chaining allows many devices to be cascaded together to increase system channel count. The SER/

SPI

high and the the DSP-/SPI-/MICROWIRE-compatible serial interface. In serial interface mode, the user does not need to drive the parallel input data pins. The serial interface’s control pins are:

/I2C pin (Pin 97) should be tied low to enable

C-compatible. The SER/

PA R

signal indicates the current status of

SYNC

PA R

pin must be tied

Figure 3 and Figure 5 show timing diagrams for a serial write to the AD5383 in standalone and daisy-chain modes. The 24-bit data-word format for the serial interface is shown in Table 19.

/B. When toggle mode is enabled, this pin selects whether the

data write is to the A or B register. With toggle disabled, this bit should be set to zero to select the A data register.

is the read or write control bit.

A4 to A0 address the input channels.

REG1 and REG0 select the register to which data is written, as

shown in Table 11.

DB11 to DB0 contain the input data-word.

X is a don’t care condition.

Standalone Mode

By connecting the DCEN (daisy-chain enable) pin low, standalone mode is enabled. The serial interface works with both a continuous and a noncontinuous serial clock. The first falling

SYNC

edge of

starts the write cycle and resets a counter that counts the number of serial clocks to ensure that the correct number of bits are shifted into the serial shift register. Any

SYNC

further edges on

, except for a falling edge, are ignored until 24 bits are clocked in. Once 24 bits have been shifted in, the SCLK is ignored. In order for another serial transfer to take place, the counter must be reset by the falling edge of

SYNC

, DIN, SCLK—Standard 3-wire interface pins. DCEN—Selects standalone mode or daisy-chain mode. SDO—Data out pin for daisy-chain mode.

Table 19. 40-Channel, 12-Bit DAC Serial Input Register Configuration

MSB

W 0 A4 A3 A2 A1 A0 REG1 REG0 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 X X

/B R/

Rev. A | Page 26 of 40

LSB

Page 27

AD5383

Daisy-Chain Mode

For systems that contain several devices, the SDO pin may be used to daisy-chain several devices together. This daisy-chain mode can be useful in system diagnostics and in reducing the number of serial interface lines.

By connecting the DCEN (daisy-chain enable) pin high, daisy-

SYNC

chain mode is enabled. The first falling edge of

starts the write cycle. The SCLK is continuously applied to the input shift register when

SYNC

is low. If more than 24 clock pulses are applied, the data ripples out of the shift register and appears on the SDO line. This data is clocked out on the rising edge of SCLK and is valid on the falling edge. By connecting the SDO of the first device to the DIN input on the next device in the chain, a multidevice interface is constructed. Twenty-four clock pulses are required for each device in the system. Therefore, the total number of clock cycles must equal 24N, where N is the total number of AD538x devices in the chain.

SYNC

When the serial transfer to all devices is complete,

is taken high. This latches the input data in each device in the daisy-chain and prevents any further data from being clocked into the input shift register.

SYNC

is taken high before 24 clocks are clocked into the part,

this is considered a bad frame and the data is discarded.

Readback Mode

Readback mode is invoked by setting the R/

serial input register write. With R/

= 1, Bits A4 to A0, in

bit = 1 in the

association with Bits REG1 and REG0, select the register to be read. The remaining data bits in the write sequence are don’t cares. During the next SPI write, the data appearing on the SDO output will contain the data from the previously addressed register. For a read of a single register, the NOP command can be used in clocking out the data from the selected register on SDO. Figure 30 shows the readback sequence. For example, to read back the m register of Channel 0 on the AD5383, the following sequence should be implemented. First, write 0x404XXX to the AD5383 input register. This configures the AD5383 for read mode with the m register of Channel 0 selected. Note that Data Bits DB11 to DB0 are don’t cares. Follow this with a second write, a NOP condition, 0x000000. During this write, the data from the m register is clocked out on the D

line, that is, data clocked out will contain the data from

OUT

the m register in Bits DB11 to DB0, and the top 10 bits contain the address information as previously written. In readback mode, the

SYNC

signal must frame the data. Data is clocked out on the rising edge of SCLK and is valid on the falling edge of the SCLK signal. If the SCLK idles high between the write and read operations of a readback operation, the first bit of data is clocked out on the falling edge of

SYNC

The serial clock may be either a continuous or a gated clock. A

SYNC

continuous SCLK source can only be used if

can be held low for the correct number of clock cycles. In gated clock mode, a burst clock containing the exact number of clock cycles must be used and

SYNC

must be taken high after the final clock to

latch the data.

24 48SCLK

SYNC

DIN

SDO

DB23 DB0 DB0DB23

UNDEFINED SELECTED REGISTER DATA CLOCKED OUT

Figure 30. Serial Readback Operation

NOP CONDITIONINPUT WORD SPECIFIES REGISTER TO BE READ

03734-030

Rev. A | Page 27 of 40

Page 28

AD5383

I2C SERIAL INTERFACE

The AD5383 features an I2C-compatible, 2-wire interface consisting of a serial data line (SDA) and a serial clock line (SCL). SDA and SCL facilitate communication between the AD5383 and the master at rates up to 400 kHz. Figure 6 shows the 2-wire interface timing diagram that incorporates three different modes of operation. In selecting the I mode, first configure serial operating mode (SER/

then select I

C mode by configuring the Logic 1. The device is connected to the I (that is, no clock is generated by the AD5383). The AD5383 has a 7-bit slave address 10101 (AD1) (AD0). The 5 MSBs are hardcoded and the 2 LSBs are determined by the state of the AD1 and AD0 pins. The facility to hardware-configure AD1 and AD0 allows four of these devices to be configured on the bus.

C Data Transfer

One data bit is transferred during each SCL clock cycle. The data on SDA must remain stable during the high period of the SCL clock pulse. Changes in SDA while SCL is high are control signals that configure START and STOP conditions. Both SDA and SCL are pulled high by the external pull-up resistors when

the I

C bus is not busy.

START and STOP Conditions

A master device initiates communication by issuing a START condition. A START condition is a high-to-low transition on SDA with SCL high. A STOP condition is a low-to-high transition on SDA while SCL is high. A START condition from the master signals the beginning of a transmission to the AD5383. The STOP condition frees the bus. If a repeated START condition (Sr) is generated instead of a STOP condition, the bus remains active.

Repeated START Conditions

A repeated START (Sr) condition may indicate a change of data direction on the bus. Sr may be used when the bus master is

writing to several I

C devices and wants to maintain control of

the bus.

Acknowledge Bit (ACK)

The acknowledge bit (ACK) is the ninth bit attached to any 8-bit data-word. ACK is always generated by the receiving device. The AD5383 devices generate an ACK when receiving an address or data by pulling SDA low during the ninth clock period. Monitoring ACK allows for detection of unsuccessful data transfers. An unsuccessful data transfer occurs if a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master should reattempt communication.

C operating

PA R

= 1) and

SPI

/I2C pin to a

C bus as a slave device

AD5383 Slave Addresses

A bus master initiates communication with a slave device by issuing a START condition followed by the 7-bit slave address. When idle, the AD5383 waits for a START condition followed by its slave address. The LSB of the address word is the read/

write (R/ communicating with the AD5383, R/

) bit. The AD5383 is a receive-only device; when

= 0. After receiving the proper address 10101 (AD1) (AD0), the AD5383 issues an ACK by pulling SDA low for one clock cycle.

The AD5383 has four different user-programmable addresses determined by the AD1 and AD0 bits.

Write Operation

There are three specific modes in which data can be written to the AD5383 DAC.

4-Byte Mode

When writing to the AD5383 DACs, the user must begin with

an address byte (R/

= 0) after which the DAC acknowledges that it is prepared to receive data by pulling SDA low. The address byte is followed by the pointer byte; this addresses the specific channel in the DAC to be addressed and is also acknowledged by the DAC. Two bytes of data are then written to the DAC, as shown in Figure 31. A STOP condition follows. This allows the user to update a single channel within the AD5383 at any time and requires four bytes of data to be transferred from the master.

3-Byte Mode

In 3-byte mode, the user can update more than one channel in a write sequence without having to write the device address byte each time. The device address byte is only required once; subsequent channel updates require the pointer byte and the data bytes. In 3-byte mode, the user begins with an address byte

= 0), after which the DAC acknowledges that it is

(R/ prepared to receive data by pulling SDA low. The address byte is followed by the pointer byte. This addresses the specific channel in the DAC to be addressed and is also acknowledged by the DAC. This is then followed by the two data bytes. REG1 and REG0 determine the register to be updated.

If a STOP condition does not follow the data bytes, another channel can be updated by sending a new pointer byte followed by the data bytes. This mode only requires three bytes to be sent to update any channel once the device has been initially addressed, and reduces the software overhead in updating the AD5383 channels. A STOP condition at any time exits this mode. Figure 32 shows a typical configuration.

Rev. A | Page 28 of 40

Page 29

AD5383

SDA

SCL

START COND

BY MASTER

SCL

START COND

BY MASTER

SCL

1 0 1 0 1 AD1 AD0 R/W 0 0 0 A4 A3 A2 A1 A0

ACK BY

ADDRESS BYTE

REG1 REG0 MSB LSB MSB LSB

MOST SIGNIFICANT BYTE LEAST SIGNIFICANT BYTE

AD538x

Figure 31. 4-Byte, I

0 1 0 0 0 0 A4A3A2A1A01 AD1 AD0 R/W

ACK BY

ADDRESS BYTE POINTER BYTE FOR CHANNEL "N"

AD538x

MSB ACK BY

POINTER BYTE

ACK BY AD538x

C Write Operation

MSB

AD538x

ACK BY AD538x

STOP COND

MASTER

03734-031

REG1 REG0 MSB LSB MSB LSB

SCL

ACK BY

MOST SIGNIFICANT DATA BYTE

0 0 0 A4A3A2A1A0

MSB ACK BY

POINTER BYTE FOR CHANNEL "NEXT CHANNEL"

REG1 REG0 MSB LSB MSB LSB

MOST SIGNIFICANT DATA BYTE LEAST SIGNIFICANT DATA BYTE

DATA FOR CHANNEL "NEXT CHANNEL"

Figure 32. 3-Byte, I

AD538x

DATA FOR CHANNEL "N"

AD538x

ACK BY AD538x

C Write Operation

LEAST SIGNIFICANT DATA BYTE

ACK BY AD538x

STOP COND BY MASTER

03734-032

Rev. A | Page 29 of 40

Page 30

AD5383

2-Byte Mode

Following initialization of 2-byte mode, the user can sequentially update channels. The device address byte is only required once, and the address pointer is configured for autoincrement or burst mode.

The user must begin with an address byte (R/ which the DAC acknowledges that it is prepared to receive data by pulling SDA low. The address byte is followed by a specific pointer byte (0xFF) that initiates the burst mode of operation. The address pointer initializes to Channel 0, the data following the pointer is loaded to Channel 0, and the address pointer automatically increments to the next address.

The REG0 and REG1 bits in the data byte determine which register is updated. In this mode, following the initializa-tion, only the two data bytes are required to update a channel. The channel address automatically increments from Address 0 to Channel 31 and then returns to the normal 3-byte mode of operation. This mode allows transmission of data to all channels in one block and reduces the software overhead in configuring all channels. A STOP condition at any time exits this mode. Toggle mode is not supported in 2-byte mode. Figure 33 shows a typical configuration.

= 0), after

PARALLEL INTERFACE

The SER/ interface and disable the serial interfaces. Figure 7 shows the timing diagram for a parallel write. The parallel interface is controlled by the following pins:

PA R

pin must be tied low to enable the parallel

Active low device select pin.

On the rising edge of

, with CS low, the addresses on Pin A4 to Pin A0 are latched; data present on the data bus is loaded into the selected input registers.

REG0, REG1 Pins

The REG0 and REG1 pins determine the destination register of the data being written to the AD5383. See Table 11.

Pins A4 to A0

Each of the 32 DAC channels can be addressed individually.

Pins DB11 to DB0

The AD5383 accepts a straight 12-bit parallel word on DB11 to DB0, where DB11 is the MSB and DB0 is the LSB.

SCL

SDA

START COND

BY MASTER

SCL

SDA

SCL

SDA

SCL

SDA

1 0 1 0 1 AD1 AD0 R/W A7 = 1 A6 = 1 A5 = 1 A4 = 1 A3 = 1 A2 = 1 A1 = 1 A0 = 1

ACK BY

ADDRESS BYTE POINTER BYTE

REG1 REG0 MSB LSB MSB LSB

MOST SIGNIFICANT DATA BYTE

REG1 REG0 MSB LSB MSB LSB

MOST SIGNIFICANT DATA BYTE

REG1 REG0 MSB LSB MSB LSB

MOST SIGNIFICANT DATA BYTE

CONVERTER

CHANNEL N DATA FOLLOWED BY STOP

Figure 33. 2-Byte, I

MSB ACK BY

ACK BY

AD538x

CHANNEL 0 DATA

ACK BY

CHANNEL 1 DATA

ACK BY

CONVERTER

C Write Operation

LEAST SIGNIFICANT DATA BYTE

CONVERTER

ACK BY AD538x

ACK BY

CONVERTER

STOP

COND

MASTER

03734-033

Rev. A | Page 30 of 40

Page 31

AD5383

MICROPROCESSOR INTERFACING

Parallel Interface

The AD5383 can be interfaced to a variety of 16-bit microcontrollers or DSP processors. Figure 35 shows the AD5383 family interfaced to a generic 16-bit microcontroller/DSP processor. The lower address lines from the processor are connected to A0 to A4 on the AD5383. The upper address lines are decoded to provide a

CS, LDAC

signal for the AD5383. The fast interface timing of the AD5383 allows direct interface to a wide variety of microcontrollers and DSPs, as shown in Figure 35.

AD5383 to MC68HC11

The serial peripheral interface (SPI) on the MC68HC11 is configured for master mode (MSTR = 1), the clock polarity bit (CPOL) = 0, and the clock phase bit (CPHA) = 1. The SPI is configured by writing to the SPI control register (SPCR)—see the 68HC11 User Manual. SCK of the 68HC11 drives the SCLK of the AD5383, the MOSI output drives the serial data line (DIN) of the AD5383, and the MISO input is driven from DOUT. The

SYNC

signal is derived from a port line (PC7).

When data is being transmitted to the AD5383, the is taken low (PC7). Data appearing on the MOSI output is valid on the falling edge of SCK. Serial data from the 68HC11 is transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle.

MC68HC11

MISO MOSI

SCK

PC7

Figure 34. AD5383-to-MC68HC11 Interface

AD5383

SER/PAR RESET SDO DIN SCLK SYNC

SPI/I

SYNC

line

03734-034

µCONTROLLER/

DSP PROCESSOR*

D15

DATA

BUS

UPPER BITS OF

ADDRESS BUS

R/W

ADDRESS

DECODE

A4 A3 A2 A1 A0

*ADDITIONAL PINS OMITTED FOR CLARITY

REG1 REG0 D11

D0 CS LDAC

A4 A3 A2 A1 A0 WR

AD5383

03734-035

Figure 35. AD5383-to-Parallel Interface

Rev. A | Page 31 of 40

Page 32

AD5383

AD5383 to PIC16C6x/7x

The PIC16C6x/7x synchronous serial port (SSP) is configured as an SPI master with the clock polarity bit = 0. This is done by writing to the synchronous serial port control register (SSPCON). See the PIC16/17 Microcontroller User Manual. In this example

SYNC

I/O, Port RA1 is being used to pulse

and enable the serial port of the AD5383. This microcontroller transfers only eight bits of data during each serial transfer operation; therefore, three consecutive read/write operations may be needed depending on the mode. Figure 36 shows the connection diagram.

PIC16C6X/7X

SDI/RC4 SDO/RC5 SCK/RC3

RA1

AD5383

SER/PAR RESET SDO DIN SCLK SYNC

SPI/I

Figure 36. AD5383-to-PIC16C6x/7x Interface

AD5383 to 8051

The AD5383 requires a clock synchronized to the serial data. Therefore, the 8051 serial interface must be operated in Mode 0. In this mode, serial data enters and exits through RxD, and a shift clock is output on TxD. Figure 37 shows how the 8051 is connected to the AD5383. Because the AD5383 shifts data out on the rising edge of the shift clock and latches data in on the falling edge, the shift clock must be inverted. The AD5383 requires its data to be MSB first. Since the 8051 outputs the LSB first, the transmit routine must take this into account.

03734-036

8XC51

RxD

TxD

P1.1

AD5383

SER/PAR RESET

SDO DIN SCLK SYNC

SPI/I

Figure 37. AD5383-to-8051 Interface

AD5383 to ADSP-2101/ADSP-2103

Figure 38 shows a serial interface between the AD5383 and the ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103 should be set up to operate in SPORT transmit alternate framing mode. The ADSP-2101/ADSP-2103 SPORT is programmed through the SPORT control register and should be configured as follows: internal clock operation, active low framing, and 16-bit word length. Transmission is initiated by writing a word to the Tx register after the SPORT has been enabled.

ADSP-2101/ ADSP-2103

DR DT

SCK

TFS

RFS

Figure 38. AD5383-to-ADSP-2101/ADSP-2103 Interface

AD5383

SER/PAR RESET SDO DIN SCLK

SYNC SPI/I2C

03734-037

03734-038

Rev. A | Page 32 of 40

Page 33

AD5383

APPLICATION INFORMATION

POWER SUPPLY DECOUPLING

In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board on which the AD5383 is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. If the AD5383 is in a system where multiple devices require an AGND-to-DGND connection, the connection should be made at one point only, a star ground point established as close to the device as possible.

For supplies with multiple pins (AV be tied together. The AD5383 should have ample supply bypassing of 10 µF in parallel with 0.1 µF on each supply, located as close to the package as possible and ideally right up against the device. The 10 µF capacitors are the tantalum bead type. The

0.1 µF capacitor should have low effective series resistance (ESR) and effective series inductance (ESI), like the common ceramic types that provide a low impedance path to ground at high frequencies, to handle transient currents due to internal logic switching.

The power supply lines of the AD5383 should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other parts of the board, and should never be run near the reference inputs. A ground line routed between the DIN and SCLK lines will help reduce crosstalk between them (this is not required on a multilayer board because there will be a separate ground plane, but separating the lines will help). It is essential to minimize noise on the V and REFIN lines.

, DVDD), these pins should

an ADR421 or ADR431 2.5 V reference. Suitable external references for the AD5383-3 include the ADR280 1.2 V reference. The reference should be decoupled at the REFOUT/REFIN pin of the device with a 0.1 µF capacitor.

0.1µF

ADR431/

10µF 0.1µF

ADR421

REFOUT/REFIN

0.1µF REFGND

AD5383-5

SIGNAL

DAC

GND

GND DGND

Figure 39. Typical Configuration with External Reference

AGND

OUT

03734-039

Figure 40 shows a typical configuration when using the internal reference. On power-up, the AD5383 defaults to an external reference; therefore, the internal reference needs to be configured and turned on via a write to the AD5383 control register. Control Register Bit CR10 allows the user to choose the reference value; Bit CR 8 is used to select the internal reference. It is recommended to use the 2.5 V reference when AV and the 1.25 V reference when AV

0.1µF

10µF 0.1µF

= 3 V.

= 5 V,

Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough through the board. A micro-strip technique is by far the best, but is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to the ground plane while signal traces are placed on the solder side.

.1µF

REFOUT/REFIN

REFGND

AD5383

SIGNAL

DAC GND DGND

GND

AGND

OUT

TYPICAL CONFIGURATION CIRCUIT

03734-040

Figure 39 shows a typical configuration for the AD5383-5 when configured for use with an external reference. In the circuit

Figure 40. Typical Configuration with Internal Reference

shown, all AGND, SIGNAL_GND, and DAC_GND pins are tied together to a common AGND. AGND and DGND are connected together at the AD5383 device. On power-up, the AD5383 defaults to external reference operation. All AV

lines are connected together and driven from the same 5 V source. It is recommended to decouple close to the device with a 0.1 µF ceramic and a 10 µF tantalum capacitor. In this application, the

Digital connections have been omitted for clarity. The AD5383 contains an internal power-on reset circuit with a 10 ms brownout time. If the power supply ramp rate exceeds 10 ms, the user should reset the AD5383 as part of the initialization process to ensure the calibration data gets loaded correctly into the device.

reference for the AD5383-5 is provided externally from either

Rev. A | Page 33 of 40

Page 34

AD5383

CHANNEL MONITOR FUNCTION

The AD5383 contains a channel monitor function that consists of a multiplexer addressed via the interface, allowing any channel output to be routed to this pin for monitoring using an external ADC. The channel monitor function must be enabled in the control register before any channels are routed to MON_OUT. Table 18 contains the decoding information needed to route any channel to MON_OUT. To three-state MON_OUT, select Channel Address 63. Figure 41 shows a typical monitoring circuit using a 12-bit SAR ADC in a 6-lead SOT-23 package. The controller output port selects the channel to be monitored, and the input port reads the converted data from the ADC.

TOGGLE MODE FUNCTION

The toggle mode function allows an output signal to be generated

LDAC

using the data registers. This function is configured using the SFR control register as follows. A write with REG1 = REG0 = 0 and A4 to A0 = 01100 specifies a control register write. The toggle mode function is enabled in groups of eight channels using Bit CR3 to Bit CR0 in the control register. See the AD5383 Control Register Write/Read section. Figure 42 shows a block diagram of toggle mode implementation. Each of the 32 DAC channels on the AD5383 contain an A and B data register. Note that the B registers can only be loaded when toggle mode is enabled. The sequence of events when configuring the AD5383 for toggle mode is:

1. Enable toggle mode for the required channels via the

control register.

2. Load data to A registers.

3. Load data to B registers.

4. Apply

control signal that switches between two DAC

LDAC

AVCC

LDAC

The determining the analog output. The first

is used to switch between the A and B registers in

LDAC

configures the output to reflect data in the A registers. This mode offers significant advantages if the user wants to generate a square wave at the output of all 32 channels, as might be required to drive a liquid crystal-based variable optical attenuator. In this case, the user writes to the control register and enables the toggle function by setting CR3 to CR2 = 1, thus enabling the four groups of eight for toggle mode operation. The user must then load data

LDAC

to all 32 A and B registers. Toggling

sets the output

values to reflect the data in the A and B registers. The frequency

LDAC

of the

determines the frequency of the square wave

output.

Toggle mode is disabled via the control register. The first

LDAC

following the disabling of the toggle mode updates the outputs with the data contained in the A registers.

THERMAL MONITOR FUNCTION

The AD5383 contains a temperature shutdown function to protect the chip in case multiple outputs are shorted. The short circuit current of each output amplifier is typically 40 mA. Operating the AD5383 at 5 V results in power dissipation of 200 mW per shorted amplifier. With five channels shorted, this amounts to an extra watt of power dissipation. For the 100-lead LQFP, the θ

The thermal monitor is enabled by the user via CR6 in the control register. The output amplifiers on the AD5383 are automatically powered down if the die temperature exceeds approximately 130°C. After a thermal shutdown has occurred, the user can re-enable the part by executing a soft power-up if the temperature has dropped below 130°C or by turning off the thermal monitor function via the control register.

is typically 44°C/W.

AVCC

OUT

REFOUT/REFIN

MON_IN1 MON_IN2

OUT

DAC_GND SIGNAL_GND

Figure 41. Typical Channel Monitoring Circuit

AD5383

DIN SYNC SCLK

MON_OUT

AGND

Rev. A | Page 34 of 40

AD7476

AVCC

SCLK

SDATA

GND

OUTPUT PORT

INPUT PORT

CONTROLLER

03734-041

Page 35

AD5383

DATA

INPUT

DATA

A/B

DWDM

INPUT

AWG

1n–1

ADD

PORTS

DAC

DATA

Figure 42. Toggle Mode Function

DROP

PORTS

OPTICAL

SWITCH

ATTENUATOR

AD5383,

32-CHANNEL,

12-BIT DAC

PHOTODIODES

TIA/LOG AMP (AD8304/AD8305)

N:1 MULTIPLEXER

OUT

LDAC CONTROL INPUT

AWG

FIBREFIBRE

ADG731 (32:1 MUX)

DWDM

OUT

03734-042

Figure 43. OADM Using the AD5383 as Part of an Optical Attenuator

OPT I CAL ATT ENUATOR S

Based on its high channel count, high resolution, monotonic behavior, and high level of integration, the AD5383 is ideally targeted at optical attenuation applications used in dynamic gain equalizers, variable optical attenuators (VOA), and optical add-drop multiplexers (OADM). In these applications, each wavelength is individually extracted using an arrayed wave guide; its power is monitored using a photodiode, transimped-

16-BIT ADCCONTROLLER

AD7671 (0-5V, 1MSPS)

03734-043

ance amplifier and ADC in a closed-loop control system. The AD5383 controls the optical attenuator for each wavelength, ensuring that the power is equalized in all wavelengths before being multiplexed onto the fiber. This prevents information loss and saturation from occurring at amplification stages further along the fiber.

Rev. A | Page 35 of 40

Page 36

AD5383

UTILIZING THE FIFO

The AD5383 FIFO mode optimizes total system update rates in applications where a large number of channels need to be updated. FIFO mode is only available when parallel interface mode is selected. The FIFO EN pin is used to enable the FIFO. The status of FIFO EN is sampled during the initialization sequence. Therefore, the FIFO status can only be changed by resetting the device. In a telescope that provides for the cancellation of atmospheric distortion, for example, a large number of channels need to be updated in a short period of time. In such

systems, as many as 320 channels need to be updated within 25 µs to 30 µs. 320 channels require the use of 10 AD5383s. With FIFO mode enabled, the data write cycle time is 40 ns; therefore, each group consisting of 32 channels can be fully loaded in 1.28 µs. In FIFO mode, a complete group of 32 channels updates in 11.5 µs. The time taken to update all 320 channels is 11.5 µs + 9 × 1.28 µs = 23 µs. Figure 44 shows the FIFO operation scheme.

GROUP A

CHNLS 0-31

FIFO DATA LOAD

GROUP A

1.28µs

11.5µs

GROUP B

CHNLS 32-63

1.28µs

GROUP C

CHNLS

64-95

FIFO DATA LOAD

GROUP B

OUTPUT UPDATE

TIME FOR GROUP A

11.5µs

GROUP D

CHNLS

96-127

OUTPUT UPDATE

TIME FOR GROUP B

GROUP E

CHNLS

128-159

TIME TO UPDATE 320 CHANNELS = 23µs

GROUP F

CHNLS 160-191

GROUP G

CHNLS

192-223

GROUP H

CHNLS

224-255

FIFO DATA LOAD

GROUP J

OUTPUT UPDATE

TIME FOR GROUP J

Figure 44. Using FIFO Mode 320 Channels Updated in Under 25 µs

GROUP I

CHNLS

256-287

GROUP J

CHNLS 288-319

1.28µs

11.5µs

03734-044

Rev. A | Page 36 of 40

Page 37

AD5383

OUTLINE DIMENSIONS

16.00 BSC SQ

1.60 MAX

0.75

0.60

0.45

SEATING

PLANE

12° TYP

14.00 BSC SQ

PIN 1

76100

12.00 REF

1.45

1.40

1.35

0.15

0.05

ROTATED 90° CCW

10°

SEATING PLANE

VIEW A

6° 2°

0.08 MAX COPLANARITY

0.20

0.09 7°

3.5° 0°

COMPLIANT TO JEDEC STANDARDS MS-026BED

VIEW A

0.50 BSC

TOP VIEW

(PINS DOWN)

0.27

0.22

0.17

Figure 45. 100-Lead Low Profile Quad Flat Package [LQFP]

(ST-100)

Dimensions shown in millimeters

ORDERING GUIDE

Temperature

Model Resolution

Range

AD5383BST-3 12 Bits –40°C to +85°C 2.7 V to 3.6 V 32 ±1 LSB 100-Lead LQFP ST-100 AD5383BST-3-REEL 12 Bits –40°C to +85°C 2.7 V to 3.6 V 32 ±1 LSB 100-Lead LQFP ST-100 AD5383BST-5 12 Bits –40°C to +85°C 4.5 V to 5.5 V 32 ±1 LSB 100-Lead LQFP ST-100 AD5383BST-5-REEL 12 Bits –40°C to +85°C 4.5 V to 5.5 V 32 ±1 LSB 100-Lead LQFP ST-100 EVAL-AD5383EB Evaluation Kit

Range

Output Channels

Linearity Error

Package Description

Package Option

Rev. A | Page 37 of 40

Page 38

AD5383

NOTES

Rev. A | Page 38 of 40

Page 39

AD5383

NOTES

Rev. A | Page 39 of 40

Page 40

AD5383

NOTES

Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I

D03734–0–3/05(A)

C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.

Rev. A | Page 40 of 40

Datasheet AD5383 Datasheet (Analog Devices)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

FUNCTIONAL BLOCK DIAGRAM

INTEGRATED FUNCTIONS

APPLICATIONS

GENERAL DESCRIPTION

SPECIFICATIONS

AD5383-5 SPECIFICATIONS

AD5383-3 SPECIFICATIONS

TIMING CHARACTERISTICS

SERIAL INTERFACE TIMING

I2C SERIAL INTERFACE TIMING

PARALLEL INTERFACE TIMING

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TERMINOLOGY

TYPICAL PERFORMANCE CHARACTERISTICS

FUNCTIONAL DESCRIPTION

DAC ARCHITECTURE—GENERAL

DATA DECODING

ON-CHIP SPECIAL FUNCTION REGISTERS (SFR)

SFR COMMANDS

NOP (No Operation)

Soft CLR

Soft Power-Down

Soft Power-Up

Write CLR Code

Soft RESET

Control Register Write/Read

Channel Monitor Function

HARDWARE FUNCTIONS

RESET FUNCTION

ASYNCHRONOUS CLEAR FUNCTION

FIFO OPERATION IN PARALLEL MODE

POWER-ON RESET

POWER-DOWN

INTERFACES

DSP-, SPI-, MICROWIRE-COMPATIBLE SERIAL INTERFACES

Standalone Mode

Daisy-Chain Mode

Readback Mode

I2C SERIAL INTERFACE

START and STOP Conditions

Repeated START Conditions

Acknowledge Bit (ACK)

AD5383 Slave Addresses

Write Operation

PARALLEL INTERFACE

REG0, REG1 Pins

Pins A4 to A0

Pins DB11 to DB0

MICROPROCESSOR INTERFACING

Parallel Interface

AD5383 to MC68HC11

AD5383 to PIC16C6x/7x

AD5383 to 8051

AD5383 to ADSP-2101/ADSP-2103

APPLICATION INFORMATION

POWER SUPPLY DECOUPLING

TYPICAL CONFIGURATION CIRCUIT

CHANNEL MONITOR FUNCTION

TOGGLE MODE FUNCTION

THERMAL MONITOR FUNCTION

OPT I CAL ATT ENUATOR S

UTILIZING THE FIFO

OUTLINE DIMENSIONS

ORDERING GUIDE