Datasheet AD5370 Datasheet (ANALOG DEVICES)

40-Channel,16-Bit,

www.BDTIC.com/ADI

FEATURES

40-channel DAC in a 64-lead LFCSP and a 64-lead LQFP
Guaranteed monotonic to 16 bits
Maximum output voltage span of 4 × V
Nominal output voltage span of −4 V to +8 V
Multiple, independent output spans available
System calibration function allowing user-programmable

off

set and gain
Channel grouping and addressing features
Thermal shutdown function
DSP/microcontroller-compatible serial interface
SPI serial interface

DV

CCVDDVSS

STATE

16

8 8

16

16

16

16

16

16

16

16

8 8

16

16

16

16

16

16

16

16

16

A/B SELECT

REGISTER

X1A

REGISTER

X1B

REGISTER

M REGISTER

C REGIS TER

X1A

REGISTER

X1B

REGISTER

M REGISTER

C REGISTER

A/B SELECT

REGISTER

X1A

REGISTER

X1B

REGISTER

M REGISTER

C REGIS TER

X1A

REGISTER

X1B

REGISTER

M REGISTER

C REGISTER

SYNC

SDI

SCLK

SDO

BUSY

RESET

CLR

CONTROL
REGISTER

SERIAL

INTERFACE

MACHINE

AD5370

(20 V)

REF

AGND DGND

MUX 1MUX 1MUX 1MUX 1

FUNCTIONAL BLOCK DIAGRAM

TO

MUX2

16

16

TO

MUX2

16

16

16

16

16

16

REGISTER

REGISTER

REGISTER

REGISTER

REGISTER

REGISTER

REGISTER

REGISTER

16

16

16

16

16

16

16

16

Serial Input, Voltage Output DAC

2.5 V to 5.5 V digital interface

X2A

X2B

X2A

X2B

X2A

X2B

X2A

X2B

Digital reset (
Clear function to user-defined SIGGNDx
Simultaneous update of DAC outputs

APPLICATIONS

Level setting in automatic test equipment (ATE)
Variable optical attenuators (VOA)
Optical switches
Industrial control systems
Instrumentation

LDAC

1616

OFS0

REGISTER

MUX 2

MUX 2

MUX 2

MUX 2

16

16

16

16

REGISTER

REGISTER

REGISTER

REGISTER

REGISTER

16

DAC 0

16

DAC 7

1616

OFS1

16

DAC 0

16

DAC 7

GROUP 2 TO GROUP 4

ARE THE SAME AS GROUP 1

RESET

OFFSET

DAC 0

DAC 0

DAC 7

OFFSET

DAC 1

DAC 0

DAC 7

)

BUFFER

BUFFER

BUFFER

BUFFER

GROUP 0

OUTPUT BUFFER

AND

POWER-DOW N

CONTROL

OUTPUT BUFFER

AND

POWER-DOW N

CONTROL

GROUP 1

OUTPUT BUFFER

AND

POWER-DOW N

CONTROL

OUTPUT BUFFER

AND

POWER-DOW N

CONTROL

AD5370

VREF0

VOUT0

VOUT1

VOUT2

VOUT3

VOUT4

VOUT5

VOUT6

VOUT7

SIGGND0

VREF1

VOUT8

VOUT9

VOUT10

VOUT11

VOUT12

VOUT13

VOUT14

VOUT15

SIGGND1

VOUT16
TO
VOUT39

Figure 1.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2008 Analog Devices, Inc. All rights reserved.

SIGGND4SIGGND3SIGGND2

05813-001

AD5370

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TABLE OF CONTENTS

Features.............................................................................................. 1

Applications....................................................................................... 1

Functional Block Diagram ..............................................................1

Revision History ...............................................................................2

General Description......................................................................... 3

Specifications..................................................................................... 4

Performance Specifications......................................................... 4

AC Characteristics........................................................................ 5

Timing Characteristics ................................................................ 6

Timing Diagrams.......................................................................... 6

Absolute Maximum Ratings............................................................ 9

ESD Caution.................................................................................. 9

Pin Configurations and Function Descriptions......................... 10

Typical Performance Characteristics........................................... 12

Terminology.................................................................................... 14

Theory of Operation ......................................................................15

DAC Architecture....................................................................... 15

Channel Groups.......................................................................... 15

A

/B Registers and Gain/Offset Adjustment............................ 16

Load DAC.................................................................................... 16

Offset DAC Channels ................................................................16

Output Amplifier........................................................................ 17

Transfer Function....................................................................... 17

Reference Selection .................................................................... 17

Calibration................................................................................... 18

Additional Calibration............................................................... 18

Reset Function............................................................................ 19

Clear Function............................................................................ 19

and

LDAC

Functions...................................................... 19

BUSY

Power-Down Mode.................................................................... 19

Thermal Shutdown Function ...................................................19

Toggle Mode................................................................................ 20

Serial Interface ................................................................................ 21

SPI Write Mode .......................................................................... 21

SPI Readback Mode................................................................... 21

Register Update Rates................................................................ 21

Channel Addressing and Special Modes................................. 21

Special Function Mode.............................................................. 23

Power Supply Decoupling......................................................... 25

Power Supply Sequencing .........................................................25

Interfacing Examples ................................................................. 26

Outline Dimensions....................................................................... 27

Ordering Guide .......................................................................... 27

REVISION HISTORY

4/08—Revision 0: Initial Version

Rev. 0 | Page 2 of 28

AD5370

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GENERAL DESCRIPTION

The AD53701 contains forty 16-bit DACs in a single 64-lead
LFCSP and a 64-lead LQFP. The device provides buffered
voltage outputs with a span that is 4× the reference voltage. The
gain and offset of each DAC channel can be independently
trimmed to remove errors. For even greater flexibility, the device is
divided into five groups of eight DACs. Three offset DAC channels
allow the output range of blocks to be adjusted. Group 0 can be
adjusted by Offset DAC 0, Group 1 can be adjusted by Offset
DAC 1, and Group 2 to Group 4 can be adjusted by Offset DAC 2.

The AD5370 offers guaranteed operation over a wide supply

nge, with V

ra

from −16.5 V to −4.5 V and VDD from +9 V to

SS

+16.5 V. The output amplifier headroom requirement is 1.4 V
operating with a load current of 1 mA.

1

Protected by U.S. Patent No. 5,969,657; other patents pending.

Table 1. High Channel Count Bipolar DACs

Model Resolution Nominal Output Span Output Channels Linearity Error (LSB)

AD5360 16 bits 4 × V
AD5361 14 bits 4 × V
AD5362 16 bits 4 × V
AD5363 14 bits 4 × V

AD5370 16 bits 4 × V

AD5371 14 bits 4 × V
AD5372 16 bits 4 × V
AD5373 14 bits 4 × V
AD5378 14 bits ±8.75 V 32 ±3
AD5379 14 bits ±8.75 V 40 ±3

(20 V) 16 ±4

REF

(20 V) 16 ±1

REF

(20 V) 8 ±4

REF

(20 V) 8 ±1

REF

(12 V) 40 ±4

REF

(12 V) 40 ±1

REF

(12 V) 32 ±4

REF

(12 V) 32 ±1

REF

The AD5370 has a high speed serial interface that is compatible
with SPI, QSPI™, MICROWIRE™, and DSP interface standards
and can handle clock speeds of up to 50 MHz.

The DAC registers are updated on receipt of new data. All the
o

utputs can be updated simultaneously by taking the

LDAC
input low. Each channel has a programmable gain and an offset
adjust register to allow removal of gain and offset errors.

Each DAC output is gained and buffered on chip with respect to

n external SIGGNDx input. The DAC outputs can also be

a
switched to SIGGNDx via the

CLR

pin.

Rev. 0 | Page 3 of 28

AD5370

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SPECIFICATIONS

PERFORMANCE SPECIFICATIONS

DVCC = 2.5 V to 5.5 V; VDD = 9 V to 16.5 V; VSS = −16.5 V to −8 V; V
R

= open circuit; gain (M), offset (C), and DAC offset registers at default values; all specifications T

L

= 3 V; AGND = DGND = SIGGND = 0 V; CL = open circuit;

REF

MIN

to T

, unless otherwise noted.

MAX

Table 2.

Parameter Min Type Max Unit Test Conditions/Comments

ACCURACY

Resolution 16 Bits
Integral Nonlinearity −4 +4 LSB
Differential Nonlinearity −1 +1 LSB Guaranteed monotonic by design
Zero-Scale Error −10 +10 mV Before calibration
Full-Scale Error −10 +10 mV Before calibration
Gain Error 0.1 % FSR
Zero-Scale Error
Full-Scale Error
Span Error of Offset DAC −35 +35 mV

VOUT Temperature Coefficient

(VOUT0 to VOUT39)

DC Crosstalk

REFERENCE INPUTS (VREF0, VREF1)

VREF Input Current −10 +10 µA Per input, typically ±30 nA
VREF Range 2 5 V ±2% for specified operation

SIGGND INPUT (SIGGND0 to SIGGND4)2

DC Input Impedance 50 kΩ Typically 55 kΩ
Input Range −0.5 +0.5 V
SIGGND Gain 0.995 1.005

OUTPUT CHARACTERISTICS

Output Voltage Range VSS + 1.4 VDD − 1.4 V I
Nominal Output Voltage Range −4 +8 V
Short-Circuit Current 15 mA VOUTx to DVCC, VDD, or VSS
Load Current −1 +1 mA
Capacitive Load 2200 pF
DC Output Impedance 0.5

DIGITAL INPUTS

Input High Voltage 1.7 V DVCC = 2.5 V to 3.6 V

2.0 V DVCC = 3.6 V to 5.5 V
Input Low Voltage 0.8 V DVCC = 2.5 V to 5.5 V
Input Current −1 +1 µA

CLR High Impedance Leakage

Current

Input Capacitance

DIGITAL OUTPUTS (SDO, BUSY)

Output Low Voltage 0.5 V Sinking 200 A
Output High Voltage (SDO) DVCC − 0.5 V Sourcing 200 A
SDO High Impedance Leakage

Current

High Impedance Output

Capacitance

2

2

2

2

2

2

1 LSB After calibration
1 LSB After calibration

See the Offset DAC Channels section for

etails

d

5 ppm FSR/°C Includes linearity, offset, and gain drift

120 µV

2

−20 +20 µA

10 pF

−5 +5 µA

10 pF

Typically 20 µV; measured channel at midscale,

e change on any other channel

full-scal

= 1 mA

LOAD

Excluding the CLR

pin

1

Rev. 0 | Page 4 of 28

AD5370

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Parameter Min Type Max Unit Test Conditions/Comments

1

POWER REQUIREMENTS

DVCC 2.5 5.5 V
VDD 9 16.5 V
VSS −16.5 −4.5 V
Power Supply Sensitivity

2

Full Scale/VDD −75 dB
Full Scale/VSS −75 dB
Full Scale/DVCC −90 dB

DICC 2 mA

= 5.5 V, VIH = DVCC, VIL = GND; normal

DV

CC

operating conditions
IDD 18 mA Outputs unloaded, DAC outputs = 0 V
20 mA Outputs unloaded, DAC outputs = full scale
ISS −18 mA Outputs unloaded, DAC outputs = 0 V

−20 mA Outputs unloaded, DAC outputs = full scale
Power Dissipation Unloaded (P) 280 mW VSS = −8 V, VDD = +9.5 V, DVCC = 2.5 V
Power-Down Mode Control register power-down bit set

DICC 5 µA
IDD 35 µA
ISS −35 µA

Junction Temperature

1

Temperature range for the AD5370 is −40°C to +85°C. Typical specifications are at 25°C.

2

Guaranteed by design and characterization, not production tested.

3

Where θJA represents the package thermal impedance.

3

130 °C TJ = TA + P

TOTAL

× θJA

AC CHARACTERISTICS

DVCC = 2.5 V; VDD = 15 V; VSS = −15 V; VREF0 = VREF1 = 3 V; AGND = DGND = SIGGND = 0 V; CL = 200 pF; RL = 10 kΩ; gain (M),
offset (C), and DAC offset registers at default values; all specifications T

Table 3. AC Characteristics

1

Parameter Min Typ Max Unit Test Conditions/Comments

DYNAMIC PERFORMANCE

Output Voltage Settling Time 20 µs Settling to 1 LSB from a full-scale change
30 µs DAC latch contents alternately loaded with all 0s and all 1s
Slew Rate 1 V/µs
Digital-to-Analog Glitch Energy 5 nV-s
Glitch Impulse Peak Amplitude 10 mV
Channel-to-Channel Isolation 100 dB VREF0 = VREF1 = 2 V p-p, 1 kHz
DAC-to-DAC Crosstalk 20 nV-s
Digital Crosstalk 0.2 nV-s
Digital Feedthrough 0.02 nV-s Effect of input bus activity on DAC output under test
Output Noise Spectral Density @ 10 kHz 250 nV/√Hz VREF0 = VREF1 = 0 V

1

Guaranteed by design and characterization, not production tested.

MIN

to T

, unless otherwise noted.

MAX

Rev. 0 | Page 5 of 28

AD5370

T

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TIMING CHARACTERISTICS

DVCC = 2.5 V to 5.5 V; VDD = 9 V to 16.5 V; VSS = −16.5 V to −4.5 V; V
R

= open circuit; gain (M), offset (C), and DAC offset registers at default values; all specifications T

L

Table 4. SPI Interface

Parameter

t1

1, 2, 3

Limit at T

Min Typ Max

20 ns SCLK cycle time

MIN

, T

MAX

Unit Description

t2 8 ns SCLK high time
t3 8 ns SCLK low time
t4 11 ns

t

5

20 ns
t6 10 ns
t

7

5 ns Data setup time

SYNC
Minimum SYNC
24

t8 5 ns Data hold time

4

t

42 ns

9

t

1.5 μs

10

SYNC

BUSY
t11 600 ns Single-channel update cycle time
t12 20 ns
t13 10 ns
t14 3 μs
t15 0 ns
t16 3 μs

SYNC

LDAC

BUSY

BUSY

LDAC
t17 20 30 μs DAC output settling time
t18 140 ns
t19 30 ns
t20 400 μs
t21 270 ns

5

t

25 ns SCLK rising edge to SDO valid

22

t23 80 ns

1

Guaranteed by design and characterization, not production tested.

2

All input signals are specified with tR = tF = 2 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V.

3

See Figure 4 and Figure 5.

4

This is measured with the load circuit shown in Figure 2.

5

This is measured with the load circuit shown in Figure 3.

CLR

RESET

RESET

Minimum SYNC

RESET

= 3 V; AGND = DGND = SIGGND = 0 V; CL = 200 pF to GND;

REF

falling edge to SCLK falling edge setup time

high time

th

SCLK falling edge to SYNC rising edge

rising edge to BUSY falling edge
pulse width low (single-channel update); see Table 8

rising edge to LDAC falling edge
pulse width low
rising edge to DAC output response time
rising edge to LDAC falling edge
falling edge to DAC output response time

/RESET pulse activation time

pulse width low
time indicated by BUSY low

high time in readback mode

rising edge to BUSY falling edge

MIN

to T

, unless otherwise noted.

MAX

TIMING DIAGRAMS

DV

CC

R

L

2.2k

TO

OUTPUT

PIN

Figure 2. Load Circuit for

Ω

C

L

50pF

BUSY

Timing Diagram

V

OL

05813-002

O OUTPUT

PIN

Figure 3. Load Circuit for SDO Timing Diagram

Rev. 0 | Page 6 of 28

50pF

C

200µA I

L

200µA I

OL

VOH (MIN) – VOL (MAX)

OH

2

5813-003

AD5370

www.BDTIC.com/ADI

SCLK

SYNC

BUSY

LDAC

VOUTx

LDAC

VOUTx

SDI

1

1

2

2

1

2

t

t

4

t

5

t

7

t

8

DB23

t

1

24

3

t

2

t

6

DB0

t

9

t

1

t

11

t

10

12

t

13

24

t

17

t

14

t

15

t

13

t

17

t

16

CLR

VOUTx

RESET

VOUTx

BUSY

1

LDAC ACTIVE DURI NG BUSY.

2

LDAC ACTIVE AFTER BUSY.

t

18

t

19

t

18

t

20

t

23

05813-004

Figure 4. SPI Write Timing

Rev. 0 | Page 7 of 28

AD5370

SYNC

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SCLK

SDI

INPUT WORD SPECIFIES

REGIS TER TO BE READ

SDO

t

22

DB0 DB23DB23

LSB FROM PREVIOUS WRITE

Figure 5. SPI Read Timing

t

21

NOP CONDITIO N

DB0

DB23

SELECTED REG ISTER DAT A CLOCKED OUT

48

DB0

DB0

5813-005

Rev. 0 | Page 8 of 28

AD5370

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ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted. Transient currents of up to
60 mA do not cause SCR latch-up.

Table 5.

Parameter Rating

VDD to AGND −0.3 V to +17 V
VSS to AGND −17 V to +0.3 V
DVCC to DGND −0.3 V to +7 V
Digital Inputs to DGND −0.3 V to DVCC + 0.3 V
Digital Outputs to DGND −0.3 V to DVCC + 0.3 V
VREF0, VREF1 to AGND −0.3 V to +5.5 V
VOUT0 through VOUT39 to AGND VSS − 0.3 V to VDD + 0.3 V
SIGGND0 through SIGGND4 to AGND −1 V to +1 V
AGND to DGND −0.3 V to +0.3 V
Operating Temperature Range (TA)

Industrial (B Version) −40°C to +85°C
Storage −65°C to +150°C

Operating Junction Temperature

max)

(T

J

θJA Thermal Impedance

64-Lead LFCSP 25°C/W
64-Lead LQFP 45.5°C/W

Reflow Soldering

Peak Temperature 230°C
Time at Peak Temperature 10 sec to 40 sec

130°C

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. 0 | Page 9 of 28

AD5370

S

S

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PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

RESET

BUSY

VOUT27

IGGND3
VOUT28
VOUT29
VOUT30
VOUT31
VOUT32
VOUT33
VOUT34
VOUT35

IGGND4
VOUT36
VOUT37

V

VOUT24

AGND

AD5370

TOP VIEW

(Not to Scale)

VOUT8

VOUT9

VOUT39

DGND

VOUT10

DV

VOUT11

CC

SDO

SDI

SCLK

DVCCDGND

VOUT7

VOUT6

SYNC

49

1

RESET

2

BUSY

VOUT27

SIGGND3

VOUT28

VOUT29

VOUT30

VOUT31

VOUT32

VOUT33

VOUT34

VOUT35

SIGGND4

VOUT36

VOUT37

V

3

4

5

6

7

8

9

10

11

12

13

14

15

16

DD

SIGGND1

VOUT5

48

VOUT4

47

SIGGND0

46

VOUT3

45

VOUT2

44

VOUT1

43

VOUT0

42

VREF0

41

VOUT23

40

VOUT22

39

VOUT21

38

VOUT20

37

V

36

SS

35

V

DD

34

SIGGND2

33

VOUT19

32

VOUT12

VOUT13

VOUT14

VOUT15

VOUT16

VOUT17

VOUT18

05813-007

CLR

VOUT26

VOUT25

LDAC

646362616059585756555453525150

PIN 1

1

INDICATOR

2
3
4
5
6
7
8

9
10
11
12
13
14
15
16

DD

171819202122232425262728293031

SS

V

VREF1

VOUT38

VOUT26

VOUT25

VOUT24

AGND

DGND

DVCCSDO

SDI

SCLK

DVCCDGND

CLR

LDAC

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

PIN 1
INDICAT OR

AD5370

TOP VIEW

(Not to Scale)

17

18

SS

V

21 22 23 24 25 2627282930 31 32

19 20

VREF1

VOUT8

VOUT38

VOUT9

VOUT39

VOUT10

VOUT11

VOUT12

SIGGND1

VOUT13

VOUT7

SYNC

VOUT14

VOUT15

VOUT16

VOUT17

VOUT6

VOUT18

48

VOUT5

47

VOUT4

46

SIGGND0

45

VOUT3

44

VOUT2

43

VOUT1

42

VOUT0

41

VREF0

40

VOUT23

39

VOUT22

38

VOUT21

37

VOUT20

V

36

V

35

34

SIGGND2

33

VOUT19

SS

DD

Figure 6. 64-Lead LFCSP Pin Configuration Figure 7. 64-Lead LQFP Pin Configuration

Table 6. Pin Function Descriptions

Pin No. Mnemonic Description

1
2

RESET
BUSY

Digital Reset Input.
BUSY Input/Output (Active Low). BUSY is open-drain when an output. See the BUSY and

LDAC Functions section for more information.

3, 5 to 12, 14, 15, 19 to
24, 26 to 33, 37 to 40, 42
to 45, 47 to 50, 60 to 62

VOUT0 to VOUT39

DAC Outputs. Buffered analog outputs for each of the 40 D

AC channels. Each analog
output is capable of driving an output load of 10 kΩ to ground. Typical output impedance
of these amplifiers is 0.5 Ω.

46 SIGGND0 Reference Ground for DAC 0 to DAC 7. VOUT0 to VOUT7 are referenced to this voltage.
25 SIGGND1 Reference Ground for DAC 8 to DAC 15. VOUT8 to VOUT15 are referenced to this voltage.
34 SIGGND2 Reference Ground for DAC 16 to DAC 23. VOUT16 to VOUT23 are referenced to this voltage.
4 SIGGND3 Reference Ground for DAC 24 and DAC 31. VOUT24 to VOUT31 are referenced to this voltage.
13 SIGGND4 Reference Ground for DAC 32 to DAC 39. VOUT32 to VOUT39 are referenced to this voltage.
41 VREF0 Reference Input for DAC 0 to DAC 7. This reference voltage is referred to AGND.
18 VREF1 Reference Input for DAC 8 to DAC 39. This reference voltage is referred to AGND.

05813-025

Rev. 0 | Page 10 of 28

AD5370

www.BDTIC.com/ADI

Pin No. Mnemonic Description

16, 35 VDD

17, 36 VSS

51, 58 DGND Ground for All Digital Circuitry. Both DGND pins should be connected to the DGND plane.
52, 57 DVCC

53

54 SCLK

55 SDI

56 SDO

59 AGND Ground for All Analog Circuitry. The AGND pin should be connected to the AGND plane.
63

64

Exposed Paddle

SYNC

LDAC
CLR

Positive Analog Power Supply; +9 V to +16.5 V for specified performance. These pins

be decoupled with 0.1 µF ceramic capacitors and 10 µF capacitors.

should
Negative Analog Power Supply; −16.5 V to −8 V for specified performance. These pins

be decoupled with 0.1 µF ceramic capacitors and 10 µF capacitors.

should

Logic Power Supply; 2.5 V to 5.5 V. These pins should be decoupled with 0.1 µF ceramic
capacitors and 1

Active Low Input. This is the frame synchronization signal for the serial interface. See the
Timing Characteristics section for more details.

Serial Clock Input. Data is clock
pin operates at clock speeds up to 50 MHz. See the Timing Characteristics section for
mor

e details.

Serial Data Input. Data must be valid on the falli

teristics section for more details.

Charac
Serial Data Output for SPI Interface. CMOS output. SDO can be used f

clocked out on SDO on the rising edge of SCLK and is valid on the falling edge of SCLK.

Load DAC Logic Input (Active Low).
Asynchronous Clear Input (Level Sensitive, Active Low). See the Clear Function section for

more information.
The lead-free chip scale package (LFCSP) has an exposed paddle on the underside. The

paddle should b

0 µF capacitors.

ed into the shift register on the falling edge of SCLK. This

e connected to V

ng edge of SCLK. See the Timing

or readback. Data is

.

SS

Rev. 0 | Page 11 of 28

AD5370

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TYPICAL PERFORMANCE CHARACTERISTICS

2

1

0

TA = 25°C

= –15V

V

SS

= +15V

V

DD

VREF = +4.096V

0

INL (LSB)

–1

–2

0

16384 32768 49152

DAC CO DE

Figure 8.Typical INL Plot

7

6

5

4

3

NUMBER OF UNIT S

2

1

0

–0.6 –0.3 0 0.3 0.6

INL (LSB)

Figure 9. Typical INL Distribution

VDD = +15V
V

= –15V

SS

T

= 25°C

A

65535

–0.01

AMPLITUDE ( V)

–0.02

02468

05813-009

Figure 11. Analog Crosstalk Due to

0.0050

0.0025

AMPLITUDE (V)

–0.0025

–0.0050

05813-010

= 25°C

T

A

= –15V

V

SS

= +15V

V

DD

VREF = +4.096V

0

012345

TIME (µs)

LDAC

TIME (µs)

10

05813-012

05813-013

Figure 12. Digital Crosstalk

4

2

0

INL ERROR (LSB)

–2

–4

TEMPERATURE (° C)

VDD = +15V

= –15V

V

SS

= +5V

DV

CC

VREF = +3V

806040200

05813-011

Figure 10. Typical INL Error vs. Temperature

4

2

0

DNL (LSB)

–2

–4

0

16384 32768 49152

Figure 13. Typical DNL Plot

Rev. 0 | Page 12 of 28

DAC CO DE

65535

05813-014

AD5370

www.BDTIC.com/ADI

600

500

400

300

200

OUTPUT NOISE (nV/ Hz)

100

0

012345

FREQUENCY (Hz)

Figure 14. Noise Spectral Density

05813-015

14

12

10

8

6

NUMBER OF UNITS

4

2

0

(mA)

I

DD

Figure 17. Typical I

Distribution

DD

VDD = 15V

= 15V

V

SS

= 25°C

T

A

14.0013.7513.5013.2513.00

05813-018

0.50

VSS = –12V
V

= +12V

DD

VREF = +3V

0.45

DV

= +5.5V

0.40

(mA)

CC

DI

0.35

0.30

0.25
–40–200 20406080

14.0

13.5

( |mA| )

13.0

SS

/I

DD

I

CC

TEMPERATURE (° C)

Figure 15.DI

DV

= +2.5V

CC

vs. Temperature

CC

I

DD

I

SS

DV

= +3.6V

CC

14

12

10

8

6

NUMBER OF UNIT S

4

2

0

I

(mA)

05813-016

Figure 18. Typical DI

CC

Distribution

CC

DVCC = 5V
T

= 25°C

A

0.500.450. 400.350. 30

05813-019

12.5

VSS = –12V

= +12V

V

DD

VREF = +3V

12.0

–40–200 20406080

Figure 16. I

TEMPERATURE (°C)

vs. Temperature

DD/ISS

05813-017

Rev. 0 | Page 13 of 28

AD5370

www.BDTIC.com/ADI

TERMINOLOGY

Integral Nonlinearity (INL)

Integral nonlinearity, or endpoint linearity, is a measure of the
max

imum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
adjusting for zero-scale error and full-scale error and is
expressed in least significant bits (LSB).

Differential Nonlinearity (DNL)

Differential nonlinearity is the difference between the measured
cha

nge and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of 1 LSB maximum
ensures monotonicity.

Zero-Scale Error

Zero-scale error is the error in the DAC output voltage when all
0s a

re loaded into the DAC register.

Zero-scale error is a measure of the difference between VOUT
(ac

tual) and VOUT (ideal), expressed in millivolts, when the
channel is at its minimum value. Zero-scale error is mainly due
to offsets in the output amplifier.

Full-Scale Error

Full-scale error is the error in DAC output voltage when all 1s
a

re loaded into the DAC register. Full-scale error is a measure
of the difference between VOUT (actual) and VOUT (ideal),
expressed in millivolts, when the channel is at its maximum
value. It does not include zero-scale error.

Gain Error

Gain error is the difference between full-scale error and zero­s

cale error. It is expressed in millivolts.

Gain Error = F

VOUT Temperature Coefficient

This includes output error contributions from linearity, offset,
a

nd gain drift.

DC Output Impedance

DC output impedance is the effective output source resistance.

t is dominated by package lead resistance.

I

DC Crosstalk

The DAC outputs are buffered by op amps that share common
V

and VSS power supplies. If the dc load current changes in

DD

one channel (due to an update), this can result in a further dc
change in one or more channel outputs. This effect is more

ull-Scale Error − Zero-Scale Error

significant at high load currents and reduces as the load currents
are reduced. With high impedance loads, the effect is virtually
immeasurable. Multiple V
minimize dc crosstalk.

Output Voltage Settling Time

The amount of time it takes for the output of a DAC to settle to
a sp

ecified level for a full-scale input change.

Digital-to-Analog Glitch Energy

The amount of energy injected into the analog output at the

ajor code transition. It is specified as the area of the glitch in

m
nV-s. It is measured by toggling the DAC register data between
0x1FFF and 0x2000.

Channel-to-Channel Isolation

Channel-to-channel isolation refers to the proportion of input
sig

nal from the reference input of one DAC that appears at the
output of another DAC operating from another reference. It is
expressed in decibels and measured at midscale.

DAC-to-DAC C rosst a l k

DAC-to-DAC crosstalk is the glitch impulse that appears at the
o

utput of one converter due to both the digital change and
subsequent analog output change at another converter. It is
specified in nV-s.

Digital Crosstalk

The glitch impulse transferred to the output of one converter
d

ue to a change in the DAC register code of another converter is
defined as the digital crosstalk and is specified in nV-s.

Digital Feedthrough

When the device is not selected, high frequency logic activity
o

n the digital inputs of the device can be capacitively coupled
both across and through the device to appear as noise on the
VOUTx pins. It can also be coupled along the supply and
ground lines. This noise is digital feedthrough.

Output Noise Spectral Density

Output noise spectral density is a measure of internally gener­a

ted random noise. Random noise is characterized as a spectral
density (voltage per √Hz). It is measured by loading all DACs
to midscale and measuring noise at the output. It is measured
in nV/√Hz.

and VSS terminals are provided to

DD

Rev. 0 | Page 14 of 28

AD5370

www.BDTIC.com/ADI

THEORY OF OPERATION

DAC ARCHITECTURE

The AD5370 contains 40 DAC channels and 40 output amplifiers
in a single package. The architecture of a single DAC channel
consists of a 16-bit resistor-string DAC followed by an output
buffer amplifier. The resistor-string section is simply a string of
resistors, of equal value, from VREF to AGND. This type of
architecture guarantees DAC monotonicity. The 16-bit binary
digital code loaded to the DAC register determines at which
node on the string the voltage is tapped off before being fed into
the output amplifier. The output amplifier multiplies the DAC
output voltage by 4. The nominal output span is 12 V with a 3 V
reference and 20 V with a 5 V reference.

Table 7. AD5370 Registers

Word
Register
Name

X1A 16 0x1555 Input Data Register A. One for each DAC channel.
X1B 16 0x1555 Input Data Register B. One for each DAC channel.
M 16 0x3FFF Gain trim register. One for each DAC channel.
C 16 0x2000 Offset trim register. One for each DAC channel.
X2A 16

X2B 16

DAC

OFS0 14 0x1555 Offset DAC 0 data register. Sets the offset for Group 0.
OFS1 14 0x1555 Offset DAC 1 data register. Sets the offset for Group 1 to Group 4.
Control 3 0x00

A/B Select 0

A/B Select 1

A/B Select 2

A/B Select 3

A/B Select 4

Leng

(Bits)

8 0x00

8 0x00

8 0x00

8 0x00

8 0x00

Default

th

alue Description

V

Not user

ccessible

a
Not user

ccessible

a
Not user

ccessible

a

Output Data Register A. One for each DAC channel. These registers store the final calibrated DAC
data after gain and offset trimming. They are not readable or directly writable.

Output Data Register B. One for each DAC channel. These registers store the final calibrated DAC
data after gain and offset trimming. They are not readable or directly writable.

Data registers from which the DAC channels take their final input data. The DAC registers are
updated from the X2A or X2B register. They are not readable or directly writable.

Bit 2 = A
0 = global selection of X1A input data registers.
1 = X1B registers.
Bit 1 = enable temperature shutdown.
0 = d
1 = enable.
Bit 0 = soft power-down.
0 = sof

1 = soft power-down.
Each bit in this register determines if a DAC channel in Group 0 takes its data from Register X2A or X2B.

0 = X2A.
1 = X2B.

Each bit in this register determines if a DAC channel in Group 1 takes its data from Register X2A or X2B.
0 = X2A.
1 = X2B.

Each bit in this register determines if a DAC channel in Group 2 takes its data from Register X2A or X2B.
0 = X2A.
1 = X2B.

Each bit in this register determines if a DAC channel in Group 3 takes its data from Register X2A or X2B.
0 = X2A.
1 = X2B.

Each bit in this register determines if a DAC channel in Group 4 takes its data from Register X2A or X2B.
0 = X2A.
1 = X2B.

/B.

isable temperature shutdown.

t power-up.

CHANNEL GROUPS

The 40 DAC channels of the AD5370 are arranged into five
groups of eight channels. The eight DACs of Group 0 derive
their reference voltage from VREF0. Group 1 to Group 4 derive
their reference voltage from VREF1. Each group has its own
signal ground pin.

Rev. 0 | Page 15 of 28

AD5370

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A/B REGISTERS AND GAIN/OFFSET ADJUSTMENT

Each DAC channel has seven data registers. The actual DAC
data-word can be written to either the X1A or X1B input register,
depending on the setting of the

A

If the

/B bit is 0, data is written to the X1A register. If the A/B
bit is 1, data is written to the X1B register. Note that this single
bit is a global control and affects every DAC channel in the
device. It is not possible to set up the device on a per-channel
basis so that some writes are to X1A registers and some writes
are to X1B registers.

X1A

REGISTER

X1B

REGISTER

REGISTER

REGISTER

Figure 19. Data Registers Associated with Each DAC Channel

MUX

M

C

Each DAC channel also has a gain (M) register and an offset (C)
register, which allow trimming out of the gain and offset errors
of the entire signal chain. Data from the X1A register is operated on
by a digital multiplier and an adder controlled by the contents of
the M and C registers. The calibrated DAC data is then stored in
the X2A register. Similarly, data from the X1B register is operated
on by the multiplier and adder and stored in the X2B register.

Although Figure 19 indicates a multiplier and an adder for each

nnel, there is only one multiplier and one adder in the device,

cha
and they are shared among all channels. This has implications
for the update speed when several channels are updated at once,
as described in the

Register Update Rates section.

Each time data is written to the X1A register, or to the M or C

egister with the

r

A

/B control bit set to 0, the X2A data is recal­culated and the X2A register is automatically updated. Similarly,
X2B is updated each time data is written to X1B or to M or C

A

with

/B set to 1. The X2A and X2B registers are not readable

or directly writable by the user.
Data output from the X2A and X2B registers is routed to the

inal DAC register by a multiplexer. Whether each individual

f
DAC takes its data from the X2A or X2B register is controlled
by an 8-bit

A

/B select register associated with each group of
eight DACs. If a bit in this register is 0, the DAC takes its data
from the X2A register; if 1, the DAC takes its data from the X2B
register (Bit 0 through Bit 7 control DAC0 to DAC7).

Note that, because there are 40 bits in five registers, it is possible

o set up, on a per-channel basis, whether each DAC takes its

t
data from the X2A or X2B register. A global command is also
provided, which sets all bits in the

A

/B bit in the Control register.

X2A

REGISTER

REGISTER

MUX

X2B

A

/B select registers to 0 or to 1.

DAC

REGIS TER

DAC

05813-020

Rev. 0 | Page 16 of 28

LOAD DAC

All DAC channels in the AD5370 can be updated simultane-

LDAC

ously by taking

low when each DAC register is updated

from either its X2A or X2B register, depending on the setting of

A

the

/B select registers. The DAC register is not readable or

directly writable by the user.

OFFSET DAC CHANNELS

In addition to the gain and offset trim for each DAC channel,
there are two 14-bit offset DAC channels, one for Group 0 and
one for Group 1 to Group 4. These allow the output range of all
DAC channels connected to them to be offset within a defined
range. Thus, subject to the limitations of headroom, it is possible to
set the output range of Group 0 or Group 1 to Group 4 to be
unipolar positive, unipolar negative, or bipolar, either symmetrical
or asymmetrical about 0 V. The DAC channels in the AD5370
are factory trimmed with the offset DAC channels set at their
default values. This results in optimum offset and gain performance
for the default output range and span.

When the output range is adjusted by changing the value of the
o

ffset DAC channel, an extra offset is introduced due to the
gain error of the offset DAC channel. The amount of offset is
dependent on the magnitude of the reference and how much
the offset DAC channel deviates from its default value. This
offset is quoted in the

Specifications section.

The worst-case offset occurs when the offset DAC channel is at
p

ositive or negative full scale. This value can be added to the
offset present in the main DAC channel to give an indication of
the overall offset for that channel. In most cases, the offset can be
removed by programming the channel’s C register with an
appropriate value. The extra offset caused by the offset DAC s
only needs to be taken into account when an offset DAC
channel is changed from its default value.

Figure 20 shows the allowable code range that can be loaded to
t

he offset DAC channel; this is dependent on the reference value
used. Thus, for a 5 V reference, the offset DAC channel should
not be programmed with a value greater than 8192 (0x2000).

5

4

3

)
V

(
F

E
R
V

2

1

0

0 4096 8192 12288 16383

OFFSET DAC CODE

Figure 20. Offset DAC Code Range

RESERVED

05813-021

AD5370

V

S

(

)

www.BDTIC.com/ADI

OUTPUT AMPLIFIER

The output amplifiers can swing to 1.4 V below the positive
supply and 1.4 V above the negative supply, which limits how
much the output can be offset for a given reference voltage. For
example, it is not possible to have a unipolar output range of 20 V
because the maximum supply voltage is ±16.5 V.

S1

OUT

S2

CLR

R6
10kΩ

S3

SIGGND

CLR

05813-022

IGGND

DAC

CHANNEL

R4

R3

60kΩ

20kΩ

OFFSET

DAC

Figure 21. Output Amplif

R5

60kΩ

R1

20kΩ

CLR

R2
20kΩ

ier and Offset DAC

Figure 21 shows details of a DAC output amplifier and its
connections to its corresponding offset DAC. On power-up, S1
is open, disconnecting the amplifier from the output. S3 is
closed; thus, the output is pulled to the corresponding SIGGND
(R1 and R2 are much greater than R6). S2 is also closed to
prevent the output amplifier being open-loop. If

power-up, the output remains in this condition until

CLR

is low at

CLR

is
taken high. The DAC registers can be programmed, and the
outputs assume the programmed values when
high. Even if

CLR

is high at power-up, the output remains in the

CLR

is taken

previously described condition until VDD > 6 V and VSS
< −4 V and the initialization sequence has finished. The outputs
then go to their power-on default values.

TRANSFER FUNCTION

OUTPUT

VOLTAGE

8V

ACTUAL
TRANSFER
FUNCTION

IDEAL
TRANSFER
FUNCTION

0

–4V

Figure 22. DAC Transfer Function

DAC CODE

ZERO-SCALE
ERROR

The output voltage of a DAC in the AD5370 is dependent on the
value in the input register, the value of the M and C registers,
and the value in the offset DAC. The transfer functions for the
AD5370 are shown in the following section.

16383

FULL-SCAL E
ERROR
+
ZERO-SCALE
ERROR

05813-008

Rev. 0 | Page 17 of 28

The input code is the value in the X1A or X1B register that is

pplied to DAC (X1A, X1B default code = 5461), as follows:

a

)1(_

+×

_ −+

= C

CODEDAC

MCODEINPUT

16

2

15

2

DAC output voltage is calculated as follows:

_4_

4

VREFVOUT +

××=

×−

16

2

CODEOFFSETCODEDAC

V

where:
DAC_CODE s

hould be within the range of 0 to 65,535.
For 12 V span, VREF = 3.0 V.
For 20 V span, VREF = 5.0 V.

M = code in gain register − default code = 2
C = code in offset register − default code = 2

16

15

– 1.

.
OFFSET_CODE is the code loaded to the offset DAC. It is
multiplied by 4 in the transfer function because the offset DAC
is a 14-bit device. On power-up, the default code loaded to the
offset DAC is 5461 (0x1555). With a 3 V reference, this gives a
span of −4 V to +8 V.

REFERENCE SELECTION

The AD5370 has two reference input pins. The voltage applied
to the reference pins determines the output voltage span on
VOUT0 to VOUT39. VREF0 determines the voltage span for
VOUT0 to VOUT7 (Group 0) and VREF1 determines the
voltage span for VOUT8 to VOUT39 (Group 2 to Group 4).
The reference voltage applied to each VREF pin can be
different, if required, allowing each group to have a different
voltage span. The output voltage range and span can be adjusted
further by programming the offset and gain registers for each
channel and by programming the offset DAC channels. If the
offset and gain features are not used (that is, the M and C
registers are left at their default values), the required reference
levels can be calculated as follows:

VREF = (VOUT

− VOUT

MAX

If the offset and gain features of the AD5370 are used, the

equired output range is slightly different. The chosen output

r
range should take into account the system offset and gain errors
that need to be trimmed out. Therefore, the chosen output
range should be larger than the actual required range.

The required reference levels can be calculated as follows:

1. I

dentify the nominal output range on VOUT.

2. I

dentify the maximum offset span and the maximum gain

required on the full output signal range.

3. C

alculate the new maximum output range on VOUT,

including the expected maximum offset and gain errors.

4. Ch

oose the new required VOUT
the VOUT limits centered on the nominal values. Note that
V

and VSS must provide sufficient headroom.

DD

alculate the value of VREF as follows:

5. C

VREF = (VOUT

− VOUT

MAX

MIN

MIN

)/4

MAX

)/4

and VOUT

, keeping

MIN

SIGGND

AD5370

www.BDTIC.com/ADI

Reference Selection Example

If

• N

ominal Output Range = 12 V (−4 V to +8 V)

• Z

ero-Scale Error = ±70 mV

• Ga

in Error = ±3%

• S

IGGND = AGND = 0 V

Then

in Error = ±3%

• Ga

=> Maximum Positive Gain Error = +3%
=> Output Range Including Gain Error = 12 + 0.03(12) =

12.36 V
fset Error = ±70 mV

• Of

=> Maximum Offset Error Span = 2(70 mV) = 0.14 V
=> Output Range Including Gain Error and Offset Error =

12.36 V + 0.14 V = 12.5 V

• VREF C

Actual Output Range = 12.5 V, that is, −4.25 V to +8.25 V;
VREF = (8.25 V + 4.25 V)/4 = 3.125 V

If the equation yields an inconvenient reference level, the user

n adopt one of the following approaches:

ca

• U

reference level to the required level.

• S

the gain and offset registers to downsize the reference digitally.
In this way, the user can use almost any convenient reference
level but may reduce the performance by overcompaction
of the transfer function.

• U

CALIBRATION

The user can perform a system calibration on the AD5370 to
reduce gain and offset errors to below 1 LSB. This is achieved
by calculating new values for the M and C registers and reprogram­ming them.

Reducing Zero-Scale Error

Zero-scale error can be reduced as follows:

1. S

2. M

required value. This gives the zero-scale error.

3. C

add this from the default value of the C register. Note that
only negative zero-scale error can be reduced.

alculation

se a resistor divider to divide down a convenient, higher

elect a convenient reference level above VREF, and modify

se a combination of these two approaches.

et the output to the lowest possible value.

easure the actual output voltage and compare it with the

alculate the number of LSBs equivalent to the error and

Reducing Full-scale Error

Full-scale error can be reduced as follows:

1. M

easure the zero-scale error.

2. S

et the output to the highest possible value.

easure the actual output voltage and compare it with the

3. M

required value. Add this error to the zero-scale error. This
is the span error, which includes the full-scale error.

alculate the number of LSBs equivalent to the full-scale

4. C

error and subtract it from the default value of the M register.
Note that only positive full-scale error can be reduced.

5. The M an

both zero-scale and full-scale errors have been calculated.

d C registers should not be programmed until

AD5370 Calibration Example

This example assumes that a −4 V to +8 V output is required.
The DAC output is set to −4 V but measured at −4.03 V. This
gives a zero-scale error of −30 mV.

1. 1 LS

2. 30 mV = 164 LS

The full-scale error can now be calculated. The output is set to
+8 V a
+20 mV – (–30 mV) = +50 mV.

The errors can now be removed.

1. 164 LS

2. 273 LS

3. 65,262 s

B = 12 V/65,536 = 183.11 μV

B

nd a value of +8.02 V is measured. The full-scale error is

50 mV = 273 LSBs

B should be added to the default C register value,

that is (32,768 + 164) = 32,932.

B should be subtracted from the default M register

value; that is, (65,535 − 273) = 65,262.

hould be programmed to the M register and 32,932

should be programmed to the C register.

ADDITIONAL CALIBRATION

The techniques described in the previous section are usually
enough to reduce the zero-scale and full-scale errors in most
applications. However, there are limitations whereby the errors
may not be sufficiently removed. For example, the offset (C)
register can only be used to reduce the offset caused by the
negative zero-scale error. A positive offset cannot be reduced.
Likewise, if the maximum voltage is below the ideal value, that
is, a negative full-scale error, the gain (M) register cannot be
used to increase the gain to compensate for the error.

These limitations can be overcome by increasing the reference
va

lue. With a 3 V reference, a 12 V span is achieved. The ideal
voltage range for the AD5370 is −4 V to +8 V. Using a 3.1 V
reference increases the range to −4.133 V to +8.2667 V. Clearly,
in this case, the offset and gain errors are insignificant, and the
M and C registers can be used to raise the negative voltage to

−4 V and then reduce the maximum voltage to +8 V to give the
most accurate values possible.

Rev. 0 | Page 18 of 28

AD5370

www.BDTIC.com/ADI

RESET FUNCTION

The reset function is initiated by the
edge of
sequence to reset the X, M, and C registers to their default
values. This sequence typically takes 300 μs, and the user should

not write to the part during this time. On power-up, it is recom­mended that the user bring
properly initialize the registers.

When the reset sequence is complete (and provided that
high), the DAC output is at a potential specified by the default
register settings, which are equivalent to SIGGNDx. The DAC
outputs remain at SIGGNDx until the X, M, or C register is
updated and
to the default state by pulsing
that, because the reset function is triggered on the rising edge,
bringing

RESET

, the AD5370 state machine initiates a reset

RESET

LDAC

is taken low. The AD5370 can be returned

RESET

low has no effect on the operation of the AD5370.

RESET

pin. On the rising

high as soon as possible to

RESET

low for at least 30 ns. Note

CLR

is

CLEAR FUNCTION

CLR

is an active low input that should be high for normal

CLR

operation. The
resistor. When
buffer stages, VOUT0 to VOUT39, is switched to the externally
set potential on the relevant SIGGND pin. While
LDAC

pulses are ignored. When
DAC outputs remain cleared until
of the input registers and DAC registers are not affected by taking

CLR

low. To prevent glitches from appearing on the outputs,
should be brought low by writing to the offset DAC whenever
the output span is adjusted.

pin has in internal 500 kΩ pull-down

CLR

is low, the input to each of the DAC output

CLR

CLR

is taken high again, the

LDAC

is taken low. The contents

is low, all

CLR

BUSY AND LDAC FUNCTIONS

The value of an X2 (A or B) register is calculated each time the
user writes new data to the corresponding X1, C, or M register.
During the calculation of X2, the
BUSY

is low, the user can continue writing new data to the X1,
M, or C register (see the Register Update Rates section for more
d

etails), but no DAC output updates can take place.

BUSY

The
resistor. In cases where multiple AD5370 devices are used in
one system, the
when it is required that no DAC channel in any device be
updated until all other DAC channels are ready to be updated.
When each device finishes updating the X2 (A or B) register, it
releases the
updating its X2 register, it holds
effect of

The DAC outputs are updated by taking the
LDAC

and the DAC outputs update immediately after
high. A user can also hold the
this case, the DAC outputs update immediately after

pin is bidirectional and has a 50 kΩ internal pull-up

BUSY

pins can be tied together. This is useful

BUSY

pin. If another device has not finished

LDAC

going low.

goes low while

BUSY

BUSY

output goes low. While

BUSY

low, thus delaying the

is active, the

LDAC

input permanently low. In

LDAC

LDAC

event is stored

BUSY

input low. If

goes

BUSY

goes

A

high. Whenever the
also goes low, for approximately 600 ns.

The AD5370 has flexible addressing that allows writing of data

o a single channel, all channels in a group, the same channel in

t
Group 0 to Group 4 or the same channel in Group 1 to Group 4,
or all channels in the device. This means that 1, 4, 5, 8, or 40
DAC register values may need to be calculated and updated.
Because there is only one multiplier shared among 40 channels,
this task must be done sequentially so that the length of the
BUSY

pulse varies according to the number of channels being

updated.

Table 8.

Action

Loading X1A, X1B, C, or M to 1 channel2 1.5
Loading X1A, X1B, C, or M to 4 channels 3.3
Loading X1A, X1B, C, or M to 5 channels 3.9
Loading X1A, X1B, C, or M to 8 channels 5.7
Loading X1A, X1B, C, or M to 40 channels 24.9

1

2

A single channel update is typically 1 µs.

The AD5370 contains an extra feature whereby a DAC register
is not updated unless its X2A or X2B register has been written
to since the last time
LDAC
contents of the X2A or X2B register, depending on the setting of
the
register only if the X2 data has changed, thereby removing
unnecessary digital crosstalk.

BUSY

BUSY

Pulse Width = ((Number of Channels + 1) × 600 ns) + 300 ns.

is brought low, the DAC registers are filled with the

A

/B select registers. However, the AD5370 updates the DAC

/B select registers are written to,

Pulse Widths

LDAC

was brought low. Normally, when

BUSY
(μs max)

POWER-DOWN MODE

The AD5370 can be powered down by setting Bit 0 in the
control register to 1. This turns off the DAC channels, thus
reducing the current consumption. The DAC outputs are
connected to their respective SIGGND potentials. The power­down mode does not change the contents of the registers, and
the DAC channels return to their previous voltage when the
power-down bit is cleared to 0.

THERMAL SHUTDOWN FUNCTION

The AD5370 can be programmed to power down the DACs if
the temperature on the die exceeds 130°C. Setting Bit 1 in the
control register to 1 (see the Special Function Mode section)
ena

bles this function. If the die temperature exceeds 130°C, the
AD5370 enters a temperature power-down mode, which is
equivalent to setting the power-down bit in the control register.
To indicate that the AD5370 has entered temperature shutdown
mode, Bit 4 of the control register is set to 1. The AD5370 remains
in temperature shutdown mode, even if the die temperature
falls, until Bit 1 in the control register is cleared to 0.

BUSY

Pulse Width1

Rev. 0 | Page 19 of 28

AD5370

www.BDTIC.com/ADI

TOGGLE MODE

The AD5370 has two X2 registers per channel, X2A and X2B,
that can be used to switch the DAC output between two levels
with ease. This approach greatly reduces the overhead required
by a microprocessor that would otherwise have to write to each
channel individually. When the user writes to the X1A, X2A, M,
or C register, the calculation engine takes a certain amount of
time to calculate the appropriate X2A or X2B value. If the
application only requires that the DAC output switch between
two levels, as is the case with a data generator, any method that
reduces the amount of calculation time necessary is advantageous.

For the data generator example, the user need only set the high
and low levels for each channel once by writing to the X1A and
X1B registers. The values of X2A and X2B are calculated and
stored in their respective registers. The calculation delay
therefore happens only during the setup phase, that is, when
programming the initial values. To toggle a DAC output
between the two levels, it is only required to write to the
relevant
more, because there are eight MUX2 control bits per register, it
is possible to update eight channels with a single write.
s

A

/B select register to set the MUX2 register bit. Further-

hows the bits that correspond to each DAC output.

Table 15

Rev. 0 | Page 20 of 28

AD5370

www.BDTIC.com/ADI

SERIAL INTERFACE

The AD5370 contains a high speed SPI-compatible serial interface
operating at clock frequencies up to 50 MHz (20 MHz for read
operations). To minimize both the power consumption of the
device and on-chip digital noise, the interface powers up fully
only when the device is being written to, that is, on the falling
edge of
when operating from a 2.5 V to 3.6 V DV
trolled by four pins:
(serial data input pin), SCLK (clocks data in and out of the device),
and SDO (serial data output pin for data readback).

SYNC

. The serial interface is 2.5 V LVTTL-compatible

supply. It is con-

CC

SYNC

(frame synchronization input), SDI

SPI WRITE MODE

The AD5370 allows writing of data via the serial interface to
every register directly accessible to the serial interface, which is
all registers except the X2A and X2B registers and the DAC
registers. The X2A and X2B registers are updated when the user
writes to the X1A, X1B, M, or C register, and the DAC registers
are updated by

The serial word (see Table 10) is 24 bits long; 16 of these bits are

ta bits, six bits are address bits, and two bits are mode bits that

da
determine what is done with the data.

The serial interface works with both a continuous and a burst

ted) serial clock. Serial data applied to SDI is clocked into

(ga
the AD5370 by clock pulses applied to SCLK. The first falling

SYNC

edge of
must be applied to SCLK to clock in 24 bits of data before
is taken high again. If
clock edge, the write operation is aborted.

If a continuous clock is used,

th

the 25

falling clock edge. This inhibits the clock within the
AD5370. If more than 24 falling clock edges are applied before
SYNC

is taken high again, the input data becomes corrupted. If
an externally gated clock of exactly 24 pulses is used,
be taken high any time after the 24

The input register addressed is updated on the rising edge of
SYNC

. For another serial transfer to take place,
taken low again.

LDAC

.

starts the write cycle. At least 24 falling clock edges

SYNC

SYNC

is taken high before the 24th falling

SYNC

must be taken high before

SYNC

th

falling clock edge.

SYNC

can

must be

SPI READBACK MODE

The AD5370 allows data readback via the serial interface from
every register directly accessible to the serial interface, which is
all registers except the X2A, X2B, and DAC registers. To read
back a register, it is first necessary to tell the AD5370 which
register to read. This is achieved by writing a word whose

Table 10. Serial Word Bit Assignment

I23 I22 I21 I20 I19 I18 I17 I16 I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0
M1 M0 A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

first two bits are the Special Function Code 00 to the device. The

emaining bits then determine which register is to be read back.

r
If a readback command is written to a special function register,

d

ata from the selected register is clocked out of the SDO pin
during the next SPI operation. The SDO pin is normally three­stated but becomes driven as soon as a read command is issued.
The pin remains driven until the register data is clocked out.
See

Figure 5 for the read timing diagram. Note that, due to the

ming requirements of t

ti
SPI interface during a read operation should not exceed 20 MHz.

(25 ns), the maximum speed of the

5

REGISTER UPDATE RATES

The value of the X2A or X2B register is calculated each time the
user writes new data to the corresponding X1, C, or M register.
The calculation is performed by a three-stage process. The first
two stages take approximately 600 ns each, and the third stage
takes approximately 300 ns. When the write to the X1, C, or M
register is complete, the calculation process begins. If the write
operation involves the update of a single DAC channel, the user
is free to write to another register, provided that the write
operation does not finish until the first stage calculation is
complete, that is, 600 ns after completion of the first write
operation. If a group of channels is being updated by a single
write operation, the first stage calculation is repeated for each
channel, taking 600 ns per channel. In this case, the user should not
complete the next write operation until this time has elapsed.

CHANNEL ADDRESSING AND SPECIAL MODES

If the mode bits are not 00, the data-word for D13 to D0 is
written to the device. Address Bit A5 to Address Bit A0
determine which channels are written to, whereas the mode bits
determine the register (X1A, X1B, C, or M) to which the data is
written, as shown in
X1B r

egister, the setting of the
determines the register to which the data is written (that is,
0 → X1A, 1 → X1B).

Table 9. Mode Bits

M1 M0 Action

1 1

1 0 Writes to the DAC offset (C) register
0 1 Writes to the DAC gain (M) register
0 0

Table 9 . If data is to be written to the X1A or

A

/B bit in the control register

Writes to the DAC input data (X) register,
depending on the c

Special function, used in combination
with other bits

ontrol register A

of the data-word

/B bit

Rev. 0 | Page 21 of 28

AD5370

www.BDTIC.com/ADI

Table 11 shows the groups and channels that are addressed for every combination of Address Bit A5 to Address Bit A0.

Table 11. Group and Channel Addressing

Address Bit A5 to Address Bit A3 Address Bit A2 to

Address Bit A0

000

001

010

011

100

101

110 Reserved

111 Reserved

000 001 010 011 100 101 110 111

All groups,

annels

all ch

Group 0,

annels

all ch

Group 1,

annels

all ch

Group 2,

annels

all ch

Group 3,

annels

all ch

Group 4,

annels

all ch

Group 0,
Channel 0

Group 0,
Channel 1

Group 0,
Channel 2

Group 0,
Channel 3

Group 0,
Channel 4

Group 0,
Channel 5

Group 0,
Channe

Group 0,
Channe

l 6

l 7

Group 1,
Channel 0

Group 1,
Channel 1

Group 1,
Channel 2

Group 1,
Channel 3

Group 1,
Channel 4

Group 1,
Channel 5

Group 1,
Channel 6

Group 1,
Channel 7

Group 2,
Channel 0

Group 2,
Channel 1

Group 2,
Channel 2

Group 2,
Channel 3

Group 2,
Channel 4

Group 2,
Channel 5

Group 2,
Channel 6

Group 2,
Channel 7

Group 3,
Channel 0

Group 3,
Channel 1

Group 3,
Channel 2

Group 3,
Channel 3

Group 3,
Channel 4

Group 3,
Channel 5

Group 3,
Channel 6

Group 3,
Channel 7

Group 4,
Channel 0

Group 4,
Channel 1

Group 4,
Channel 2

Group 4,
Channel 3

Group 4,
Channel 4

Group 4,
Channel 5

Group 4,
Channel 6

Group 4,
Channel 7

Group 0,
Group 1,
Group 2,
Group 3,
Group 4;
Channel 0

Group 0,
Group 1,
Group 2,
Group 3,
Group 4;
Channel 1

Group 0,
Group 1,
Group 2,
Group 3,
Group 4;
Channel 2

Group 0,
Group 1,
Group 2,
Group 3,
Group 4;
Channel 3

Group 0,
Group 1,
Group 2,
Group 3,
Group 4;
Channel 4

Group 0,
Group 1,
Group 2,
Group 3,
Group 4;
Channel 5

Group 0,
Group 1,
Group 2,
Group 3,
Group 4;
Channel 6

Group 0,
Group 1,
Group 2,
Group 3,
Group 4;
Channel 7

Group 1,
Group 2,
Group 3,
Group 4;
Channel 0

Group 1,
Group 2,
Group 3,
Group 4;
Channel 1

Group 1,
Group 2,
Group 3,
Group 4;
Channel 2

Group 1,
Group 2,
Group 3,
Group 4;
Channel 3

Group 1,
Group 2,
Group 3,
Group 4;
Channel 4

Group 1,
Group 2,
Group 3,
Group 4;
Channel 5

Group 1,
Group 2,
Group 3,
Group 4;
Channel 6

Group 1,
Group 2,
Group 3,
Group 4;
Channel 7

Rev. 0 | Page 22 of 28

AD5370

www.BDTIC.com/ADI

SPECIAL FUNCTION MODE

If the mode bits are 00, the special function mode is selected, as shown in Table 12. Bit I21 to Bit I16 of the serial data-word select the special
function, and the remaining bits are data required for execution of the special function, for example, the channel address for data readback.

The codes for the special functions are shown in Table 13. Ta ble 1 4 shows the addresses for data readback.

Table 12. Special Function Mode

I23 I22 I21 I20 I19 I18 I17 I16 I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0
0 0 S5 S4 S3 S2 S1 S0 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0

Table 13. Special Function Codes

Special Function Code

S5 S4 S3 S2 S1 S0 Data (F15 to F0) Action

0 0 0 0 0 0 0000 0000 0000 0000 NOP.
0 0 0 0 0 1 XXXX XXXX XXXX X [F2:F0] Write to the Control register.

F3 = reserved. This bit should be 0 when writing to the Control register.
F2 = 1: select register X1B for input.
F2 = 0: select register X1A for input.
F1 = 1: enable temperature shutdown.
F1 = 0: disable temperature shutdown.
F0 = 1: soft power-down.
F0 = 0: soft power-up.
0 0 0 0 1 0 XX[F13:F0] Write data in F13:F0 to OFS0 register.
0 0 0 0 1 1 XX[F13:F0] Write data in F13:F0 to OFS1 register.
0 0 0 1 0 0 Reserved Reserved.
0 0 0 1 0 1 See Table 14 Select register for readback.
0 0 0 1 1 0 XXXX XXXX [F7:F0]

0 0 0 1 1 1 XXXX XXXX [F7:F0]
0 0 1 0 0 0 XXXX XXXX [F7:F0]
0 0 1 0 0 1 XXXX XXXX [F7:F0]
0 0 1 0 1 0 XXXX XXXX [F7:F0]
0 0 1 0 1 1 XXXX XXXX [F7:F0]
F7:F0 = 0, write all 0s (all channels use X2A register).
F7:F0 = 1, write all 1s (all channels use X2B register).
0 1 1 1 0 0 Reserved

F4 = overtemperature indicator (read-only bit). This bit should be 0 when

iting to the Control register.

wr

Write data in F7:F0 to A
Write data in F7:F0 to A
Write data in F7:F0 to A
Write data in F7:F0 to A
Write data in F7:F0 to A
Block write A

/B select registers.

/B Select Register 0.
/B Select Register 1.
/B Select Register 2.
/B Select Register 3.
/B Select Register 4.

Rev. 0 | Page 23 of 28

AD5370

www.BDTIC.com/ADI

Table 14. Address Codes for Data Readback

F15 F14 F13 F12 F11 F10 F9 F8 F7 Register Read

0 0 0 X1A register
0 0 1 X1B register
0 1 0 C register
0 1 1
1 0 0 0 0 0 0 0 1 Control register
1 0 0 0 0 0 0 1 0 OFS0 data register
1 0 0 0 0 0 0 1 1 OFS1 data register
1 0 0 0 0 0 1 0 0 Reserved
1 0 0 0 0 0 1 1 0
1 0 0 0 0 0 1 1 1
1 0 0 0 0 1 0 0 0
1 0 0 0 0 1 0 0 1
1 0 0 0 0 1 0 1 0

1

F6 to F0 are don’t cares for the data readback function.

Table 15. DAC Channels Selected by

/B Select

A
Register

0 VOUT7 VOUT6 VOUT5 VOUT4 VOUT3 VOUT2 VOUT1 VOUT0
1 VOUT15 VOUT14 VOUT13 VOUT12 VOUT11 VOUT10 VOUT9 VOUT8
2 VOUT23 VOUT22 VOUT21 VOUT20 VOUT19 VOUT18 VOUT17 VOUT16
3 VOUT31 VOUT30 VOUT29 VOUT28 VOUT27 VOUT26 VOUT25 VOUT24
4 VOUT39 VOUT38 VOUT37 VOUT36 VOUT35 VOUT34 VOUT33 VOUT32

1

If the bit is 0, Register A is selected. If the bit is 1, Register B is selected.

F7 F6 F5 F4 F3 F2 F1 F0

Bit F12 to Bit F7 select the channel to be read back from;

1

Channel 0 = 001000 to Channel 39 = 101111

A

/B Select Registers

Bits

M register

/B Select Register 0

A

/B Select Register 1

A

/B Select Register 2

A

/B Select Register 3

A

/B Select Register 4

A

1

Rev. 0 | Page 24 of 28

AD5370

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POWER SUPPLY DECOUPLING

In any circuit where accuracy is important, careful consideration
of the power supply and ground return layout helps to ensure
the rated performance. The printed circuit board on which the
AD5370 is mounted should be designed so that the analog and
digital sections are separated and confined to certain areas of
the board. If the AD5370 is in a system where multiple devices
require an AGND-to-DGND connection, the connection should
be made at one point only. The star ground point should be
established as close as possible to the device. For supplies with
multiple pins (V
pins together and to decouple each supply once.

The AD5370 should have ample supply decoupling of 10 μF in
p

arallel with 0.1 μF on each supply located as close to the package
as possible, ideally right up against the device. The 10 μF capacitors
are the tantalum bead type. The 0.1 μF capacitor should have
low effective series resistance (ESR) and low effective series
inductance (ESI)—such as is typical of the common ceramic types
that provide a low impedance path to ground at high frequencies—
to handle transient currents due to internal logic switching.

Digital lines running under the device should be avoided

ecause they can couple noise onto the device. The analog

b
ground plane should be allowed to run under the AD5370 to
avoid noise coupling. The power supply lines of the AD5370
should use as large a trace as possible to provide low impedance
paths and reduce the effects of glitches on the power supply line.
Fast-switching digital signals should be shielded with digital
ground to avoid radiating noise to other parts of the board,
and they should never be run near the reference inputs. It is
essential to minimize noise on all VREF lines.

, VDD, DVCC), it is recommended to tie these

SS

Avoid crossover of digital and analog signals. Traces on opposite

f the board should run at right angles to each other. This

sides o
reduces the effects of feedthrough through the board. A microstrip
technique is by far the best approach, but it is not always possible
with a double-sided board. In this technique, the component side
of the board is dedicated to ground plane, and signal traces are
placed on the solder side.

As is the case for all thin packages, care must be taken to avoid

lexing the package and to avoid a point load on the surface of

f
this package during the assembly process.

POWER SUPPLY SEQUENCING

When the supplies are connected to the AD5370, it is important
that the AGND and DGND pins be connected to the relevant
ground plane before the positive or negative supplies are applied.
In most applications, this is not an issue because the ground pins
for the power supplies are connected to the ground pins of the
AD5370 via ground planes. When the AD5370 is used in a hot
swap card, care should be taken to ensure that the ground pins
are connected to the supply grounds before the positive or
negative supply is connected. This is required to prevent currents
from flowing in directions other than toward an analog or
digital ground.

Rev. 0 | Page 25 of 28

AD5370

www.BDTIC.com/ADI

INTERFACING EXAMPLES

The SPI interface of the AD5370 is designed to allow the parts to be
e

asily connected to industry-standard DSPs and microcontrollers.
Figure 23 shows how the AD5370 can be connected to the
Anal

og Devices, Inc., Blackfin® DSP. The Blackfin has an integrated
SPI port that can be connected directly to the SPI pins of the
AD5370, as well as programmable input/output pins that can be
used to set or read the state of the digital input or output pins
associated with the interface.

AD5370

SYNC

SCLK

SDI

SDO

RESET

LDAC

CLR

BUSY

ADSP-BF531

Figure 23. Interfacing to a Blackfin DSP

SPISELx

SCK

MOSI

MISO

PF10

PF9

PF8

PF7

The Analog Devices ADSP-21065L is a floating point DSP with
two serial ports (SPORTs). Figure 24 shows how one SPORT
ca

n be used to control the AD5370. In this example, the transmit
frame synchronization (TFS) pin is connected to the receive
frame synchronization (RFS) pin. The transmit and receive
clocks (TCLK and RCLK) are also connected together. The user
can write to the AD5370 by writing to the transmit register. A read
operation can be accomplished by first writing to the AD5370
to tell the part that a read operation is required. A second write
operation with an NOP instruction causes the data to be read
from the AD5370. The DSP receive interrupt can be used to
indicate when the read operation is complete.

ADSP-21065L

05813-023

TFSx

RFSx

TCLKx

RCLKx

DTxA

DRxA

FLAG

0

FLAG

1

FLAG

2

FLAG

3

Figure 24. Interfacing to an ADSP-21065L DSP

AD5370

SYNC

SCLK

SDI

SDO

RESET

LDAC

CLR

BUSY

05813-024

Rev. 0 | Page 26 of 28

AD5370

www.BDTIC.com/ADI

OUTLINE DIMENSIONS

49

48

0.60 MAX

EXPOSED PAD

(BOTTOM VIEW)

PIN 1

64

INDICATOR

1

7.25

7.10 SQ

6.95

PIN 1

INDICATOR

9.00

BSC SQ

TOP VIEW

8.75

BSC SQ

0.60

MAX

0.50

BSC

1.00

0.85

0.80

SEATING

PLANE

12° MAX

0.50

0.40

0.30

0.80 MAX

0.65 TYP

0.30

0.23

0.18

COMPLIANT TO JEDEC S TANDARDS MO-220-VMMD-4

0.05 MAX

0.02 NOM

0.20 REF

33

32

7.50
REF

16

17

0.25 MIN

051007-C

Figure 25. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

9 mm × 9 mm Body, Very Thin Quad

(CP-64-3)

Dimensions shown in millimeters

12.20

12.00 SQ

11. 80

PIN 1

TOP VIEW

(PINS DOWN)

0.50

BSC

LEAD PITCH

0.27

0.22

0.17

4964

48

10.20

10.00 SQ

9.80

33

32

1.45

1.40

1.35

0.15

SEATING

0.05

PLANE

VIEW A

ROTATED 90° CCW

0.75

0.60

0.45

0.20

0.09
7°

3.5°
0°

0.08
COPLANARIT Y

1.60
MAX

1

16

17

VIEW A

COMPLIANT TO JEDEC STANDARDS MS-026-BCD

Figure 26. 64-Lead Low Profile Quad Flat Package [LQFP]

(ST-64-2)

Dimensions shown in millimeters

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD5370BCPZ −40°C to +85°C
AD5370BCPZ-REEL7 −40°C to +85°C 64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-3
AD5370BSTZ −40°C to +85°C 64-Lead Low Profile Quad Flat Package (LQFP) ST-64-2
AD5370BSTZ-REEL −40°C to +85°C 64-Lead Low Profile Quad Flat Package (LQFP) ST-64-2

1

Z = RoHS Compliant Part.

1

1

1

1

64-Lead Lead Frame Chip Scale Package (LFCSP_VQ) CP-64-3

Rev. 0 | Page 27 of 28

051706-A

AD5370

www.BDTIC.com/ADI

NOTES

© 2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.

D05813-0-4/08(0)

Rev. 0 | Page 28 of 28