Datasheet AD5360 Datasheet (ANALOG DEVICES)

16-Channel, 16-/14-Bit,

VDDV

www.BDTIC.com/ADI

FEATURES

16-channel DAC in 52-lead LQFP and 56-lead LFCSP

packages
Guaranteed monotonic to 16/14 bits
Nominal output voltage range of −10 V to +10 V
Multiple output spans available
Temperature monitoring function
Channel monitoring multiplexer
GPIO function
System calibration function allowing user-programmable

offset and gain
Channel grouping and addressing features
Data error checking feature

FUNCTIONAL BLOCK DIAGRAM

8

TO
MUX 2s

n

n

n

n

n

A/B

n

n

8

n

n

MUX

n

·

n

n

n

·

·

·

·

·

n

TO
MUX 2s

n

·

·

·

·

·

·

n

A/B
MUX

A/B
MUX

A/B
MUX

·

·

·

·

·

·

·

·

·

·

·

·

·

·

·

·

·

·

·

·

·

·

·

·

TEMP_OUT

PEC

MON_IN0

MON_IN1

MON_OUT

GPIO

BIN/2S COMP

SYNC

SDI

SCLK

SDO

BUSY

RESET

CLR

DV

TEMP

SENSOR

CONTROL
REGISTER

VOUT0 TO
VOUT15

MUX

GPIO

REGISTER

SERIAL

INTERFACE

STATE

MACHINE

AD5360/

AD5361

CC

8

6

2

n

AGND DGND LDAC

SS

n = 16 FOR AD5360
n = 14 FOR AD5361

8

A/B SELECT

REGISTER

n

X1 REGISTER

n

M REGISTER

n

C REGIST ER

·

·

·

·

·

·

n

X1 REGISTER

n

M REGISTER

n

C REGIST ER

8

A/B SELECT

REGISTER

n

X1 REGISTER

n

M REGISTER

n

C REGIST ER

·

·

·

·

·

·

n

X1 REGISTER

n

M REGISTER

n

C REGIST ER

X2A REGISTER

X2B REGISTER

·

·

·

·

·

X2A REGISTER

X2B REGISTER

X2A REGISTER

X2B REGISTER

·

·

·

·

·

·

X2A REGISTER

X2B REGISTER

Figure 1.

Serial Input, Voltage-Output DAC

AD5360/AD5361

SPI-compatible serial interface

2.5 V to 5.5 V digital interface

OFS0

DAC 0

·

·

·

·

·

·

DAC 7

OFS1

DAC 0

·

·

·

·

·

DAC 7

RESET

14

n

n

n

n

n

OFFSET

DAC 0

DAC 0

·

·

·

·

·

·

DAC 7

OFFSET

DAC 1

DAC 0

·

·

·

·

·

·

DAC 7

)

VREF0

VOUT0

VOUT1

VOUT2

VOUT3

VOUT4

VOUT5

VOUT6

VOUT7

SIGGND0

VREF1

VOUT8

VOUT9

VOUT10

VOUT11

VOUT12

VOUT13

VOUT14

VOUT15

SIGGND1

05761-007

BUFFER

BUFFER

BUFFER

GROUP 0

OUTPUT BUFFER

AND POWER-

DOWN CONTROL

·

·

·

·

·

·

OUTPUT BUFFER

AND POWER-

DOWN CONTROL

GROUP 1

OUTPUT BUFFER

AND POWER-

DOWN CONTROL

·

·

·

·

·

·

OUTPUT BUFFER

AND POWER-

DOWN CONTROL

Digital reset (
Clear function to user-defined SIGGNDx
Simultaneous update of DAC outputs

APPLICATIONS

Instrumentation
Industrial control systems
Level setting in automatic test equipment (ATE)
Variable optical attenuators (VOA)
Optical line cards

14

REGISTER

n

MUX

REGISTER

2

·

·

·

·

·

n

MUX

2

REGISTER

14

REGISTER

n

MUX

REGISTER

2

·

·

·

·

·

·

n

MUX

REGISTER

2

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] ©2007–2008 Analog Devices, Inc. All rights reserved.

AD5360/AD5361

www.BDTIC.com/ADI

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

General Description ......................................................................... 3

Specifications ..................................................................................... 4

AC Characteristics ........................................................................ 5

Timing Characteristics ................................................................ 6

Absolute Maximum Ratings ............................................................ 9

ESD Caution .................................................................................. 9

Pin Configuration and Function Descriptions ........................... 10

Typical Performance Characteristics ........................................... 12

Terminology .................................................................................... 14

Functional Description .................................................................. 15

DAC Architecture ....................................................................... 15

Channel Groups .......................................................................... 15

A

/B Registers Gain/Offset Adjustment ................................... 16

Offset DACs ................................................................................ 16

Output Amplifier ........................................................................ 17

Transfer Function ....................................................................... 17

Reference Selection .................................................................... 17

Calibration ................................................................................... 18

Reset Function ............................................................................ 19

Clear Function ............................................................................ 19

BUSY
BIN

Temperature Sensor ................................................................... 19

Monitor Function ....................................................................... 20

GPIO Pin ..................................................................................... 20

Power-Down Mode .................................................................... 20

Thermal Monitoring Function ................................................. 20

Toggle Mode ................................................................................ 20

Serial Interface ................................................................................ 21

SPI Write Mode .......................................................................... 21

SPI Readback Mode ................................................................... 22

Register Update Rates ................................................................ 22

Packet Error Checking ............................................................... 22

Channel Addressing and Special Modes ................................. 23

Special Function Mode .............................................................. 24

Power Supply Decoupling ......................................................... 25

Power Supply Sequencing ......................................................... 25

Interfacing Examples ...................................................................... 26

Outline Dimensions ....................................................................... 27

Ordering Guide .......................................................................... 27

LDAC

and

/2SCOMP PIN ..................................................................... 19

Functions...................................................... 19

REVISION HISTORY

2/08—Rev. 0 to Rev. A

Added LFCSP Package ....................................................... Universal

Change to DC Crosstalk Parameter ............................................... 4

Change to Power Dissipation Unloaded (P) Parameter .............. 5

Added t

Change to Figure 4 ........................................................................... 7

Change to Table 5 Summary ........................................................... 9

Added Figure 8 ................................................................................ 10

Changes to Table 6 .......................................................................... 10

Changes to Calibration Section .................................................... 18

Changes to Reset Function Section .............................................. 19

Added Packet Error Checking Section ........................................ 22

Updated Outline Dimensions ....................................................... 27

Changes to Ordering Guide .......................................................... 27

10/07—Revision 0: Initial Version

Parameter ......................................................................... 6

23

Rev. A | Page 2 of 28

AD5360/AD5361

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GENERAL DESCRIPTION

The AD5360/AD5361 contain sixteen, 16-/14-bit DACs in a
single 52-lead LQFP or 56-lead LFCSP package. They provide
buffered voltage outputs with a span four times the reference
voltage. The gain and offset of each DAC can be independently
trimmed to remove errors. For even greater flexibility, the device is
divided into two groups of eight DACs, and the output range of
each group can be independently adjusted by an offset DAC.

The AD5360/AD5361 offer guaranteed operation over a wide
supply range with V
+8 V to +16.5 V. The output amplifier headroom requirement
is 1.4 V.

from −4.5 V to −16.5 V and VDD from

SS

The AD5360/AD5361 have a high speed 4-wire serial interface,
which is compatible with SPI, QSPI™, MICROWIRE™, and DSP

interface standards and can handle clock speeds of up to
50 MHz. All the outputs can be updated simultaneously by
taking the
gain register and an offset adjust register.

Each DAC output is amplified and buffered on-chip with
respect to an external SIGGNDx input. The DAC outputs can
also be switched to SIGGNDx via the

LDAC

input low. Each channel has a programmable

CLR

pin.

Rev. A | Page 3 of 28

AD5360/AD5361

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SPECIFICATIONS

DVCC = 2.5 V to 5.5 V; VDD = 9 V to 16.5 V; VSS = −16.5 V to −4.5 V; V
gain (M), offset (C), and DAC offset registers at default value; all specifications T

Table 1.

Parameter B Version1Unit Test Conditions/Comments

ACCURACY

Resolution

AD5360 16 Bits
AD5361 14 Bits

Relative Accuracy

AD5360 ±4 LSB max

AD5361 ±1 LSB max
Differential Nonlinearity ±1 LSB max Guaranteed monotonic by design over temperature
Zero-Scale Error ±15 mV max Before calibration
Full-Scale Error ±20 mV max Before calibration
Gain Error 0.1 % FSR Before calibration
Zero-Scale Error
Full-Scale Error
Span Error of Offset DAC ±75 mV max
VOUTx3 Temperature Coefficient 5 ppm FSR/°C typ Includes linearity, offset, and gain drift
DC Crosstalk4 180 μV max Typically 20 μV; measured channel at midscale, full-scale

REFERENCE INPUTS (VREF0, VREF1)

VREF Input Current ±10 μA max Per input; typically ±30 nA
VREF Range

SIGGND INPUT (SIGGND0 to SIGGND1)4

DC Input Impedance 50 kΩ min Typically 55 kΩ
Input Range ±0.5 V max
SIGGND Gain 0.995/1.005 Min/max

OUTPUT CHARACTERISTICS

Output Voltage Range VSS + 1.4 V min I
V
Nominal Output Voltage Range −10 to +10 V nominal
Short-Circuit Current 15 mA max VOUTx3 to DVCC, VDD, or VSS
Load Current ±1 mA max
Capacitive Load 2200 pF max
DC Output Impedance 0.5 Ω max

MONITOR PIN (MON_OUT)

Output Impedance

DAC Output at Positive Full-Scale 1000 Ω typ

DAC Output at Negative Full-Scale 500 Ω typ
Three-State Leakage Current 100 nA typ
Continuous Current Limit 2 mA max

DIGITAL INPUTS JEDEC compliant

Input High Voltage 1.7 V min DVCC = 2.5 V to 3.6 V

2.0 V min DV
Input Low Voltage 0.8 V max DVCC = 2.5 V to 5.5 V
Input Current ±1 μA max
±20 μA max

Input Capacitance

2

2

1 LSB typ After calibration

2

2

2/5 V min/max ±2% for specified operation

2

4

4

1 LSB typ After calibration

− 1.4 V max I

DD

10 pF max

= 5 V; AGND = DGND = SIGGND = 0 V; RL = open circuit;

REF

to T

MIN

See the

, unless otherwise noted.

MAX

Offset DACS section for details

change on any other channel

= 1 mA

LOAD

= 1 mA

LOAD

= 3.6 V to 5.5 V

CC

RESET

SYNC

,

, SDI, and SCLK pins

CLR

BIN

,

/2SCOMP, and GPIO pins

Rev. A | Page 4 of 28

AD5360/AD5361

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Parameter B Version1Unit Test Conditions/Comments

DIGITAL OUTPUTS (SDO,

BUSY

, GPIO,

PEC

Output Low Voltage 0.5 V max Sinking 200 μA
Output High Voltage (SDO) DVCC − 0.5 V min Sourcing 200 μA
High Impedance Leakage Current ±5 μA max SDO only
High Impedance Output Capacitance

TEMPERATURE SENSOR (TEMP_OUT)

4

4

Accuracy ±1 °C typ @ 25°C
±5 °C typ −40°C < T < +85°C
Output Voltage at 25°C 1.46 V typ
Output Voltage Scale Factor 4.4 mV/°C typ
Output Load Current 200 μA max Current source only
Power-On Time 10 ms typ To within ±5°C

POWER REQUIREMENTS

DVCC 2.5/5.5 V min/max
VDD 8/16.5 V min/max
VSS −4.5/−16.5 V min/max
Power Supply Sensitivity

4

∆ Full Scale/∆ VDD −75 dB typ
∆ Full Scale/∆ VSS −75 dB typ

∆ Full Scale/∆ DVCC −90 dB typ
DICC 2 mA max VCC = 5.5 V, VIH = DVCC, VIL = GND
IDD 10 mA max Outputs unloaded
ISS 10 mA max Outputs unloaded
Power-Down Mode Bit 0 in the Control Register is 1

DICC 5 μA typ

IDD 35 μA typ

ISS −35 μA typ
Power Dissipation

Power Dissipation Unloaded (P) 245 mW max VSS = −12 V, VDD = +12 V, DVCC = 2.5 V

Junction Temperature 130 °C max TJ = TA + P

1

Temperature range for B version: −40°C to +85°C. Typical specifications are at 25°C.

2

Specifications are guaranteed for a 5 V reference only.

3

VOUTx refers to any of VOUT0 to VOUT15.

4

Guaranteed by design and characterization, not production tested.

)

10 pF typ

TOTAL

× θJA

AC CHARACTERISTICS

DVCC = 2.5 V; VDD = 15 V; VSS = −15 V; V
DAC offset registers at default value; all specifications T

Table 2.

Parameter B Version1Unit Test Conditions/Comments

DYNAMIC PERFORMANCE

1

Output Voltage Settling Time 20 μs typ Full-scale change
30 μs max DAC latch contents alternately loaded with all 0s and all 1s
Slew Rate 1 V/μs typ
Digital-to-Analog Glitch Energy 5 nV-s typ
Glitch Impulse Peak Amplitude 10 mV max
Channel-to-Channel Isolation 100 dB typ VREF0, VREF1 = 2 V p-p, 1 kHz
DAC-to-DAC Crosstalk 10 nV-s typ
Digital Crosstalk 0.2 nV-s typ
Digital Feedthrough 0.02 nV-s typ Effect of input bus activity on DAC output under test
Output Noise Spectral Density @ 10 kHz 250 nV/√Hz typ VREF0 = VREF1 = 0 V

1

Guaranteed by design and characterization, not production tested.

= 5 V; AGND = DGND = SIGGND = 0 V; CL = 200 pF; RL = 10 kΩ; gain (M), offset (C), and

REF

MIN

to T

, unless otherwise noted.

MAX

Rev. A | Page 5 of 28

AD5360/AD5361

T

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TIMING CHARACTERISTICS

DVCC = 2.5 V to 5.5 V; VDD = 9 V to 16.5 V; VSS = −8 V to −16.5 V; V
R

= open circuit; gain (M), offset (C), and DAC offset registers at default values; all specifications T

L

= 5 V; AGND = DGND = SIGGND = 0 V; CL = 200 pF to GND;

REF

MIN

to T

, unless otherwise noted.

MAX

Table 3. SPI Interface (See Figure 4 and Figure 5)

1, 2

Parameter

t

1

Limit at T

MIN

, T

Unit Description

MAX

20 ns min SCLK cycle time
t2 8 ns min SCLK high time
t3 8 ns min SCLK low time
t4 11 ns min
t

5

20 ns min
t6 10 ns min
t

7

5 ns min Data setup time

falling edge to SCLK falling edge setup time

SYNC
Minimum SYNC
24th SCLK falling edge to SYNC

high time

rising edge

t8 5 ns min Data hold time

3

t

9

t

1/1.5 μs typ/max

10

42 ns max

rising edge to BUSY falling edge

SYNC

pulse width low (single-channel update); see Table 8

BUSY
t11 600 ns max Single-channel update cycle time
t12 20 ns min
t13 10 ns min
t14 3 μs max
t15 0 ns min
t16 3 μs max

rising edge to LDAC falling edge

SYNC

pulse width low

LDAC

rising edge to DAC output response time

BUSY

rising edge to LDAC falling edge

BUSY

falling edge to DAC output response time

LDAC
t17 20/30 μs typ/max DAC output settling time
t18 140 ns max
t19 30 ns min
t20 400 μs max
t21 270 ns min

4

t

22

25 ns max SCLK rising edge to SDO valid

t23 80 ns max

1

Guaranteed by design and characterization, not production tested.

2

All input signals are specified with tr = tf = 2 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V.

3

This is measured with the load circuit shown in Figure 2.

4

This is measured with the load circuit shown in Figure 3.

/RESET pulse activation time

CLR

pulse width low

RESET

time indicated by BUSY low

RESET

Minimum SYNC

rising edge to BUSY falling edge

RESET

high time in readback mode

200µA I

DV

CC

R

L

2.2k

TO

OUTPUT

PIN

Figure 2. Load Circuit for

Ω

C

L

50pF

BUSY

Timing Diagram

V

OL

05761-008

Rev. A | Page 6 of 28

O OUTPUT

PIN

C

L

50pF

200µA I

Figure 3. Load Circuit for SDO Timing Diagram

OL

OH

VOH (MIN) – VOL (MAX)

2

5761-009

AD5360/AD5361

V

V

www.BDTIC.com/ADI

t

1

SCLK

SYNC

BUSY

LDAC

OUTx

LDAC

OUTx

SDI

1

1

2

2

1

2

t

3

t

4

t

5

t

7

t

8

DB23

24

t

2

t

6

DB0

t

9

t

1

t

11

t

10

12

t

13

24

t

17

t

14

t

15

t

13

t

17

t

16

CLR

VOUTx

RESET

VOUTx

BUSY

1

LDAC ACTIVE DURING BUSY.

2

LDAC ACTIVE AFTER BUSY.

t

18

t

19

t

18

t

20

t

23

05761-010

Figure 4. SPI Write Timing

Rev. A | Page 7 of 28

AD5360/AD5361

www.BDTIC.com/ADI

SCLK

SYNC

SDI

INPUT WORD SPECIFIES

REGISTER TO BE READ

SDO

t

22

DB0 DB23DB23

LSB FRO M PREVIOUS W RITE

t

21

NOP CONDITI ON

DB0

DB23 DB15

SELECTED REG ISTER DATA CLOCKED OUT

48

DB0

DB0

05761-011

Figure 5. SPI Read Timing

OUTPUT

VOLTAGE

VMAX

ACTUAL
TRANSFER
FUNCTION

IDEAL
TRANSFER
FUNCTION

FULL-SCAL E
ERROR
+
ZERO-SCALE
ERROR

N

– 1

2

n = 16 FOR AD5360
n = 14 FOR AD5361

05761-001

VMIN

0

DAC CODE

ZERO-SCALE
ERROR

Figure 6. DAC Transfer Function

Rev. A | Page 8 of 28

AD5360/AD5361

www.BDTIC.com/ADI

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted. Transient currents of up to
60 mA do not cause SCR latch-up.

Table 4.

Parameter Rating

VDD to AGND −0.3 V to +17 V
VSS to AGND −17 V to +0.3 V
DVCC to DGND −0.3 V to +7 V
Digital Inputs to DGND −0.3 V to DVCC + 0.3 V
Digital Outputs to DGND −0.3 V to DVCC + 0.3 V
VREF0, VREF1 to AGND −0.3 V to +5.5 V
VOUT0 to VOUT15 to AGND VSS − 0.3 V to VDD + 0.3 V
SIGGND0, SIGGND1 to AGND −1 V to +1 V
AGND to DGND −0.3 V to +0.3 V
MON_IN0, MON_IN1, MON_OUT to AGND VSS − 0.3 V to VDD + 0.3 V
Operating Temperature (TA)

Industrial (B Version) −40°C to +85°C
Storage −65°C to +150°C
Junction (TJ max) 130°C

θJA Thermal Impedance

52-Lead LQFP 38°C/W
56-Lead LFCSP 25°C/W

Reflow Soldering

Peak Temperature 230°C
Time at Peak Temperature 10 sec to 40 sec

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. A | Page 9 of 28

AD5360/AD5361

5

T

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PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

22

VOUT1223V

CC

OUT7

DGND46DV

SYNC48SCLK49SDI50PEC51SDO52DV

VOUT6

V

47

45

44

43

42

VOUT5

41

VOUT4

40

SIGGND0

39

VOUT3

38

VOUT2

37

VOUT1

36

VOUT0

35

TEMP_OU

34

MON_IN1

33

VREF0

32

NC

31

NC

30

V

SS

29

V

DD

24

26NC27NC28

NC

OUT13

VOUT1425VOUT15

LDAC

CLR

RESET

BIN/2SCOMP

BUSY

GPIO

MON_OUT

MON_IN0

NC

NC

V

DD

V

SS

VREF1

NC = NO CONNECT

AGND

DVCCSDO

PEC

SDI

SCLK

SYNC

SIGGND1

DVCCDGND

VOUT12

VOUT13

VOUT14

DGND

52 51 50 49 48 43 42 41 4047 46 45 44

1

2

PIN 1
INDICAT OR

3

4

5

6

7

8

9

10

11

12

13

14 15 16 17 18 19 20 21 22 23 24 25 26

NC

VOUT8

(Not to Scale)

VOUT9

VOUT10

AD5360/

AD5361

TOP VIEW

VOUT11

VOUT7VOUT6VOUT

NCNCNC

VOUT15

39

VOUT4

38

SIGGND0

37

VOUT3

36

VOUT2

35

VOUT1

34

VOUT0

33

TEMP_OUT

32

MON_IN1

31

VREF0

30

NC

29

V

SS

28

V

DD

27

NC

CC

GND
D

AGND

LDAC56CLR

53

54

55

PIN 1

1

RESET

BIN/2SCOMP

BUSY

GPIO

MON_OUT

MON_IN0

NC
NC
NC

10

NC

11

NC

12

V

DD

13

V

SS

14

VREF1

NC = NO CONNECT

05761-022

INDICATO R

2
3
4
5
6
7
8
9

15NC16NC17

AD5360/

AD5361

TOP VIEW

(Not to Scale)

19

18

VOUT8

VOUT9

VOUT10

21

20

T11

VOU

SIGGND1

Figure 7. 52-Lead LQFP Pin Configuration Figure 8. 56-Lead LFCSP Pin Configuration

Table 5. LQFP Pin Function Descriptions

Pin No.

LQFP LFCSP

1 55

Mnemonic Description

Load DAC Logic Input (Active Low). See the BUSY and LDAC Functions

LDAC

section for more information.

2 56

Asynchronous Clear Input (Level Sensitive, Active Low). See the Clear

CLR

Func tion section for more information.

3 1
4 2

RESET

/2SCOMP Data Format Digital Input. Connecting this pin to DGND selects offset binary.

BIN

Digital Reset Input.

Connecting this pin to logic 1 selects twos complement. This input has a weak
pull-down.

5 3

Digital Input/Open-Drain Output. BUSY is open drain when it is an output.

BUSY

See the BUSY and LDAC Functions section for more information.

6 4 GPIO

Digital I/O Pin. This pin can be configured as an input or output that can be
read or programmed high or low via the serial interface. When configured as
an input, it has a weak pull-down.

7 5 MON_OUT

Analog Multiplexer Output. Any DAC output, the MON_IN0 input, or the

MON_IN1 input can be switched to this output.
8, 32 6, 34 MON_IN0, MON_IN1 Analog Multiplexer Inputs. Can be switched to MON_OUT.
9, 10, 14, 24, 25,

26, 27, 30

7 to 11, 15, 16,
26 to 28, 31, 32

11, 28 12, 29 VDD

NC No Connect.

Positive Analog Power Supply; +9 V to +16.5 V for specified performance.

These pins should be decoupled with 0.1 μF ceramic capacitors and 10 μF

capacitors.
12, 29 13, 30 VSS

Negative Analog Power Supply; −16.5 V to −8 V for specified performance.

These pins should be decoupled with 0.1 μF ceramic capacitors and 10 μF

capacitors.
13 14 VREF1 Reference Input for DAC 8 to DAC 15. This voltage is referred to AGND.
19 21 SIGGND1

Reference Ground for DAC 8 to DAC 15. VOUT8 to VOUT15 are referenced to

this voltage.
31 33 VREF0 Reference Input for DAC 0 to DAC 7. This voltage is referred to AGND.
33 35 TEMP_OUT

Provides an output voltage proportional to chip temperature. This is typically

1.46 V at 25°C with an output variation of 4.4 mV/°C.

34 to 37, 39 to
42, 15 to 18, 20
to 23

36 to 39, 41 to
44, 17 to 20, 22
to 25

VOUT0 to VOUT15

DAC Outputs. Buffered analog outputs for each of the 16 DAC channels. Each

analog output is capable of driving an output load of 10 kΩ to ground.

Typical output impedance of these amplifiers is 0.5 Ω.

Rev. A | Page 10 of 28

5761-028

AD5360/AD5361

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Pin No.

LQFP LFCSP

38 40 SIGGND0

43, 51 45, 53 DGND

44, 50 46, 52 DVCC

45 47

46 48 SCLK

47 49 SDI

48 50

49 51 SDO

52 54 AGND

EP Connect to VSS Exposed Paddle.

Mnemonic Description

Reference Ground for DAC 0 to DAC 7. VOUT0 to VOUT7 are referenced to
this voltage.

Ground for All Digital Circuitry. Both DGND pins should be connected to the
DGND plane.

Logic Power Supply; 2.5 V to 5.5 V. These pins should be decoupled with 0.1
μF ceramic capacitors and 10 μF capacitors.

Active Low or SYNC Input for SPI Interface. This is the frame synchronization

SYNC

PEC

signal for the SPI serial interface. See , , and the
Interface

Serial Clock Input for SPI Interface. See Figure 4, Figure 5, and the Serial
Interface section for more details.

Serial Data Input for SPI Interface. See Figure 4, Figure 5, and the Serial
Interface section for more details.

Packet Error Check Output. This is an open-drain output with a 50 kΩ pull-up
that goes low if the packet error check fails.

Serial Data Output for SPI Interface. See Figure 4, Figure 5, and the Serial
Interface section for more details.

Ground for All Analog Circuitry. The AGND pin should be connected to the
AGND plane.

section for more details.

Figure 4 Figure 5 Serial

Rev. A | Page 11 of 28

AD5360/AD5361

www.BDTIC.com/ADI

TYPICAL PERFORMANCE CHARACTERISTICS

2

1

0

INL (LSB)

–1

–2

0 65535

16384 32768 49152

DAC CODE

Figure 9. Typical AD5360 INL Plot Figure 12. Digital Crosstalk

1.0

0.5

0

INL ERROR (LSB)

–0.5

VDD = +15V
V
DV
V

= –15V

SS

CC

REF

= +5V

= +3V

0.0050

0.0025

0

AMPLITUDE ( V)

–0.0025

–0.0050

05

05761-012

1.0

0.5

0

DNL (LSB)

–0.5

1234

TIME (µs)

TA = 25°C

= –15V

V

SS

= +15V

V

DD

V

= +4.096V

REF

05761-015

–1.0

08

20 40 60

TEMPERATURE ( °C)

0

05761-013

–1.0

0 65535

Figure 10. Typical INL Error vs. Temperature Figure 13. Typical AD5360 DNL Plot

0

TA = 25°C

= –15V

V

SS

= +15V

V

DD

= +4.096V

V

REF

–0.01

AMPLITUDE ( V)

–0.02

024681

Figure 11. Analog Crosstalk Due to

TIME (µs)

LDAC

0

5761-014

600

500

400

300

200

OUTPUT NOI SE (nV/ √Hz)

100

0

05

Rev. A | Page 12 of 28

16384 32768 49152

DAC CODE

1234

FREQUENCY (Hz)

Figure 14. Noise Spectral Density

05761-016

05761-017

AD5360/AD5361

www.BDTIC.com/ADI

0.50

VSS = –12V

= +12V

V

DD

= +3V

V

REF

0.45

0.40

(mA)

CC

I

0.35

0.30

0.25
–40 80

DVCC = +5.5V

= +2.5V

DV

CC

–20 0 20 6040

TEMPERATURE (° C)

DV

CC

Figure 15. ICC vs. Temperature

8.0

7.5

I

DD

(mA)

7.0

SS

/I

DD

I

6.5

VSS= –12V

VDD = +12V
V

= +3V

REF

6.0
–40 80

–20 0 20 6040

TEMPERATURE ( °C)

I

SS

Figure 16. IDD/ISS vs. Temperature

= +3.6V

6

5

4

3

2

NUMBER OF UNITS

1

0

0.48 0.58

05761-018

0.50 0.52 0.54 0.56

I

(mA)

CC

DVCC = 5V
T

= 25°C

A

05761-021

Figure 18. Typical ICC Distribution

2.0

1.9

1.8

1.7

1.6

1.5

1.4

VOLTAGE (V)

1.3

1.2

1.1

1.0
–40 –25 –10 5 20 35 50 65 80

05761-019

TEMPERATURE (°C)

05761-027

Figure 19. TEMP_OUT Voltage vs. Temperature

14

12

10

8

6

NUMBER OF UNIT S

4

2

0

7.00 7.25 7.50

Figure 17. Typical IDD Distribution

IDD (mA)

V

= 15V

DD

V

= 15V

SS

T

= 25°C

A

7.75 8.00

5761-020

1.0

FULL-SCALE

0.5

MIDSCALE

ZERO-SCALE

0

VOUTx – MON_OUT (V)

–0.5

–1.0

–1.0 1.0

–0.5 0 0.5

MON_OUT CURRENT (mA)

Figure 20. (VOUTx − MON_OUT Voltage) vs. MON_OUT Current

05761-026

Rev. A | Page 13 of 28

AD5360/AD5361

www.BDTIC.com/ADI

TERMINOLOGY

Integral Nonlinearity (INL)

Integral nonlinearity, or relative accuracy, is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
adjusting for zero-scale error and full-scale error and is
expressed in least significant bits (LSB).

Differential Nonlinearity (DNL)

Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of 1 LSB maximum
ensures monotonicity.

Zero-Scale Error

Zero-scale error is the error in the DAC output voltage when all
0s are loaded into the DAC register.

Zero-scale error is a measure of the difference between VOUT
(actual) and VOUT (ideal), expressed in millivolts, when the
channel is at its minimum value. Zero-scale error is mainly due
to offsets in the output amplifier.

Full-Scale Error

Full-scale error is the error in DAC output voltage when all 1s
are loaded into the DAC register.

Full-scale error is a measure of the difference between VOUT
(actual) and VOUT (ideal), expressed in millivolts, when
the channel is at its maximum value. It does not include zero­scale error.

Gain Error

Gain error is the difference between full-scale error and zero­scale error. It is expressed in millivolts.

Gain Error = Full-Scale Error − Zero-Scale Error

VOUT Temperature Coefficient

This includes output error contributions from linearity, offset,
and gain drift.

DC Output Impedance

DC output impedance is the effective output source resistance.
It is dominated by package lead resistance.

DC Crosstalk

The DAC outputs are buffered by op amps that share common
V

and VSS power supplies. If the dc load current changes in

DD

one channel (due to an update), this can result in a further dc
change in one or more channel outputs. This effect is more
significant at high load currents and reduces as the load
currents are reduced. With high impedance loads, the effect is
virtually immeasurable. Multiple V
provided to minimize dc crosstalk.

and VSS terminals are

DD

Output Voltage Settling Time

The amount of time it takes for the output of a DAC to settle to
a specified level for a full-scale input change.

Digital-to-Analog Glitch Energy

This is the amount of energy injected into the analog output at
the major code transition. It is specified as the area of the glitch
in nV-s. It is measured by toggling the DAC register data between
0x7FFF and 0x8000 (AD5360) or 0x1FFF and 0x2000 (AD5361).

Channel-to-Channel Isolation

Channel-to-channel isolation refers to the proportion of input
signal from the reference input of one DAC that appears at the
output of another DAC operating from another reference. It is
expressed in decibels and measured at midscale.

DAC-to-DAC Crosstalk

DAC-to-DAC crosstalk is the glitch impulse that appears at the
output of one converter due to both the digital change and
subsequent analog output change at another converter. It is
specified in nV-s.

Digital Crosstalk

Digital crosstalk is defined as the glitch impulse transferred to
the output of one converter due to a change in the DAC register
code of another converter and is specified in nV-s.

Digital Feedthrough

When the device is not selected, high frequency logic activity
on the device’s digital inputs can be capacitively coupled both
across and through the device to show up as noise on the
VOUTx pins. It can also be coupled along the supply and
ground lines. This noise is digital feedthrough.

Output Noise Spectral Density

Output noise spectral density is a measure of internally
generated random noise. Random noise is characterized as a
spectral density (voltage per √Hz). It is measured by loading all
DACs to midscale and measuring noise at the output. It is
measured in nV/√Hz.

Rev. A | Page 14 of 28

AD5360/AD5361

www.BDTIC.com/ADI

FUNCTIONAL DESCRIPTION

DAC ARCHITECTURE

The AD5360/AD5361 contain 16 DAC channels and 16 output
amplifiers in a single package. The architecture of a single DAC
channel consists of a 16-bit resistor-string DAC in the case of
the AD5360 and a 14-bit DAC in the case of the AD5361,
followed by an output buffer amplifier. The resistor-string
section is simply a string of resistors, of equal value, from
VREF0 or VREF1 to AGND. This type of architecture
guarantees DAC monotonicity. The 16-/14-bit binary digital
code loaded to the DAC register determines at which node
on the string the voltage is tapped off before being fed into
the output amplifier. The output amplifier multiplies the
DAC output voltage by 4. The nominal output span is 12 V
with a 3 V reference and 20 V with a 5 V reference.

Table 6. AD5360/AD5361 Registers

Register Name Word Length in Bits Description

X1A (group) (channel) 16 (14) Input Data Register A, one for each DAC channel.
X1B (group) (channel) 16 (14) Input Data Register B, one for each DAC channel.
M (group) (channel) 16 (14) Gain trim register, one for each DAC channel.
C (group) (channel) 16 (14) Offset trim register, one for each DAC channel.
X2A (group) (channel) 16 (14)

X2B (group) (channel) 16 (14)

DAC (group) (channel)

OFS0 14 Offset DAC 0 data register, sets offset for Group 0.
OFS1 14 Offset DAC 1 data register, sets offset for Group 1.
Control 5 Control register.
Monitor 6 Monitor enable and configuration register.
GPIO 2 GPIO configuration register.

Output Data Register A, one for each DAC channel. These registers store the final,
calibrated DAC data after gain and offset trimming. They are not readable or directly
writable.

Output Data Register B, one for each DAC channel. These registers store the final,
calibrated DAC data after gain and offset trimming. They are not readable or directly
writable.

Data registers from which the DACs take their final input data. The DAC registers are
updated from the X2A or X2B registers. They are not readable or directly writable.

CHANNEL GROUPS

The 16 DAC channels of the AD5360/AD5361 are arranged into
two groups of eight channels. The eight DACs of Group 0 derive
their reference voltage from VREF0. Group 1 derives its refer­ence voltage from VREF1. Each group has its own signal
ground pin.

Table 7. AD5360/AD5361 Input Register Default Values

Register Name AD5360 Default Value AD5361 Default Value

X1A, X1B 0x8000 0x2000
M 0xFFFF 0x3FFF
C 0x8000 0x2000
OFS0, OFS1 0x2000 0x2000
Control 0x00 0x00
A/B Select 0 and A/B Select 1

0x00 0x00

Rev. A | Page 15 of 28

AD5360/AD5361

www.BDTIC.com/ADI

A/B REGISTERS GAIN/OFFSET ADJUSTMENT

Each DAC channel has seven data registers. The actual DAC
data word can be written to either the X1A or X1B input
register, depending on the setting of the

register. If the

A

the

/B bit is 1, data is written to the X1B register. Note that

A

/B bit is 0, data is written to the X1A register. If

A

/B bit in the control

this single bit is a global control and affects every DAC channel
in the device. It is not possible to set up the device on a per­channel basis so that some writes are to the X1A register and
some writes are to the X1B register.

X1A

REGIS TER

X1B

REGIS TER

REGIS TER

REGIS TER

Figure 21. Data Registers Associated with Each DAC Channel

MUX

M

C

X2A

REGISTER

X2B

REGISTER

MUX

DAC

REGISTER

DAC

Each DAC channel also has a gain register (M) and an offset (C)
register, which allow trimming out of the gain and offset errors
of the entire signal chain. Data from the X1A register is oper­ated on by a digital multiplier and adder by the contents of the
M and C registers. The calibrated DAC data is then stored in the
X2A register. Similarly, data from the X1B register is operated
on by the multiplier and adder and stored in the X2B register.

Although a multiplier and adder symbol are shown for each
channel, there is only one multiplier and one adder in the
device, which are shared among all channels. This has
implications for the update speed when several channels are
updated at once, as described in the Register Update Rates
section.

Each time data is written to the X1A register, or to the M or
C register with the

A

/B control bit set to 0, the X2A data is
recalculated and the X2A register is automatically updated.
Similarly, X2B is updated each time data is written to X1B, or
to M or C with

A

/B set to 1. The X2A and X2B registers are

not readable or directly writable by the user.
Data output from the X2A and X2B registers is routed to the

final DAC register by a multiplexer. An 8-bit

A

/B select register
associated with each group of eight DACs controls whether
each individual DAC takes its data from the X2A or X2B
register. If a bit in this register is 0, the DAC takes its data
from the X2A register; if 1, the DAC takes its data from the
X2B register (Bit 0 through Bit 7 control DAC 0 through
DAC 7, respectively).

Note that because there are 16 bits in two registers, it is possible
to set up, on a per-channel basis, whether each DAC takes its
data from the X2A register or X2B register. A global command
is also provided that sets all bits in the

A

/B select registers to 0

or to 1.

05761-023

All DACs in the AD5360/AD5361 can be updated simultane­ously by taking

LDAC

low, when each DAC register is updated

from either its X2A or X2B register, depending on the setting of

A

the

/B select registers. The DAC register is not readable or

directly writable by the user.

OFFSET DACs

In addition to the gain and offset trim for each DAC, there are
two 14-bit offset DACs, one for Group 0, and one for Group 1.
These allow the output range of all DACs connected to them to
be offset within a defined range. Thus, subject to the limitations
of headroom, it is possible to set the output range of Group 0
and/or Group 1 to be unipolar positive, unipolar negative, or
bipolar (either symmetrical or asymmetrical) about 0 V. The
DACs in the AD5360/AD5361 are factory trimmed with the
offset DACs set at their default values. This gives the best offset
and gain performance for the default output range and span.

When the output range is adjusted by changing the value of
the offset DAC, an extra offset is introduced due to the gain
error of the offset DAC. The amount of offset is dependent on
the magnitude of the reference and how much the offset DAC
moves from its default value. This offset is shown in Table 1. The
worst-case offset occurs when the offset DAC is at positive full
scale or negative full scale. This value can be added to the offset
present in the main DAC of a channel to give an indication of
the overall offset for that channel. In most cases, the offset can be
removed by programming the C register of the channel with an
appropriate value. The extra offset caused by the offset DACs
needs to be taken into account only when the offset DAC is
changed from its default value. Figure 22 shows the allowable
code range that can be loaded to the offset DAC, and this is
dependent on the reference value used. Thus, for a 5 V
reference, the offset DAC should not be programmed with
a value greater than 8192 (0x2000).

5

4

3

)
V

(
F

E
R
V

2

1

0

0 4096 8192 12288 16 383

OFFSET DAC CODE

Figure 22. Offset DAC Code Range

RESERVED

5761-005

Rev. A | Page 16 of 28

AD5360/AD5361

S

www.BDTIC.com/ADI

OUTPUT AMPLIFIER

Because the output amplifiers can swing to 1.4 V below the
positive supply and 1.4 V above the negative supply, this limits
how much the output can be offset for a given reference voltage.
For example, it is not possible to have a unipolar output range of
20 V because the maximum supply voltage is ±16.5 V.

S1

OUTPUT

S2

CLR

R6
10kΩ

S3

SIGGND

CLR

05761-006

IGGND

DAC

CHANNEL

R5

60kΩ

R1

20kΩ

CLR

R4

R3

60kΩ

20kΩ

OFFSET

DAC

Figure 23. Output Amplifier and Offset DAC

R2
20kΩ

Figure 23 shows details of a DAC output amplifier and its
connections to the offset DAC. On power-up, S1 is open,
disconnecting the amplifier from the output. S3 is closed, so
the output is pulled to SIGGND. S2 is also closed to prevent
the output amplifier from being open-loop. If
power-up, the output remains in this condition until

CLR

is low at

CLR

is
taken high. The DAC registers can be programmed, and the
outputs assume the programmed values when
high. Even if
in this condition until V

CLR

is high at power-up, the output remains

> 6 V and VSS < −4 V and the

DD

CLR

is taken

initialization sequence has finished. The outputs then go to
their power-on default values.

TRANSFER FUNCTION

The output voltage of a DAC in the AD5360/AD5361 is dependent
on the value in the input register, the value of the M and C
registers, and the value in the offset DAC. The transfer functions
for the AD5360/AD5361 are shown in the following sections.

AD5360 Transfer Function

The input code is the value in the X1A or X1B register that is
applied to DAC (X1A, X1B default code = 32,768)

16

– 1.

15

.

16

+ C − 215

DAC_CODE = INPUT_CODE × (M + 1)/2

DAC output voltage

V

= 4 × V

OUT

2

× (DAC_CODE − (OFFSET_CODE × 4))/

REF

16

+ V

SIGGND

where:

DAC_CODE should be within the range of 0 to 65,535.
V

= 3.0 V, for a 12 V span.

REF

V

= 5.0 V, for a 20 V span.

REF

M = code in gain register − default code = 2
C = code in offset register − default code = 2

OFFSET_CODE is the code loaded to the offset DAC. It is
multiplied by 4 in the transfer function because this DAC is a
14-bit device. On power-up, the default code loaded to the
offset DAC is 8192 (0x2000). With a 10 V reference, this gives
a span of −10 V to +10 V.

AD5361 Transfer Function

The input code is the value in the X1A or X1B register that is
applied to DAC (X1A, X1B default code = 8192)

DAC_CODE = INPUT_CODE × (M + 1)/2

14

+ C − 213

DAC output voltage

V

= 4 × V

OUT

V

× (DAC_CODE − OFFSET_CODE)/214 +

REF

SIGGND

where:

DAC_CODE should be within the range of 0 to 16,383.
V

= 3.0 V, for a 12 V span.

REF

= 5.0 V, for a 20 V span.

V

REF

M = code in gain register − default code = 2
C = code in offset register − default code = 2

14

13

− 1.
.

OFFSET_CODE is the code loaded to the offset DAC.
On power-up, the default code loaded to the offset DAC
is 8192 (0x2000). With a 5 V reference, this gives a span of

−10 V to +10 V.

REFERENCE SELECTION

The AD5360/AD5361 have two reference input pins. The
voltage applied to the reference pins determines the output
voltage span on VOUT0 to VOUT15. VREF0 determines the
voltage span for VOUT0 to VOUT7 (Group 0), and VREF1
determines the voltage span for VOUT8 to VOUT15 (Group 1).
The reference voltage applied to each VREF pin can be different,
if required, allowing each group of eight channels to have a
different voltage span. The output voltage range and span can
be adjusted by programming the offset register and gain register
for each channel as well as programming the offset DAC. If the
offset and gain features are not used (that is, the M and C
registers are left at their default values), the required reference
levels can be calculated as follows:

VREF = (VOUT

If the offset and gain features of the AD5360/AD5361 are used,
the required output range is slightly different. The chosen
output range should take into account the system offset and
gain errors that need to be trimmed out. Therefore, the chosen
output range should be larger than the actual, required range.

The required reference levels can be calculated as follows:

1. Identify the nominal output range on VOUT.

2. Identify the maximum offset span and the maximum gain

required on the full output signal range.

3. Calculate the new maximum output range on VOUT,

including the expected maximum offset and gain errors.

− VOUT

MAX

MIN

)/4

Rev. A | Page 17 of 28

AD5360/AD5361

www.BDTIC.com/ADI

4. Choose the new required VOUT

the VOUT limits centered on the nominal values. Note that
V

and VSS must provide sufficient headroom.

DD

5. Calculate the value of VREF as follows:

VREF = (VOUT

− VOUT

MAX

MIN

MAX

)/4

and VOUT

, keeping

MIN

Reference Selection Example

Nominal output range = 20 V (−10 V to +10 V)
Offset error = ±100 mV
Gain error = ±3%
SIGGND = AGND = 0 V

Gain error = ±3%

Maximum positive gain error = +3%
Output range including gain error = 20 + 0.03 (20) =

20.6 V

Offset error = ±100 mV

Maximum offset error span = 2 (100 mV) = 0.2 V
Output range including gain error and offset error =

20.6 V + 0.2 V = 20.8 V

VREF calculation

Actual output range = 20.6 V, that is, −10.3 V to +10.3 V

(centered);

VREF = (10.3 V + 10.3 V)/4 = 5.15 V

If the solution yields an inconvenient reference level, the user
can adopt one of the following approaches:

• Use a resistor divider to divide down a convenient, higher

reference level to the required level.

• Select a convenient reference level above VREF and modify

the gain and offset registers to digitally downsize the
reference. In this way, the user can use almost any conven­ient reference level but may reduce the performance by
overcompaction of the transfer function.

• Use a combination of these two approaches.

CALIBRATION

The user can perform a system calibration on the AD5360 and
AD5361 to reduce gain and offset errors to below 1 LSB. This is
achieved by calculating new values for the M and C registers and
reprogramming them.

Reducing Zero-Scale and Full-Scale Error

Zero-scale error can be reduced as follows:

1. Set the output to the lowest possible value.

2. Measure the actual output voltage and compare it with the

required value. This gives the zero-scale error.

3. Calculate the number of LSBs equivalent to the error and

add this from the default value of the C register. Note that
only negative zero-scale error can be reduced.

Full-scale error can be reduced as follows:

1. Measure the zero-scale error.

2. Set the output to the highest possible value.

3. Measure the actual output voltage and compare it with the

required value. Add this error to the zero-scale error. This
is the span error, which includes full-scale error.

4. Calculate the number of LSBs equivalent to the span error

and subtract it from the default value of the M register.
Note that only positive full-scale error can be reduced.

The M and C registers should not be programmed until both
zero-scale errors and full-scale errors have been calculated.

AD5360 Calibration Example

This example assumes that a −10 V to +10 V output is required.
The DAC output is set to −10 V but is measured at −10.03 V.
This gives a zero-scale error of −30 mV.

1 LSB = 20 V/65,536 = 305.176 μV
30 mV = 98 LSBs

The full-scale error can now be removed. The output is set
to +10 V, and a value of +10.02 V is measured. The full-scale
error is +20 mV. The span error is +20 mV − (−30 mV) =
+50 mV.

+50 mV = 164 LSBs

The errors can now be removed.

1. 98 LSBs should be added to the default C register value;

(32,768 + 98) = 32,866.

2. 32,866 should be programmed to the C register.

3. 164 LSBs should be subtracted from the default M register

value; (65,535 − 164) = 65,371.

4. 65,371 should be programmed to the M register.

Additional Calibration

The techniques described in the previous section are usually
enough to reduce the zero-scale errors and full-scale errors in
most applications. However, there are limitations whereby the
errors may not be sufficiently removed. For example, the offset
(C) register can only be used to reduce the offset caused by the
negative zero-scale error. A positive offset cannot be reduced.
Likewise, if the maximum voltage is below the ideal value, that
is, a negative full-scale error, the gain (M) register cannot be
used to increase the gain to compensate for the error.

These limitations can be overcome by increasing the refer­ence value. With a 2.5 V reference, a 10 V span is achieved.
The ideal voltage range, for the AD5360 or AD5361, is

−5 V to +5 V. Using a 2.6 V reference increases the range
to −5.2 V to +5.2 V. Clearly, in this case, the offset and gain
errors are insignificant and the M and C registers can be
used to raise the negative voltage to −5 V and then reduce
the maximum voltage down to +5 V to give the most
accurate values possible.

Rev. A | Page 18 of 28

AD5360/AD5361

www.BDTIC.com/ADI

RESET FUNCTION

The reset function is initiated by the

RESET

edge of
reset sequence to reset the X, M, and C registers to their default
values. This sequence typically takes 300 μs, and the user should
not write to the part during this time. On power-up, it is recom­mended that the user bring
properly initialize the registers.

When the reset sequence is complete (and provided that
high), the DAC output is at a potential specified by the default
register settings, which are equivalent to SIGGNDx. The DAC
outputs remain at SIGGNDx until the X, M, or C register is
updated and
returned to the default state by pulsing
30 ns. Note that, because the reset function is rising edge trig­gered, bringing
the AD5360/AD5361.

, the AD5360/AD5361 state machine initiates a

RESET

LDAC

is taken low. The AD5360/AD5361 can be

RESET

low has no effect on the operation of

RESET

pin. On the rising

high as soon as possible to

CLR

RESET

low for at least

is

CLEAR FUNCTION

CLR

is an active low input that should be high for normal
operation. The
resistor. When
buffer stages (VOUT0 to VOUT15) is switched to the externally
set potential on the relevant SIGGNDx pin. While

LDAC

all
DAC outputs return to their previous values. The contents of
input registers and DAC Register 0 to DAC Register 15 are not
affected by taking
the outputs,
span is adjusted by writing to the offset DAC.

CLR

pin has an internal 500 kΩ pull-down

CLR

is low, the input to each of the DAC output

pulses are ignored. When

CLR

low. To prevent glitches appearing on

CLR

should be brought low whenever the output

CLR

CLR

is taken high again, the

is low,

BUSY AND LDAC FUNCTIONS

The value of an X2 (A or B) register is calculated each time the
user writes new data to the corresponding X1, C, or M register.
During the calculation of X2, the
BUSY

is low, the user can continue writing new data to the X1,
M, or C register (see the Register Update Rates section for more
details), but no DAC output updates can take place.

BUSY

The
resistor. When multiple AD5360 or AD5361 devices may be
used in one system, the
useful when it is required that no DAC in any device be updated
until all other DACs are ready. When each device has finished
updating the X2 (A or B) register, it releases the
another device has not finished updating its X2 registers, it
holds

The DAC outputs are updated by taking the
LDAC

and the DAC outputs update immediately after
high. A user can also hold the
this case, the DAC outputs update immediately after

pin is bidirectional and has a 50 kΩ internal pull-up

BUSY

BUSY

low, thus delaying the effect of

goes low while

BUSY

BUSY

output goes low. While

pins can be tied together. This is

BUSY

pin. If

LDAC

going low.

LDAC

input low. If

is active, the

LDAC

LDAC

event is stored

BUSY

goes

input permanently low. In

BUSY

goes

high. Whenever the
also goes low, for approximately 600 ns.

The AD5360/AD5361 have flexible addressing that allows
writing of data to a single channel, all channels in a group, the
same channel in Group 0 and Group 1, or all channels in the
device. This means that 1, 2, 8, or 16 DAC register values may
need to be calculated and updated. Because there is only one
multiplier shared among 16 channels, this task must be done
sequentially, so the length of the
the number of channels being updated.

Table 8.

Action

Loading Input, C, or M to 1 Channel2 1.5 μs maximum
Loading Input, C, or M to 2 Channels 2.1 μs maximum
Loading Input, C, or M to 8 Channels 5.7 μs maximum
Loading Input, C, or M to 16 Channels 10.5 μs maximum

1

2

A single channel update is typically 1 μs.

The AD5360/AD5361 contain an extra feature whereby a DAC
register is not updated unless its X2A or X2B register has been
written to since the last time
when
the contents of the X2A or X2B registers, depending on the
setting of the
AD5361 update the DAC register only if the X2A or X2B data has
changed, thereby removing unnecessary digital crosstalk.

BUSY

BUSY

pulse width = ((number of channels + 1) × 600 ns) + 300 ns.

LDAC

A

/B select registers are written to,

BUSY

pulse varies according to

Pulse Widths

BUSY

LDAC

was brought low. Normally,

is brought low, the DAC registers are filled with

A

/B select register. However, the AD5360/

BIN/2SCOMP PIN

BIN

The
as offset binary or twos complement. If this pin is low, the data
is straight binary. If it is high, the data is twos complement. This
affects only the X, C, and offset DAC registers; the M register
and the control and command data are interpreted as straight
binary.

/2SCOMP pin determines if the output data is presented

TEMPERATURE SENSOR

The on-chip temperature sensor provides a voltage output
at the TEMP_OUT pin that is linearly proportional to the
Centigrade temperature scale. The typical accuracy of the
temperature sensor is ±1°C at +25°C and ±5°C over the −40°C
to +85°C range. Its nominal output voltage is 1.46 V at +25°C,
varying at 4.4 mV/°C. Its low output impedance, low self­heating, and linear output simplify interfacing to temperature
control circuitry and analog-to-digital converters.

BUSY

Pulse Width1

Rev. A | Page 19 of 28

AD5360/AD5361

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MONITOR FUNCTION

The AD5360/AD5361 contain a channel monitor function
that consists of an analog multiplexer addressed via the serial
interface, allowing any channel output to be routed to this pin
for monitoring using an external ADC. In addition, two monitor
inputs, MON_IN0 and MON_IN1, are provided, which can also
be routed to MON_OUT. The monitor function is controlled by
the monitor register, which allows the monitor output to be
enabled or disabled, and selection of a DAC channel or one of
the monitor pins. When disabled, the monitor output is high
impedance, so several monitor outputs can be connected in
parallel and only one enabled at a time. Table 9 shows the
control register settings relevant to the monitor function.

Table 9. Control Register Monitor Functions

F5 F4 F3 F2 F1 F0 Function

0 X X X X X MON_OUT disabled
1 X X X X X MON_OUT enabled
1 0 0 0 0 0 MON_OUT = VOUT0
1 0 0 0 0 1 MON_OUT = VOUT1
1 0 1 1 1 1 MON_OUT = VOUT15
1 1 0 0 0 0 MON_OUT = MON_IN0
1 1 0 0 0 1 MON_OUT = MON_IN1

The multiplexer is implemented as a series of analog switches.
Because this could conceivably cause a large amount of current
to flow from the input of the multiplexer, that is, VOUTx or
MON_INx to the output of the multiplexer, MON_OUT, care
should taken to ensure that whatever is connected to the
MON_OUT pin is of high enough impedance to prevent the
continuous current limit specification from being exceeded.
Because the MON_OUT pin is not buffered, the amount of
current drawn from this pin creates a voltage drop across the
switches, which in turn leads to an error in the voltage being
monitored. Where accuracy is important, it is recommended
that the MON_OUT pin be buffered. Figure 20 shows the
typical error due to the MON_OUT current

GPIO PIN

The AD5360/AD5361 have a general-purpose I/O pin, GPIO.
This can be configured as an input or an output and read back
or programmed (when configured as an output) via the serial
interface. Typical applications for this pin include monitoring
the status of a logic signal, monitoring a limit switch, or
controlling an external multiplexer. The GPIO pin is configured
by writing to the GPIO register, which has the special function
code of 001101 (see Tabl e 14 and Ta ble 1 5 ). When Bit F1 is set,
the GPIO pin becomes an output and F0 determines whether
the pin is high or low. The GPIO pin can be set as an input by
writing 0 to both F1 and F0. The status of the GPIO pin can be
determined by initiating a read operation using the appropriate
bits in Tab le 16. The status of the pin is indicated by the LSB of
the register read.

POWER-DOWN MODE

The AD5360/AD5361 can be powered down by setting Bit 0 in
the control register to 1. This turns off the DACs, thus reducing
the current consumption. The DAC outputs are connected to
their respective SIGGND potentials. The power-down mode
does not change the contents of the registers, and the DACs
return to their previous voltage when the power-down bit is
cleared to 0.

THERMAL MONITORING FUNCTION

The AD5360/AD5361 can be programmed to power down the
DACs if the temperature on the die exceeds 130°C. Setting Bit 1
in the control register to 1 (see Ta bl e 15 ) enables this function.
If the die temperature exceeds 130°C, the AD5360/AD5361
enter a temperature power-down mode, which is equivalent to
setting the power-down bit in the control register. To indicate
that the AD5360/AD5361 have entered temperature shutdown
mode, Bit 4 of the control register is set to 1. The AD5360/AD5361
remain in temperature shutdown mode, even if the die tempera­ture falls, until Bit 1 in the control register is cleared to 0.

TOGGLE MODE

The AD5360/AD5361 have two X2 registers per channel, X2A
and X2B, which can be used to switch the DAC output between
two levels with ease. This approach greatly reduces the overhead
required by a microprocessor, which would otherwise have to
write to each channel individually. When the user writes to
either the X1A, X2A, M, or C register, the calculation engine
takes a certain amount of time to calculate the appropriate X2A
or X2B values. If the application only requires that the DAC
output switch between two levels, such as a data generator, any
method that reduces the amount of calculation time encoun­tered is advantageous. For the data generator example, the user
should set the high and low levels for each channel once, by
writing to the X1A and X1B registers. The values of X2A and
X2B are calculated and stored in their respective registers. The
calculation delay, therefore, only happens during the setup
phase, that is, when programming the initial values. To toggle a
DAC output between the two levels, it is only required to write
to the relevant
Furthermore, because there are eight MUX 2 control bits per
register, it is possible to update eight channels with a single
write. shows the bits that correspond to each DAC

Table 17

output.

A

/B select register to set the MUX 2 register bit.

Rev. A | Page 20 of 28

AD5360/AD5361

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SERIAL INTERFACE

The AD5360/AD5361 contain a high speed SPI operating at
clock frequencies up to 50 MHz (20 MHz for read operations).
To minimize both the power consumption of the device and
on-chip digital noise, the interface powers up fully only when
the device is being written to, that is, on the falling edge of
SYNC

. The serial interface is 2.5 V LVTTL-compatible when
operating from a 2.5 V to 3.6 V DV
four pins:
input), SCLK (clocking of data in and out of the device), and
SDO (serial data output for data readback).

SYNC

(frame synchronization input), SDI (serial data

supply. It is controlled by

CC

SPI WRITE MODE

The AD5360/AD5361 allow writing of data via the serial inter­face to every register directly accessible to the serial interface,
which are all registers except the X2A, X2B, and DAC registers.
The X2A and X2B registers are updated when writing to the
X1A, X1B, M, and C registers, and the DAC registers are
updated by
is 24 bits long; 16 or 14 of these bits are data bits, six bits are
address bits, and two bits are mode bits that determine what
is done with the data. Two bits are reserved on the AD5361.

LDAC

. The serial word (see or )

Table 1 0 Tabl e 11

The serial interface works with both a continuous and a burst
(gated) serial clock. Serial data applied to SDI is clocked into
the AD5360/AD5361 by clock pulses applied to SCLK. The first
falling edge of
clock edges must be applied to SCLK to clock in 24 bits of data,
before
the 24th falling clock edge, the write operation is aborted.

If a continuous clock is used,
the 25th falling clock edge. This inhibits the clock within the
AD5360/AD5361. If more than 24 falling clock edges are
applied before
corrupted. If an externally gated clock of exactly 24 pulses is

SYNC

used,
clock edge.

The input register addressed is updated on the rising edge of
SYNC

. For another serial transfer to take place,

taken low again.

SYNC

starts the write cycle. At least 24 falling

SYNC

is taken high again. If

SYNC

is taken high again, the input data is

may be taken high any time after the 24th falling

SYNC

is taken high before

SYNC

must be taken high before

SYNC

must be

Table 10. AD5360 Serial Word Bit Assignation

I23 I22 I21 I20 I19 I18 I17 I16 I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0

M1 M0 A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Table 11. AD5361 Serial Word Bit Assignation

I23 I22 I21 I20 I19 I18 I17 I16 I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I11I0

M1 M0 A5 A4 A3 A2 A1 A0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0

1

I1 and I0 are reserved for future use and should be 0 when writing the serial word. These bits read back as 0.

1

Rev. A | Page 21 of 28

AD5360/AD5361

S

S

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SPI READBACK MODE

The AD5360/AD5361 allow data readback via the serial inter­face from every register directly accessible to the serial interface,
which is all registers except the X2A, X2B, and DAC data
registers. To read back a register, it is first necessary to tell the
AD5360/AD5361 which register is to be read. This is achieved
by writing a word whose first two bits are the Special Function
Code 00 to the device. The remaining bits then determine if the
operation is a readback and which register is to be read back, or
if it is a write to of the special function registers, such as the
control register.

If a readback command is written to a special function register,
data from the selected register is clocked out of the SDO pin
during the next SPI operation. The SDO pin is normally three­stated but becomes driven as soon as a read command is issued.
The pin remains driven until the register’s data is clocked out.
See Figure 5 for the read timing diagram. Note that, due to the
timing requirements of t

(25 ns), the maximum speed of the

22

SPI interface during a read operation should not exceed 20 MHz.

REGISTER UPDATE RATES

The value of the X2A or X2B register is calculated each time the
user writes new data to the corresponding X1, C, or M register.
The calculation is performed by a three-stage process. The first
two stages take approximately 600 ns each, and the third stage
takes approximately 300 ns. When the write to a X1, C, or M
register is complete, the calculation process begins. If the write
operation involves the update of a single DAC channel, the user
is free to write to another register provided that the write
operation does not finish until the first stage calculation is
complete, that is, 600 ns after the completion of the first write
operation. If a group of channels is being updated by a single
write operation, the first stage calculation is repeated for each
channel, taking 600 ns per channel. In this case, the user should
not complete the next write operation until this time has elapsed.

PACKET ERROR CHECKING

To verify that data has been received correctly in noisy environ­ments, the AD5360/AD5361 offer the option of error checking
based on an 8-bit (CRC-8) cyclic redundancy check. The device
controlling the AD5360/AD5361 should generate an 8-bit
checksum using the polynomial C(x) = x
checksum is added to the end of the data word, and 32 data bits
are sent to the AD5360/AD5361 before taking
the AD5360/AD5361 see a 32-bit data frame, they perform the
error check when

SYNC

goes high. If the checksum is valid, the
data is written to the selected register. If the checksum is invalid,
the data is ignored, the packet error check output (
low, and Bit 3 of the control register is set. After reading the
control register, the error flag is cleared automatically and
goes high again.

YNC

SCLK

SDI

YNC

SCLK

SDI

PEC

MSB

D23

MSB

D31

Figure 24. SPI Write with and Without Error Checking

UPDATE ON SYNC HIG H

24-BIT DATA

24-BIT DATA T RANSFER—NO ERRO R CHECKING

UPDATE AFTER S YNC HIGH

ONLY IF ERROR CHECK PASSED

24-BIT DATA

24-BIT DATA TRANSFER WIT H ERROR CHECKING

8

+ x2 + x1 +1. The

SYNC

LSB

D0

LSB

D7 D0

D8

8-BIT CHECKSUM

PEC GOES LOW IF

ERROR CHECK FAIL S

high. If

PEC

) goes

PEC

05761-029

Rev. A | Page 22 of 28

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CHANNEL ADDRESSING AND SPECIAL MODES

If the mode bits are not 00, then the data word D15 to D0
(AD5360) or D13 to D0 (AD5361) is written to the device.
Address Bit A4 to Address Bit A0 determine which channel or
channels is/are written to, while the mode bits determine to
which register (X1A, X1B, C, or M) the data is written, as
shown in Tabl e 10 and Ta ble 1 1. Data is to be written to the
X1A when the
register when the bit is 1.

The AD5360/AD5361 have very flexible addressing that allows
writing of data to a single channel, all channels in a group, the
same channel in Group 0 and Group 1 or all channels in the

Table 13. Group and Channel Addressing

Address Bit A2 to Address Bit A0

000 All groups, all channels Group 0, Channel 0 Group 1, Channel 0 Unused
001 Group 0, all channels Group 0, Channel 1 Group 1, Channel 1 Unused
010 Group 1, all channels Group 0, Channel 2 Group 1, Channel 2 Unused
011 Unused Group 0, Channel 3 Group 1, Channel 3 Unused
100 Unused Group 0, Channel 4 Group 1, Channel 4 Unused
101 Unused Group 0, Channel 5 Group 1, Channel 5 Unused
110 Unused Group 0, Channel 6 Group 1, Channel 6 Unused
111 Unused Group 0, Channel 7 Group 1, Channel 7 Unused

A

/B bit in the control register is 0 or to the X1B

00 01 10 11

device. Tabl e 13 shows all these address modes. It shows which
group(s) and which channel(s) is/are addressed for every
combination of Address Bit A4 to Address Bit A0.

Table 12. Mode Bits

M1 M0 Action

1 1 Write DAC data (X) register
1 0 Write DAC offset (C) register
0 1 Write DAC gain (M) register
0 0

Address Bit A4 to Address Bit A3

Special function, used in combination with other
bits of a word

Rev. A | Page 23 of 28

AD5360/AD5361

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SPECIAL FUNCTION MODE

If the mode bits are 00, then the special function mode is
selected, as shown in Tabl e 14 . Bits I21 to I16 of the serial data
word select the special function, while the remaining bits are

Table 14. Special Function Mode

I23 I22 I21 I20 I19 I18 I17 I16 I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0

0 0 S5 S4 S3 S2 S1 S0 F15 F14 F13 F12 F11 F10 F9 F8 F7 F6 F5 F4 F3 F2 F1 F0

Table 15. Special Function Codes

Special Function Code

Data (F15 to F0) Action S5 S4 S3 S2 S1 S0

0 0 0 0 0 0 0000 0000 0000 0000 NOP.
0 0 0 0 0 1 XXXX XXXX XXXX X [F2:F0] Write control register.

F2 = 1: select Register X1B for input.
F2 = 0: select Register X1A for input.
F1 = 1: enable temperature shutdown.
F1 = 0: disable temperature shutdown.
F0 = 1: soft power-down.
F0 = 0: soft power-up.
0 0 0 0 1 0 XX [F13:F0] Write data in F13 to F0 to OFS0 register.
0 0 0 0 1 1 XX [F13:F0] Write data in F13 to F0 to OFS1 register.
0 0 0 1 0 0 Reserved
0 0 0 1 0 1 See Table 16 Select register for readback.
0 0 0 1 1 0 XXXX XXXX [F7:F0]

0 0 0 1 1 1 XXXX XXXX [F7:F0]
0 0 1 0 0 0 Reserved

0 0 1 0 0 1 Reserved
0 0 1 0 1 0 Reserved
0 0 1 0 1 1 XXXX XXXX [F7:F0]

F7 to F0 = 0: write all 0s (all channels use X2A register).
F7 to F0 = 1: write all 1s (all channels use X2B register).
0 0 1 1 0 0 XXXX XXXX XX [F5:F0]

F4 = 1: monitor input pin selected by F0.

F3 = not used if F4 = 1.
F2 = not used if F4 = 1.
F1 = not used.
F0 = 0: MON_IN0 selected for monitoring (if F4 and F5 = 1).
F0 = 1: MON_IN1 selected for monitoring (if F4 and F5 = 1).
0 0 1 1 0 1 XXXX XXXX XXXX XX [F1:F0] GPIO configure and write.
F1 = 1: GPIO is an output. Data to output is written to F0.
F1 = 0: GPIO is an input. Data can be read from F0 on readback.

data required for execution of the special function, for example
the channel address for data readback.

The codes for the special functions in Table 16 show the
addresses for data readback.

F4 = 1: temperature over 130°C.
F4 = 0: temperature under 130°C.
Read-only bit. This bit should be 0 when writing to the control register.

F3 = 1: PEC
F3 = 0: No PEC
Read-only bit. This bit should be 0 when writing to the control register.

Write data in F7 to F0 to A
Write data in F7 to F0 to A

Block write A

F5 = 1: monitor enable.
F5 = 0: monitor disable.

F4 = 0: monitor DAC channel selected by F3:F0
(0000 = DAC0; 1111 = DAC15).

error.

error. Reserved.

/B Select Register 0.
/B Select Register 1.

/B select registers.

Rev. A | Page 24 of 28

AD5360/AD5361

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Table 16. Address Codes for Data Readback1

F15 F14 F13 F12 F11 F10 F9 F8 F7 Register Read

0 0 0
0 0 1 X1B Register
0 1 0 C Register
0 1 1 M Register
1 0 0 0 0 0 0 0 1 Control Register
1 0 0 0 0 0 0 1 0 OFS0 Data Register
1 0 0 0 0 0 0 1 1 OFS1 Data Register
1 0 0 0 0 0 1 0 0 Reserved
1 0 0 0 0 0 1 1 0

1 0 0 0 0 0 1 1 1
1 0 0 0 0 1 0 0 0 Reserved

1 0 0 0 0 1 0 0 1 Reserved
1 0 0 0 0 1 0 1 0 Reserved
1 0 0 0 0 1 0 1 1 GPIO Read (Data in F0)

1

F6 to F0 are don’t cares for the data readback function.

2

F6 to F0 should be 0 for GPIO read.

Bit F12 to Bit F7 select channel to be read back,

Channel 0 = 001000 to Channel 15 = 010111

Table 17. DACs Selected by A/B Select Registers

1

/B Select

A
Register

0 DAC7 DAC6 DAC5 DAC4 DAC3 DAC2 DAC1 DAC0
1 DAC15 DAC14 DAC13 DAC12 DAC11 DAC10 DAC9 DAC8

1

If the bit is 0, Register X2A is selected. If the bit is 1, Register X2B is selected.

F7 F6 F5 F4 F3 F2 F1 F0

POWER SUPPLY DECOUPLING

In any circuit where accuracy is important, careful considera­tion of the power supply and ground return layout helps to
ensure the rated performance. The printed circuit board on
which the AD5360/AD5361 are mounted should be designed so
that the analog and digital sections are separated and confined
to certain areas of the board. If the AD5360/AD5361 are in a
system where multiple devices require an AGND-to-DGND
connection, the connection should be made at one point only.
The star ground point should be established as close as possible
to the device. For supplies with multiple pins (V
it is recommended to tie these pins together and to decouple
each supply once.

The AD5360/AD5361 should have ample supply decoupling of
10 μF in parallel with 0.1 μF on each supply located as close to
the package as possible, ideally right up against the device. The
10 μF capacitors are the tantalum bead type. The 0.1 μF capaci­tor should have low effective series resistance (ESR) and effective
series inductance (ESI), such as the common ceramic types that
provide a low impedance path to ground at high frequencies, to
handle transient currents due to internal logic switching.

, VDD, DVCC),

SS

Bits

supply line. Fast switching digital signals should be shielded
with digital ground to avoid radiating noise to other parts of the
board and should never be run near the reference inputs. It is
essential to minimize noise on all VREFx lines.

Avoid crossover of digital and analog signals. Traces on
opposite sides of the board should run at right angles to each
other. This reduces the effects of feedthrough through the
board. A microstrip technique is by far the best, but this is not
always possible with a double-sided board. In this technique,
the component side of the board is dedicated to the ground
plane, while signal traces are placed on the solder side.

As is the case for all thin packages, care must be taken to avoid
flexing the package and to avoid a point load on the surface of
this package during the assembly process.

POWER SUPPLY SEQUENCING

When the supplies are connected to the AD5360/AD5361, it is
important that the AGND and DGND pins be connected to the
relevant ground plane before the positive or negative supplies
are applied. In most applications, this is not an issue because the
ground pins for the power supplies are connected to the ground
pins of the AD5360/AD5361 via ground planes. Where the

Digital lines running under the device should be avoided
because these couple noise onto the device. The analog ground
plane should be allowed to run under the AD5360/AD5361 to
avoid noise coupling. The power supply lines of the AD5360/
AD5361 should use as large a trace as possible to provide low

AD5360/AD5361 are used in a hot-swap card, care should be
taken to ensure that the ground pins are connected to the
supply grounds before the positive or negative supplies are
connected. This is required to prevent currents from flowing in
directions other than toward an analog or digital ground.

impedance paths and reduce the effects of glitches on the power

Rev. A | Page 25 of 28

X1A Register

/B Select Register 0

A

/B Select Register 1

A

2

AD5360/AD5361

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INTERFACING EXAMPLES

The SPI interface of the AD5360 and AD5361 is designed to
allow the parts to be easily connected to industry standard DSPs
and microcontrollers. Figure 25 shows how the AD5360/AD5361
can be connected to the Analog Devices, Inc., Blackfin® DSP. The
Blackfin has an integrated SPI port that can be connected directly
to the SPI pins of the AD5360 or AD5361, and programmable
I/O pins that can be used to set or read the state of the digital
input or output pins associated with the interface.

AD5360/

AD5361

SYNC

SCLK

SDI

SDO

RESET

LDAC

CLR

BUSY

ADSP-BF531

SPISELx

SCK

MOSI

MISO

PF10

PF9

PF8

PF7

Figure 25. Interfacing to a Blackfin DSP

05761-024

The Analog Devices ADSP-21065L is a floating-point DSP with
two serial ports (SPORTs). Figure 26 shows how one SPORT
can be used to control the AD5360 or AD5361. In this example,
the transmit frame synchronization (TFS) pin is connected
to the receive frame synchronization (RFS) pin. Similarly,
the transmit and receive clocks (TCLK and RCLK) are also
connected together. The user can write to the AD5360 or
AD5361 by writing to the transmit register. A read operation
can be accomplished by first writing to the AD5360/AD5361
to tell the part that a read operation is required. A second write
operation with a NOP instruction causes the data to be read
from the AD5360/AD5361. The DSPs receive interrupt can be
used to indicate when the read operation is complete.

ADSP-21065L

TFSx

RFSx

TCLKx

RCLKx

DTxA

DRxA

FLAG

0

FLAG

1

FLAG

2

FLAG

3

Figure 26. Interfacing to an ADSP-21065L DSP

AD5360/

AD5361

SYNC

SCLK

SDI

SDO

RESET

LDAC

CLR

BUSY

5761-025

Rev. A | Page 26 of 28

AD5360/AD5361

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OUTLINE DIMENSIONS

12.20

52

PIN 1

14

0.65
BSC

LEAD PITCH

12.00 SQ

11. 80

TOP VIEW

(PINS DOWN)

0.38

0.32

0.22

40

39

10.20

10.00 SQ

9.80

27

26

1.45

1.40

1.35

0.15

SEATING

0.05

PLANE

VIEW A

ROTATED 90° CCW

0.75

0.60

0.45

0.20

0.09
7°

3.5°
0°

0.10
COPLANARIT Y

1.60
MAX

1

13

VIEW A

COMPLIANT TO JEDEC STANDARDS MS-026-BCC

051706-A

Figure 27. 52-Lead Low Profile Quad Flat Package [LQFP]

(ST-52)

Dimensions shown in millimeters

PAD

6.50
REF

0.30

0.23

0.18

PIN 1

56

15

INDICATOR

1

6.25

6.10 SQ

5.95

14

0.25 MIN

112805-0

1.00

0.85

0.80

SEATING

PLANE

12° MAX

BSC SQ

PIN 1
INDICATO R

8.00

0.60 MAX

TOP

VIEW

0.80 MAX

0.65 TYP

0.50 BSC

COMPLIANT TO JEDEC STANDARDS MO-220-VLL D-2

7.75

BSC SQ

0.20 REF

0.50

0.40

0.30

0.05 MAX

0.02 NOM
COPLANARITY

0.08

43

42

29

28

0.60 MAX

EXPOSED

(BOTTOM VIEW)

Figure 28. 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ]

8 mm × 8 mm, Very Thin Quad (CP-56-1)

Dimensions shown in millimeter

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD5360BSTZ
AD5360BSTZ-REEL
AD5360BCPZ
AD5360BCPZ-REEL7
AD5361BSTZ
AD5361BSTZ-REEL
AD5361BCPZ
AD5361BCPZ-REEL7
EVAL-AD5360EBZ
EVAL-AD5361EBZ

1

Z = RoHS Compliant Part.

1

1

1

−40°C to +85°C 56-Lead Lead Frame Chip Scale Package [LFCSP _VQ] CP-56-1

1

1

−40°C to +85°C 52-Lead Low Profile Quad Flat Pack [LQFP] ST-52

1

1

−40°C to +85°C 56-Lead Lead Frame Chip Scale Package [LFCSP _VQ] CP-56-1

1

1

1

−40°C to +85°C 52-Lead Low Profile Quad Flat Pack [LQFP] ST-52

−40°C to +85°C 52-Lead Low Profile Quad Flat Pack [LQFP] ST-52

−40°C to +85°C 56-Lead Lead Frame Chip Scale Package [LFCSP _VQ] CP-56-1

−40°C to +85°C 52-Lead Low Profile Quad Flat Pack [LQFP] ST-52

−40°C to +85°C 56-Lead Lead Frame Chip Scale Package [LFCSP _VQ] CP-56-1
Evaluation Board
Evaluation Board

Rev. A | Page 27 of 28

AD5360/AD5361

www.BDTIC.com/ADI

NOTES

©2007–2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05761-0-2/08(A)

Rev. A | Page 28 of 28