FEATURES
250 MHz Operation
Driver/Comparator and Active Load Included
On-Chip Schottky Diode Bridge
52-Lead LQFP Package with Built-In Heat Sink
APPLICATIONS
Automatic Test Equipment
Semiconductor Test Systems
Board Test Systems
Instrumentation and Characterization Equipment
PRODUCT DESCRIPTION
The AD53509 is a single chip that performs the pin electronics
functions of driver, comparator and active load in ATE VLSI
and memory testers. In addition, a Schottky diode bridge for the
active load and a VCOM buffer are included internally.
The driver is a proprietary design that features three active
states: Data High Mode, Data Low Mode and Term Mode as
well as an Inhibit State. This facilitates the implementation of
high speed active termination. The output voltage range is –2 V
to +7 V to accommodate a wide variety of test devices. The
output leakage is typically less than 250 nA over the entire signal range.
The dual comparator, with an input range equal to the driver
output range, features built-in latches and ECL-compatible
outputs. The outputs are capable of driving 50 Ω signal lines
terminated to –2 V. Signal tracking capability is upwards of
5 V/ns.
The active load can be set for up to 40 mA load current with
less than a 10 µA linearity error through the entire set range.
I
, IOL and the buffered VCOM are independently adjustable.
OH
On-board Schottky diodes provide high speed switching and low
capacitance.
Also included on the chip is an on-board temperature sensor
whose purpose is to give an indication of the surface temperature of the DCL. This information can be used to measure θ
and θJA or flag an alarm if proper cooling is lost. Output from
the sensor is a current sink that is proportional to absolute temperature. The gain is trimmed to a nominal value of 1.0 µA/K.
As an example, the output current can be sensed by using a
10 kΩ resistor connected from 10 V to the THERM (IOUT) pin.
A voltage drop across the resistor will be developed that equals:
10K × 1 µA/K = 10 mV/K = 2.98 V at room temperature.
JC
Active Load on a Single Chip
AD53509
FUNCTIONAL BLOCK DIAGRAM
V
VEEVEEVEEV
CC
CC
515239404132
34
EE
AD53509
DRIVER
COMPARATOR
ACTIVE LOAD
+1
2,5,89,33,44,46,48
VCCO
NC = NO CONNECT
46
1.0A/K
HQGND2HQGND
14, 26
CHDCPL
VHDCPL
V
OUT
VLDCPL
VCOMS
OUT_L
THERM
VH
VTERM
DATA
DATA
IOD
IOD
RLD
RLD
HCOMP
LEH
LEH
QH
QH
QL
QL
LEL
LEL
LCOMP
VCOMI
IOLC
IOLRTN
IOHRTN
INHL
INHL
IOHC
V
L
VCCVCCV
47
45
37
38
43
42
49
50
31
V/I
36
35
V/I
PWRGND
39nF
NC
39nF
CLDCPL
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
(All specifications are at TJ = 85C 5C, VS = 11 V 3%, –VS = –6 V = 3% unless otherwise noted. All temperature coefficients are
measured at TJ = 75C to 95C.)
ParameterMinTypMaxUnitTest Conditions
DIFFERENTIAL INPUT CHARACTERISTICS
(DATA to DATA, IOD to IOD, RLD to RLD)
Input Voltage–2+3V
Differential Input Range2VAll Digital Inputs Within a 2 V Range
Bias Current–250+250µAV
REFERENCE INPUTS
Bias Currents–50+50µAV
OUTPUT CHARACTERISTICS
Logic High Range–2+7VDATA = H, VH = –2 V to +7 V, VL = –2 V, VT = 0 V
Logic Low Range–2+6VDATA = L, VL = –2 V to +6 V, VH = 7 V, VT = 0 V
Amplitude (V
and VL)0.19VVL = 0.0 V, VH = 0.1 V, VT = 0 V
H
Absolute AccuracyV
VH Offset–50+50mVDATA = H, VH = 0 V, VL = –2 V, VT = –1 V
VH Gain + Linearity Error0.3 – 5+0.3 + 5 % of VH + mVDATA = H, VH = –1 V to +7 V, VL = –2 V, VT = –2 V
VL Offset–50+50mVDATA = L, VL = 0 V, VH = 5 V, VT = 3 V
VL Gain + Linearity Error–0.3 – 5+0.3 + 5 % of VL + mVDATA = L, VL = –2 V to +6 V, VH = 7 V, VT = 7 V
Offset TC0.5mV/°CV
Delay Time, Active to Inhibit3.3nsMeasured at 50%, VH = +2 V, VL = –2 V, VT = 0 V
Delay Time, Inhibit to Active2.9nsMeasured at 50%, V
= +2 V, VL = –2 V, VT = 0 V
H
Delay Time Matching (Z)<2nsZ = Delay Time Active to Inhibit Test (Above)—
Delay Time Inhibit to Active Test (Above)
(Of Worst Two Edges)
I/O Spike150mV, p-pVH = 0 V, VL = 0 V, VT = 0 V
Rise, Fall Time, Active to Inhibit1.6nsV
= +2 V, VL = –2 V (Measured 20%/80% of 1 V Output)
H
Rise, Fall Time, Inhibit to Active1.4nsVH = +2 V, VL = –2 V (Measured 20%/80% of 1 V Output)
DYNAMIC PERFORMANCE , V
Delay Time, VH to V
Delay Time, V
to VH and V
TERM
TERM
Overshoot and Preshoot<3.0 + 75% of Step + mVVH/VL, V
, VL to V
TERM
TERM
TERM
to V
2.5nsMeasured at 50%, VL = –1 V, VH = +1 V, V
L
2.5nsMeasured at 50%, VL = VH = +0.4 V, V
= (0 V, –1 V), (0 V, –2.0 V),
TERM
TERM
= 0 V
TERM
= –0.4 V
(0 V, 6.0 V)
V
Mode Rise Time2.2nsVL = –2 V, VH = +2 V, V
TERM
V
Mode Fall Time2.2nsVL = –2 V, VH = +2 V, V
TERM
= 0 V, 20%–80%
TERM
= 0 V, 20%–80%
TERM
PSRR, DRIVE or TERM Mode35dBVS = VS ± 3%
Specifications subject to change without notice.
COMPARATOR SPECIFICATIONS
(All specifications are at TJ = 85C 5C. [Outputs terminated in 150 to GND, +VS = 11 V 3% –VS = 6 V 3%, VCCO = 3.3 V unless
otherwise specified.] All temperatures coefficients are measured at TJ = 75C to 95C.)
ParameterMinTypMaxUnitTest Conditions
DC INPUT CHARACTERISTICS
Offset Voltage (VOS)–25+25mVCMV = 0 V
Offset Voltage (Drift)50µV/°CCMV = 0 V
HCOMP, LCOMP Bias Current–50+50µAV
= 0 V
IN
Voltage Range (VCM)–2+7.0V
Differential Voltage (V
)9.0V
DIFF
Gain and Linearity–0.05+0.05% FSRVIN = –2 V to +7 V (9 V FSR)
LATCH ENABLE INPUTS
Logic “1” Current (IIH)250µALEA, LEA, LEB, LEB = +3 V
Logic “0” Current (IIL)–250µALEA, LEA, LEB, LEB = –2 V
Logic Input Range–2+3V
DIGITAL OUTPUTS
Logic “1” Voltage (VOH)VCCO – 0.98VQ or Q, 16.7 mA Load
Logic “0” Voltage (VOL)VCCO – 1.5VQ or Q, 10 mA Load
Slew Rate1V/ns
VCCO Range08V
SWITCHING PERFORMANCE
Propagation Delay
Input to Output1.8nsVIN = 2 V p-p,
Latch Enable to Output2nsHCOMP = 1 V, LCOMP = 1 V
Propagation Delay Temperature Coefficient2ps/°C
Propagation Delay Change with Respect to
Slew Rate: 0.5 V, 1.0 V, 3.0 V/ns<± 100psVIN = 0 V to 5 V
Slew Rate: 5.0 V/ns<±350psVIN = 0 V to 5 V
Amplitude: 1.0 V, 3.0 V, 5.0 V<± 200psVIN = 1.0 V/ns
Equivalent Input Rise Time450psVIN = 0 V to 3 V, 3 V/ns
Pulsewidth Linearity<±200psVIN = 0 V to 3 V, 3 V/ns, PW = 3 ns–8 ns
Settling Time25nsSettling to ±8 mV, VIN = 1 V to 0 V
Latch Timing
Input Pulsewidth1.68ns
Setup Time1.0ns
Hold Time1.1ns
Hysteresis6mVLatch Inputs Programmed for Hysteresis
Specifications subject to change without notice.
–3–REV. A
Page 4
AD53509–SPECIFICATIONS
ACTIVE LOAD SPECIFICATIONS
(All specifications are at TJ = 85C 5C, +VS = 11 V 3%, –VS = –6 V = 3% unless otherwise noted. All temperature coefficients are
measured at TJ = 75C to 95C.)
Gain Error–0.2+0.2%IOL, IOH = 40 mA, VCOMI = –1 V to +6 V,
Linearity Error–10+10mVIOL, IOH = 40 mA, VCOMI = –1 V to +6 V,
Output Current TC<± 2µA/°CMeasured at IOH, IOL = 200 µA
DYNAMIC PERFORMANCE
Propagation Delay
± I
to Inhibit1.9nsVCOM = ± 2 V, IOL = +20 mA, IOH = –20 mA
OUT
Inhibit to ± I
Propagation Delay Matching<1.8ns
I/O Spike240mVVCOM = 0 V, IOL = +20 mA, IOH = –20 mA
Settling Time to 15 mV<50nsIOL = +20 mA, IOH = –20 mA, 50 Ω Load, to ⫾15 mV
Settling Time to 4 mV<10µsIOL = +20 mA, IOH = –20 mA, 50 Ω Load, to ⫾4 mV
Specifications subject to change without notice.
OUT
2.8nsVCOM = ± 2 V, IOL = +20 mA, IOH = 20 mA
+ µAIOL, IOH = 25 µA–40 mA, VCOM = 0 V, OUT_L = ± 2 V and
SET
IOL = 25 µA–40 mA, VCOM = +7 V, OUT_L = +5.7 V and
IOH = 25 µA–40 mA, VCOM = –2 V, OUT_L = –0.7 V
VOUT = VCOM
VOUT = VCOM
–4–
REV. A
Page 5
AD53509
TOTAL FUNCTION SPECIFICATIONS
(All specifications are at TJ = 85C 5C, VS = 11 V 3%, –VS = –6 V = 3% unless otherwise noted. All temperature coefficients are
measured at TJ = 75C to 95C.)
ParameterMinTypMaxUnitTest Conditions
OUTPUT CHARACTERISTICS
Output Leakage Current, V
Output Leakage Current, V
Output Capacitance8pFDriver and Load INHIBITED
POWER SUPPLIES
Total Supply Range17V
Positive Supply11V
Negative Supply–6V
Positive Supply Current280mADriver = INH, I
Negative Supply Current290mADriver = INH, I
VCCO Current65mAVCCO = 3.3 V, Comparator Output 150 ⍀ to GND
Total Power Dissipation4.8WDriver = INH, I
Temperature Sensor Gain Factor1µA/KR
NOTES
Connecting or shorting the decoupling pins to ground will result in the destruction of the device.
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Absolute maximum limits apply
individually, not in combination. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
2
Output short circuit protection is guaranteed as long as proper heat sinking is
employed to ensure compliance with the operating temperature limits.
3
To ensure lead coplanarity (± 0.002 inches) and solderability, handling with bare
hands should be avoided and the device should be stored in environments at 24 °C± 5°C (75°F ± 10°F) with relative humidity not to exceed 65%.
3
. . . . . . . . . . . 260°C
Table IV. Package Thermal Characteristics
Air Flow, FM JA, C/W
0 33
200 25
400 22
ORDERING GUIDE
Shipment Method
PackageQuantity perPackage
ModelDescriptionShipping ContainerOption
AD53509JSQ52-Lead LQFP-EDQUAD90SQ-52
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD53509 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
–6–
REV. A
Page 7
PIN CONFIGURATION
AD53509
V
VCCO
QL
QL
VCCO
QH
QH
VCCO
PWRGND
LEL
LEL
LEH
LEH
CC
CC
V
V
52 51 50 49 4843 42 41 4047 46 45 44
1
CC
PIN 1
IDENTIFIER
2
3
4
5
6
7
8
9
10
11
12
13
14 15 16 17 18 19 20 21 22 23 24 25 26
PWRGND
RLD
RLD
AD53509
HEAT SINK UP
(Not to Scale)
VH
NC
THERM
LCOMP
HCOMP
VHDCPL
HQGND2
NC = NO CONNECT
VTERM
PWRGND
OUT
V
OUT_L
IOD
PWRGND
IOLRTN
VLDCPL
EE
V
IOD
VCOMI
VCOMS
NC
V
EE
39
V
38
DATA
37
DATA
36
INHL
35
INHL
34
V
PWRGND
33
32
V
31
V
30
IOLC
29
IOHC
28
HQGND
27
IOHRTN
EE
CC
EE
L
–7–REV. A
Page 8
AD53509
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
52-Lead LQFP–EDQUAD with Integral Heat Slug
(SQ-52)
0.030 (0.75)
0.024 (0.60)
0.018 (0.45)
SEATING
PLANE
STANDOFF
0.004 (0.10)
MAX
0.063 (1.60)
MAX
5240
1
13
14
0.006 (0.15)
0.002 (0.05)
0.008 (0.20)
0.004 (0.09)
CENTER FIGURES ARE TYPICAL UNLESS OTHERWISE NOTED
0.630 (16.00) SQ
0.551 (14.00) SQ
TOP VIEW
(PINS DOWN)
0.039 (1.00)
BSC
0.020 (0.50)
0.017 (0.42)
0.014 (0.35)
39
27
26
0.057 (1.45)
0.055 (1.40)
0.053 (1.35)
0.270
(6.86)
DIA
7
3.5
0
C01539–0–12/00 (rev. A)
–8–
PRINTED IN U.S.A.
REV. A
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