Datasheet AD5344BRU, AD5344, AD5336BRU, AD5336, AD5335BRU Datasheet (Analog Devices)

2.5 V to 5.5 V, 500 ␮A, Parallel Interface

a

Quad Voltage-Output 8-/10-/12-Bit DACs

FEATURES
AD5334: Quad 8-Bit DAC in 24-Lead TSSOP
AD5335: Quad 10-Bit DAC in 24-Lead TSSOP
AD5336: Quad 10-Bit DAC in 28-Lead TSSOP
AD5344: Quad 12-Bit DAC in 28-Lead TSSOP
Low Power Operation: 500 ␮A @ 3 V, 600 ␮A @ 5 V
Power-Down to 80 nA @ 3 V, 200 nA @ 5 V via PD Pin

2.5 V to 5.5 V Power Supply
Double-Buffered Input Logic
Guaranteed Monotonic by Design Over All Codes
Output Range: 0–V

or 0–2 V

REF

REF

Power-On Reset to Zero Volts
Simultaneous Update of DAC Outputs via LDAC Pin
Asynchronous CLR Facility
Low Power Parallel Data Interface
On-Chip Rail-to-Rail Output Buffer Amplifiers
Temperature Range: –40ⴗC to +105ⴗC

APPLICATIONS
Portable Battery-Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Programmable Attenuators
Industrial Process Control

AD5334/AD5335/AD5336/AD5344*

GENERAL DESCRIPTION

The AD5334/AD5335/AD5336/AD5344 are quad 8-, 10-, and
12-bit DACs. They operate from a 2.5 V to 5.5 V supply con­suming just 500 µA at 3 V, and feature a power-down mode that
further reduces the current to 80 nA. These devices incorporate
an on-chip output buffer that can drive the output to both sup­ply rails.

The AD5334/AD5335/AD5336/AD5344 have a parallel interface.
CS selects the device and data is loaded into the input registers
on the rising edge of WR.

The GAIN pin on the AD5334 and AD5336 allows the output
range to be set at 0 V to V

Input data to the DACs is double-buffered, allowing simultaneous
update of multiple DACs in a system using the LDAC pin.

On the AD5334, AD5335 and AD5336 an asynchronous CLR
input is also provided. This resets the contents of the Input
Register and the DAC Register to all zeros. These devices also
incorporate a power-on-reset circuit that ensures that the DAC
output powers on to 0 V and remains there until valid data is
written to the device.

The AD5334/AD5335/AD5336/AD5344 are available in Thin
Shrink Small Outline Packages (TSSOP).

or 0 V to 2 × V

REF

REF

.

AD5334 FUNCTIONAL BLOCK DIAGRAM

(Other Diagrams Inside)

POWER-ON

RESET

GAIN

DB

7

.
.
.

DB

0

CS

WR

A0

A1

CLR

LDAC

*Protected by U.S. Patent Number 5,969,657; other patents pending.

INTER-

FACE

LOGIC

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

DAC

REGISTER

DAC

REGISTER

DAC

REGISTER

DAC

REGISTER

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

V

A/B

REF

V

DD

AD5334

8-BIT

DAC

8-BIT

DAC

8-BIT

8-BIT

DAC

DAC

8-BIT

DAC

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 2000

BUFFER

BUFFER

BUFFER

BUFFER

TO ALL DACS

AND BUFFERS

POWER-DOWN

LOGIC

V

REF

C/D

PD

GND

V

A

OUT

V

B

OUT

C

V

OUT

D

V

OUT

AD5334/AD5335/AD5336/AD5344–SPECIFICATIONS

(VDD = 2.5 V to 5.5 V, V

Parameter

DC PERFORMANCE

DAC REFERENCE INPUT

OUTPUT CHARACTERISTICS

LOGIC INPUTS

POWER REQUIREMENTS

NOTES

1

See Terminology section.

2

Temperature range: B Version: –40°C to +105°C; typical specifications are at 25°C.

3

Linearity is tested using a reduced code range: AD5334 (Code 8 to 255); AD5335/AD5336 (Code 28 to 1023); AD5344 (Code 115 to 4095).

4

DC specifications tested with outputs unloaded.

5

This corresponds to x codes. x = Deadband voltage/LSB size.

6

Guaranteed by design and characterization, not production tested.

7

In order for the amplifier output to reach its minimum voltage, Offset Error must be negative. In order for the amplifier output to reach its maximum voltage, V
“Offset plus Gain” Error must be positive.

Specifications subject to change without notice.

1

AD5334

Resolution 8 Bits
Relative Accuracy ± 0.15 ± 1 LSB
Differential Nonlinearity ± 0.02 ± 0.25 LSB Guaranteed Monotonic By Design Over All Codes

AD5335/AD5336

Resolution 10 Bits
Relative Accuracy ± 0.5 ± 4 LSB
Differential Nonlinearity ± 0.05 ± 0.5 LSB Guaranteed Monotonic By Design Over All Codes

AD5344

Resolution 12 Bits
Relative Accuracy ± 2 ± 16 LSB

Differential Nonlinearity ± 0.2 ± 1 LSB Guaranteed Monotonic By Design Over All Codes
Offset Error ± 0.4 ± 3 % of FSR
Gain Error ± 0.1 ± 1 % of FSR
Lower Deadband
Upper Deadband 10 60 mV VDD = 5 V. Upper Deadband Exists Only if V
Offset Error Drift
Gain Error Drift
DC Power Supply Rejection Ratio
DC Crosstalk

V

Input Range 0.25 V

REF

V

Input Impedance 180 kΩ Gain = 1. Input Impedance = R

REF

6

6

Reference Feedthrough –90 dB Frequency = 10 kHz
Channel-to-Channel Isolation –90 dB Frequency = 10 kHz

Minimum Output Voltage
Maximum Output Voltage
DC Output Impedance 0.5 Ω
Short Circuit Current 50 mA VDD = 5 V

Power-Up Time 2.5 µs Coming Out of Power-Down Mode. VDD = 5 V

6

Input Current ± 1 µA
VIL, Input Low Voltage 0.8 V V

VIH, Input High Voltage 2.4 V VDD = 5 V ± 10%

Pin Capacitance 3.5 pF

V

DD

IDD (Normal Mode) All DACs active and excluding load currents.

VDD = 4.5 V to 5.5 V 600 900 µAV

VDD = 2.5 V to 3.6 V 500 700 µAI
IDD (Power-Down Mode)

VDD = 4.5 V to 5.5 V 0.2 1 µA

VDD = 2.5 V to 3.6 V 0.08 1 µA

= 2 V. RL = 2 k⍀ to GND; CL =200 pF to GND; all specifications T

REF

B Version

2

Min Typ Max Unit Conditions/Comments

3, 4

5

6

6

10 60 mV Lower Deadband Exists Only if Offset Error Is Negative

–12 ppm of FSR/°C
–5 ppm of FSR/°C
–60 dB ∆VDD = ±10%
200 µVR

6

DD

V

90 kΩ Gain = 2. Input Impedance = R
90 kΩ Gain = 1. Input Impedance = R
45 kΩ Gain = 2. Input Impedance = R

6

4, 7

4, 7

0.001 V min Rail-to-Rail Operation
VDD – 0.001 V max

20 mA VDD = 3 V

5 µs Coming Out of Power-Down Mode. VDD = 3 V

0.6 V VDD = 3 V ± 10%

0.5 V VDD = 2.5 V

2.1 V VDD = 3 V ± 10%

2.0 V VDD = 2.5 V

2.5 5.5 V

to T

MIN

= 2 kΩ to GND, 2 kΩ to VDD; CL = 200 pF to GND;

L

unless otherwise noted.)

MAX

Gain = 0

(AD5336/AD5344)

DAC

(AD5336)

DAC

(AD5334/AD5335)

DAC

(AD5334)

DAC

= 5 V ± 10%

DD

= VDD, V

IH

increases by 50 µA at V

DD

= GND.

IL

> VDD – 100 mV.

REF

REF = VDD

= VDD and

REF

–2–

REV. 0

AD5334/AD5335/AD5336/AD5344

(VDD = 2.5 V to 5.5 V. RL = 2 k⍀ to GND; CL = 200 pF to GND. All specifications T

AC CHARACTERISTICS

Parameter

2

1

wise noted.)

B Version

3

Min Typ Max Unit Conditions/Comments

Output Voltage Settling Time V

= 2 V. See Figure 20

REF

MIN

to T

MAX

unless other-

AD5334 6 8 µs 1/4 Scale to 3/4 Scale Change (40 H to C0 H)
AD5335 7 9 µs 1/4 Scale to 3/4 Scale Change (100 H to 300 H)
AD5336 7 9 µs 1/4 Scale to 3/4 Scale Change (100 H to 300 H)

AD5344 8 10 µs 1/4 Scale to 3/4 Scale Change (400 H to C00 H)
Slew Rate 0.7 V/µs
Major Code Transition Glitch Energy 8 nV-s 1 LSB Change Around Major Carry
Digital Feedthrough 0.5 nV-s
Digital Crosstalk 3 nV-s
Analog Crosstalk 0.5 nV-s
DAC-to-DAC Crosstalk 3.5 nV-s
Multiplying Bandwidth 200 kHz V
Total Harmonic Distortion –70 dB V

NOTES

1

Guaranteed by design and characterization, not production tested.

2

See Terminology section.

3

Temperature range: B Version: –40°C to +105°C; typical specifications are at 25°C.

Specifications subject to change without notice.

1, 2, 3

TIMING CHARACTERISTICS

Parameter Limit at T

t

1

t

2

t

3

t

4

t

5

t

6

t

7

t

8

t

9

t

10

t

11

t

12

t

13

t

14

t

15

NOTES

1

Guaranteed by design and characterization, not production tested.

2

All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD)
and timed from a voltage level of (VIL + VIH)/2.

3

See Figure 1.

Specifications subject to change without notice.

0 ns min CS to WR Setup Time
0 ns min CS to WR Hold Time
20 ns min WR Pulsewidth
5 ns min Data, GAIN, HBEN Setup Time

4.5 ns min Data, GAIN, HBEN Hold Time
5 ns min Synchronous Mode. WR Falling to LDAC Falling.
5 ns min Synchronous Mode. LDAC Falling to WR Rising.

4.5 ns min Synchronous Mode. WR Rising to LDAC Rising.
5 ns min Asynchronous Mode. LDAC Rising to WR Rising.

4.5 ns min Asynchronous Mode. WR Rising to LDAC Falling.
20 ns min LDAC Pulsewidth
20 ns min CLR Pulsewidth
50 ns min Time Between WR Cycles
20 ns min A0, A1 Setup Time
0 ns min A0, A1 Hold Time

MIN

, T

(VDD = 2.5 V to 5.5 V, All specifications T

MAX

Unit Condition/Comments

DATA,

GAIN,
HBEN

LDAC

LDAC

CS

WR

1

2

CLR

A0,

A1

NOTES:

1

SYNCHRONOUS LDAC UPDATE MODE

2

ASYNCHRONOUS LDAC UPDATE MODE

= 2 V ± 0.1 V p-p. Unbuffered Mode

REF

= 2.5 V ± 0.1 V p-p. Frequency = 10 kHz

REF

to T

MIN

t

unless otherwise noted.)

MAX

1

t

3

t

4

t

6

t

7

t

9

t

14

t

2

t

13

t

5

t

8

t

10

t

15

t

11

t

12

Figure 1. Parallel Interface Timing Diagram

REV. 0

–3–

AD5334/AD5335/AD5336/AD5344

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS*

(TA = 25°C unless otherwise noted)

VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

Digital Input Voltage to GND . . . . . . . .–0.3 V to V

Digital Output Voltage to GND . . . . . .–0.3 V to V

Reference Input Voltage to GND . . . . –0.3 V to V

V

to GND . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V

OUT

+ 0.3 V

DD

+ 0.3 V

DD

+ 0.3 V

DD

Operating Temperature Range

Reflow Soldering

Peak Temperature . . . . . . . . . . . . . . . . . . . . . . 220 +5/–0°C

Time at Peak Temperature . . . . . . . . . . . . .10 sec to 40 sec

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

Industrial (B Version) . . . . . . . . . . . . . . . –40°C to +105°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C

TSSOP Package

Power Dissipation . . . . . . . . . . . . . . . (T

θ

Thermal Impedance (24-Lead TSSOP) . . . . . 128°C/W

JA

Thermal Impedance (28-Lead TSSOP) . . . . . 97.9°C/W

θ

JA

θ

Thermal Impedance (24-Lead TSSOP) . . . . . . 42°C/W

JC

θ

Thermal Impedance (28-Lead TSSOP) . . . . . . 14°C/W

JC

max – TA)/θJA mW

J

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD5334BRU –40°C to +105°C TSSOP (Thin Shrink Small Outline Package) RU-24
AD5335BRU –40°C to +105°C TSSOP (Thin Shrink Small Outline Package) RU-24
AD5336BRU –40°C to +105°C TSSOP (Thin Shrink Small Outline Package) RU-28
AD5344BRU –40°C to +105°C TSSOP (Thin Shrink Small Outline Package) RU-28

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD5334/AD5335/AD5336/AD5344 features proprietary ESD protection circuitry, permanent
damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.

–4–

REV. 0

AD5334/AD5335/AD5336/AD5344

GAIN

DB

DB

CS

WR

A0

A1

CLR

LDAC

AD5334 FUNCTIONAL BLOCK DIAGRAM

V

A/B

REF

POWER-ON

RESET

7

.
.
.

0

INTER-

FACE

LOGIC

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

DAC

REGISTER

DAC

REGISTER

DAC

REGISTER

DAC

REGISTER

8-BIT

DAC

8-BIT

DAC

8-BIT

DAC

8-BIT

DAC

8-BIT

DAC

BUFFER

BUFFER

BUFFER

BUFFER

V

C/D

REF

V

DD

AD5334

TO ALL DACS

AND BUFFERS

POWER-DOWN

LOGIC

PD

GND

V

A

OUT

V

B

OUT

C

V

OUT

D

V

OUT

AD5334 PIN CONFIGURATION

8-BIT

24

CLR

23

GAIN

22

DB

7

21

DB

6

20

DB

5

19

DB

4

18

DB

3

17

DB

2

16

DB

1

15

DB

0

14

V

DD

13

PD

V

V

REF

REF

V

OUT

V

OUT

V

OUT

V

OUT

LDAC

C/D

A/B

GND

CS

WR

A

B

C

D

A0

A1

1

2

3

4

5

AD5334

6

TOP VIEW

(Not to Scale)

7

8

9

10

11

12

AD5334 PIN FUNCTION DESCRIPTIONS

Pin
No. Mnemonic Function

1V
2V
3V
4V
5V
6V

C/D Unbuffered Reference Input for DACs C and D.

REF

A/B Unbuffered Reference Input for DACs A and B.

REF

A Output of DAC A. Buffered Output with Rail-to-Rail Operation.

OUT

B Output of DAC B. Buffered Output with Rail-to-Rail Operation.

OUT

C Output of DAC C. Buffered Output with Rail-to-Rail Operation.

OUT

D Output of DAC D. Buffered Output with Rail-to-Rail Operation.

OUT

7 GND Ground Reference Point for All Circuitry on the Part.
8 CS Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface.
9 WR Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface.
10 A0 LSB Address Pin for Selecting which DAC Is to Be Written to.
11 A1 MSB Address Pin for Selecting which DAC Is to Be Written to.
12 LDAC Active Low Control Input that Updates the DAC Registers with the Contents of the Input Registers.

This allows all DAC outputs to be simultaneously updated.

13 PD Power-Down Pin. This active low control pin puts all DACs into power-down mode.
14 V

DD

Power Supply Pin. This part can operate from 2.5 V to 5.5 V and the supply should be decoupled with a

10 µF capacitor in parallel with a 0.1 µF capacitor to GND.
15–22 DB
23 GAIN Gain Control Pin. This controls whether the output range from the DAC is 0–V

–DB

0

7

Eight Parallel Data Inputs. DB7 is the MSB of these eight bits.

or 0–2 V

REF

REF

24 CLR Asynchronous Active Low Control Input that Clears All Input Registers and DAC Registers to Zeros.

REV. 0

–5–

AD5334/AD5335/AD5336/AD5344

TOP VIEW

(Not to Scale)

24

23

22

21

20

19

18

17

16

15

14

13

1

2

3

4

5

6

7

8

9

10

11

12

AD5335

LDAC

A1

A0

WR

CS

V

REF

C/D

V

REF

A/B

V

OUT

A

V

OUT

B

GND

V

OUT

D

V

OUT

C

PD

V

DD

DB

0

DB

1

DB

2

CLR

HBEN

DB

7

DB

6

DB

3

DB

4

DB

5

10-BIT

DB

DB

CS

WR

A0

A1

HBEN

CLR

LDAC

AD5335 FUNCTIONAL BLOCK DIAGRAM

V

A/B

REF

POWER-ON

RESET

HIGH BYTE

REGISTER

7

.
.
.
.
.
.

0

INTER-

FACE

LOGIC

RESET

LOW BYTE
REGISTER

HIGH BYTE

REGISTER

LOW BYTE
REGISTER

HIGH BYTE

REGISTER

LOW BYTE
REGISTER

HIGH BYTE

REGISTER

LOW BYTE
REGISTER

DAC

REGISTER

DAC

REGISTER

DAC

REGISTER

DAC

REGISTER

10-BIT

DAC

10-BIT

DAC

10-BIT

DAC

10-BIT

DAC

BUFFER

BUFFER

BUFFER

BUFFER

AND BUFFERS

V

AD5335

TO ALL DACS

POWER-DOWN

DD

LOGIC

V

OUT

V

OUT

V

OUT

V

OUT

AD5335 PIN CONFIGURATION

A

B

C

D

V

REF

C/D

PD

GND

AD5335 PIN FUNCTION DESCRIPTIONS

Pin
No. Mnemonic Function

1V
2V
3V
4V
5V
6V

C/D Unbuffered Reference Input for DACs C and D.

REF

A/B Unbuffered Reference Input for DACs A and B.

REF

A Output of DAC A. Buffered output with rail-to-rail operation.

OUT

B Output of DAC B. Buffered output with rail-to-rail operation.

OUT

C Output of DAC C. Buffered output with rail-to-rail operation.

OUT

D Output of DAC D. Buffered output with rail-to-rail operation.

OUT

7 GND Ground Reference Point for All Circuitry on the Part.
8 CS Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface.
9 WR Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface.
10 A0 LSB Address Pin for Selecting which DAC Is to Be Written to.
11 A1 MSB Address Pin for Selecting which DAC Is to Be Written to.
12 LDAC Active Low Control Input that Updates the DAC Registers with the Contents of the Input Registers.

13 PD Power-Down Pin. This active low control pin puts all DACs into power-down mode.
14 V

15–22 DB
23 HBEN This pin is used when writing to the device to determine if data is written to the high byte register or the

24 CLR Asynchronous Active Low Control Input that Clears All Input Registers and DAC Registers to Zeros.

DD

–DB

0

7

This allows all DAC outputs to be simultaneously updated.

Power Supply Pin. This part can operate from 2.5 V to 5.5 V and the supply should be decoupled with a
10 µF capacitor in parallel with a 0.1 µF capacitor to GND.

Eight Parallel Data Inputs. DB7 is the MSB of these eight bits.

low byte register.

–6–

REV. 0

AD5334/AD5335/AD5336/AD5344

TOP VIEW

(Not to Scale)

28

27

26

25

24

23

22

21

20

19

18

17

16

15

1

2

3

4

5

6

7

8

9

10

11

12

13

14

AD5336

LDAC

A1

A0

WR

CS

GND

V

OUT

D

V

REF

C

V

REF

B

V

REF

A

V

OUT

C

V

OUT

B

V

OUT

A

V

REF

D

PD

V

DD

DB

0

DB

1

DB

2

DB

3

DB

4

CLR

GAIN

DB

9

DB

8

DB

5

DB

6

DB

7

10-BIT

GAIN

DB

DB

CS

WR

A0

A1

CLR

LDAC

AD5336 FUNCTIONAL BLOCK DIAGRAM

V

V

A

REF

POWER-ON

RESET

DAC

REGISTER

DAC

REGISTER

DAC

REGISTER

DAC

REGISTER

V

REF

10-BIT

DAC

10-BIT

DAC

10-BIT

DAC

10-BIT

DAC

D

RESET

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

9

.
.
.

0

INTER-

FACE

LOGIC

B

REF

BUFFER

BUFFER

BUFFER

BUFFER

V

C

REF

V

DD

AD5336

TO ALL DACS

AND BUFFERS

POWER-DOWN

LOGIC

PD

GND

V

A

OUT

V

B

OUT

C

V

OUT

D

V

OUT

AD5336 PIN CONFIGURATION

AD5336 PIN FUNCTION DESCRIPTIONS

Pin
No. Mnemonic Function

1V
2V
3V
4V
5V
6V
7V
8V

D Unbuffered Reference Input for DAC D.

REF

C Unbuffered Reference Input for DAC C.

REF

B Unbuffered Reference Input for DAC B.

REF

A Unbuffered Reference Input for DAC A.

REF

A Output of DAC A. Buffered output with rail-to-rail operation.

OUT

B Output of DAC B. Buffered output with rail-to-rail operation.

OUT

C Output of DAC C. Buffered output with rail-to-rail operation.

OUT

D Output of DAC D. Buffered output with rail-to-rail operation.

OUT

9 GND Ground Reference Point for All Circuitry on the Part.
10 CS Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface.
11 WR Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface.
12 A0 LSB Address Pin for Selecting which DAC Is to Be Written to.
13 A1 MSB Address Pin for Selecting which DAC is to Be Written to.
14 LDAC Active Low Control Input that Updates the DAC Registers with the Contents of the Input Registers.

This allows all DAC outputs to be simultaneously updated.

15 PD Power-Down Pin. This active low control pin puts all DACs into power-down mode.
16 V

17–26 DB
27 GAIN Gain Control Pin. This controls whether the output range from the DAC is 0–V
28 CLR Asynchronous Active Low Control Input that Clears All Input Registers and DAC Registers to Zeros.

REV. 0

DD

–DB

0

9

Power Supply Pin. This part can operate from 2.5 V to 5.5 V and the supply should be decoupled with a
10 µF capacitor in parallel with a 0.1 µF capacitor to GND.

10 Parallel Data Inputs. DB9 is the MSB of these 10 bits.

or 0–2 V

REF

–7–

REF

.

AD5334/AD5335/AD5336/AD5344

DB

.
.
.
.
.
.

DB

CS

WR

A0

A1

LDAC

AD5344 FUNCTIONAL BLOCK DIAGRAM

V

V

REF

REF

B

BUFFER

BUFFER

BUFFER

BUFFER

C

V

A

REF

POWER-ON

RESET

11

0

INTER-

FACE

LOGIC

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

DAC

REGISTER

DAC

REGISTER

DAC

REGISTER

DAC

REGISTER

12-BIT

DAC

12-BIT

DAC

12-BIT

DAC

12-BIT

DAC

V

REF

D

V

DD

AD5344

TO ALL DACS

AND BUFFERS

POWER-DOWN

LOGIC

PD

GND

V

A

OUT

V

B

OUT

C

V

OUT

D

V

OUT

AD5344 PIN CONFIGURATION

1

V

REF

V

REF

V

REF

V

REF

V

OUT

V

OUT

V

OUT

V

OUT

GND

LDAC

D

C

B

A

A

B

C

D

CS

WR

A0

A1

2

3

4

5

12-BIT

6

AD5344

7

TOP VIEW

(Not to Scale)

8

9

10

11

12

13

14

28

DB

11

27

DB

10

26

DB

9

25

DB

8

24

DB

7

23

DB

6

22

DB

5

21

DB

4

DB

20

3

19

DB

2

18

DB

1

17

DB

0

16

V

DD

15

PD

AD5344 PIN FUNCTION DESCRIPTIONS

Pin
No. Mnemonic Function

1V
2V
3V
4V
5V
6V
7V
8V

D Unbuffered Reference Input for DAC D.

REF

C Unbuffered Reference Input for DAC C.

REF

B Unbuffered Reference Input for DAC B.

REF

A Unbuffered Reference Input for DAC A.

REF

A Output of DAC A. Buffered output with rail-to-rail operation.

OUT

B Output of DAC B. Buffered output with rail-to-rail operation.

OUT

C Output of DAC C. Buffered output with rail-to-rail operation.

OUT

D Output of DAC D. Buffered output with rail-to-rail operation.

OUT

9 GND Ground Reference Point for All Circuitry on the Part.
10 CS Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface.
11 WR Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface.
12 A0 LSB Address Pin for Selecting which DAC Is to Be Written to.
13 A1 MSB Address Pin for Selecting which DAC Is to Be Written to.
14 LDAC Active Low Control Input that Updates the DAC Registers with the Contents of the Input Registers.

This allows all DAC outputs to be simultaneously updated.

15 PD Power-Down Pin. This active low control pin puts all DACs into power-down mode.
16 V

DD

Power Supply Pin. This part can operate from 2.5 V to 5.5 V and the supply should be decoupled with a
10 µF capacitor in parallel with a 0.1 µF capacitor to GND.

17–28 DB0–DB

11

12 Parallel Data Inputs. DB11 is the MSB of these 12 bits.

–8–

REV. 0

TERMINOLOGY

OUTPUT

VOLTAGE

DAC CODE

POSITIVE

OFFSET

GAIN ERROR
AND
OFFSET
ERROR

ACTUAL

IDEAL

OUTPUT

VOLTAGE

DAC CODE

NEGATIVE

OFFSET

GAIN ERROR
AND
OFFSET
ERROR

AMPLIFIER

FOOTROOM

(~1mV)

NEGATIVE

OFFSET

DEADBAND CODES

ACTUAL

IDEAL

RELATIVE ACCURACY

For the DAC, Relative Accuracy or Integral Nonlinearity (INL)
is a measure of the maximum deviation, in LSBs, from a straight
line passing through the actual endpoints of the DAC transfer
function. Typical INL versus Code plot can be seen in Figures
5, 6, and 7.

DIFFERENTIAL NONLINEARITY

Differential Nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A specified differential nonlinearity of ±1 LSB
maximum ensures monotonicity. This DAC is guaranteed mono­tonic by design. Typical DNL versus Code plot can be seen in
Figures 8, 9, and 10.

OFFSET ERROR

This is a measure of the offset error of the DAC and the output
amplifier. It is expressed as a percentage of the full-scale range.

If the offset voltage is positive, the output voltage will still be
positive at zero input code. This is shown in Figure 3. Because
the DACs operate from a single supply, a negative offset cannot
appear at the output of the buffer amplifier. Instead, there will
be a code close to zero at which the amplifier output saturates
(amplifier footroom). Below this code there will be a deadband
over which the output voltage will not change. This is illustrated
in Figure 4.

AD5334/AD5335/AD5336/AD5344

Figure 3. Positive Offset Error and Gain Error

GAIN ERROR

This is a measure of the span error of the DAC (including any
error in the gain of the buffer amplifier). It is the deviation in
slope of the actual DAC transfer characteristic from the ideal
expressed as a percentage of the full-scale range. This is illus­trated in Figure 2.

POSITIVE
GAIN ERROR

NEGATIVE
GAIN ERROR

OUTPUT

VOLTAGE

ACTUAL

DAC CODE

Figure 2. Gain Error

IDEAL

Figure 4. Negative Offset Error and Gain Error

REV. 0

–9–

AD5334/AD5335/AD5336/AD5344

OFFSET ERROR DRIFT

This is a measure of the change in Offset Error with changes in
temperature. It is expressed in (ppm of full-scale range)/°C.

GAIN ERROR DRIFT

This is a measure of the change in Gain Error with changes in
temperature. It is expressed in (ppm of full-scale range)/°C.

DC POWER-SUPPLY REJECTION RATIO (PSRR)

This indicates how the output of the DAC is affected by changes in
the supply voltage. PSRR is the ratio of the change in V
change in V
in dBs. V

DC CROSSTALK

for full-scale output of the DAC. It is measured

DD

is held at 2 V and VDD is varied ±10%.

REF

OUT

to a

This is the dc change in the output level of one DAC at mid­scale in response to a full-scale code change (all 0s to all 1s and
vice versa) and output change of another DAC. It is expressed
in µV.

REFERENCE FEEDTHROUGH

This is the ratio of the amplitude of the signal at the DAC output
to the reference input when the DAC output is not being updated
(i.e., LDAC is high). It is expressed in dBs.

CHANNEL-TO-CHANNEL ISOLATION

This is a ratio of the amplitude of the signal at the output of one
DAC to a sine wave on the reference inputs of the other DACs.
It is measured by grounding one V
4 V peak-to-peak sine wave to the other V

pin and applying a 10 kHz,

REF

pins. It is expressed

REF

in dBs.

DIGITAL FEEDTHROUGH

Digital Feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital input pins of the
device but is measured when the DAC is not being written to
(CS held high). It is specified in nV-secs and is measured with a
full-scale change on the digital input pins, i.e. from all 0s to all
1s and vice versa.

DIGITAL CROSSTALK

This is the glitch impulse transferred to the output of one DAC
at midscale in response to a full-scale code change (all 0s to all
1s and vice versa) in the input register of another DAC. It is
expressed in nV secs.

ANALOG CROSSTALK

This is the glitch impulse transferred to the output of one DAC
due to a change in the output of another DAC. It is measured
by loading one of the input registers with a full-scale code change
(all 0s to all 1s and vice versa) while keeping LDAC high. Then
pulse LDAC low and monitor the output of the DAC whose
digital code was not changed. The area of the glitch is expressed
in nV secs.

DAC-TO-DAC CROSSTALK

This is the glitch impulse transferred to the output of one DAC
due to a digital code change and subsequent output change of
another DAC. This includes both digital and analog crosstalk. It
is measured by loading one of the DACs with a full-scale code
change (all 0s to all 1s and vice versa) with the LDAC pin set
low and monitoring the output of another DAC. The energy of
the glitch is expressed in nV secs.

MAJOR-CODE TRANSITION GLITCH ENERGY

Major-Code Transition Glitch Energy is the energy of the
impulse injected into the analog output when the DAC changes
state. It is normally specified as the area of the glitch in nV secs
and is measured when the digital code is changed by 1 LSB at
the major carry transition (011 . . . 11 to 100 . . . 00 or 100 . . . 00
to 011 . . . 11).

MULTIPLYING BANDWIDTH

The amplifiers within the DAC have a finite bandwidth. The
Multiplying Bandwidth is a measure of this. A sine wave on the
reference (with full-scale code loaded to the DAC) appears on
the output. The Multiplying Bandwidth is the frequency at which
the output amplitude falls to 3 dB below the input.

TOTAL HARMONIC DISTORTION

This is the difference between an ideal sine wave and its attenuated
version using the DAC. The sine wave is used as the reference
for the DAC and the THD is a measure of the harmonics present
on the DAC output. It is measured in dBs.

–10–

REV. 0

Typical Performance Characteristics–

AD5334/AD5335/AD5336/AD5344

1.0

TA = 25ⴗC
V

= 5V

DD

0.5

0

INL ERROR – LSBs

–0.5

–1.0

50 250100 150 200

0

CODE

Figure 5. AD5334 Typical INL Plot

0.3
TA = 25ⴗC

= 5V

V

DD

0.2

0.1

0

–0.1

DNL ERROR – LSBs

–0.2

3

TA = 25ⴗC
V

= 5V

DD

2

1

0

–1

INL ERROR – LSBs

–2

–3

0

200 1000

400 600 800

CODE

Figure 6. AD5335 Typical INL Plot

0.6
TA = 25ⴗC

= 5V

V

DD

0.4

0.2

0

–0.2

DNL ERROR – LSBs

–0.4

12

TA = 25ⴗC
V

= 5V

8

DD

4

0

–4

INL ERROR – LSBs

–8

–12

0 4000

1000 2000 3000

CODE

Figure 7. AD5336 Typical INL Plot

1

TA = 25ⴗC

= 5V

V

DD

0.5

0

DNL ERROR – LSBs

–0.5

–0.3

050 250100 150 200

CODE

Figure 8. AD5334 Typical DNL Plot

0.5

VDD = 5V

= 25ⴗC

T

A

0.25

0

ERROR – LSBs

–0.25

–0.5

01 5234

MAX INL

MIN DNL

MIN INL

V

REF

MAX DNL

– V

Figure 11. AD5334 INL and DNL
Error vs. V

REF

–0.6

2000

CODE

600400

800 1000

Figure 9. AD5335 Typical DNL Plot

0.5

VDD = 5V

0.4

V

= 2V

REF

0.3

0.2

0.1

0

–0.1

ERROR – LSBs

–0.2

–0.3

–0.4

–0.5

ⴚ40 0 40

MAX INL

MAX DNL

MIN DNL

MIN INL

80 120

TEMPERATURE – ⴗC

Figure 12. AD5334 INL Error and
DNL Error vs. Temperature

–1

10000

2000

CODE

3000 4000

Figure 10. AD5336 Typical DNL Plot

1

VDD = 5V

= 2V

V

REF

0.5

GAIN ERROR

0

ERROR – %

–0.5

–1

ⴚ40 0 40

OFFSET ERROR

80 120

TEMPERATURE – ⴗC

Figure 13. AD5334 Offset Error
and Gain Error vs. Temperature

REV. 0

–11–

AD5334/AD5335/AD5336/AD5344

CH1 500mV, CH2 5V, TIME BASE = 1␮s/DIV

CH1

CH2

TA = 25ⴗC
V

DD

= 5V

V

REF

= 2V

V

OUT

A

PD

0.2

TA = 25ⴗC

0.1

V

= 2V

REF

0

–0.1

–0.2

ERROR – %

–0.3

–0.4

–0.5

–0.6

01 3

GAIN ERROR

OFFSET ERROR

25

VDD – Volts

46

Figure 14. Offset Error and Gain
Error vs. V

600

500

400

300

– ␮A

DD

I

200

100

0

2.5 3.0 3.5 4.0 4.5 5.0 5.5

TA = 25ⴗC

DD

V

– V

DD

Figure 17. Supply Current vs. Supply
Voltage

5

5V SOURCE

3

– Volts

OUT

2

V

1

0

01 3446

Figure 15. V

3V SOURCE

5V SINK

25

SINK/SOURCE CURRENT – mA

Source and Sink

OUT

3V SINK

Current Capability

0.5
= 25ⴗC

T

A

0.4

0.3

– ␮A

DD

I

0.2

0.1

0

2.5

3.0 3.5 4.0 4.5 5.0 5.5
V

– V

Figure 18. Power-Down Current vs.
Supply Voltage

600

V

= 5.5V

500

400

300

– ␮A

DD

I

200

100

0

ZERO-SCALE FULL SCALE

DD

V

DD

DAC CODE

= 3.6V

TA = 25ⴗC
V

REF

= 2V

Figure 16. Supply Current
vs. DAC Code

1800

1600

1400

1200

1000

– ␮A

800

DD

I

600

400

200

V

= 3V

DD

0

0

1

2345

V

LOGIC

– V

V

= 5V

DD

Figure 19. Supply Current
vs. Logic Input Voltage

T

= 25ⴗC

5µs

A

= 5V

V

DD

V

= 5V

REF

CH1

V

A

OUT

LDAC

CH2

CH1 1V, CH2 5V, TIME BASE= 1␮s/DIV

Figure 20. Half-Scale Settling (1/4 to
3/4 Scale Code Change)

TA = 25ⴗC

= 5V

V

DD

V

= 2V

REF

CH1

V

DD

V

A

CH2

CH1 2V, CH2 200mV, TIME BASE = 200␮s/DIV

OUT

Figure 21. Power-On Reset to 0 V

–12–

Figure 22. Exiting Power-Down
to Midscale

REV. 0

AD5334/AD5335/AD5336/AD5344

VDD = 5VVDD = 3V

FREQUENCY

300 350 600400 450 500 550

IDD – ␮A

Figure 23. IDD Histogram with VDD =

V
T

DD

A

DD

= 5V

= 25ⴗC

= 5 V

3 V and V

0.4

0.3

0.2

0.1

0

0.929

0.928

0.927

0.926

0.925

0.924

– Volts

OUT

0.923

V

0.922

0.921

0.920

0.919
500ns/DIV

Figure 24. AD5344 Major-Code Tran­sition Glitch Energy

1mV/DIV

10

0

–10

–20

dB

–30

–40

–50

–60

0.01

0.1 1 10 100 1k 10k
FREQUENCY – kHz

Figure 25. Multiplying Bandwidth
(Small-Signal Frequency Response)

FULL-SCALE ERROR – %FSR

–0.1

–0.2

0

1

23456

V

– V

REF

Figure 26. Full-Scale Error vs. V

REF

Figure 27. DAC-DAC Crosstalk

750ns/DIV

FUNCTIONAL DESCRIPTION

The AD5334/AD5335/AD5336/AD5344 are quad resistor­string DACs fabricated on a CMOS process with resolutions of
8, 10, 10, and 12 bits, respectively. They are written to using a
parallel interface. They operate from single supplies of 2.5 V to

5.5 V and the output buffer amplifiers offer rail-to-rail output
swing. The gain of the buffer amplifiers in the AD5334 and
AD5336 can be set to 1 or 2 to give an output voltage range of
0 to V

or 0 to 2 V

REF

. The AD5335 and AD5344 have out-

REF

put buffers with unity gain.

The devices have a power-down feature that reduces current
consumption to only 80 nA @ 3 V.

Digital-to-Analog Section

The architecture of one DAC channel consists of a reference
buffer and a resistor-string DAC followed by an output buffer
amplifier. The voltage at the V

pin provides the reference

REF

voltage for the DAC. Figure 28 shows a block diagram of the
DAC architecture. Since the input coding to the DAC is
straight binary, the ideal output voltage is given by:

where:

D = decimal equivalent of the binary code which is loaded to
the DAC register:

0–255 for AD5334 (8 Bits)
0–1023 for AD5335/AD5336 (10 Bits)
0–4095 for AD5344 (12 Bits)

N = DAC resolution

Gain = Output Amplifier Gain (1 or 2)

V

REF

GAIN

INPUT

REGISTER

DAC

REGISTER

RESISTOR

STRING

OUTPUT

BUFFER AMPLIFIER

V

OUT

Figure 28. Single DAC Channel Architecture

REV. 0

VV

=××

OUT REF

D

Gain

N

2

–13–

AD5334/AD5335/AD5336/AD5344

Resistor String

The resistor string section is shown in Figure 29. It is simply a
string of resistors, each of value R. The digital code loaded
to

the DAC register determines at what node on the string the
voltage is tapped off to be fed into the output amplifier. The
voltage is tapped off by closing one of the switches connecting
the string to the amplifier. Because it is a string of resistors, it is
guaranteed monotonic.

V

REF

R

R

R

R

R

TO OUTPUT
AMPLIFIER

Figure 29. Resistor String

DAC Reference Input

The DACs operate with an external reference. The reference
inputs are unbuffered and have an input range of 0.25 V to V
The impedance per DAC is typically 180 kΩ for 0–V
and 90 kΩ for 0–2 V

mode. The AD5336 and AD5344 have

REF

REF

mode

DD

.

separate reference inputs for each DAC, while the AD5334 and
AD5335 have a reference inputs for each pair of DACS (A/B
and C/D).

Output Amplifier

The output buffer amplifier is capable of generating output
voltages to within 1 mV of either rail. Its actual range depends
on V

, GAIN, the load on V

REF

, and offset error.

OUT

If a gain of 1 is selected (GAIN = 0), the output range is 0.001 V
to V

.

REF

If a gain of 2 is selected (GAIN = 1), the output range is 0.001 V
to 2 V
is limited to V

. However because of clamping the maximum output

REF

– 0.001 V.

DD

The output amplifier is capable of driving a load of 2 kΩ to
GND or V

, in parallel with 500 pF to GND or VDD. The

DD

source and sink capabilities of the output amplifier can be seen
in Figure 15.

The slew rate is 0.7 V/µs with a half-scale settling time to ±0.5 LSB
(at 8 bits) of 6 µs with the output unloaded. See Figure 20.

PARALLEL INTERFACE

The AD5334, AD5336, and AD5344 load their data as a single
8-, 10-, or 12-bit word, while the AD5335 loads data as a low
byte of 8 bits and a high byte containing 2 bits.

Double-Buffered Interface

The AD5334/AD5335/AD5336/AD5344 DACs all have double­buffered interfaces consisting of an input register and a DAC
register. DAC data and GAIN inputs (when available) are written
to the input register under control of the Chip Select (CS) and
Write (WR).

Access to the DAC register is controlled by the LDAC function.
When LDAC is high, the DAC register is latched and the input
register may change state without affecting the contents of the
DAC register. However, when LDAC is brought low, the DAC
register becomes transparent and the contents of the input
register are transferred to it. The gain control signal is also
double-buffered and is only updated when LDAC is taken low.

This is useful if the user requires simultaneous updating of all
DACs and peripherals. The user may write to all input registers
individually and then, by pulsing the LDAC input low, all out­puts will update simultaneously.

Double-buffering is also useful where the DAC data is loaded in
two bytes, as in the AD5335, because it allows the whole data
word to be assembled in parallel before updating the DAC register.
This prevents spurious outputs that could occur if the DAC
register were updated with only the high byte or the low byte.

These parts contain an extra feature whereby the DAC register
is not updated unless its input register has been updated since
the last time that LDAC was brought low. Normally, when
LDAC is brought low, the DAC registers are filled with the
contents of the input registers. In the case of the AD5334/
AD5335/AD5336/AD5344, the part will only update the DAC
register if the input register has been changed since the last
time the DAC register was updated. This removes unnecessary
crosstalk.

Clear Input (CLR)

CLR is an active low, asynchronous clear that resets the input and
DAC registers. Note that the AD5344 has no CLR function.

Chip Select Input (CS)

CS is an active low input that selects the device.

Write Input (WR)

WR is an active low input that controls writing of data to the
device. Data is latched into the input register on the rising edge
of WR.

Load DAC Input (LDAC)

LDAC transfers data from the input register to the DAC register
(and hence updates the outputs). Use of the LDAC function
enables double buffering of the DAC and GAIN data. There
are two LDAC modes:

Synchronous Mode: In this mode the DAC register is updated
after new data is read in on the rising edge of the WR input.
LDAC can be tied permanently low or pulsed as in Figure 1.

Asynchronous Mode: In this mode the outputs are not updated
at the same time that the input register is written to. When LDAC
goes low the DAC register is updated with the contents of the
input register.

High-Byte Enable Input (HBEN)

High-Byte Enable is a control input on the AD5335 only that
determines if data is written to the high-byte input register or
the low-byte input register.

The low data byte of the AD5335 consists of data bits 0 to 7 at
data inputs DB
Bits 8 and 9 at data inputs DB

to DB7, while the high byte consists of Data

0

and DB1. DB2 to DB7 are

0

ignored during a high byte write. See Figure 30.

–14–

REV. 0

AD5334/AD5335/AD5336/AD5344

HIGH BYTE

DB9X

XX

DB7

DB6

X = UNUSED BIT

XX

LOW BYTE

DB4DB5

X

DB3

DB8

DB0DB1DB2

Figure 30. Data Format For AD5335

POWER-ON RESET

The AD5334/AD5335/AD5336/AD5344 are provided with a
power-on reset function, so that they power up in a defined state.
The power-on state is:

• Normal operation

•0 – V

output range

REF

• Output voltage set to 0 V

Both input and DAC registers are filled with zeros and remain
so until a valid write sequence is made to the device. This is
particularly useful in applications where it is important to know
the state of the DAC outputs while the device is powering up.

POWER-DOWN MODE

The AD5334/AD5335/AD5336/AD5344 have low power con­sumption, dissipating typically 1.5 mW with a 3 V supply and
3 mW with a 5 V supply. Power consumption can be further
re

duced when the DACs are not in use by putting them into

power-down mode, which is selected by taking pin PD low.

When the PD pin is high, the DACs work normally with a typical
power consumption of 600 µA at 5 V (500 µA at 3 V). In power­down mode, however, the supply current falls to 200 nA at 5 V
(80 nA at 3 V) when the DACs are powered down. Not only
does the supply current drop, but the output stage is also internally
switched from the output of the amplifier, making it open-circuit.
This has the advantage that the outputs are three-state while
the part is in power-down mode, and provides a defined input
condition for whatever is connected to the outputs of the
DAC amplifiers. The output stage is illustrated in Figure 31.

RESISTOR

STRING DAC

AMPLIFIER

POWER-DOWN

CIRCUITRY

V

OUT

Figure 31. Output Stage During Power-Down

The bias generator, the output amplifier, the resistor string, and
all other associated linear circuitry are all shut down when the
power-down mode is activated. However, the contents of the
registers are unaffected when in power-down. The time to exit
power-down is typically 2.5 µs for V

= 3 V. This is the time from a rising edge on the PD pin

V

DD

= 5 V and 5 µs when

DD

to when the output voltage deviates from its power-down volt­age. See Figure 22.

Table I. AD5334/AD5336/AD5344 Truth Table

CLR LDAC CS WR A1 A0 Function

1 1 1 X X X No Data Transfer
1 1 X 1 X X No Data Transfer
0 X X X X X Clear All Registers
11 0 0➝1 0 0 Load DAC A Input Register, GAIN A (AD5334/AD5336)
11 0 0➝1 0 1 Load DAC B Input Register, GAIN B (AD5334/AD5336)
11 0 0➝1 1 0 Load DAC C Input Register, GAIN C (AD5334/AD5336)
11 0 0➝1 1 1 Load DAC D Input Register, GAIN D (AD5334/AD5336)
1 0 X X X X Update DAC Registers

X = don’t care.

Table II. AD5335 Truth Table

CLR LDAC CS WR A1 A0 HBEN Function

1 1 1 X X X X No Data Transfer
1 1 X 1 X X X No Data Transfer
0 X X X X X X Clear All Registers
11 00➝1 0 0 0 Load DAC A Low Byte Input Register
11 00➝1 0 0 1 Load DAC A High Byte Input Register
11 00➝1 0 1 0 Load DAC B Low Byte Input Register
11 00➝1 0 1 1 Load DAC B High Byte Input Register
11 00➝1 1 0 0 Load DAC C Low Byte Input Register
11 00➝1 1 0 1 Load DAC C High Byte Input Register
11 00➝1 1 1 0 Load DAC D Low Byte Input Register
11 00➝1 1 1 1 Load DAC D High Byte Input Register
1 0 X X X X X Update DAC Registers

X = don’t care.

REV. 0

–15–

AD5334/AD5335/AD5336/AD5344

SUGGESTED DATABUS FORMATS

In many applications the GAIN input of the AD5334 and
AD5336 may be hard-wired. However, if more flexibility is
required, it can be included in a data bus. This enables the user
to software program GAIN, giving the option of doubling the
resolution in the lower half of the DAC range. In a bused system
GAIN may be treated as a data input since it is written to the
device during a write operation and takes effect when LDAC is
taken low. This means that the output amplifier gain of multiple
DAC devices can be controlled using a common GAIN line.

The AD5336 databus must be at least 10 bits wide and is best
suited to a 16-bit databus system.

Examples of data formats for putting GAIN on a 16-bit databus
are shown in Figure 32. Note that any unused bits above the
actual DAC data may be used for GAIN.

AD5336

XX

X

X = UNUSED BIT

X

GAIN

X

DB8DB9

DB7

DB3DB4DB5DB6

DB1DB2

DB0

Figure 32. AD5336 Data Format for Byte Load with GAIN
Data on 8-Bit Bus

APPLICATIONS INFORMATION
Typical Application Circuits

The AD5334/AD5335/AD5336/AD5344 can be used with a
wide range of reference voltages and offer full, one-quadrant
multiplying capability over a reference range of 0.25 V to V

DD

.
More typically, these devices may be used with a fixed, preci­sion reference voltage. Figure 33 shows a typical setup for the
devices when using an external reference connected to the refer­ence inputs. Suitable references for 5 V operation are the AD780
and REF192. For 2.5 V operation, a suitable external reference
would be the AD589, a 1.23 V bandgap reference.

V

= 2.5V TO 5.5V

DD

10␮F

V

V

REF

DD

*

AD5334/AD5335/

V

*

OUT

EXT
REF

V

GND

0.1␮F

IN

V

OUT

AD5336/AD5344

AD780/REF192

= 5V

WITH V

DD

OR

AD589 WITH V

*ONLY ONE CHANNEL OF V

DD

= 2.5V

REF

AND V

OUT

GND

SHOWN

Figure 33. AD5334/AD5335/AD5336/AD5344 Using
External Reference

Driving VDD from the Reference Voltage

If an output range of zero to VDD is required,
solution is to connect the reference inputs to V
may not be very accurate, and may be noisy, the

the simplest

.

As this supply

DD

devices
may be powered from the reference voltage, for example
using a 5 V reference such as the ADM663 or ADM666,
as shown in Figure 34.

6V TO 16V

0.1␮F

10␮F

V

DD

V

*

REF

AD5334/AD5335/

V

*

OUT

V

IN

ADM663/ADM666

VSET SHDN

GND

SENSE

V

OUT(2)

0.1␮F

AD5336/AD5344

GND

*ONLY ONE CHANNEL OF V

REF

AND V

OUT

SHOWN

Figure 34. Using an ADM663/ADM666 as Power and
Reference to AD5334/AD5335/AD5336/AD5344

Bipolar Operation Using the AD5334/AD5335/AD5336/AD5344

The AD5334/AD5335/AD5336/AD5344 have been designed
for single supply operation, but bipolar operation is achievable
using the circuit shown in Figure 35. The circuit shown has been
configured to achieve an output voltage range of –5 V < V

<

O

+5 V. Rail-to-rail operation at the amplifier output is achievable
using an AD820 or OP295 as the output amplifier.

The output voltage for any input code can be calculated as
follows:

VO= [(1 + R4/R3) × (R2/(R1 + R2) × (2 × V

REF

× D/

N

2

)] – R4 × V

REF

/R3

where:

D is the decimal equivalent of the code loaded to the DAC, N is
DAC resolution and V

is the reference voltage input.

REF

With:

V

= 2.5 V

REF

R1 = R3 = 10 kΩ
R2 = R4 = 20 kΩ and V
V

= (10 × D/2N) – 5

OUT

0.1␮F

V

IN

EXT
REF

AD589 WITH V

*ONLY ONE CHANNEL OF V

V

OUT

GND

AD780/REF192
WITH V

= 5V

DD

OR

DD

0.1␮F

= 2.5V

= 5 V.

DD

VDD = 5V

10␮F

V

V

*

REF

AD5334/AD5335/

AD5336/AD5344

GND

AND V

REF

OUT

DD

V

SHOWN

R3

10k⍀

OUT

R4

20k⍀

+5V

ⴞ5V

R2
20k⍀

–5V

R1

10k⍀

*

Figure 35. Bipolar Operation using the AD5334/AD5335/
AD5336/AD5344

–16–

REV. 0

AD5334/AD5335/AD5336/AD5344

AD5334/AD5335/

AD5336/AD5344

GND

VDD = 5V

EXT
REF

V

OUT

*

AD780/REF192
WITH V

DD

= 5V

GND

V

IN

V

OUT

V

REF

*

V

DD

4.7k⍀

5V

*ONLY ONE CHANNEL OF V

REF

AND V

OUT

SHOWN

0.1␮F

0.1␮F

10␮F

470⍀

LOAD

V

SOURCE

AD820/

OP295

Decoding Multiple AD5334/AD5335/AD5336/AD5344

The CS pin on these devices can be used in applications to decode
a number of DACs. In this application, all DACs in the system
receive the same data and WR pulses, but only the CS to one of
the DACs will be active at any one time, so data will only be
written to the DAC whose CS is low. If multiple AD5343s are
being used, a common HBEN line will also be required to
determine if the data is written to the high-byte or low-byte
register of the selected DAC.

The 74HC139 is used as a 2- to 4-line decoder to address any
of the DACs in the system. To prevent timing errors from oc­curring, the enable input should be brought to its inactive state
while the coded address inputs are changing state. Figure 36 shows
a diagram of a typical setup for decoding multiple devices in a
system. Once data has been written sequentially to all DACs in
a system, all the DACs can be updated simultaneously using a
common LDAC line. A common CLR line can also be used to
reset all DAC outputs to zero (except on the AD5344).

AD5334/AD5335/

AD5336/AD5344

A1
A0
HBEN*

WR
LDAC
CLR
CS

AD5334/AD5335/

AD5336/AD5344

A1
A0
HBEN*

WR
LDAC
CLR
CS

AD5334/AD5335/

AD5336/AD5344

A1
A0
HBEN*

WR
LDAC
CLR
CS

AD5334/AD5335/

AD5336/AD5344

A1
A0
HBEN*

WR
LDAC
CLR
CS

*AD5335 ONLY

DATA

INPUTS

DATA

INPUTS

DATA

INPUTS

DATA

INPUTS

DATA BUS

HBEN

WR

LDAC

CLR

ENABLE

CODED

ADDRESS

A0
A1

V

DD

V

CC

1G

1A

1B

74HC139

DGND

1Y0

1Y1

1Y2

1Y3

Figure 36. Decoding Multiple DAC Devices

used for some other purpose. The AD5336 and AD5344 have
separate reference inputs for each DAC.

The upper and lower limits for the test are loaded to DACs A
and B which, in turn, set the limits on the CMP04. If a signal at
the V

input is not within the programmed window, an LED

IN

will indicate the fail condition.

5V

0.1␮F

V

REF

10␮F

V

REF

V

REF

AD5336/AD5344

V

A

V

OUT

B

V

GND

DD

OUT

V

IN

A

1/2

CMP04

B

1k⍀ 1k⍀

FAIL PASS

PASS/
FAIL

1/6 74HC05

Figure 37. Programmable Window Detector

Programmable Current Source

Figure 38 shows the AD5334/AD5335/AD5336/AD5344 used
as the control element of a programmable current source. In this
example, the full-scale current is set to 1 mA. The output volt­age from the DAC is applied across the current setting resistor
of 4.7 kΩ in series with the 470 Ω adjustment potentiometer,
which gives an adjustment of about ±5%. Suitable transistors to
place in the feedback loop of the amplifier include the BC107
and the 2N3904, which enable the current source to operate
from a minimum V

of 6 V. The operating range is deter-

SOURCE

mined by the operating characteristics of the transistor. Suitable
amplifiers include the AD820 and the OP295, both having rail­to-rail operation on their outputs. The current for any digital
input code and resistor value can be calculated as follows:

D

N

mA

R

×()2

Where:

IGV

=× ×

REF

G is the gain of the buffer amplifier (1 or 2)
D is the digital input code
N is the DAC resolution (8, 10, or 12 bits)
R is the sum of the resistor plus adjustment potentiometer in kΩ

AD5334/AD5335/AD5336/AD5344 as a Digitally Programmable
Window Detector

A digitally programmable upper/lower limit detector using two
of the DACs in the AD5334/AD5335/AD5336/AD5344 is
shown in Figure 37.

Any pair of DACs in the device may be used, but for simplicity
the description will refer to DACs A and B.

Care must be taken to connect the correct reference inputs to
the reference source. The AD5334 and AD5335 have only two
reference inputs, V
DACs C and D. If DACs A and B are used (for example) then
only V

REF

REV. 0

A/B for DACs A and B and V

REF

A/B is needed. DACs C and D and V

REF

C/D for

REF

C/D may be

Figure 38. Programmable Current Source

–17–

AD5334/AD5335/AD5336/AD5344

Coarse and Fine Adjustment Using the AD5334/AD5335/
AD5336/AD5344

Two of the DACs in the AD5334/AD5335/AD5336/AD5344 can
be paired together to form a coarse and fine adjustment function,
as shown in Figure 39. As with the window comparator previ­ously described, the description will refer to DACs A, and B and
the reference connections will depend on the actual device used.

DAC A is used to provide the coarse adjustment while DAC B
provides the fine adjustment. Varying the ratio of R1 and R2 will
change the relative effect of the coarse and fine adjustments. With
the resistor values shown the output amplifier has unity gain for
the DAC A output, so the output range is zero to (V
For DAC B the amplifier has a gain of 7.6 × 10

– 1 LSB).

REF

–3

, giving DAC B

a range equal to 2 LSBs of DAC A.

The circuit is shown with a 2.5 V reference, but reference volt­ages up to V

may be used. The op amps indicated will allow a

DD

rail-to-rail output swing.

V

IN

EXT

V

OUT

REF

GND

AD780/REF192
WITH V

= 5V

DD

0.1␮F

0.1␮F

VDD = 5V

10␮F

V

DD

A

V

REF

AD5336/AD5344

V

B

REF

GND

V

V

OUT

OUT

R3

51.2k⍀

A

51.2k⍀

B

390⍀

R4

390⍀

5V

V

OUT

R1

R2

Power Supply Bypassing and Grounding

In any circuit where accuracy is important, careful consideration
of the power supply and ground return layout helps to ensure
the rated performance. The printed circuit board on which the
AD5334/AD5335/AD5336/AD5344 is mounted should be
designed so that the analog and digital sections are separated,
and confined to certain areas of the board. If the device is in a
system where multiple devices require an AGND-to-DGND
connection, the connection should be made at one point only.
The star ground point should be established as closely as pos­sible to the device. The AD5334/AD5335/AD5336/AD5344
should have ample supply bypassing of 10 µF in parallel with

0.1 µF on the supply located as close to the package as possible,
ideally right up against the device. The 10 µF capacitors are the
tantalum bead type. The 0.1 µF capacitor should have low
Effective Series Resistance (ESR) and Effective Series Inductance
(ESI), like the common ceramic types that provide a low imped­ance path to ground at high frequencies to handle transient
currents due to internal logic switching.

The power supply lines of the device should use as large a trace
as possible to provide low impedance paths and reduce the
effects of glitches on the power supply line. Fast switching sig­nals such as clocks should be shielded with digital ground to
avoid radiating noise to other parts of the board, and should
never be run near the reference inputs. Avoid crossover of digital
and analog signals. Traces on opposite sides of the board should
run at right angles to each other. This reduces the effects of
feedthrough through the board. A microstrip technique is by
far the best, but not always possible with a double-sided board.
In this technique, the component side of the board is dedicated
to ground plane while signal traces are placed on the solder side.

Figure 39. Coarse and Fine Adjustment

–18–

REV. 0

AD5334/AD5335/AD5336/AD5344

Table III. Overview of AD53xx Parallel Devices

Part No. Resolution DNL V

SINGLES BUF GAIN HBEN CLR

AD5330 8 ± 0.25 1 6 µs ✓✓ ✓ TSSOP 20
AD5331 10 ± 0.5 1 7 µs ✓✓TSSOP 20
AD5340 12 ± 1.0 1 8 µs ✓✓ ✓ TSSOP 24
AD5341 12 ± 1.0 1 8 µs ✓✓✓✓TSSOP 20

DUALS

AD5332 8 ± 0.25 2 6 µs ✓ TSSOP 20
AD5333 10 ± 0.5 2 7 µs ✓✓ ✓ TSSOP 24
AD5342 12 ± 1.0 2 8 µs ✓✓ ✓ TSSOP 28
AD5343 12 ± 1.0 1 8 µs ✓✓TSSOP 20

QUADS

AD5334 8 ± 0.25 2 6 µs ✓✓TSSOP 24
AD5335 10 ± 0.5 2 7 µs ✓✓TSSOP 24
AD5336 10 ± 0.5 4 7 µs ✓✓TSSOP 28
AD5344 12 ± 1.0 4 8 µs TSSOP 28

Part No. Resolution No. of DACS DNL Interface Settling Time Package Pins

SINGLES

AD5300 8 1 ±0.25 SPI 4 µs SOT-23, MicroSOIC 6, 8
AD5310 10 1 ± 0.5 SPI 6 µs SOT-23, MicroSOIC 6, 8
AD5320 12 1 ± 1.0 SPI 8 µs SOT-23, MicroSOIC 6, 8

AD5301 8 1 ±0.25 2-Wire 6 µs SOT-23, MicroSOIC 6, 8
AD5311 10 1 ± 0.5 2-Wire 7 µs SOT-23, MicroSOIC 6, 8
AD5321 12 1 ± 1.0 2-Wire 8 µs SOT-23, MicroSOIC 6, 8

DUALS

AD5302 8 2 ±0.25 SPI 6 µs MicroSOIC 8
AD5312 10 2 ± 0.5 SPI 7 µs MicroSOIC 8
AD5322 12 2 ± 1.0 SPI 8 µs MicroSOIC 8

AD5303 8 2 ±0.25 SPI 6 µs TSSOP 16
AD5313 10 2 ± 0.5 SPI 7 µs TSSOP 16
AD5323 12 2 ± 1.0 SPI 8 µs TSSOP 16

QUADS

AD5304 8 4 ±0.25 SPI 6 µs MicroSOIC 10
AD5314 10 4 ± 0.5 SPI 7 µs MicroSOIC 10
AD5324 12 4 ± 1.0 SPI 8 µs MicroSOIC 10

AD5305 8 4 ±0.25 2-Wire 6 µs MicroSOIC 10
AD5315 10 4 ± 0.5 2-Wire 7 µs MicroSOIC 10
AD5325 12 4 ± 1.0 2-Wire 8 µs MicroSOIC 10

AD5306 8 4 ±0.25 2-Wire 6 µs TSSOP 16
AD5316 10 4 ± 0.5 2-Wire 7 µs TSSOP 16
AD5326 12 4 ± 1.0 2-Wire 8 µs TSSOP 16

AD5307 8 4 ±0.25 SPI 6 µs TSSOP 16
AD5317 10 4 ± 0.5 SPI 7 µs TSSOP 16
AD5327 12 4 ± 1.0 SPI 8 µs TSSOP 16

Visit our web-page at http://www.analog.com/support/standard_linear/selection_guides/AD53xx.html

Pins Settling Time Additional Pin Functions Package Pins

REF

Table IV. Overview of AD53xx Serial Devices

REV. 0

–19–

AD5334/AD5335/AD5336/AD5344

Dimensions shown in inches and (mm).

24-Lead Thin Shrink Small Outline Package TSSOP

0.311 (7.90)

0.303 (7.70)

OUTLINE DIMENSIONS

(RU-24)

24 13

PIN 1

0.006 (0.15)

0.002 (0.05)

SEATING

0.0256 (0.65)

PLANE

BSC

0.0118 (0.30)

0.0075 (0.19)

0.177 (4.50)

0.169 (4.30)

121

0.0433 (1.10)
MAX

0.256 (6.50)

0.246 (6.25)

0.0079 (0.20)

0.0035 (0.090)

8ⴗ
0ⴗ

28-Lead Thin Shrink Small Outline Package TSSOP

(RU-28)

0.386 (9.80)

0.378 (9.60)

28 15

PIN 1

0.006 (0.15)

0.002 (0.05)

0.177 (4.50)

0.169 (4.30)

141

0.0433 (1.10)
MAX

0.256 (6.50)

0.246 (6.25)

C3830–2.5–4/00 (rev. 0)

0.028 (0.70)

0.020 (0.50)

SEATING

PLANE

0.0256 (0.65)
BSC

0.0118 (0.30)

0.0075 (0.19)

–20–

0.0079 (0.20)

0.0035 (0.090)

8ⴗ
0ⴗ

0.028 (0.70)

0.020 (0.50)

PRINTED IN U.S.A.

REV. 0