Datasheet AD5341BRU, AD5341, AD5331BRU, AD5331, AD5330BRU Datasheet (Analog Devices)

...

Page 1

2.5 V to 5.5 V, 115 ␮A, Parallel Interface

Single Voltage-Output 8-/10-/12-Bit DACs

FEATURES AD5330: Single 8-Bit DAC in 20-Lead TSSOP AD5331: Single 10-Bit DAC in 20-Lead TSSOP AD5340: Single 12-Bit DAC in 24-Lead TSSOP AD5341: Single 12-Bit DAC in 20-Lead TSSOP Low Power Operation: 115 ␮A @ 3 V, 140 ␮A @ 5 V Power-Down to 80 nA @ 3 V, 200 nA @ 5 V via PD Pin

2.5 V to 5.5 V Power Supply Double-Buffered Input Logic Guaranteed Monotonic by Design Over All Codes Buffered/Unbuffered Reference Input Options Output Range: 0–V

or 0–2 V

REF

Power-On Reset to Zero Volts Simultaneous Update of DAC Outputs via LDAC Pin Asynchronous CLR Facility Low Power Parallel Data Interface On-Chip Rail-to-Rail Output Buffer Ampliﬁers Temperature Range: –40ⴗC to +105ⴗC

APPLICATIONS Portable Battery-Powered Instruments Digital Gain and Offset Adjustment Programmable Voltage and Current Sources Programmable Attenuators Industrial Process Control

AD5330/AD5331/AD5340/AD5341*

GENERAL DESCRIPTION

The AD5330/AD5331/AD5340/AD5341 are single 8-, 10-, and 12-bit DACs. They operate from a 2.5 V to 5.5 V supply consuming just 115 µA at 3 V, and feature a power-down mode that further reduces the current to 80 nA. These devices incorporate an on-chip output buffer that can drive the output to both supply rails, while the AD5330, AD5340, and AD5341 allow a choice of buffered or unbuffered reference input.

The AD5330/AD5331/AD5340/AD5341 have a parallel interface. CS selects the device and data is loaded into the input registers on the rising edge of WR.

The GAIN pin allows the output range to be set at 0 V to V or 0 V to 2 × V

Input data to the DACs is double-buffered, allowing simultaneous update of multiple DACs in a system using the LDAC pin.

An asynchronous CLR input is also provided, which resets the contents of the Input Register and the DAC Register to all zeros. These devices also incorporate a power-on reset circuit that ensures that the DAC output powers on to 0 V and remains there until valid data is written to the device.

The AD5330/AD5331/AD5340/AD5341 are available in Thin Shrink Small Outline Packages (TSSOP).

REF

AD5330 FUNCTIONAL BLOCK DIAGRAM

(Other Diagrams Inside)

POWER-ON

RESET

BUF

GAIN

. .

CLR

LDAC

*Protected by U.S. Patent Number 5,969,657; other patents pending.

INTER-

FACE

LOGIC

RESET

INPUT

DAC

REV. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

REF

8-BIT

DAC

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2000

AD5330

BUFFER

POWER-DOWN

LOGIC

GND

OUT

Page 2

AD5330/AD5331/AD5340/AD5341–SPECIFICATIONS

(VDD = 2.5 V to 5.5 V, V

Parameter

DC PERFORMANCE

DAC REFERENCE INPUT

OUTPUT CHARACTERISTICS

LOGIC INPUTS

POWER REQUIREMENTS

NOTES

See Terminology section.

Temperature range: B Version: –40°C to +105°C; typical speciﬁcations are at 25°C.

Linearity is tested using a reduced code range: AD5330 (Code 8 to 255); AD5331 (Code 28 to 1023); AD5340/AD5341 (Code 115 to 4095).

DC speciﬁcations tested with output unloaded.

This corresponds to x codes. x = Deadband voltage/LSB size.

Guaranteed by design and characterization, not production tested.

In order for the ampliﬁer output to reach its minimum voltage, Offset Error must be negative. In order for the ampliﬁer output to reach its maximum voltage, V “Offset plus Gain” Error must be positive.

Speciﬁcations subject to change without notice.

AD5330

Resolution 8 Bits Relative Accuracy ± 0.15 ± 1 LSB Differential Nonlinearity ± 0.02 ± 0.25 LSB Guaranteed Monotonic By Design Over All Codes

AD5331

Resolution 10 Bits Relative Accuracy ± 0.5 ± 4 LSB Differential Nonlinearity ± 0.05 ± 0.5 LSB Guaranteed Monotonic By Design Over All Codes

AD5340/AD5341

Resolution 12 Bits Relative Accuracy ± 2 ± 16 LSB

Differential Nonlinearity ± 0.2 ± 1 LSB Guaranteed Monotonic By Design Over All Codes Offset Error ± 0.4 ± 3 % of FSR Gain Error ± 0.15 ± 1 % of FSR Lower Deadband Upper Deadband 10 60 mV V Offset Error Drift Gain Error Drift DC Power Supply Rejection Ratio

Input Range 1 V

REF

Input Impedance >10 MΩ Buffered Reference (AD5330, AD5340, and AD5341)

REF

Reference Feedthrough –90 dB Frequency = 10 kHz

Minimum Output Voltage4, Maximum Output Voltage DC Output Impedance 0.5 Ω Short Circuit Current 25 mA VDD = 5 V

Power-Up Time 2.5 µs Coming Out of Power-Down Mode. VDD = 5 V

Input Current ± 1 µA VIL, Input Low Voltage 0.8 V V

VIH, Input High Voltage 2.4 V VDD = 5 V ± 10%

Pin Capacitance 3 pF

IDD (Normal Mode) DACs active and excluding load currents. Unbuffered

VDD = 4.5 V to 5.5 V 140 250 µA Reference. VIH = VDD, V

VDD = 2.5 V to 3.6 V 115 200 µAI

IDD (Power-Down Mode)

VDD = 4.5 V to 5.5 V 0.2 1 µA

VDD = 2.5 V to 3.6 V 0.08 1 µA

= 2 V. RL = 2 k⍀ to GND; CL = 200 pF to GND; all speciﬁcations T

REF

B Version

Min Typ Max Unit Conditions/Comments

3, 4

0.25 V

10 60 mV Lower Deadband Exists Only if Offset Error Is Negative

–12 ppm of FSR/°C –5 ppm of FSR/°C –60 dB ∆VDD = ±10%

V Buffered Reference (AD5330, AD5340, and AD5341) V Unbuffered Reference

180 kΩ Unbuffered Reference. Gain = 1, Input Impedance = R 90 kΩ Unbuffered Reference. Gain = 2, Input Impedance = R

4, 7

0.001 V min Rail-to-Rail Operation VDD–0.001 V max

15 mA VDD = 3 V

5 µs Coming Out of Power-Down Mode. VDD = 3 V

0.6 V VDD = 3 V ± 10%

0.5 V VDD = 2.5 V

2.1 V VDD = 3 V ± 10%

2.0 V VDD = 2.5 V

2.5 5.5 V

to T

MIN

In Buffered Mode extra current is (5 + V where R

unless otherwise noted.)

MAX

= 5 V. Upper Deadband Exists Only if V

= 5 V ± 10%

= GND.

increases by 50 µA at V

is the resistance of the resistor string.

DAC

> VDD – 100 mV.

REF

REF/RDAC

REF = VDD

= VDD and

REF

) µA,

DAC

–2–

REV. 0

Page 3

AD5330/AD5331/AD5340/AD5341

(VDD = 2.5 V to 5.5 V. RL = 2 k⍀ to GND; CL = 200 pF to GND; all speciﬁcations T

AC CHARACTERISTICS

Parameter

Output Voltage Settling Time V

unless otherwise noted.)

B Version Min Typ Max Unit Conditions/Comments

= 2 V. See Figure 20

REF

AD5330 6 8 µs 1/4 Scale to 3/4 Scale Change (40 H to C0 H) AD5331 7 9 µs 1/4 Scale to 3/4 Scale Change (100 H to 300 H) AD5340 8 10 µs 1/4 Scale to 3/4 Scale Change (400 H to C00 H)

AD5341 8 10 µs 1/4 Scale to 3/4 Scale Change (400 H to C00 H) Slew Rate 0.7 V/µs Major Code Transition Glitch Energy 6 nV-s 1 LSB Change Around Major Carry Digital Feedthrough 0.5 nV-s Multiplying Bandwidth 200 kHz V Total Harmonic Distortion –70 dB V

NOTES

Guaranteed by design and characterization, not production tested.

See Terminology section.

Temperature range: B Version: –40°C to +105°C; typical speciﬁcations are at 25 °C.

Speciﬁcations subject to change without notice.

= 2 V ± 0.1 V p-p. Unbuffered Mode

REF

= 2.5 V ± 0.1 V p-p. Frequency = 10 kHz

REF

MIN

to T

MAX

MIN

DATA,

GAIN,

HBEN

LDAC

1, 2, 3

(VDD = 2.5 V to 5.5 V, All speciﬁcations T

, T

MAX

BUF,

CLR

NOTES:

SYNCHRONOUS LDAC UPDATE MODE

ASYNCHRONOUS LDAC UPDATE MODE

Unit Condition/Comments

to T

MIN

MAX

TIMING CHARACTERISTICS

Parameter Limit at T

NOTES

Guaranteed by design and characterization, not production tested.

All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.

See Figure 1.

0 ns min CS to WR Setup Time 0 ns min CS to WR Hold Time 20 ns min WR Pulsewidth 5 ns min Data, GAIN, BUF, HBEN Setup Time

4.5 ns min Data, GAIN, BUF, HBEN Hold Time 5 ns min Synchronous Mode. WR Falling to LDAC Falling. 5 ns min Synchronous Mode. LDAC Falling to WR Rising.

4.5 ns min Synchronous Mode. WR Rising to LDAC Rising. 5 ns min Asynchronous Mode. LDAC Rising to WR Rising.

4.5 ns min Asynchronous Mode. WR Rising to LDAC Falling. 20 ns min LDAC Pulsewidth 20 ns min CLR Pulsewidth 50 ns min Time Between WR Cycles

Figure 1. Parallel Interface Timing Diagram

unless otherwise noted.)

REV. 0

–3–

Page 4

AD5330/AD5331/AD5340/AD5341

WARNING!

ESD SENSITIVE DEVICE

ABSOLUTE MAXIMUM RATINGS*

(TA = 25°C unless otherwise noted)

VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

Digital Input Voltage to GND . . . . . . . –0.3 V to V

Digital Output Voltage to GND . . . . . –0.3 V to V

Reference Input Voltage to GND . . . . –0.3 V to V

to GND . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V

OUT

+ 0.3 V

Operating Temperature Range

Reflow Soldering

Peak Temperature . . . . . . . . . . . . . . . . . . . . . 220 +5/–0°C

Time at Peak Temperature . . . . . . . . . . . . 10 sec to 40 sec

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this speciﬁcation is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Industrial (B Version) . . . . . . . . . . . . . . . –40°C to +105°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C

TSSOP Package

Power Dissipation . . . . . . . . . . . . . . . (T

Thermal Impedance (20-Lead TSSOP) . . . . . 143°C/W

Thermal Impedance (24-Lead TSSOP) . . . . . 128°C/W

Thermal Impedance (20-Lead TSSOP) . . . . . . 45°C/W

Thermal Impedance (24-Lead TSSOP) . . . . . . 42°C/W

max – TA)/θJA mW

ORDERING GUIDE

Package

Model Temperature Range Package Description Option

AD5330BRU –40°C to +105°C TSSOP (Thin Shrink Small Outline Package) RU-20 AD5331BRU –40°C to +105°C TSSOP (Thin Shrink Small Outline Package) RU-20 AD5340BRU –40°C to +105°C TSSOP (Thin Shrink Small Outline Package) RU-24 AD5341BRU –40°C to +105°C TSSOP (Thin Shrink Small Outline Package) RU-20

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD5330/AD5331/AD5340/AD5341 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

–4–

REV. 0

Page 5

AD5330/AD5331/AD5340/AD5341

TOP VIEW

(Not to Scale)

AD5330

LDAC

GAIN

GND

BUF

REF

OUT

8-BIT

CLR

NC = NO CONNECT

BUF

GAIN

CLR

LDAC

AD5330 FUNCTIONAL BLOCK DIAGRAM

BUFFER

AD5330

POWER-DOWN

LOGIC

GND

OUT

REF

POWER-ON

RESET

INPUT

. .

INTER-

FACE

LOGIC

RESET

DAC

8-BIT

DAC

AD5330 PIN CONFIGURATION

AD5330 PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Function

1 BUF Buffer Control Pin. This pin controls whether the reference input to the DAC is buffered or unbuffered. 2 NC No Connect. 3V 4V

REF

OUT

Reference Input. Output of DAC. Buffered output with rail-to-rail operation.

5 GND Ground reference point for all circuitry on the part. 6 CS Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface. 7 WR Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface. 8 GAIN Gain Control Pin. This controls whether the output range from the DAC is 0–V

or 0–2 V

REF

REF.

9 CLR Asynchronous active low control input that clears all input registers and DAC registers to zero. 10 LDAC Active low control input that updates the DAC registers with the contents of the input registers. 11 PD Power-Down Pin. This active low control pin puts the DAC into power-down mode. 12 V

Power Supply Input. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND.

13–20 DB0–DB

Eight Parallel Data Inputs. DB7 is the MSB of these eight bits.

REV. 0

–5–

Page 6

AD5330/AD5331/AD5340/AD5341

BUF

CLR

LDAC

AD5331 FUNCTIONAL BLOCK DIAGRAM

REF

POWER-ON

RESET

INPUT

. .

INTER-

FACE

LOGIC

RESET

DAC

10-BIT

DAC

AD5331

BUFFER

POWER-DOWN

LOGIC

PD GND

OUT

AD5331 PIN CONFIGURATION

REF

OUT

GND

GAIN

CLR

LDAC

(Not to Scale)

10-BIT

AD5331

TOP VIEW

AD5331 PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Function

1DB 2DB 3V 4V

REF

OUT

Parallel Data Input. Most Significant Bit of Parallel Data Input. Unbuffered Reference Input. Output of DAC. Buffered output with rail-to-rail operation.

or 0–2 V

REF

9 CLR Active low control input that clears all input registers and DAC registers to zero. 10 LDAC Active low control input that updates the DAC registers with the contents of the input registers. 11 PD Power-Down Pin. This active low control pin puts the DAC into power-down mode. 12 V

Power Supply Input. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND.

13–20 DB0–DB

Eight Parallel Data Inputs.

–6–

REV. 0

Page 7

AD5330/AD5331/AD5340/AD5341

AD5340 PIN CONFIGURATION

BUF

REF

OUT

GND

GAIN

CLR

LDAC

NC = NO CONNECT

12-BIT

AD5340

TOP VIEW

(Not to Scale)

BUF

GAIN

CLR

LDAC

AD5340 FUNCTIONAL BLOCK DIAGRAM

REF

POWER-ON

RESET

INPUT

. .

INTER-

FACE

LOGIC

RESET

DAC

12-BIT

DAC

AD5340

BUFFER

POWER-DOWN

LOGIC

GND

OUT

AD5340 PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Function

1DB 2DB

Parallel Data Input.

Most Significant Bit of Parallel Data Input. 3 BUF Buffer Control Pin. This pin controls whether the reference input to the DAC is buffered or unbuffered. 4V 5V

REF

OUT

Reference Input.

Output of DAC. Buffered output with rail-to-rail operation. 6 NC No Connect. 7 GND Ground reference point for all circuitry on the part. 8 CS Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface. 9 WR Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface. 10 GAIN Gain Control Pin. This controls whether the output range from the DAC is 0–V

or 0–2 V

REF

REF.

11 CLR Asynchronous active low control input that clears all input registers and DAC registers to zero. 12 LDAC Active low control input that updates the DAC registers with the contents of the input registers. 13 PD Power-Down Pin. This active low control pin puts the DAC into power-down mode. 14 V

Power Supply Input. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled

with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND. 15–24 DB0–DB

10 Parallel Data Inputs.

REV. 0

–7–

Page 8

AD5330/AD5331/AD5340/AD5341

TOP VIEW

(Not to Scale)

AD5341

LDAC

GAIN

GND

REF

OUT

12-BIT

CLR

HBEN

BUF

AD5341 PIN CONFIGURATION

BUF

GAIN

HBEN

CLR

LDAC

AD5341 FUNCTIONAL BLOCK DIAGRAM

REF

POWER-ON

RESET

. .

INTER-

FACE

LOGIC

RESET

HIGH BYTE

LOW BYTE

DAC

12-BIT

DAC

BUFFER

AD5341

POWER-DOWN

LOGIC

GND

OUT

AD5341 PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Function

1 HBEN High Byte Enable Pin. This pin is used when writing to the device to determine if data is written

to the high byte register or the low byte register. 2 BUF Buffer Control Pin. This pin controls whether the reference input to the DAC is buffered or unbuffered. 3V 4V

REF

OUT

Reference Input.

Output of DAC. Buffered output with rail-to-rail operation. 5 GND Ground reference point for all circuitry on the part. 6 CS Active low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface. 7 WR Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface. 8 GAIN Gain Control Pin. This controls whether the output range from the DAC is 0–V

or 0–2 V

REF

REF.

Power Supply Input. These parts can operate from 2.5 V to 5.5 V and the supply should be decoupled

with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND. 13–20 DB0–DB

Eight Parallel Data Inputs. DB7 is the MSB of these eight bits.

–8–

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Page 9

TERMINOLOGY

OUTPUT

VOLTAGE

DAC CODE

POSITIVE

OFFSET

GAIN ERROR

AND

OFFSET ERROR

ACTUAL

IDEAL

RELATIVE ACCURACY

For the DAC, Relative Accuracy or Integral Nonlinearity (INL) is a measure of the maximum deviation, in LSBs, from a straight line passing through the actual endpoints of the DAC transfer function. Typical INL versus Code plot can be seen in Figures 5, 6, and 7.

DIFFERENTIAL NONLINEARITY

Differential Nonlinearity (DNL) is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A speciﬁed differential nonlinearity of ± 1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic by design. Typical DNL versus Code plot can be seen in Figures 8, 9, and 10.

GAIN ERROR

This is a measure of the span error of the DAC (including any error in the gain of the buffer ampliﬁer). It is the deviation in slope of the actual DAC transfer characteristic from the ideal expressed as a percentage of the full-scale range. This is illustrated in Figure 2.

OFFSET ERROR

This is a measure of the offset error of the DAC and the output ampliﬁer. It is expressed as a percentage of the full-scale range.

If the offset voltage is positive, the output voltage will still be positive at zero input code. This is shown in Figure 3. Because the DACs operate from a single supply, a negative offset cannot appear at the output of the buffer ampliﬁer. Instead, there will be a code close to zero at which the ampliﬁer output saturates (ampliﬁer footroom). Below this code there will be a deadband over which the output voltage will not change. This is illustrated in Figure 4.

AD5330/AD5331/AD5340/AD5341

Figure 3. Positive Offset Error and Gain Error

OFFSET ERROR

OUTPUT

VOLTAGE

ACTUAL

IDEAL

NEGATIVE

OFFSET

DAC CODE

GAIN ERROR

AND

VOLTAGE

REV. 0

OUTPUT

DAC CODE

Figure 2. Gain Error

POSITIVE

GAIN ERROR

NEGATIVE

GAIN

ERROR

ACTUAL

IDEAL

–9–

DEADBAND CODES

AMPLIFIER

FOOTROOM

(~1mV)

NEGATIVE

OFFSET

Figure 4. Negative Offset Error and Gain Error

Page 10

AD5330/AD5331/AD5340/AD5341

OFFSET ERROR DRIFT

This is a measure of the change in Offset Error with changes in temperature. It is expressed in (ppm of full-scale range)/°C.

GAIN ERROR DRIFT

This is a measure of the change in Gain Error with changes in temperature. It is expressed in (ppm of full-scale range)/°C.

POWER-SUPPLY REJECTION RATIO (PSRR)

This indicates how the output of the DAC is affected by changes in the supply voltage. PSRR is the ratio of the change in V change in V in dBs. V

REFERENCE FEEDTHROUGH

for full-scale output of the DAC. It is measured

is held at 2 V and VDD is varied ± 10%.

REF

OUT

to a

This is the ratio of the amplitude of the signal at the DAC output to the reference input when the DAC output is not being updated (i.e., LDAC is high). It is expressed in dBs.

MAJOR-CODE TRANSITION GLITCH ENERGY

Major-Code Transition Glitch Energy is the energy of the impulse injected into the analog output when the DAC changes state. It is normally speciﬁed as the area of the glitch in nV secs and is measured when the digital code is changed by 1 LSB at the major carry transition (011 . . . 11 to 100 ...00 or 100...00 to 011 . . . 11).

DIGITAL FEEDTHROUGH

Digital Feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital input pins of the device, but is measured when the DAC is not being written to (CS held high). It is speciﬁed in nV secs and is measured with a full-scale change on the digital input pins, i.e., from all 0s to all 1s and vice versa.

MULTIPLYING BANDWIDTH

The ampliﬁers within the DAC have a ﬁnite bandwidth. The Multiplying Bandwidth is a measure of this. A sine wave on the reference (with full-scale code loaded to the DAC) appears on the output. The Multiplying Bandwidth is the frequency at which the output amplitude falls to 3 dB below the input.

TOTAL HARMONIC DISTORTION

This is the difference between an ideal sine wave and its attenuated version using the DAC. The sine wave is used as the reference for the DAC and the THD is a measure of the harmonics present on the DAC output. It is measured in dBs.

–10–

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Page 11

Typical Performance Characteristics–

TA = 25ⴗC V

= 5V

CODE

DNL ERROR – LSBs

1.0

0.5

–1.0

0 1000 40002000 3000

–0.5

AD5330/AD5331/AD5340/AD5341

1.0

TA = 25ⴗC V

= 5V

0.5

INL ERROR – LSBs

–0.5

–1.0

50 250100 150 200

CODE

Figure 5. AD5330 Typical INL Plot

0.3

TA = 25ⴗC V

= 5V

0.2

0.1

–0.1

DNL ERROR – LSBs

–0.2

TA = 25ⴗC V

= 5V

–1

INL ERROR – LSBs

–2

–3

200 1000

400 600 800

CODE

Figure 6. AD5331 Typical INL Plot

0.6 TA = 25ⴗC V

= 5V

0.4

0.2

–0.2

DNL ERROR – LSBs

–0.4

TA = 25ⴗC

= 5V

–4

INL ERROR – LSBs

–8

–12

0 4000

1000 2000 3000

CODE

Figure 7. AD5340 Typical INL Plot

–0.3

0 50 250

100 150 200

CODE

Figure 8. AD5330 Typical DNL Plot

1.00

0.75

0.50

0.25

0.00

–0.25

ERROR – LSBs

–0.50

–0.75

–1.00

2345

MAX INL

MAX DNL

MIN DNL

MIN INL

– V

REF

Figure 11. AD5330 INL and DNL Error vs. V

REF

VDD = 5V

= 25ⴗC

–0.6

200 1000

400 600 800

CODE

Figure 9. AD5331 Typical DNL Plot

1.00 VDD = 5V

0.75

0.50

0.25

–0.25

ERROR – LSBs

–0.50

–0.75

–1.00

= 3V

REF

MAX INLMAX DNL

MIN DNLMIN INL

–40 0 120

40 80

TEMPERATURE – ⴗC

Figure 12. AD5330 INL Error and DNL Error vs. Temperature

Figure 10. AD5340 Typical DNL Plot

1.0

VDD = 5V

= 2V

REF

0.5

GAIN ERROR

0.0

ERROR – %

–0.5

–1.0

–40 0 12040 80

OFFSET ERROR

TEMPERATURE – ⴗC

Figure 13. AD5330 Offset Error and Gain Error vs. Temperature

REV. 0

–11–

Page 12

AD5330/AD5331/AD5340/AD5341

DAC CODE

– ␮A

300

250

ZERO-SCALE FULL-SCALE

200

150

100

VDD = 3.6V

VDD = 5.5V

TA = 25ⴗC

REF

= 2V

CH1 500mV, CH2 5V, TIME BASE = 1␮s/DIV

CH1

CH2

TA = 25ⴰC V

= 5V

REF

= 2V

OUT

0.2

TA = 25ⴰC

ERROR – %

0.1

–0.1

–0.2

–0.3

–0.4

–0.5

–0.6

= 2V

REF

OFFSET ERROR

01 3

VDD – Volts

GAIN ERROR

Figure 14. Offset Error and Gain Error vs. V

300

200

– ␮A

100

2.5 5.5

TA = 25ⴗC

3.0 5.0

3.5 4.0 4.5 VDD – Volts

Figure 17. Supply Current vs. Supply Voltage

5V SOURCE

– Volts

OUT

01 3446

Figure 15. V

3V SOURCE

5V SINK

SINK/SOURCE CURRENT – mA

Source and Sink

OUT

3V SINK

Current Capability

0.5

TA = 25ⴗC

0.4

0.3

– ␮A

0.2

0.1

3.0 5.0

2.5 5.5

3.5 4.0 4.5 VDD – Volts

Figure 18. Power-Down Current vs. Supply Voltage

Figure 16. Supply Current vs. DAC Code

1800

TA = 25ⴗC

1600

1400

1200

1000

– ␮A

800

600

400

200

VDD = 5V

VDD = 3V

234

– Volts

LOGIC

Figure 19. Supply Current vs. Logic Input Voltage

VDD = 5V T

= 25ⴗC

CH2

CLK

OUT

CH1

CH1 1V, CH2 5V, TIME BASE = 5␮s/DIV

Figure 20. Half-Scale Settling (1/4 to 3/4 Scale Code Change)

TA = 25ⴰC

= 5V

= 2V

REF

CH1

CH2

CH1 2V, CH2 200mV, TIME BASE = 200␮s/DIV

OUT

Figure 21. Power-On Reset to 0 V

–12–

Figure 22. Exiting Power-Down to Midscale

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Page 13

AD5330/AD5331/AD5340/AD5341

VDD = 3V

FREQUENCY

120 200190

IDD – ␮A

VDD = 5V

1801701601501401301101009080

Figure 23. IDD Histogram with VDD = 3 V and V

0.4

0.2

= 5 V

VDD = 5V

= 25ⴗC

0.917

0.916

0.915

0.914

0.913

0.912

0.911

0.910

0.909

0.908

0.907

0.906

0.905

0.904

0.903

250ns/DIV

Figure 24. AD5340 Major-Code Transition Glitch Energy

–10

–20

–30

–40

–50

–60

0.01

0.1 1 10 100 1k 10k FREQUENCY – kHz

Figure 25. Multiplying Bandwidth (Small-Signal Frequency Response)

FULL-SCALE ERROR – %FSR

–0.2

Figure 26. Full-Scale Error vs. V

34 50

– Volts

REF

FUNCTIONAL DESCRIPTION

The AD5330/AD5331/AD5340/AD5341 are single resistor-string DACs fabricated on a CMOS process with resolutions of 8, 10, 12, and 12 bits, respectively. They are written to using a parallel interface. They operate from single supplies of 2.5 V to 5.5 V and the output buffer amplifiers offer rail-to-rail output swing. The AD5330, AD5340, and AD5341 have a reference input that may be buffered to draw virtually no current from the reference source. The reference input of the AD5331 is unbuffered. The devices have a power-down feature that reduces current consumption to only 80 nA @ 3 V.

Digital-to-Analog Section

The architecture of one DAC channel consists of a reference buffer and a resistor-string DAC followed by an output buffer ampliﬁer. The voltage at the V

pin provides the reference

REF

voltage for the DAC. Figure 27 shows a block diagram of the DAC architecture. Since the input coding to the DAC is straight binary, the ideal output voltage is given by:

=××

OUT REF

Gain

where:

D = decimal equivalent of the binary code which is loaded to the DAC register:

0–255 for AD5330 (8 Bits) 0–1023 for AD5331 (10 Bits) 0–4095 for AD5340/AD5341 (12 Bits)

N = DAC resolution

Gain = Output Ampliﬁer Gain (1 or 2)

REF

INPUT

REFERENCE

DAC

BUFFER

RESISTOR

STRING

OUTPUT

BUFFER AMPLIFIER

GAIN

BUF

OUT

Figure 27. Single DAC Channel Architecture

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AD5330/AD5331/AD5340/AD5341

Resistor String

The resistor string section is shown in Figure 28. It is simply a string of resistors, each of value R. The digital code loaded to the DAC register determines at what node on the string the voltage is tapped off to be fed into the output ampliﬁer. The voltage is tapped off by closing one of the switches connecting the string to the ampliﬁer. Because it is a string of resistors, it is guaranteed monotonic.

REF

TO OUTPUT AMPLIFIER

Figure 28. Resistor String

DAC Reference Input

There is a reference input pin for the DAC. The reference input is buffered on the AD5330/AD5340/AD5341 but can be configured as unbuffered also. The reference input of the AD5331 is unbuffered. The buffered/unbuffered option is controlled by the BUF pin.

In buffered mode (BUF = 1), the current drawn from an external reference voltage is virtually zero as the impedance is at least 10 MΩ. The reference input range is 1 V to 5 V with a 5 V supply.

In unbuffered mode (BUF = 0), the user can have a reference voltage as low as 0.25 V and as high as V

since there is no

restriction due to headroom and footroom of the reference amplifier. The impedance is still large at typically 180 kΩ for 0–V mode and 90 kΩ for 0–2 V

mode. If there is an external

REF

buffered reference (e.g., REF192) there is no need to use the on-chip buffer.

Output Ampliﬁer

The output buffer ampliﬁer is capable of generating output voltages to within 1 mV of either rail. Its actual range depends on V

, GAIN, the load on V

REF

, and offset error.

OUT

If a gain of 1 is selected (GAIN = 0), the output range is 0.001 V to V

REF

If a gain of 2 is selected (GAIN = 1), the output range is 0.001 V to 2 V is limited to V

. However, because of clamping, the maximum output

REF

– 0.001 V.

The output ampliﬁer is capable of driving a load of 2 kΩ to GND or V

, in parallel with 500 pF to GND or VDD. The

source and sink capabilities of the output ampliﬁer can be seen in Figure 15.

The slew rate is 0.7 V/µs with a half-scale settling time to ± 0.5 LSB (at eight bits) of 6 µs with the output unloaded. See Figure 20.

PARALLEL INTERFACE

The AD5330, AD5331, and AD5340 load their data as a single 8-, 10-, or 12-bit word, while the AD5341 loads data as a low byte of eight bits and a high byte containing four bits.

Double-Buffered Interface

The AD5330/AD5331/AD5340/AD5341 DACs all have doublebuffered interfaces consisting of an input register and a DAC register. DAC data, BUF, and GAIN inputs are written to the input register under control of the Chip Select (CS) and Write (WR).

Access to the DAC register is controlled by the LDAC function. When LDAC is high, the DAC register is latched and the input register may change state without affecting the contents of the DAC register. However, when LDAC is brought low, the DAC register becomes transparent and the contents of the input register are transferred to it. The gain and buffer control signals are also double-buffered and are only updated when LDAC is taken low.

Double-buffering is also useful where the DAC data is loaded in two bytes, as in the AD5341, because it allows the whole data word to be assembled in parallel before updating the DAC register. This prevents spurious outputs that could occur if the DAC register were updated with only the high byte or the low byte.

These parts contain an extra feature whereby the DAC register is not updated unless its input register has been updated since the last time that LDAC was brought low. Normally, when LDAC is brought low, the DAC register is filled with the contents of the input register. In the case of the AD5330/AD5331/ AD5340/AD5341, the part will only update the DAC register if the input register has been changed since the last time the DAC register was updated. This removes unnecessary crosstalk.

Clear Input (CLR)

CLR is an active low, asynchronous clear that resets the input and DAC registers.

Chip Select Input (CS)

CS is an active low input that selects the device.

Write Input (WR)

WR is an active low input that controls writing of data to the device. Data is latched into the input register on the rising edge of WR.

Load DAC Input (LDAC)

LDAC transfers data from the input register to the DAC register (and hence updates the outputs). Use of the LDAC function enables double-buffering of the DAC data, GAIN, and BUF. There are two LDAC modes:

Synchronous Mode: In this mode the DAC register is updated after new data is read in on the rising edge of the WR input. LDAC can be tied permanently low or pulsed as in Figure 1.

Asynchronous Mode: In this mode the outputs are not updated at the same time that the input register is written to. When LDAC goes low, the DAC register is updated with the contents of the input register.

High-Byte Enable Input (HBEN)

High-Byte Enable is a control input on the AD5341 only that determines if data is written to the high-byte input register or the low-byte input register.

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AD5330/AD5331/AD5340/AD5341

The low data byte of the AD5341 consists of data bits 0 to 7 at data inputs DB bits 8 to 11 at data inputs DB

to DB7 are ignored during a high-byte write, but they may

to DB7, while the high byte consists of data

to DB3 as shown in Figure 29.

be used for data to set up the reference input as buffered/ unbuffered, and buffer amplifier gain. See Figure 33.

HIGH BYTE

DB6DB7

X = UNUSED BIT

LOW BYTE

DB4DB5

DB3

DB10DB11

DB2

DB8DB9

DB0DB1

Figure 29. Data Format for AD5341

POWER-ON RESET

The AD5330/AD5331/AD5340/AD5341 are provided with a power-on reset function, so that they power up in a deﬁned state. The power-on state is:

• Normal Operation

• Reference Input Unbuffered

•0 – V

Output Range

REF

• Output Voltage Set to 0 V

Both input and DAC registers are ﬁlled with zeros and remain so until a valid write sequence is made to the device. This is particularly useful in applications where it is important to know the state of the DAC outputs while the device is powering up.

POWER-DOWN MODE

The AD5330/AD5331/AD5340/AD5341 have low power consumption, dissipating only 0.35 mW with a 3 V supply and

0.7 mW with a 5 V supply. Power consumption can be further

reduced when the DAC is not in use by putting it into powerdown mode, which is selected by taking pin PD low.

When the PD pin is high, the DAC works normally with a typical power consumption of 140 µA at 5 V (115 µA at 3 V). In power-down mode, however, the supply current falls to 200 nA at 5 V (80 nA at 3 V) when the DAC is powered-down. Not only does the supply current drop, but the output stage is also internally switched from the output of the amplifier making it open-circuit. This has the advantage that the output is three-state while the part is in power-down mode and provides a defined input condition for whatever is connected to the output of the DAC amplifier. The output stage is illustrated in Figure 30.

RESISTOR

STRING DAC

AMPLIFIER

POWER-DOWN

CIRCUITRY

OUT

Figure 30. Output Stage During Power-Down

The bias generator, the output ampliﬁer, the resistor string, and all other associated linear circuitry are shut down when the power-down mode is activated. However, the contents of the registers are unaffected when in power-down. The time to exit power-down is typically 2.5 µs for V when V

= 3 V. This is the time from a rising edge on the

= 5 V and 5 µs

PD pin to when the output voltage deviates from its powerdown voltage. See Figure 22.

Table I. AD5330/AD5331/AD5340 Truth Table

CLR LDAC CS WR Function

111XNo Data Transfer 1 1 X 1 No Data Transfer 0 XXXClear All Registers 1100➝1 Load Input Register 1000➝1 Load Input Register and DAC Register 1 0 X X Update DAC Register

X = don’t care.

Table II. AD5341 Truth Table

CLR LDAC CS WR HBEN Function

1 1 1 X X No Data Transfer 1 1 X 1 X No Data Transfer 0 XXXXClear All Registers 1100➝1 0 Load Low-Byte Input Register 1100➝1 1 Load High-Byte Input Register 1000➝1 0 Load Low-Byte Input Register and DAC Register 1000➝1 1 Load High-Byte Input Register and DAC Register 1 0 XXXUpdate DAC Register

X = don’t care.

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AD5330/AD5331/AD5340/AD5341

SUGGESTED DATABUS FORMATS

In most applications GAIN and BUF are hard-wired. However, if more flexibility is required, they can be included in a databus. This enables you to software program GAIN, giving the option of doubling the resolution in the lower half of the DAC range. In a bused system, GAIN and BUF may be treated as data inputs since they are written to the device during a write operation and take effect when LDAC is taken low. This means that the reference buffers and the output amplifier gain of multiple DAC devices can be controlled using common GAIN and BUF lines.

In the case of the AD5330 this means that the databus must be wider than eight bits. The AD5331 and AD5340 databuses must be at least 10 and 12 bits wide respectively and are best suited to a 16-bit databus system.

Examples of data formats for putting GAIN and BUF on a 16bit databus are shown in Figure 31. Note that any unused bits above the actual DAC data may be used for BUF and GAIN. DAC devices can be controlled using common GAIN and BUF lines.

AD5330

GAIN

BUF X X

GAINBUF X X

X = UNUSED BIT

DB11

DB10

XBUF

AD5331

DB9 DB8

AD5340

DB9 DB8

DB7GAIN

DB7

DB6

DB5

DB5DB6DB7

DB5

DB4

DB0DB1DB2DB3DB4

DB0

DB1DB2DB3DB4

DB1DB2DB3

DB0

Figure 31. GAIN and BUF Data on a 16-Bit Bus

The AD5341 is a 12-bit device that uses byte load, so only four bits of the high byte are actually used as data. Two of the unused bits can be used for GAIN and BUF data by connecting them to the GAIN and BUF inputs; e.g., Bits 6 and 7, as shown in Figures 32 and 33.

8-BIT

DATA BUS

DATA INPUTS

7DB6

BUF

AD5341

GAIN

LDAC

CLR

HBEN

Figure 32. AD5341 Data Format for Byte Load with GAIN and BUF Data on 8-Bit Bus

In this case, the low byte is written first in a write operation with HBEN = 0. Bits 6 and 7 of DAC data will be written into GAIN and BUF registers but will have no effect. The high byte is then written. Only the lower four bits of data are written into the DAC high byte register, so Bits 6 and 7 can be GAIN and BUF data.

LDAC is used to update the DAC, GAIN and BUF values.

APPLICATIONS INFORMATION Typical Application Circuits

The AD5330/AD5331/AD5340/AD5341 can be used with a wide range of reference voltages, especially if the reference inputs are configured to be unbuffered, in which case the devices offer full, one-quadrant multiplying capability over a reference range of 0.25 V to V

. More typically, these devices may be used with a

fixed, precision reference voltage. Figure 34 shows a typical setup for the devices when using an external reference connected to the unbuffered reference inputs. If the reference inputs are unbuffered, the reference input range is from 0.25 V to VDD, but if the on-chip reference buffers are used, the reference range is reduced. Suitable references for 5 V operation are the AD780 and REF192. For 2.5 V operation, a suitable external reference would be the AD589, a 1.23 V bandgap reference.

= 2.5V TO 5.5V

10␮F

REF

AD5330/AD5331/

OUT

EXT REF

GND

0.1␮F

OUT

AD5340/AD5341

AD780/REF192

= 5V

WITH V

AD589 WITH V

= 2.5V

GND

Figure 34. AD5330/AD5331/AD5340/AD5341 Using External Reference

Driving VDD From the Reference Voltage

If an output range of zero to VDD is required, the simplest solution is to connect the reference inputs to V

. As this supply may

not be very accurate, and may be noisy, the devices may be powered from the reference voltage, for example using a 5 V reference such as the ADM663 or ADM666, as shown in Figure 35.

6V TO 16V

0.1␮F

10␮F

REF

AD5330/AD5331/

AD5340/AD5341

GND

OUT

ADM663/ADM666

SENSE

GND

OUT(2)

VSET SHDN

0.1␮F

HIGH BYTE

BUF GAIN

DB6DB7

X = UNUSED BIT

LOW BYTE

DB4DB5

DB3

DB10DB11

DB2

DB8DB9

DB0DB1

Figure 33. AD5341 with GAIN and BUF Data on 8-Bit Bus

Figure 35. Using an ADM663/ADM666 as Power and Reference to AD5330/AD5331/AD5340/AD5341

–16–

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AD5330/AD5331/AD5340/AD5341

Bipolar Operation Using the AD5330/AD5331/AD5340/AD5341

The AD5330/AD5331/AD5340/AD5341 have been designed for single supply operation, but bipolar operation is achievable using the circuit shown in Figure 36. The circuit shown has been conﬁgured to achieve an output voltage range of –5 V < V

+5 V. Rail-to-rail operation at the ampliﬁer output is achievable using an AD820 or OP295 as the output ampliﬁer.

The output voltage for any input code can be calculated as follows:

VO= [(1 + R4/R3) × (R2/(R1 + R2) × (2 × V

REF

× D/

)] – R4 × V

REF

/R3

where:

D is the decimal equivalent of the code loaded to the DAC, N is DAC resolution and V

is the reference voltage input.

REF

With:

= 2.5 V

REF

R1 = R3 = 10 kΩ R2 = R4 = 20 kΩ and V V

= (10 × D/2N) – 5

OUT

0.1␮F

EXT

GND

OUT

0.1␮F

= 5V

= 2.5V

REF

AD780/REF192 WITH V

AD589 WITH V

= 5 V.

VDD = 5V

10␮F

REF

AD5330/AD5331/ AD5340/AD5341

GND

10k⍀

OUT

10k⍀

20k⍀

R2 20k⍀

+5V

ⴞ5V

–5V

Figure 36. Bipolar Operation using the AD5330/AD5331/ AD5340/AD5341

Decoding Multiple AD5330/AD5331/AD5340/AD5341

The CS pin on these devices can be used in applications to decode a number of DACs. In this application, all DACs in the system receive the same data and WR pulses, but only the CS to one of the DACs will be active at any one time, so data will only be written to the DAC whose CS is low. If multiple AD5341s are being used, a common HBEN line will also be required to determine if the data is written to the high-byte or low-byte register of the selected DAC.

The 74HC139 is used as a 2- to 4-line decoder to address any of the DACs in the system. To prevent timing errors, the enable input should be brought to its inactive state while the coded address inputs are changing state. Figure 37 shows a diagram of a typical setup for decoding multiple devices in a system. Once data has been written sequentially to all DACs in a system, all the DACs can be updated simultaneously using a common LDAC line. A common CLR line can also be used to reset all DAC outputs to zero.

AD5330/AD5331/

AD5340/AD5341

HBEN

LDAC

CLR

ENABLE

CODED

ADDRESS

74HC139

DGND

1Y0

1Y1

1Y2

1Y3

HBEN*

WR LDAC CLR CS

AD5330/AD5331/

AD5340/AD5341

HBEN*

WR LDAC CLR CS

AD5330/AD5331/

AD5340/AD5341

HBEN*

WR LDAC CLR CS

AD5330/AD5331/

AD5340/AD5341

HBEN*

WR LDAC CLR CS

*AD5341 ONLY

DATA

INPUTS

DATA

INPUTS

DATA

INPUTS

DATA

INPUTS

DATA BUS

Figure 37. Decoding Multiple DAC Devices

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AD5330/AD5331/AD5340/AD5341

Programmable Current Source

Figure 38 shows the AD5330/AD5331/AD5340/AD5341 used as the control element of a programmable current source. In this example, the full-scale current is set to 1 mA. The output voltage from the DAC is applied across the current setting resistor of 4.7 kΩ in series with the 470 Ω adjustment potentiometer, which gives an adjustment of about ±5%. Suitable transistors to place in the feedback loop of the amplifier include the BC107 and the 2N3904, which enable the current source to operate from a minimum V

of 6 V. The operating range is deter-

SOURCE

mined by the operating characteristics of the transistor. Suitable amplifiers include the AD820 and the OP295, both having railto-rail operation on their outputs. The current for any digital input code and resistor value can be calculated as follows:

×()2

Where:

IGV

=× ×

REF

G is the gain of the buffer ampliﬁer (1 or 2) D is the digital equivalent of the digital input code N is the DAC resolution (8, 10, or 12 bits) R is the sum of the resistor plus adjustment potentiometer in kΩ

VDD = 5V

10␮F

REF

AD5330/AD5331/

AD5340/AD5341

OUT

AD820/

OP295

SOURCE

LOAD EXT REF

GND

0.1␮F

OUT

0.1␮F

Power Supply Bypassing and Grounding

In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board on which the AD5330/AD5331/AD5340/AD5341 is mounted should be designed so that the analog and digital sections are separated, and conﬁned to certain areas of the board. If the device is in a system where multiple devices require an AGND-to-DGND connection, the connection should be made at one point only. The star ground point should be established as closely as possible to the device. The AD5330/AD5331/AD5340/AD5341 should have ample supply bypassing of 10 µF in parallel with

0.1 µF on the supply located as close to the package as pos- sible, ideally right up against the device. The 10 µF capacitors are the tantalum bead type. The 0.1 µF capacitor should have low Effective Series Resistance (ESR) and Effective Series Inductance (ESI), like the common ceramic types that provide a low impedance path to ground at high frequencies to handle transient currents due to internal logic switching.

The power supply lines of the device should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other parts of the board, and should never be run near the reference inputs. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough through the board. A microstrip technique is by far the best, but not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground plane while signal traces are placed on the solder side.

AD780/REF192

= 5V

WITH V

GND

Figure 38. Programmable Current Source

4.7k⍀

470⍀

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AD5330/AD5331/AD5340/AD5341

Table III. Overview of AD53xx Parallel Devices

Part No. Resolution DNL V SINGLES BUF GAIN HBEN CLR

AD5330 8 ± 0.25 1 6 µs ✓✓ ✓ TSSOP 20 AD5331 10 ± 0.5 1 7 µs ✓✓TSSOP 20 AD5340 12 ± 1.0 1 8 µs ✓✓ ✓ TSSOP 24 AD5341 12 ± 1.0 1 8 µs ✓✓✓✓TSSOP 20

DUALS

AD5332 8 ± 0.25 2 6 µs ✓ TSSOP 20 AD5333 10 ± 0.5 2 7 µs ✓✓ ✓ TSSOP 24 AD5342 12 ± 1.0 2 8 µs ✓✓ ✓ TSSOP 28 AD5343 12 ± 1.0 1 8 µs ✓✓TSSOP 20

QUADS

AD5334 8 ± 0.25 2 6 µs ✓✓TSSOP 24 AD5335 10 ± 0.5 2 7 µs ✓✓TSSOP 24 AD5336 10 ± 0.5 4 7 µs ✓✓TSSOP 28 AD5344 12 ± 1.0 4 8 µs TSSOP 28

Part No. Resolution No. of DACs DNL Interface Settling Time Package Pins

SINGLES

AD5300 8 1 ± 0.25 SPI 4 µs SOT-23, MicroSOIC 6, 8 AD5310 10 1 ± 0.5 SPI 6 µs SOT-23, MicroSOIC 6, 8 AD5320 12 1 ± 1.0 SPI 8 µs SOT-23, MicroSOIC 6, 8

AD5301 8 1 ± 0.25 2-Wire 6 µs SOT-23, MicroSOIC 6, 8 AD5311 10 1 ± 0.5 2-Wire 7 µs SOT-23, MicroSOIC 6, 8 AD5321 12 1 ± 1.0 2-Wire 8 µs SOT-23, MicroSOIC 6, 8

DUALS

AD5302 8 2 ± 0.25 SPI 6 µs MicroSOIC 8 AD5312 10 2 ± 0.5 SPI 7 µs MicroSOIC 8 AD5322 12 2 ± 1.0 SPI 8 µs MicroSOIC 8

AD5303 8 2 ± 0.25 SPI 6 µs TSSOP 16 AD5313 10 2 ± 0.5 SPI 7 µs TSSOP 16 AD5323 12 2 ± 1.0 SPI 8 µs TSSOP 16

QUADS

AD5304 8 4 ± 0.25 SPI 6 µs MicroSOIC 10 AD5314 10 4 ± 0.5 SPI 7 µs MicroSOIC 10 AD5324 12 4 ± 1.0 SPI 8 µs MicroSOIC 10

AD5305 8 4 ± 0.25 2-Wire 6 µs MicroSOIC 10 AD5315 10 4 ± 0.5 2-Wire 7 µs MicroSOIC 10 AD5325 12 4 ± 1.0 2-Wire 8 µs MicroSOIC 10

AD5306 8 4 ± 0.25 2-Wire 6 µs TSSOP 16 AD5316 10 4 ± 0.5 2-Wire 7 µs TSSOP 16 AD5326 12 4 ± 1.0 2-Wire 8 µs TSSOP 16

AD5307 8 4 ± 0.25 SPI 6 µs TSSOP 16 AD5317 10 4 ± 0.5 SPI 7 µs TSSOP 16 AD5327 12 4 ± 1.0 SPI 8 µs TSSOP 16

Visit our web-page at http://www.analog.com/support/standard_linear/selection_guides/AD53xx.html

Pins Settling Time Additional Pin Functions Package Pins

REF

Table IV. Overview of AD53xx Serial Devices

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AD5330/AD5331/AD5340/AD5341

Dimensions shown in inches and (mm).

20-Lead Thin Shrink Small Outline Package TSSOP

0.260 (6.60)

0.252 (6.40)

OUTLINE DIMENSIONS

(RU-20)

20 11

PIN 1

0.006 (0.15)

0.002 (0.05)

0.0256 (0.65)

SEATING

PLANE

BSC

0.177 (4.50)

0.169 (4.30)

101

0.0433 (1.10) MAX

0.0118 (0.30)

0.0075 (0.19)

0.256 (6.50)

0.246 (6.25)

0.0079 (0.20)

0.0035 (0.090)

8ⴗ 0ⴗ

0.028 (0.70)

0.020 (0.50)

24-Lead Thin Shrink Small Outline Package TSSOP

(RU-24)

0.311 (7.90)

0.303 (7.70)

24 13

PIN 1

0.006 (0.15)

0.002 (0.05)

0.177 (4.50)

0.169 (4.30)

121

0.0433 (1.10) MAX

0.256 (6.50)

0.246 (6.25)

C3828–2.5–4/00 (rev. 0)

SEATING

PLANE

0.0256 (0.65) BSC

0.0118 (0.30)

0.0075 (0.19)

0.0079 (0.20)

0.0035 (0.090)

8ⴗ 0ⴗ

0.028 (0.70)

0.020 (0.50)

PRINTED IN U.S.A.

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Datasheet AD5341BRU, AD5341, AD5331BRU, AD5331, AD5330BRU Datasheet (Analog Devices)

Specifications and Main Features

Frequently Asked Questions

User Manual