Datasheet AD5325, AD5315, AD5305 Datasheet (Analog Devices)

2.5 V to 5.5 V, 500 ␮A, 2-Wire Interface

a

Quad Voltage Output, 8-/10-/12-Bit DACs

FEATURES
AD5305

Four Buffered 8-Bit DACs in 10-Lead microSOIC

AD5315

Four Buffered 10-Bit DACs in 10-Lead microSOIC

AD5325

Four Buffered 12-Bit DACs in 10-Lead microSOIC
Low Power Operation: 500 ␮A @ 3 V, 600 ␮A @ 5 V
2-Wire (I

2C®

-Compatible) Serial Interface

2.5 V to 5.5 V Power Supply
Guaranteed Monotonic By Design Over All Codes
Power-Down to 80 nA @ 3 V, 200 nA @ 5 V
Double-Buffered Input Logic
Output Range: 0–V

REF

Power-On-Reset to Zero Volts
Simultaneous Update of Outputs (LDAC Function)
Software Clear Facility
Data Readback Facility
On-Chip Rail-to-Rail Output Buffer Amplifiers

ⴗ

Temperature Range –40

C to +105ⴗC

APPLICATIONS
Portable Battery-Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Programmable Attenuators
Industrial Process Control

AD5305/AD5315/AD5325*

GENERAL DESCRIPTION

The AD5305/AD5315/AD5325 are quad 8-, 10- and 12-bit
buffered voltage output DACs in a 10-lead microSOIC package
that operate from a single 2.5 V to 5.5 V supply consuming
500 µA at 3 V. Their on-chip output amplifiers allow rail-to-rail
output swing with a slew rate of 0.7 V/µs. A 2-wire serial inter­face is used which operates at clock rates up to 400 kHz. This
interface is SMBus-compatible at V
can be placed on the same bus.

The references for the four DACs are derived from one reference
pin. The outputs of all DACs may be updated simultaneously
using the software LDAC function. The parts incorporate a
power-on-reset circuit that ensures that the DAC outputs power
up to zero volts and remain there until a valid write takes place
to the device. There is also a software clear function which resets
all input and DAC registers to 0 V. The parts contain a power­down feature that reduces the current consumption of the devices
to 200 nA @ 5 V (80 nA @ 3 V).

The low power consumption of these parts in normal operation
makes them ideally suited to portable battery-operated equip­ment. The power consumption is 3 mW at 5 V, 1.5 mW at 3 V,
reducing to 1 µW in power-down mode.

FUNCTIONAL BLOCK DIAGRAM

V

DD

REF IN

< 3.6 V. Multiple devices

DD

LDAC

INPUT

REGISTER

SCL

SDA

A0

*Protected by U.S. Patent No. 5,969,657; other patents pending.
I2C is a registered trademark of Philips Corporation.

INTERFACE

LOGIC

POWER-ON

RESET

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

REV. B

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

DAC

REGISTER

DAC

REGISTER

DAC

REGISTER

DAC

REGISTER

AD5305/AD5315/AD5325

GND

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 2000

STRING

DAC A

STRING

DAC B

STRING

DAC C

STRING

DAC D

BUFFER

POWER-DOWN

LOGIC

A

V

OUT

BBUFFER

V

OUT

V

CBUFFER

OUT

V

DBUFFER

OUT

AD5305/AD5315/AD5325–SPECIFICATIONS

GND; CL = 200 pF to GND; All specifications T

Parameter

1

DC PERFORMANCE

3, 4

B Version
Min Typ Max Unit Conditions/Comments

MIN

to T

unless otherwise noted.)

MAX

2

(VDD = 2.5 V to 5.5 V; V

= 2 V; RL = 2 k⍀ to

REF

AD5305

Resolution 8 Bits
Relative Accuracy ± 0.15 ± 1 LSB
Differential Nonlinearity ± 0.02 ± 0.25 LSB Guaranteed Monotonic by Design Over All Codes

AD5315

Resolution 10 Bits
Relative Accuracy ± 0.5 ± 4 LSB
Differential Nonlinearity ± 0.05 ± 0.5 LSB Guaranteed Monotonic by Design Over All Codes

AD5325

Resolution 12 Bits
Relative Accuracy ± 2 ± 16 LSB

Differential Nonlinearity ± 0.2 ± 1 LSB Guaranteed Monotonic by Design Over All Codes
Offset Error ± 0.4 ± 3 % of FSR
Gain Error ± 0.15 ± 1 % of FSR
Lower Deadband 20 60 mV Lower Deadband Exists Only If Offset Error Is Negative
Offset Error Drift
Gain Error Drift
Power Supply Rejection Ratio
DC Crosstalk

DAC REFERENCE INPUTS

V

Input Range 0.25 V

REF

V

Input Impedance 37 45 kΩ Normal Operation

REF

5

5

5

5

5

–12 ppm of FSR/°C
–5 ppm of FSR/°C
–60 dB ∆VDD = ±10%
200 µVR

DD

V

= 2 k⍀ to GND or V

L

DD

>10 MΩ Power-Down Mode

Reference Feedthrough –90 dB Frequency = 10 kHz

OUTPUT CHARACTERISTICS

Minimum Output Voltage
Maximum Output Voltage

5

6

6

0.001 V This is a measure of the minimum and maximum drive

VDD – 0.001 V capability of the output amplifier.
DC Output Impedance 0.5 Ω
Short Circuit Current 25 mA VDD = 5 V

16 mA VDD = 3 V
Power-Up Time 2.5 µs Coming Out of Power-Down Mode. VDD = 5 V

5 µs Coming Out of Power-Down Mode. VDD = 3 V

LOGIC INPUTS (A0)

5

Input Current ± 1 µA
VIL, Input Low Voltage 0.8 V VDD = 5 V ± 10%

0.6 V VDD = 3 V ± 10%

0.5 V VDD = 2.5 V

VIH, Input High Voltage 2.4 V VDD = 5 V ± 10%

2.1 V VDD = 3 V ± 10%

2.0 V VDD = 2.5 V

Pin Capacitance 3 pF

LOGIC INPUTS (SCL, SDA)

VIH, Input High Voltage 0.7 V
VIL, Input Low Voltage –0.3 0.3 V

5

DD

VDD+ 0.3 V SMBus-Compatible at VDD < 3.6 V

V SMBus-Compatible at VDD < 3.6 V

DD

IIN, Input Leakage Current ± 1 µA
V

, Input Hysteresis 0.05 V

HYST

DD

V
CIN, Input Capacitance 8 pF
Glitch Rejection 50 ns Input filtering suppresses noise spikes of less than 50 ns.

LOGIC OUTPUT (SDA)

VOL, Output Low Voltage 0.4 V I

5

= 3 mA

0.6 V I

SINK

SINK

= 6 mA
Three-State Leakage Current ± 1 µA
Three-State Output Capacitance 8 pF

POWER REQUIREMENTS

V

DD

IDD (Normal Mode)

7

2.5 5.5 V
VIH = VDD and VIL = GND

VDD = 4.5 V to 5.5 V 600 900 µA
VDD = 2.5 V to 3.6 V 500 700 µA

IDD (Power-Down Mode) VIH = VDD and VIL = GND,

VDD = 4.5 V to 5.5 V 0.2 1 µAI
VDD = 2.5 V to 3.6 V 0.08 1 µAI

= 4 µA (Max) During “0” Readback on SDA

DD

= 1.5 µA (Max) During “0” Readback on SDA

DD

–2–

REV. B

AD5305/AD5315/AD5325

NOTES

1

See Terminology.

2

Temperature range: B Version: –40°C to +105°C; typical at 25°C.

3

DC specifications tested with the outputs unloaded.

4

Linearity is tested using a reduced code range: AD5305 (Code 8 to 248); AD5315 (Code 28 to 995); AD5325 (Code 115 to 3981).

5

Guaranteed by design and characterization, not production tested.

6

For the amplifier output to reach its minimum voltage, Offset Error must be negative; to reach its maximum voltage, V

7

IDD specification is valid for all DAC codes. Interface inactive. All DACs active and excluding load currents.

Specifications subject to change without notice.

= VDD and “Offset plus Gain” Error must be positive.

REF

(VDD = 2.5 V to 5.5 V; RL = 2 k⍀ to GND; CL = 200 pF to GND; all specifications T

AC CHARACTERISTICS

Parameter

Output Voltage Settling Time V

2

1

otherwise noted.)

B Version
Min Typ Max Unit Conditions/Comments

3

= VDD = 5 V

REF

AD5305 6 8 µs 1/4 Scale to 3/4 Scale
AD5315 7 9 µs 1/4 Scale to 3/4 Scale
AD5325 8 10 µs 1/4 Scale to 3/4 Scale

Change
Change
Change

to T

MIN

(40 Hex to C0 Hex)
(100 Hex to 300 Hex)

(400 Hex to C00 Hex)
Slew Rate 0.7 V/µs
Major-Code Transition Glitch Energy 12 nV-s 1 LSB Change Around Major Carry
Digital Feedthrough 1 nV-s
Digital Crosstalk 1 nV-s
DAC-to-DAC Crosstalk 3 nV-s
Multiplying Bandwidth 200 kHz V
Total Harmonic Distortion –70 dB V

NOTES

1

Guaranteed by design and characterization, not production tested.

2

See Terminology.

3

Temperature range: B Version: –40°C to +105°C

Specifications subject to change without notice.

TIMING CHARACTERISTICS

Limit at T

MIN

, T

MAX

; typical at 25°C.

1, 2

(VDD = 2.5 V to 5.5 V. All specifications T

= 2 V ± 0.1 V p-p

REF

= 2.5 V ± 0.1 V p-p. Frequency = 10 kHz

REF

to T

MIN

unless otherwise noted)

MAX

Parameter (B Version) Unit Conditions/Comments

F

SCL

t

1

t

2

t

3

t

4

t

5

3

t

6

t

7

t

8

t

9

t

10

t

11

C

B

NOTES

1

See Figure 1.

2

Guaranteed by design and characterization, not production tested.

3

CB is the total capacitance of one bus line in pF. tR and tF measured between 0.3 VDD and 0.7 VDD.

Specifications subject to change without notice.

400 kHz max SCL Clock Frequency

2.5 µs min SCL Cycle Time

0.6 µs min t

1.3 µs min t

0.6 µs min t
100 ns min t

0.9 µs max t
0 µs min t

0.6 µs min t

0.6 µs min t

1.3 µs min t

, SCL High Time

HIGH

, SCL Low Time

LOW

, Start/Repeated Start Condition Hold Time

HD,STA

, Data Setup Time

SU,DAT

, Data Hold Time

HD,DAT

, Data Hold Time

HD,DAT

, Setup Time for Repeated Start

SU,STA

, Stop Condition Setup Time

SU,STO

, Bus Free Time Between a STOP and a START Condition

BUF

300 ns max tR, Rise Time of SCL and SDA when Receiving
0 ns min t

, Rise Time of SCL and SDA when Receiving (CMOS-Compatible)

R

250 ns max tF, Fall Time of SDA when Transmitting
0 ns min t
300 ns max t
20 + 0.1C

3

B

ns min tF, Fall Time of SCL and SDA when Transmitting

, Fall Time of SDA when Receiving (CMOS-Compatible)

F

, Fall Time of SCL and SDA when Receiving

F

400 pF max Capacitive Load for Each Bus Line

MAX

unless

REV. B

–3–

AD5305/AD5315/AD5325

WARNING!

ESD SENSITIVE DEVICE

SDA

SCL

t

9

START

CONDITION

t

3

t

4

t

10

t

6

t

2

Figure 1. Two-Wire Serial Interface Timing Diagram

ABSOLUTE MAXIMUM RATINGS

(TA = 25°C unless otherwise noted)

1, 2

VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

SCL, SDA to GND . . . . . . . . . . . . . . . .–0.3 V to V

A0 to GND . . . . . . . . . . . . . . . . . . . . . .–0.3 V to V

Reference Input Voltage to GND . . . . –0.3 V to V

A–D to GND . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V

V

OUT

+ 0.3 V

DD

+ 0.3 V

DD

+ 0.3 V

DD

Operating Temperature Range

Industrial (B Version) . . . . . . . . . . . . . . . –40°C to +105°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Junction Temperature (T

max) . . . . . . . . . . . . . . . . . . . 150°C

J

t

11

t

5

t

7

REPEATED

START

CONDITION

t

4

t

1

t

8

STOP

CONDITION

microSOIC Package

Power Dissipation . . . . . . . . . . . . . . . . . . (T

max – TA)/θ

J

θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 206°C/W

Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 44°C/W

θ

JC

Reflow Soldering

Peak Temperature . . . . . . . . . . . . . . . . . . . . . . 220 +5/–0°C

Time at Peak Temperature . . . . . . . . . . . . 10 sec to 40 sec

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; and functional operation
of the device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

2

Transient currents of up to 100 mA will not cause SCR latch-up.

JA

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD5305/AD5315/AD5325 features proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

ORDERING GUIDE

Temperature Package Package Branding

Model Range Description Option Information

AD5305BRM –40°C to +105°C 10-Lead microSOIC RM-10 DEB
AD5315BRM –40°C to +105°C 10-Lead microSOIC RM-10 DFB
AD5325BRM –40°C to +105°C 10-Lead microSOIC RM-10 DGB

–4–

REV. B

AD5305/AD5315/AD5325

PIN CONFIGURATION

V

1

DD

A

2

B

3

C

4

5

AD5305/
AD5315/
AD5325

TOP VIEW

(Not to Scale)

V

OUT

V

OUT

V

OUT

REFIN

PIN FUNCTION DESCRIPTIONS

Pin
No. Mnemonic Function

1V

DD

Power Supply Input. These parts can be operated from 2.5 V to 5.5 V and the supply should be

decoupled to GND.
2V
3V
4V

A Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.

OUT

B Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.

OUT

C Buffered Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.

OUT

5 REFIN Reference Input Pin for All Four DACs. It has an input range from 0.25 V to V
6V

D Buffered analog output voltage from DAC D. The output amplifier has rail-to-rail operation.

OUT

7 GND Ground Reference Point for All Circuitry on the Part.
8 SDA Serial Data Line. This is used in conjunction with the SCL line to clock data into or out of the 16-bit

input shift register. It is a bidirectional open-drain data line that should be pulled to the supply with

an external pull-up resistor.
9 SCL Serial Clock Line. This is used in conjunction with the SDA line to clock data into or out of the 16-bit

input shift register. Clock rates of up to 400 kbit/s can be accommodated in the 2-wire interface.
10 A0 Address Input. Sets the least significant bit of the 7-bit slave address.

A0

10

SCL

9

SDA

8

GND

7

6

V

D

OUT

.

DD

TERMINOLOGY
RELATIVE ACCURACY

For the DAC, relative accuracy or integral nonlinearity (INL) is
a measure of the maximum deviation, in LSBs, from a straight
line passing through the endpoints of the DAC transfer function.
Typical INL versus Code plots can be seen in Figures 4, 5, and 6.

DIFFERENTIAL NONLINEARITY

Differential Nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A specified differential nonlinearity of ±1 LSB
maximum ensures monotonicity. This DAC is guaranteed mono­tonic by design. Typical DNL versus Code plots can be seen in
Figures 7, 8, and 9.

OFFSET ERROR

This is a measure of the offset error of the DAC and the output
amplifier. It is expressed as a percentage of the full-scale range.

GAIN ERROR

This is a measure of the span error of the DAC. It is the devia­tion in slope of the actual DAC transfer characteristic from the
ideal expressed as a percentage of the full-scale range.

OFFSET ERROR DRIFT

This is a measure of the change in offset error with changes
in temperature. It is expressed in (ppm of full-scale range)/°C.

GAIN ERROR DRIFT

This is a measure of the change in gain error with changes
in temperature. It is expressed in (ppm of full-scale range)/°C.

POWER-SUPPLY REJECTION RATIO (PSRR)

This indicates how the output of the DAC is affected by
changes in the supply voltage. PSRR is the ratio of the change
in V

to a change in VDD for full-scale output of the DAC. It is

OUT

measured in dBs. V

is held at 2 V and VDD is varied ± 10%.

REF

DC CROSSTALK

This is the dc change in the output level of one DAC at mid­scale in response to a full-scale code change (all 0s to all 1s
and vice versa) and output change of another DAC. It is
expressed in µV.

REFERENCE FEEDTHROUGH

This is the ratio of the amplitude of the signal at the DAC
output to the reference input when the DAC output is not
being updated. It is expressed in dBs.

REV. B

–5–

AD5305/AD5315/AD5325

MAJOR-CODE TRANSITION GLITCH ENERGY

Major-code transition glitch energy is the energy of the impulse
injected into the analog output when the code in the DAC
register changes state. It is normally specified as the area of the
glitch in nV-secs and is measured when the digital code is changed
by 1 LSB at the major carry transition (011 . . . 11 to 100 . . . 00
or 100 . . . 00 to 011 . . . 11).

DIGITAL FEEDTHROUGH

Digital feedthrough is a measure of the impulse injected into the
analog output of the DAC from the digital input pins of the
device when the DAC output is not being updated. It is specified
in nV-secs and is measured with a worst-case change on the
digital input pins, e.g., from all 0s to all 1s or vice versa.

DIGITAL CROSSTALK

This is the glitch impulse transferred to the output of one DAC
at midscale in response to a full-scale code change (all 0s to all
1s and vice versa) in the input register of another DAC. It is
expressed in nV-secs.

DAC-TO-DAC CROSSTALK

This is the glitch impulse transferred to the output of one DAC
due to a digital code change and subsequent output change of
another DAC. This includes both digital and analog crosstalk. It
is measured by loading one of the DACs with a full-scale code
change (all 0s to all 1s and vice versa) with the LDAC bit set low
and monitoring the output of another DAC. The energy of the
glitch is expressed in nV-secs.

GAIN ERROR

PLUS

OFFSET ERROR

OUTPUT

VOLTAGE

NEGATIVE

OFFSET

ERROR

AMPLIFIER

FOOTROOM

(1mV)

NEGATIVE

OFFSET

ERROR

IDEAL

ACTUAL

DAC CODE

DEADBAND CODES

Figure 2. Transfer Function with Negative Offset

MULTIPLYING BANDWIDTH

The amplifiers within the DAC have a finite bandwidth. The
multiplying bandwidth is a measure of this. A sine wave on the
reference (with full-scale code loaded to the DAC) appears on
the output. The multiplying bandwidth is the frequency at which
the output amplitude falls to 3 dB below the input.

TOTAL HARMONIC DISTORTION

This is the difference between an ideal sine wave and its attenuated
version using the DAC. The sine wave is used as the reference
for the DAC and the THD is a measure of the harmonics present
on the DAC output. It is measured in dBs.

GAIN ERROR

PLUS

OFFSET ERROR

OUTPUT

VOLTAGE

POSITIVE

OFFSET

ACTUAL

IDEAL

DAC CODE

Figure 3. Transfer Function with Positive Offset

–6–

REV. B

AD5305/AD5315/AD5325

1.0

TA = 25ⴗC
V

= 5V

DD

0.5

0

INL ERROR – LSBs

–0.5

–1.0

50 250100 150 200

0

CODE

Figure 4. AD5305 Typical INL Plot

0.3
TA = 25ⴗC

V

= 5V

DD

0.2

0.1

0

–0.1

DNL ERROR – LSBs

–0.2

3

TA = 25ⴗC

= 5V

V

DD

2

1

0

–1

INL ERROR – LSBs

–2

–3

0

200 1000

400 600 800

CODE

Figure 5. AD5315 Typical INL Plot

0.6
TA = 25ⴗC

= 5V

V

DD

0.4

0.2

0

–0.2

DNL ERROR – LSBs

–0.4

12

TA = 25ⴗC

= 5V

V

8

DD

4

0

–4

INL ERROR – LSBs

–8

–12

0 4000

1000 2000 3000

CODE

Figure 6. AD5325 Typical INL Plot

1

TA = 25ⴗC

= 5V

V

DD

0.5

0

DNL ERROR – LSBs

–0.5

–0.3

0 50 250100 150 200

CODE

Figure 7. AD5305 Typical DNL Plot

0.5

VDD = 5V

= 25ⴗC

T

A

0.25

MAX INL MAX DNL

0

ERROR – LSBs

–0.25

–0.5

01 5234

MIN DNL

MIN INL

V

REF

– V

Figure 10. AD5305 INL and DNL
Error vs. V

REF

–0.6

2000

CODE

600400

800 1000

Figure 8. AD5315 Typical DNL Plot

0.5

VDD = 5V

0.4

0.3

0.2

0.1

–0.1

ERROR – LSBs

–0.2

–0.3

–0.4

–0.5

= 3V

V

REF

0

ⴚ40 0 40

MAX INL

MAX DNL

TEMPERATURE – ⴰC

MIN DNL

MIN INL

80 120

Figure 11. AD5305 INL Error and
DNL Error vs. Temperature

–1

10000

2000

CODE

3000 4000

Figure 9. AD5325 Typical DNL Plot

1

VDD = 5V

= 2V

V

REF

0.5

0

ERROR – %

–0.5

–1

ⴚ40 0 40

OFFSET ERROR

GAIN ERROR

80 120

TEMPERATURE – ⴰC

Figure 12. AD5305 Offset Error and
Gain Error vs. Temperature

REV. B

–7–

AD5305/AD5315/AD5325

0.2

TA = 25ⴰC

ERROR – %

0.1

–0.1

–0.2

–0.3

–0.4

–0.5

–0.6

= 2V

V

REF

0

OFFSET ERROR

01 3

25

VDD – Volts

GAIN ERROR

46

Figure 13. Offset Error and Gain
Error vs. V

600

500

400

300

– ␮A

DD

I

200

100

0

2.5

DD

ⴚ40ⴰC

+105ⴰC

3.0 4.0 4.5
VDD – Volts

+25ⴰC

5

5V SOURCE

3

– Volts

OUT

2

V

1

0

01 3446

Figure 14. V

3V SOURCE

5V SINK

25

SINK/SOURCE CURRENT – mA

Source and Sink

OUT

3V SINK

Current Capability

0.5

0.4

0.3

– ␮A

DD

I

0.2

0.1

0

5.53.5 5.0

3.0 4.0

2.5

ⴙ25ⴰC

VDD – Volts

ⴚ40ⴰC

ⴙ105ⴰC

4.5 5.53.5

5.0

600

TA = 25ⴰC

= 5V

V

DD

500

400

300

– ␮A

DD

I

200

100

ZERO – SCALE FULL – SCALE

=2V

V

REF

0

CODE

Figure 15. Supply Current vs. DAC
Code

750

TA = 25ⴗC

VDD = 5V

650

– ␮A

DD

I

550

450

DECREASING

VDD = 3V

0

1.0 2.0 3.0 4.0 5.0
V

LOGIC

INCREASING

– Volts

Figure 16. Supply Current vs. Supply
Voltage

TA = 25ⴗC

5µs

= 5V

V

DD

= 5V

V

REF

CH1

V

A

OUT

CH2

SCL

CH1 1V, CH2 5V, TIME BASE = 1␮s/DIV

Figure 19. Half-Scale Settling (1/4 to
3/4 Scale Code Change)

Figure 17. Power-Down Current vs.
Supply Voltage

TA = 25ⴗC

5µs

= 5V

V

DD

= 2V

V

REF

CH1

V

DD

V

A

CH2

CH1 2V, CH2 200mV, TIME BASE = 200␮s/DIV

OUT

Figure 20. Power-On Reset to 0 V

Figure 18. Supply Current vs. Logic
Input Voltage for SDA and SCL Volt­age Increasing and Decreasing

TA = 25ⴗC

= 5V

V

DD

= 2V

V

REF

CH1

V

A

OUT

SCL

CH2

CH1 500mV, CH2 5V, TIME BASE = 1␮s/DIV

Figure 21. Exiting Power-Down to
Midscale

–8–

REV. B

AD5305/AD5315/AD5325

VDD = 5VVDD = 3V

FREQUENCY

300 350 600400 450 500 550

IDD – ␮A

Figure 22. IDD Histogram with

= 3 V and VDD = 5 V

V

DD

0.02

VDD = 5V

= 25ⴗC

T

A

0.01

0

2.50

2.49

– Volts

OUT

V

2.48

2.47
1␮s/DIV

Figure 23. AD5325 Major-Code
Transition Glitch Energy

1mV/DIV

10

0

–10

–20

dB

–30

–40

–50

–60

0.01

0.1 1 10 100 1k 10k
FREQUENCY – kHz

Figure 24. Multiplying Bandwidth
(Small-Signal Frequency Response)

–0.01

FULL-SCALE ERROR – Volts

–0.02

01 3

25

V

REF

46

– Volts

Figure 25. Full-Scale Error vs. V

REF

50ns/DIV

Figure 26. DAC–DAC Crosstalk

REV. B

–9–

AD5305/AD5315/AD5325

FUNCTIONAL DESCRIPTION

The AD5305/AD5315/AD5325 are quad resistor-string DACs
fabricated on a CMOS process with resolutions of 8, 10, and 12
bits respectively. Each contains four output buffer amplifiers and
is written to via a 2-wire serial interface. They operate from
single supplies of 2.5 V to 5.5 V, and the output buffer amplifiers
provide rail-to-rail output swing with a slew rate of 0.7 V/µs. The
four DACs share a single reference input pin. The devices have
three programmable power-down modes, in which all DACs may
be turned off completely with a high-impedance output, or the
outputs may be pulled low by on-chip resistors.

Digital-to-Analog Section

The architecture of one DAC channel consists of a resistor-string
DAC followed by an output buffer amplifier. The voltage at the
REFIN pin provides the reference voltage for the DAC. Figure
27 shows a block diagram of the DAC architecture. Since the
input coding to the DAC is straight binary, the ideal output volt­age is given by:

VD

×

V

OUT

REF

=

N

2

where

D = decimal equivalent of the binary code, which is loaded to the
DAC register;

0–255 for AD5305 (8 Bits)
0–1023 for AD5315 (10 Bits)
0–4095 for AD5325 (12 Bits)

N = DAC resolution

REFIN

DAC Reference Inputs

There is a single reference input pin for the four DACs. The
reference input is unbuffered. The user can have a reference
voltage as low as 0.25 V and as high as V

since there is no

DD

restriction due to headroom and footroom of any reference
amplifier.

It is recommended to use a buffered reference in the external
circuit (e.g., REF192). The input impedance is typically 45 kΩ.

Output Amplifier

The output buffer amplifier is capable of generating rail-to-rail
voltages on its output, which gives an output range of 0 V to V

DD

when the reference is VDD. It is capable of driving a load of
2 kΩ to GND or V

in parallel with 500 pF to GND or VDD.

DD,

The source and sink capabilities of the output amplifier can be
seen in the plot in Figure 14.

The slew rate is 0.7 V/µs with a half-scale settling time to
± 0.5 LSB (at 8 bits) of 6 µs.

POWER-ON RESET

The AD5305/AD5315/AD5325 are provided with a power-on
reset function, so that they power up in a defined state. The
power-on state is:

– Normal operation.
– Output voltage set to 0 V.

Both input and DAC registers are filled with zeros and remain
so until a valid write sequence is made to the device. This is par­ticularly useful in applications where it is important to know the
state of the DAC outputs while the device is powering up.

INPUT

REGISTER

DAC

REGISTER

RESISTOR

STRING

OUTPUT BUFFER

AMPLIFIER

A

V

OUT

Figure 27. DAC Channel Architecture

Resistor String

The resistor string section is shown in Figure 28. It is simply a
string of resistors, each of value R. The digital code loaded to the
DAC register determines at what node on the string the voltage
is tapped off to be fed into the output amplifier. The voltage is
tapped off by closing one of the switches connecting the string to
the amplifier. Because it is a string of resistors, it is guaranteed
monotonic.

R

R

R

R

R

TO OUTPUT
AMPLIFIER

SERIAL INTERFACE

The AD5305/AD5315/AD5325 are controlled via an I2C­compatible serial bus. The DACs are connected to this bus as
slave devices (i.e., no clock is generated by the AD5305/AD5315/
AD5325 DACs). This interface is SMBus-compatible at V

DD

< 3.6 V.

The AD5305/AD5315/AD5325 have a 7-bit slave address. The
6 MSBs are 000110 and the LSB is determined by the state of
the A0 pin. The facility to make hardwired changes to A0 allows
the user to use up to two of these devices on one bus.

The 2-wire serial bus protocol operates as follows:

1. The master initiates data transfer by establishing a START
condition, which is when a high-to-low transition on the SDA
line occurs while SCL is high. The following byte is the ad­dress byte which consists of the 7-bit slave address followed
by a R/W bit (this bit determines whether data will be read
from or written to the slave device).

The slave whose address corresponds to the transmitted
address responds by pulling SDA low during the ninth clock
pulse (this is termed the acknowledge bit). At this stage, all
other devices on the bus remain idle while the selected device
waits for data to be written to or read from its shift register.

2. Data is transmitted over the serial bus in sequences of nine
clock pulses (8-data bits followed by an acknowledge bit). The
transitions on the SDA line must occur during the low period
of SCL and remain stable during the high period of SCL.

Figure 28. Resistor String

–10–

REV. B

AD5305/AD5315/AD5325

3. When all data bits have been read or written, a STOP condition
is established. In write mode, the master will pull the SDA
line high during the tenth clock pulse to establish a STOP
condition. In read mode, the master will issue a No Acknowl­edge for the ninth clock pulse (i.e., the SDA line remains
high). The master will then bring the SDA line low before
the tenth clock pulse and then high during the tenth clock
pulse to establish a STOP condition.

Read/Write Sequence

In the case of the AD5305/AD5315/AD5325, all write access
sequences and most read sequences begin with the device address
(with R/W = 0) followed by the pointer byte. This pointer byte
specifies the data format and determines which DAC is being
accessed in the subsequent read/write operation. (See Figure 29.)
In a write operation the data follows immediately. In a read
operation the address is resent with R/W = 1 and then the data
is read back. However, it is also possible to perform a read opera­tion by sending only the address with R/W = 1. The previously
loaded pointer settings are then used for the readback operation.
See overleaf for a graphical explanation of the interface.

LSBMSB

XX

Pointer Byte Bits

RIGHT/LEFT

SINGLE/DOUBLE

Figure 29. Pointer Byte

DACD

DACC DACB DACA

The following is an explanation of the individual bits that make up
the Pointer Byte.

X: Don’t Care Bits
RIGHT/LEFT:

0: Data written to the device and read from the
device is Left-Justified (in Double Byte mode)
1: Data written to the device and read from the
device is Right-Justified (in Double Byte mode)

SINGLE/DOUBLE:

0: Data Write and Readback are done as 2-byte
write/read sequences
1: Data Write and Readback are done as 1-byte
(most significant 8 bits only) write/read sequences

DACD 1: The following data bytes are for DAC D

DACC 1: The following data bytes are for DAC C

DACB 1: The following data bytes are for DAC B

DACA 1: The following data bytes are for DAC A

Input Shift Register

The input shift register is 16 bits wide. Data is loaded into the
device as a 16-bit word under the control of a serial clock input,
SCL. The timing diagram for this operation is shown in Figure

1. The 16-bit word consists of four control bits followed by 8,
10, or 12 bits of DAC data, depending on the device type. The
first two bits loaded are PD bits that control the mode of opera­tion of the device. See Power-Down Modes section for a complete
description. Bit 13 is CLR, Bit 12 is LDAC and the remaining
bits are left- or right-justified DAC data bits, starting with the
MSB. See Figure 30 overleaf.

CLR: 0: All DAC registers and input registers are filled with

zeros on completion of the write sequence.
1: Normal operation.

LDAC: 0: All four DAC registers and hence all DAC outputs

simultaneously updated on completion of the write
sequence.
1: Adqdressed input register only is updated. There
is no change in the contents of the DAC registers.

Default Readback Condition

All pointer byte bits power-up to 0. Therefore, if the user initiates
a readback without writing to the pointer byte first, no single DAC
channel has been specified. In this case, the default readback
bits are all 0, except for the CLR bit which is a 1.

Multiple-DAC Write Sequence

Because there are individual bits in the Pointer Byte for each
DAC, it is possible to write the same data and control bits to 2,
3, or 4 DACs simultaneously by setting the relevant bits to 1.

Multiple-DAC Readback Sequence

If the user attempts to readback data from more than 1 DAC at a
time, the part will read back the default, power-on-reset conditions
for a double-byte readback, i.e., all 0s except for CLR which is 1.
For a single-byte readback, the part will read back all 0s.

REV. B

–11–

AD5305/AD5315/AD5325

LEFT-JUSTIFIED DATA BYTES (WRITE AND READBACK)

MOST SIGNIFICANT DATA BYTE

PD0

PD1

PD1

CLR LDAC

10-BIT AD5315

PD0

CLR LDAC

PD0 D11 D10 D9 D8PD1

CLR

LDAC

MOST SIGNIFICANT DATA BYTE

PD0

CLR LDAC

D7 D6 D5

D9 D8 D7 D6PD1

RIGHT-JUSTIFIED DATA BYTES (WRITE AND READBACK)

X XXX

LSBMSB 8-BIT AD5305

D4

LSBMSB

LSBMSB 12-BIT AD5325

LSBMSB 8-BIT AD5305

LSBMSB 10-BIT AD5315

LEAST SIGNIFICANT DATA BYTE

LSBMSB 8-BIT AD5305

D0

D3 D2 D1

10-BIT AD5315

D5 D4 D3 D1 D1 D0 X X

12-BIT AD5325

D7 D6 D5 D4 D3 D2 D1 D0

LEAST SIGNIFICANT DATA BYTE

8-BIT AD5305

D7 D6

D5

10-BIT AD5315

XXXX

LSBMSB

LSBMSB

LSBMSB

D4 D3 D2 D1 D0

LSBMSB

PD0

CLR LDAC

PD0 D11 D10

CLR LDAC

MSB

D7 D6 D5 D4 D3 D2 D1 D0

MSB

D9 D8 D7 D6 D5 D4 D3 D2

8-BIT AD5305

10-BIT AD5315

X X D9 D8PD1

D9

SINGLE BYTE ONLY (WRITE AND READBACK)

Figure 30. Double- and Single-Byte Data Formats

LSBMSB 12-BIT AD5325

D8PD1

LSB

LSB

D7 D6 D5 D4 D3 D2 D1 D0

12-BIT AD5325

D7 D6 D5 D4 D3 D2 D1 D0

D11 D10 D9

D7 D6 D5 D4

D8

LSBMSB

LSBMSB 12-BIT AD5325

–12–

REV. B

AD5305/AD5315/AD5325

WRITE OPERATION

When writing to the AD5305/AD5315/AD5325 DACs, the user
must begin with an address byte (R/W = 0) after which the DAC
will Acknowledge that it is prepared to receive data by pulling
SDA low. This address byte is followed by the pointer byte

SCL

SDA

MASTER

SCL

SDA

SCL

SDA

MASTER

00011 A0

START

COND

BY

MSB LSB MSB LSB

MOST SIGNIFICANT DATA BYTE LEAST SIGNIFICANT DATA BYTE

00011 A0

START

COND

BY

ADDRESS BYTE

ADDRESS BYTE

0

0

R/W

R/W

ACK

BY

AD53x5

ACK

BY

AD53x5

ACK

BY

AD53x5

MSB

MSB

which is also acknowledged by the DAC. Depending on the
value of SINGLE/DOUBLE, one or two bytes of data are then
written to the DAC as shown in Figure 31 below. A STOP condi­tion follows.

X X LSB

ACK

LSB

BY

AD53x5

ACK

BY

AD53x5

ACK

BY

AD53x5

START

COND

BY

MASTER

POINTER BYTE

X

X

X

POINTER BYTE

SCL

SDA

MSB

LSB

ACK

STOP

BY

DATA BYTE

MASTER

COND

BY

MASTER

Figure 31. Double- and Single-Byte Write Sequences

REV. B

–13–

AD5305/AD5315/AD5325

S

READ OPERATION

When reading data back from the AD5305/AD5315/AD5325
DACs, the user begins with an address byte (R/W = 0) after
which the DAC will Acknowledge that it is prepared to receive
data by pulling SDA low. This address byte is usually followed
by the pointer byte which is also acknowledged by the DAC.
Following this, there is a repeated start condition by the master
and the address is resent with R/W = 1. This is acknowledged by
the DAC indicating that it is prepared to transmit data. Depending

SCL

SDA

MASTER

SCL

SDA

START

COND

BY

00 0 11 A0

00 0 11

REPEATED

START

COND

BY

MASTER

ADDRESS BYTE

0

R/W

ACK

MSB

BY

AD53x5

0

R/W

A0

AD53x5

on the value of SINGLE/DOUBLE, one or two bytes of data are
then read from the DAC as shown in Figure 32 below.

However, if the master sends an ACK and continues clocking
SCL (no STOP is sent), the DAC will retransmit the same one
or two bytes of data on SDA. This allows continuous readback
of data from the selected DAC register.

Alternatively the user may send a START followed by the address
with R/W = 1. In this case the previously loaded pointer settings
are used and readback of data can commence immediately.

X X LSB

ACK

POINTER BYTEADDRESS BYTE

MSB LSB

ACK

BY

DATA BYTE

BY

AD53x5

ACK

BY

MASTER

SCL

SDA

MASTER

SCL

SDA

SCL

SDA

START

COND

BY

MSB

LEAST SIGNIFICANT DATA BYTE

00 0 11 A0

ADDRESS BYTE

00 0 11

REPEATED

START

COND

BY

MASTER

ADDRESS BYTE

0

Figure 32. Double- and Single-Byte Read Sequences

LSB

NO

ACK

BY

TER

MA

R/W

AD53x5

0

A0

X X LSB

ACK

MSB

BY

R/W

ACK

BY

AD53x5

STOP
COND

BY

MASTER

X

ACK

POINTER BYTE

MSB LSB

DATA BYTE

BY

AD53x5

NO ACK

BY

MASTER

STOP
COND

BY

MASTER

–14–

REV. B

DOUBLE-BUFFERED INTERFACE

The AD5305/AD5315/AD5325 DACs all have double-buffered
interfaces consisting of two banks of registers—input registers and
DAC registers. The input register is directly connected to the
input shift register and the digital code is transferred to the rel­evant input register on completion of a valid write sequence.
The DAC register contains the digital code used by the resis­tor string.

Access to the DAC register is controlled by the LDAC bit. When
the LDAC bit is set high, the DAC register is latched and hence
the input register may change state without affecting the contents
of the DAC register. However, when the LDAC bit is set low,
the DAC register becomes transparent and the contents of the
input register are transferred to it.

This is useful if the user requires simultaneous updating of all
DAC outputs. The user may write to three of the input registers
individually and then, by setting the LDAC bit low when writing
to the remaining DAC input register, all outputs will update
simultaneously.

These parts contain an extra feature whereby the DAC register
is not updated unless its input register has been updated since
the last time that LDAC was brought low. Normally, when LDAC
is brought low, the DAC registers are filled with the contents of
the input registers. In the case of the AD5305/AD5315/AD5325,
the part will only update the DAC register if the input register
has been changed since the last time the DAC register was
updated, thereby removing unnecessary digital crosstalk.

POWER-DOWN MODES

The AD5305/AD5315/AD5325 have very low power consump­tion, dissipating typically 1.5 mW with a 3 V supply and 3 mW
with a 5 V supply. Power consumption can be further reduced
when the DACs are not in use by putting them into one of three
power-down modes, which are selected by Bits 15 and 14 (PD1
and PD0) of the data byte. Table I shows how the state of the
bits corresponds to the mode of operation of the DAC.

Table I. PD1/PD0 Operating Modes

PD1 PD0 Operating Mode

0 0 Normal Operation
0 1 Power-Down (1 kΩ Load to GND)
1 0 Power-Down (100 kΩ Load to GND)
1 1 Power-Down (Three-State Output)

When both bits are set to 0, the DAC works normally with its
normal power consumption of 600 µA at 5 V. However, for the
three power-down modes, the supply current falls to 200 nA at
5 V (80 nA at 3 V). Not only does the supply current drop, but
the output stage is also internally switched from the output of
the amplifier to a resistor network of known values. This has
an advantage in that the output impedance of the part is known
while the part is in power-down mode and provides a defined
input condition for whatever is connected to the output of the
DAC amplifier. There are three different options. The output is
connected internally to GND through a 1 kΩ resistor, a 100 kΩ
resistor or it is left open-circuited (Three-State). Resistor toler­ance = ± 20%. The output stage is illustrated in Figure 33.

AD5305/AD5315/AD5325

RESISTOR

STRING DAC

Figure 33. Output Stage During Power-Down

The bias generator, the output amplifiers, the resistor string, and
all other associated linear circuitry are all shut down when the
power-down mode is activated. However, the contents of the DAC
registers are unchanged when in power-down. The time to exit
power-down is typically 2.5 µs for VDD = 5 V and 5 µs when
V

= 3 V. This is the time from the rising edge of the sixteenth

DD

SCL pulse to when the output voltage deviates from its power­down voltage. See Figure 21 for a plot.

APPLICATIONS
Typical Application Circuit

The AD5305/AD5315/AD5325 can be used with a wide range
of reference voltages where the devices offer full, one-quadrant
multiplying capability over a reference range of 0 V to V
More typically, these devices are used with a fixed, precision
reference voltage. Suitable references for 5 V operation are the
AD780 and REF192 (2.5 V references). For 2.5 V operation, a
suitable external reference would be the AD589, a 1.23 V band­gap reference. Figure 34 shows a typical setup for the AD5305/
AD5315/AD5325 when using an external reference. Note that
A0 can be high or low.

0.1␮F

V

IN

V

OUT

EXT
REF

AD780/REF192

= 5V

WITH V

DD

OR AD589 WITH

= 2.5V

V

DD

Figure 34. AD5305/AD5315/AD5325 Using External
Reference

AMPLIFIER

POWER-DOWN

CIRCUITRY

10␮F

1␮F

SERIAL

INTERFACE

RESISTOR
NETWORK

VDD = 2.5V TO 5.5V

AD5305/
AD5315/
AD5325

REFIN

SCL

SDA

A0

GND

V

OUT

.

DD

V

A

OUT

V

B

OUT

V

C

OUT

D

V

OUT

REV. B

–15–

AD5305/AD5315/AD5325

If an output range of 0 V to VDD is required, the simplest solu­tion is to connect the reference input to V

. As this supply may

DD

not be very accurate and may be noisy, the AD5305/AD5315/
AD5325 may be powered from the reference voltage; for example,
using a 5 V reference such as the REF195. The REF195 will
output a steady supply voltage for the AD5305/AD5315/AD5325.
The typical current required from the REF195 is 600 µA supply
current and approximately 112 µA into the reference input. This
is with no load on the DAC outputs. When the DAC outputs are
loaded, the REF195 also needs to supply the current to the
loads. The total current required (with a 10 kΩ load on each
output) is:

712 µA + 4(5 V/10 kΩ) = 2.70 mA

The load regulation of the REF195 is typically 2 ppm/mA, which
results in an error of 5.4 ppm (27 µV) for the 2.7 mA current
drawn from it. This corresponds to a 0.0014 LSB error at 8 bits
and 0.022 LSB error at 12 bits.

Bipolar Operation Using the AD5305/AD5315/AD5325

The AD5305/AD5315/AD5325 have been designed for single­supply operation, but a bipolar output range is also possible
using the circuit in Figure 35. This circuit will give an output
voltage range of ±5 V. Rail-to-rail operation at the amplifier
output is achievable using an AD820 or an OP295 as the output
amplifier.

R2 = 10k⍀

6V TO 16V

10␮F

REF195

V

IN

PT5125

R1 = 10k⍀

0.1␮F
+5V

V

DD

V

OUT

REFIN

1␮F

A0

GND

V

AD5305

V

V

V

SCL SDA

2-WIRE
SERIAL

INTERFACE

OUT

OUT

OUT

OUT

+5V

AD820/
OP295

A

–5V

B

C

D

ⴞ5V

Figure 35. Bipolar Operation with the AD5305

The output voltage for any input code can be calculated as
follows:

V

= [(REFIN × (D/2N) × (R1+R2)/R1) – REFIN × (R2/R1)]

OUT

where:

D is the decimal equivalent of the code loaded to the DAC.

N is the DAC resolution.

REFIN is the reference voltage input.

with:

REFIN = 5 V, R1 = R2 = 10 kΩ:

V

= (10 × D/2N) – 5 V

OUT

Multiple Devices on One Bus

Figure 36 below shows two AD5305 devices on the same serial
bus. Each has a different slave address since the state of the A0
pin is different. This allows each of eight DACs to be written to
or read from independently.

V

DD

PULL-UP

RESISTORS

MICRO-

CONTROLLER

A0

SDA

A0

AD5305

SDA

SCL

SCL

AD5305

Figure 36. Multiple AD5305 Devices on One Bus

AD5305/AD5315/AD5325 as a Digitally Programmable
Window Detector

A digitally programmable upper/lower limit detector using two
of the DACs in the AD5305/AD5315/AD5325 is shown in
Figure 37. The upper and lower limits for the test are loaded to
DACs A and B which, in turn, set the limits on the CMP04. If
the signal at the V

input is not within the programmed window,

IN

an LED will indicate the fail condition. Similarly, DACs C and
D can be used for window detection on a second V

5V

0.1␮F10␮F

V

1/2
AD5305/
AD5315/
AD5325*

GND

DD

V

V

REF

DIN

SCL

REFIN

SDA

SCL

*ADDITIONAL PINS OMITTED FOR CLARITY

V

IN

V

A

OUT

1/2

CMP04

B

OUT

signal.

IN

1k⍀

FAIL

PASS/FAIL

1/6 74HC05

1k⍀

PASS

Figure 37. Window Detection

Coarse and Fine Adjustment Using the AD5305/AD5315/
AD5325

Two of the DACs in the AD5305/AD5315/AD5325 can be
paired together to form a coarse and fine adjustment function,
as shown in Figure 38. DAC A is used to provide the coarse
adjustment while DAC B provides the fine adjustment. Varying
the ratio of R1 and R2 will change the relative effect of the coarse
and fine adjustments. With the resistor values and external
reference shown, the output amplifier has unity gain for the
DAC A output, so the output range is 0 V to 2.5 V – 1 LSB.
For DAC B the amplifier has a gain of 7.6 × 10

–3

, giving DAC B a
range equal to 19 mV. Similarly, DACs C and D can be paired
together for coarse and fine adjustment.

–16–

REV. B

AD5305/AD5315/AD5325

The circuit is shown with a 2.5 V reference, but reference volt­ages up to V

may be used. The op amps indicated will allow a

DD

rail-to-rail output swing.

VDD = 5V

10␮F

0.1␮F

V

IN

EXT

V

OUT

REF

GND

AD780/REF192

= 5V

WITH V

DD

*ADDITIONAL PINS OMITTED FOR CLARITY

1␮F

REFIN

AD5305/
AD5315/
AD5325*

V

DD

1/2

GND

R3

51.2k⍀R4390⍀

A

V

OUT

R1

390⍀

V

B

OUT

R2

51.2k⍀

5V

AD820/
OP295

V

OUT

Figure 38. Coarse/Fine Adjustment

POWER SUPPLY DECOUPLING

In any circuit where accuracy is important, careful consideration
of the power supply and ground return layout helps to ensure
the rated performance. The printed circuit board on which the
AD5305/AD5315/AD5325 is mounted should be designed so
that the analog and digital sections are separated, and confined
to certain areas of the board. If the AD5305/AD5315/AD5325
is in a system where multiple devices require an AGND-to-DGND
connection, the connection should be made at one point only.

The star ground point should be established as close as possible
to the device. The AD5305/AD5315/AD5325 should have ample
supply bypassing of 10 µF in parallel with 0.1 µF on the supply
located as close to the package as possible, ideally right up against
the device. The 10 µF capacitors are the tantalum bead type.
The 0.1 µF capacitor should have low Effective Series Resistance
(ESR) and Effective Series Inductance (ESI), like the common
ceramic types that provide a low impedance path to ground at
high frequencies, to handle transient currents due to internal
logic switching.

The power supply lines of the AD5305/AD5315/AD5325 should
use as large a trace as possible to provide low impedance paths
and reduce the effects of glitches on the power supply line. Fast
switching signals such as clocks should be shielded with digital
ground to avoid radiating noise to other parts of the board, and
should never be run near the reference inputs. A ground line
routed between the SDA and SCL lines will help reduce crosstalk
between them (not required on a multilayer board as there will
be a separate ground plane, but separating the lines will help).

Avoid crossover of digital and analog signals. Traces on opposite
sides of the board should run at right angles to each other. This
reduces the effects of feedthrough through the board. A microstrip
technique is by far the best, but not always possible with a double­sided board. In this technique, the component side of the board
is dedicated to ground plane while signal traces are placed on
the solder side.

REV. B

–17–

AD5305/AD5315/AD5325

Table II. Overview of All AD53xx Serial Devices

No. of Settling

Part No. Resolution DACs DNL Interface Time Package Pins

SINGLES

AD5300 8 1 ±0.25 SPI 4 µs SOT-23, microSOIC 6, 8
AD5310 10 1 ± 0.5 SPI 6 µs SOT-23, microSOIC 6, 8
AD5320 12 1 ± 1.0 SPI 8 µs SOT-23, microSOIC 6, 8

AD5301 8 1 ± 0.25 2-Wire 6 µs SOT-23, microSOIC 6, 8
AD5311 10 1 ± 0.5 2-Wire 7 µs SOT-23, microSOIC 6, 8
AD5321 12 1 ± 1.0 2-Wire 8 µs SOT-23, microSOIC 6, 8

DUALS

AD5302 8 2 ± 0.25 SPI 6 µs microSOIC 8
AD5312 10 2 ± 0.5 SPI 7 µs microSOIC 8
AD5322 12 2 ± 1.0 SPI 8 µs microSOIC 8

AD5303 8 2 ± 0.25 SPI 6 µs TSSOP 16
AD5313 10 2 ± 0.5 SPI 7 µs TSSOP 16
AD5323 12 2 ± 1.0 SPI 8 µs TSSOP 16

QUADS

AD5304 8 4 ± 0.25 SPI 6 µs microSOIC 10
AD5314 10 4 ± 0.5 SPI 7 µs microSOIC 10
AD5324 12 4 ± 1.0 SPI 8 µs microSOIC 10

AD5305 8 4 ± 0.25 2-Wire 6 µs microSOIC 10
AD5315 10 4 ± 0.5 2-Wire 7 µs microSOIC 10
AD5325 12 4 ± 1.0 2-Wire 8 µs microSOIC 10

AD5306 8 4 ± 0.25 2-Wire 6 µs TSSOP 16
AD5316 10 4 ± 0.5 2-Wire 7 µs TSSOP 16
AD5326 12 4 ± 1.0 2-Wire 8 µs TSSOP 16

AD5307 8 4 ± 0.25 SPI 6 µs TSSOP 16
AD5317 10 4 ± 0.5 SPI 7 µs TSSOP 16
AD5327 12 4 ± 1.0 SPI 8 µs TSSOP 16

Visit our web-page at http://www.analog.com/support/standard_linear/selection_guides/AD53xx.html

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REV. B

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

10-Lead microSOIC

(RM-10)

0.122 (3.10)

0.114 (2.90)

AD5305/AD5315/AD5325

0.122 (3.10)

0.114 (2.90)

0.037 (0.94)

0.031 (0.78)

0.006 (0.15)

0.002 (0.05)

10 6

PIN 1

0.0197 (0.50) BSC

0.120 (3.05)

0.112 (2.85)

51

0.012 (0.30)

0.006 (0.15)

0.199 (5.05)

0.187 (4.75)

0.043 (1.10)
MAX

SEATING
PLANE

0.009 (0.23)

0.005 (0.13)

0.120 (3.05)

0.112 (2.85)

6ⴗ
0ⴗ

C3722a–2.5–6/00 (rev. B) 00930

0.028 (0.70)

0.016 (0.40)

REV. B

PRINTED IN U.S.A.

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