Datasheet AD5308, AD5318, AD5328 Datasheet (ANALOG DEVICES)

2.5 V to 5.5 V Octal Voltage Output

FEATURES

AD5308: 8 buffered 8-bit DACs in 16-lead TSSOP

A version: ±1 LSB INL, B version: ±0.75 LSB INL

AD5318: 8 buffered 10-bit DACs in 16-lead TSSOP

A version: ±4 LSB INL, B version: ±3 LSB INL

AD5328: 8 buffered 12-bit DACs in 16-lead TSSOP

A version: ±16 LSB INL, B version: ±12 LSB INL Low power operation: 0.7 mA @ 3 V Guaranteed monotonic by design over all codes Power-down to 120 nA @ 3 V, 400 nA @ 5 V Double-buffered input logic Buffered/unbuffered/V Output range: 0 V to V Power-on reset to 0 V Programmability

Individual channel power-down

Simultaneous update of outputs ( Low power, SPI-®, QSPI-™, MICROWIRE-™, and DSP-

compatible 3-wire serial interface On-chip rail-to-rail output buffer amplifiers Temperature range: −40°C to +125°C Qualified for automotive applications

reference input options

DD

or 0 V to 2 V

REF

LDAC

)

8-/10-/12-Bit DACs in 16-Lead TSSOP

AD5308/AD5318/AD5328

APPLICATIONS

Portable battery-powered instruments Digital gain and offset adjustment Programmable voltage and current sources Optical networking Automatic test equipment Mobile communications Programmable attenuators Industrial process control

GENERAL DESCRIPTION

The AD5308/AD5318/AD5328 are octal 8-, 10-, and 12-bit buffered voltage output DACs in a 16-lead TSSOP. They operate from a single 2.5 V to 5.5 V supply, consuming 0.7 mA typical at 3 V. Their on-chip output amplifiers allow the outputs to swing rail-to-rail with a slew rate of 0.7 V/s. The AD5308/ AD5318/AD5328 use a versatile 3-wire serial interface that operates at clock rates up to 30 MHz and is compatible with standard SPI, QSPI, MICROWIRE, and DSP interface standards.

The references for the eight DACs are derived from two reference pins (one per DAC quad). These reference inputs can be configured as buffered, unbuffered, or V

Rev. F

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

inputs. The parts

DD

incorporate a power-on reset circuit, which ensures that the DAC outputs power up to 0 V and remain there until a valid write to the device takes place. The outputs of all DACs may be updated simultaneously using the asynchronous

LDAC

The parts contain a power-down feature that reduces the current consumption of the devices to 400 nA at 5 V (120 nA at 3 V). The eight channels of the DAC may be powered down individually.

All three parts are offered in the same pinout, which allows users to select the resolution appropriate for their application without redesigning their circuit board.

input.

AD5308/AD5318/AD5328

REVISION HISTORY

4/11—Rev. E to Rev. F

Added Automotive Products Information................. Throughout

2/11—Rev. D to Rev. E

Change to Temperature Range ....................................Throughout

Changes to Table 3, t

3/07—Rev. C to Rev. D

Updated Format..................................................................Universal

Changes to Absolute Maximum Ratings Section......................... 7

9/05—Rev. B to Rev. C

Updated Format..................................................................Universal

Change to Equation........................................................................ 21

11/03—Rev. A to Rev. B

Changes to Ordering Guide............................................................ 4

Changes to Y axis on TPCs 12, 13, and 15.................................... 9

8/03—Rev. 0 to Rev. A

Added A Version.................................................................Universal

Changes to Features.......................................................................... 1

Changes to Specifications................................................................ 2

Edits to Absolute Maximum Ratings ............................................. 4

Edits to Ordering Guide .................................................................. 4

Updated Outline Dimensions....................................................... 18

Timing Characteristics.............................. 6

4

Rev. F | Page 2 of 28

AD5308/AD5318/AD5328

V

A

FUNCTIONAL BLOCK DIAGRAM

V

DD

REF

BCD

V

DD

GAIN-SELECT

LOGIC

SCLK

SYNC

DIN

LDAC

INTERFACE

LOGIC

LDAC

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

RESET

INPUT

REGISTER

POWER-ON

RESET

DAC

REGISTER

STRING

DAC

REGISTER

DAC

REGISTER

DAC

REGISTER

DAC

REGISTER

DAC

REGISTER

DAC

REGISTER

DAC

REGISTER

Figure 1.

STRING

BUFFER

DAC A

STRING

DAC B

STRING

DAC C

STRING

DAC D

STRING

DAC E

STRING

DAC F

STRING

DAC G

STRING

DD

DAC H

V

REF

EFGH

V

DD

BUFFERBUFFER

GND

GAIN-SELECT

LOGIC

POWER-DOWN

LOGIC

GND

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

V

OUT

02812-001

A

B

C

D

E

F

G

H

Rev. F | Page 3 of 28

AD5308/AD5318/AD5328

SPECIFICATIONS

VDD = 2.5 V to 5.5 V; V

= 2 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications T

REF

MIN

to T

, unless otherwise specified.

MAX

Table 1.

A Version1

B Version

Parameter2 Min Typ Max Min Typ Max Unit Conditions/Comments

DC PERFORMANCE

3, 4

AD5308

Resolution 8 8 Bits Relative Accuracy ±0.15 ±1 ±0.15 ±0.75 LSB Differential Nonlinearity ±0.02 ±0.25 ±0.02 ±0.25 LSB Guaranteed monotonic by

AD5318

Resolution 10 10 Bits Relative Accuracy ±0.5 ±4 ±0.5 ±3 LSB Differential Nonlinearity ±0.05 ±0.50 ±0.05 ±0.50 LSB Guaranteed monotonic by

AD5328

Resolution 12 12 Bits Relative Accuracy ±2 ±16 ±2 ±12 LSB Differential Nonlinearity ±0.2 ±1.0 ±0.2 ±1.0 LSB Guaranteed monotonic by

Offset Error ±5 ±60 ±5 ±60 mV VDD = 4.5 V, gain = 2, see

1

design over all codes

Figure 27 and Figure 28

Gain Error ±0.30 ±1.25 ±0.30 ±1.25 % of FSR VDD = 4.5 V, gain = 2, see

Figure 27 and Figure 28

Lower Deadband5 10 60 10 60 mV Lower deadband exists only

if offset error is negative, see

Figure 27

Upper Deadband5

10 60 10 60 mV Upper deadband exists only

= VDD and offset plus

if V

REF

gain error is positive, see

Figure 28

Offset Error Drift6 −12 −12 ppm of

FSR/°C

Gain Error Drift6

−5 −5 ppm of FSR/°C

DC Power Supply Rejection Ratio6 DC Crosstalk6

DAC REFERENCE INPUTS6

V

Input Range 1.0 VDD 1.0 VDD V Buffered reference mode

REF

−60 −60 dB V

200 200 μV R

= ±10%

DD

= 2 kΩ to GND or VDD

L

0.25 VDD 0.25 VDD V Unbuffered reference mode V

Input Impedance (R

REF

) >10.0 >10.0 MΩ Buffered reference mode

DAC

and power-down mode

37.0 45.0 37.0 45.0 kΩ Unbuffered reference mode,

0 V to V

output range

REF

18.0 22.0 18.0 22.0 kΩ Unbuffered reference mode,

0 V to 2 V

output range

REF

Reference Feedthrough −70.0 −70.0 dB Frequency = 10 kHz Channel-to-Channel Isolation −75.0 −75.0 dB Frequency = 10 kHz

OUTPUT CHARACTERISTICS6

Minimum Output Voltage7 0.001 0.001 V This is a measure of the

minimum and maximum

Maximum Output Voltage7

V

−

DD

0.001

V

− 0.001 V Drive capability of the

DD

output amplifier

DC Output Impedance 0.5 0.5 Ω

Rev. F | Page 4 of 28

AD5308/AD5318/AD5328

A Version1

B Version

1

Parameter2 Min Typ Max Min Typ Max Unit Conditions/Comments

Short Circuit Current 25.0 25.0 mA VDD = 5 V

16.0 16.0 mA VDD = 3 V Power-Up Time 2.5 2.5 μs Coming out of power-down

mode, V

= 5 V

DD

5.0 5.0 μs Coming out of power-down = 3 V

DD

LOGIC INPUTS6

mode, V

Input Current ±1 ±1 μA VIL, Input Low Voltage 0.8 0.8 V VDD = 5 V ± 10%

0.8 0.8 V VDD = 3 V ± 10%

0.7 0.7 V VDD = 2.5 V VIH, Input High Voltage 1.7 1.7 V VDD = 2.5 V to 5.5 V, TTL and

CMOS compatible

Pin Capacitance 3.0 3.0 pF

POWER REQUIREMENTS

VDD 2.5 5.5 2.5 5.5 V IDD (Normal Mode)8 VIH = VDD and VIL = GND

VDD = 4.5 V to 5.5 V 1.0 1.8 1.0 1.8 mA All DACs in unbuffered

mode, in buffered mode

VDD = 2.5 V to 3.6 V 0.7 1.5 0.7 1.5 mA Extra current is typically x μA

per DAC; x = (5 μA +

)/4

V

REF/RDAC

IDD (Power-Down Mode)9 VIH = VDD and VIL = GND

VDD = 4.5 V to 5.5 V 0.4 1 0.4 1 μA VDD = 2.5 V to 3.6 V 0.12 1 0.12 1 μA

1

Temperature range (A, B version): −40°C to +125°C; typical at 25°C.

2

See the Terminology section.

3

DC specifications tested with the outputs unloaded unless stated otherwise.

4

Linearity is tested using a reduced code range: AD5308 (Code 8 to Code 255), AD5318 (Code 28 to Code 1023), and AD5328 (Code 115 to Code 4095).

5

This corresponds to x codes. x = deadband voltage/LSB size.

6

Guaranteed by design and characterization; not production tested.

7

For the amplifier output to reach its minimum voltage, offset error must be negative. For the amplifier output to reach its maximum voltage, V

gain error must be positive.

8

Interface inactive. All DACs active. DAC outputs unloaded.

9

All eight DACs powered down.

= VDD and offset plus

REF

V

= 2.5 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications T

DD

1

Table 2. AC Characteristics

MIN

to T

, unless otherwise noted.

MAX

A, B Version2 Parameter3 Min Typ Max Unit Conditions/Comments

Output Voltage Settling Time V

= VDD = 5 V

REF

AD5308 6 8 μs 1/4 scale to 3/4 scale change (0x40 to 0xC0) AD5318 7 9 μs 1/4 scale to 3/4 scale change (0x100 To 0x300) AD5328 8 10 μs 1/4 scale to 3/4 scale change (0x400 to 0xC00)

Slew Rate 0.7 V/μs Major-Code Change Glitch Energy 12 nV-sec 1 LSB change around major carry Digital Feedthrough 0.5 nV-sec Digital Crosstalk 0.5 nV-sec Analog Crosstalk 1 nV-sec DAC-to-DAC Crosstalk 3 nV-sec Multiplying Bandwidth 200 kHz V Total Harmonic Distortion −70 dB V

1

Guaranteed by design and characterization; not production tested.

2

Temperature range (A, B version): –40°C to +125°C; typical at 25°C.

3

See the Terminology section.

= 2 V ± 0.1 V p-p, unbuffered mode

REF

= 2.5 V ± 0.1 V p-p, frequency = 10 kHz

REF

Rev. F | Page 5 of 28

AD5308/AD5318/AD5328

Table 3. Timing Characteristics

1, 2, 3

A, B Version Parameter Limit at T

MIN

, T

Unit Conditions/Comments

MAX

t1 33 ns min SCLK cycle time t2 13 ns min SCLK high time t3 13 ns min SCLK low time t4 13 ns min

to SCLK falling edge setup time; temperature range (A, B

SYNC verstion): −40°C to +105°C

15 ns min

to SCLK falling edge setup time; temperature range (A, B

SYNC

verstion): −40°C to +125°C t5 5 ns min Data set up time t6 4.5 ns min Data hold time t7 0 ns min

t8 50 ns min t9 20 ns min t10 20 ns min t11 0 ns min

1

Guaranteed by design and characterization; not production tested.

2

All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.

3

See Figure 2.

SCLK falling edge to SYNC

Minimum SYNC

pulse width

LDAC

high time

SCLK falling edge to LDAC

t

1

rising edge

rising edge falling edge

SCLK

t

8

SYNC

DIN DB15

1

LDAC

2

LDAC

NOTES

1

ASYNCHRONOUS LDAC UPDATE MODE.

2

SYNCHRONOUS LDAC UPDATE MODE.

t

4

t

6

t

5

3

2

t

7

DB0

t

9

t

11

t

10

02812-002

Figure 2. Serial Interface Timing Diagram

Rev. F | Page 6 of 28

AD5308/AD5318/AD5328

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise specified.

Table 4.

Parameter Rating1

VDD to GND −0.3 V to +7 V Digital Input Voltage to GND −0.3 V to VDD + 0.3 V Reference Input Voltage to GND −0.3 V to VDD + 0.3 V V

OUTA–VOUTD

Operating Temperature Range

Industrial (A, B Version) −40°C to +125°C Storage Temperature Range −65°C to +150°C Junction Temperature (T 16-Lead TSSOP

Power Dissipation (T

θJA Thermal Impedance 150.4°C/W Lead Temperature JEDEC industry-standard

Soldering J-STD-020

1

Transient currents of up to 100 mA do not cause SCR latch-up.

to GND −0.3 V to VDD + 0.3 V

) 150°C

J MAX

− TA)/θJA

J MAX

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

Rev. F | Page 7 of 28

AD5308/AD5318/AD5328

V

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

LDAC

2

SYNC

AD5308/

3

V

DD

AD5318/

4

V

A

OUT

V

OUT

V

OUT

V

OUT

ABCD V

REF

B C D

AD5328

5

TOP VIEW

6

(Not to Scale)

7

8

Figure 3. Pin Configuration

Table 5. Pin Function Descriptions

Pin No. Mnemonic Description

1

This active low control input transfers the contents of the input registers to their respective DAC registers. Pulsing

LDAC

this pin low allows any or all DAC registers to be updated if the input registers have new data. This allows simultaneous updates of all DAC outputs. Alternatively, this pin can be tied permanently low.

2

Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it

SYNC

powers on the SCLK and DIN buffers and enables the input shift register. Data is transferred in on the falling edges of the following 16 clocks. If SYNC

is taken high before the 16th falling edge, the rising edge of SYNC acts as an

interrupt and the write sequence is ignored by the device.

3 VDD

Power Supply Input. These parts can be operated from 2.5 V to 5.5 V, and the supply should be decoupled with a 10 μF

capacitor in parallel with a 0.1 μF capacitor to GND. 4 V 5 V 6 V 7 V 8 V

9 V

10 V 11 V 12 V 13 V

A Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.

OUT

B Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.

OUT

C Buffered Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.

OUT

D Buffered Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.

OUT

ABCD

REF

EFGH

REF

E Buffered Analog Output Voltage from DAC E. The output amplifier has rail-to-rail operation.

OUT

F Buffered Analog Output Voltage from DAC F. The output amplifier has rail-to-rail operation.

OUT

G Buffered Analog Output Voltage from DAC G. The output amplifier has rail-to-rail operation.

OUT

H Buffered Analog Output Voltage from DAC H. The output amplifier has rail-to-rail operation.

OUT

Reference Input Pin for DACs A, B, C, and D. It can be configured as a buffered, unbuffered, or V

DACs, depending on the state of the BUF and V

mode and from 1 V to V

in buffered mode.

DD

control bits. It has an input range from 0.25 V to VDD in unbuffered

DD

Reference Input Pin for DACs E, F, G, and H. It can be configured as a buffered, unbuffered, or V

DACs, depending on the state of the BUF and V

mode and from 1 V to V

in buffered mode.

DD

control bits. It has an input range from 0.25 V to VDD in unbuffered

DD

14 GND Ground Reference Point for All Circuitry on the Part. 15 DIN

Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling edge of the

serial clock input. The DIN input buffer is powered down after each write cycle. 16 SCLK

Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can

be transferred at rates up to 30 MHz. The SCLK input buffer is powered down after each write cycle.

16

SCLK

15

DIN

14

GND

13

H

V

OUT

12

V

G

OUT

11

F

V

OUT

10

V

E

OUT

9

EFGH

REF

02812-003

input to the four

DD

input to the four

DD

Rev. F | Page 8 of 28

AD5308/AD5318/AD5328

TYPICAL PERFORMANCE CHARACTERISTICS

1.0

0.5

T V

= 25°C

A

= 5V

DD

0.3

0.2

0.1

TA = 25°C V

= 5V

DD

0

INL ERROR (LSB)

–0.5

–1.0

0 50 100 150 200 250

CODE

Figure 4. AD5308 Typical INL Plot

3

= 25°C

T

A

= 5V

V

DD

2

1

0

INL ERROR (LSB)

–1

–2

–3

0 200 400 600 800 1000

CODE

Figure 5. AD5318 Typical INL Plot

02812-006

02812-007

0

–0.1

DNL ERROR (LSB)

–0.2

–0.3

0 50 100 150 200 250

CODE

Figure 7. AD5308 Typical DNL Plot

0.6 TA = 25°C

V

= 5V

DD

0.4

0.2

0

–0.2

DNL ERROR (LSB)

–0.4

–0.6

0 200 400 600 800 1000

CODE

Figure 8. AD5318 Typical DNL Plot

02812-009

02812-010

12

TA = 25°C V

= 5V

DD

8

4

0

INL ERROR (LSB)

–4

–8

–12

20001500500 10000 2500 3000 3500 4000

CODE

02812-008

Figure 6. AD5328 Typical INL Plot

1.0 TA = 25°C

V

= 5V

DD

0.5

0

DNL ERROR (LSB)

–0.5

–1.0

20001500500 10000 2500 3000 3500 4000

CODE

02812-011

Figure 9. AD5328 Typical DNL Plot

Rev. F | Page 9 of 28

AD5308/AD5318/AD5328

0.50

0.25

TA = 25°C V

= 5V

DD

MAX INL

MAX DNL

0.2

0.1

–0.1

0

TA = 25°C V

= 2V

REF

GAIN ERROR

0

ERROR (LSB)

–0.25

–0.50

012345

Figure 10. AD5308 INL and DNL Error vs. V

0.5 V

= 3V

REF

0.4 V

= 5V

DD

0.3

0.2

0.1

0

–0.1

ERROR (LSB)

–0.2

–0.3

–0.4

–0.5

– 40 0 40

MAX INL

MAX DNL

TEMPERATURE (°C)

MIN DNL

MIN INL

V

(V)

REF

MIN DNL

MIN INL

80 120

Figure 11. AD5308 INL Error and DNL Error vs. Temperature

02812-012

02812-013

ERROR (% FSR)

(V)

OUT

V

–0.2

–0.3

–0.4

–0.5

–0.6

OFFSET ERROR

2301 456

V

(V)

DD

Figure 13. Offset Error and Gain Error vs. V

5

4

3

2

1

0

Figure 14. V

OUT

5V SOURCE

3V SOURCE

2301 45

SINK/SOURCE CURRENT (mA)

Source and Sink Current Capability

5V SINK

DD

3V SINK

02812-015

02812-016

6

1.0 VDD = 5V

V

= 2V

REF

0.5

GAIN ERROR

0

ERROR (% FSR)

–0.5

–1.0

0–40 40 80 120

TEMPERATURE (°C)

OFFSET ERROR

Figure 12. AD5308 Offset Error and Gain Error vs. Temperature

02812-014

Rev. F | Page 10 of 28

1.0

0.9

0.8

0.7

0.6

(mA)

0.5

DD

I

0.4

0.3

0.2

0.1

0

ZERO SCALE FULL SCALE

HALF SCALE

DAC CODE

TA = 25°C

= 5V

V

DD

Figure 15. Supply Current vs. DAC Code

02812-017

AD5308/AD5318/AD5328

CH1C

1.3

1.2

TA = 25°C

V

= 2V, GAIN = +1,

REF

BUFFERED

TA = 25°C V

= 5V

DD

= 5V

V

REF

(mA)

DD

I

1.1

1.0

0.9

0.8

0.7

0.6

2.0

V

= V

REF

DD

V

= 2V, GAIN = +1, UNBUFFERED

REF

= VDD, GAIN = +1, UNBUFFERED

V

REF

2.5 3.0 3.5 4.0 4.5 5.0 SUPPLY VOLTAGE (V)

Figure 16. Supply Current vs. Supply Voltage

1.0 TA = 25°C

0.9

0.8

A)

μ

0.7

0.6

0.5

POWER-DOWN (

0.4

DD

I

0.3

0.2

0.1

0

2.0

2.5 3.0 3.5 4.0 4.5 5.0 5.5 VDD (V)

Figure 17. Power-Down Current vs. Supply Voltage

02812-018

02812-019

V

A

OUT

CH1

SCLK

CH2

CH1 1V, CH2 5V, TIME BASE = 1μs/DIV

Figure 19. Half-Scale Settling (1/4 to 3/4 Scale Code Change)

TA = 25°C

= 5V

V

DD

= 2V

V

REF

V

DD

V

A

H2

CH1 2.00V, CH2 200mV, TIME BASE = 200μs/DIV

OUT

Figure 20. Power-On Reset to 0 V

02812-021

02812-022

1.4

1.3

1.2

1.1

(mA)

DD

I

1.0

0.9

0.8

0.7

0.6 0 1.0

DECREASING

INCREASING

VDD = 3V

2.0 3.0 4.0

1.5 2.5 3.50.5 4.5 5.0 V

(V)

LOGIC

TA = 25°C

= 5V

V

DD

02812-020

Figure 18. Supply Current vs. Logic Input Voltage for SCLK and DIN Increasing

and Decreasing

Rev. F | Page 11 of 28

CH1

CH2

TA = 25°C V

= 5V

DD

V

= 2V

REF

V

A

OUT

PD

CH1 500V, CH2 5.00mV, TIME BASE = 1μs/DIV

Figure 21. Exiting Power-Down to Midscale

02812-023

AD5308/AD5318/AD5328

35

30

25

20

FREQUENCY

15

10

SS = 300 V

= 3V

DD

V

= 5V

DD

MEAN: 0.693798 MEAN: 1.02055

5

0.02 TA = 25°C

V

= 5V

DD

0.01

0

FULL-SCALE ERROR (V)

–0.01

(V)

OUT

V

0

2.50

2.49

2.48

2.47

Figure 22. I

0.7 0.8 0.9 1.0 1.1

0.6

Histogram with VDD = 3 V and VDD = 5 V

DD

IDD (mA)

1μs/DIV

Figure 23. AD5328 Major-Code Transition Glitch Energy

10

0

–10

02812-024

02812-025

–0.02

0123456

Figure 25. Full-Scale Error vs. V

1mV/DIV

V

REF

100ns/DIV

(V)

REF

Figure 26. DAC-to-DAC Crosstalk

02812-027

02812-028

–20

(dB)

–30

–40

–50

–60

10

100 1k 10k 100k 1M 10M

FREQUENCY (Hz)

Figure 24. Multiplying Bandwidth (Small-Signal Frequency Response)

02812-026

Rev. F | Page 12 of 28

AD5308/AD5318/AD5328

TERMINOLOGY

Relative Accuracy

For the DAC, relative accuracy or integral nonlinearity (INL) is a measure of the maximum deviation, in LSB, from a straight line passing through the endpoints of the DAC transfer function. Typical INL vs. code plots can be seen in Figure 4, Figure 5, and Figure 6.

Differential Nonlinearity

Differential nonlinearity (DNL) is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of ±1 LSB maximum ensures monotonicity. This DAC is guaranteed monotonic by design. Typical DNL vs. code plots can be seen in Figure 7, Figure 8, and Figure 9.

Offset Error

This is a measure of the offset error of the DAC and the output amplifier (see Figure 27 and Figure 28). It can be negative or positive, and is expressed in millivolts.

Gain Error

This is a measure of the span error of the DAC. It is the deviation in slope of the actual DAC transfer characteristic from the ideal expressed as a percentage of the full-scale range.

Offset Error Drift

This is a measure of the change in offset error with changes in temperature. It is expressed in (ppm of full-scale range)/°C.

Gain Error Drift

This is a measure of the change in gain error with changes in temperature. It is expressed in (ppm of full-scale range)/°C.

DC Power Supply Rejection Ratio (PSRR)

This indicates how the output of the DAC is affected by changes in the supply voltage. PSRR is the ratio of the change in V a change in V in decibels. V

for full-scale output of the DAC. It is measured

DD

is held at 2 V and VDD is varied ±10%.

REF

OUT

to

DC Crosstalk

This is the dc change in the output level of one DAC in response to a change in the output of another DAC. It is measured with a full-scale output change on one DAC while monitoring another DAC. It is expressed in microvolts.

Reference Feedthrough

This is the ratio of the amplitude of the signal at the DAC output to the reference input when the DAC output is not being updated (that is,

LDAC

is high). It is expressed in decibels.

Channel-to-Channel Isolation

This is the ratio of the amplitude of the signal at the output of one DAC to a sine wave on the reference input of another DAC. It is measured in decibels.

Major-Code Transition Glitch Energy

Major-code transition glitch energy is the energy of the impulse injected into the analog output when the code in the DAC register changes state. It is normally specified as the area of the glitch in nV-sec and is measured when the digital code is changed by 1 LSB at the major carry transition (011 ... 11 to 100 ... 00 or 100 ... 00 to 011 ... 11).

Digital Feedthrough

Digital feedthrough is a measure of the impulse injected into the analog output of a DAC from the digital input pins of the device, but is measured when the DAC is not being written to

SYNC

(

held high). It is specified in nV-sec and is measured with a full-scale change on the digital input pins, that is, from all 0s to all 1s and vice versa.

Digital Crosstalk

This is the glitch impulse transferred to the output of one DAC at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) in the input register of another DAC. It is measured in standalone mode and is expressed in nV-sec.

Analog Crosstalk

This is the glitch impulse transferred to the output of one DAC due to a change in the output of another DAC. It is measured by loading one of the input registers with a full-scale code change (all 0s to all 1s and vice versa) while keeping

LDAC

pulse

low and monitor the output of the DAC whose digital

LDAC

high. Then

code is not changed. The area of the glitch is expressed in nV-sec.

DAC-to-DAC C rosst a l k

This is the glitch impulse transferred to the output of one DAC due to a digital code change and subsequent output change of another DAC. This includes both digital and analog crosstalk. It is measured by loading one of the DACs with a full-scale code change (all 0s to all 1s and vice versa) with

LDAC

low and monitoring the output of another DAC. The energy of the glitch is expressed in nV-sec.

Multiplying Bandwidth

The amplifiers within the DAC have a finite bandwidth. The multiplying bandwidth is a measure of this. A sine wave on the reference (with full-scale code loaded to the DAC) appears on the output. The multiplying bandwidth is the frequency at which the output amplitude falls to 3 dB below the input.

Total Harmonic Distortion (THD)

This is the difference between an ideal sine wave and its attenuated version using the DAC. The sine wave is used as the reference for the DAC and the THD is a measure of the harmonics present on the DAC output. It is measured in decibels.

Rev. F | Page 13 of 28

AD5308/AD5318/AD5328

OUTPUT

VOLTAGE

NEGATIVE

OFFSET

ERROR

AMPLIFIER

FOOTROOM

NEGATIVE

OFFSET

ERROR

DAC CODE

W

LO

DEAD

BAND

DES

CO

Figure 27. Transfer Function with Negative Offset (V

ER

GAIN ERROR PLUS OFFSET ERROR

ACTUAL IDEAL

= VDD)

REF

02812-004

GAIN ERROR PLUS OFFSET ERROR

UPPER

OUTPUT

VOLTAGE

POSITIVE

OFFSET

ERROR

ACTUAL

IDEAL

DAC CODE

DEADBAND CODES

FULL SCALE

02812-005

Figure 28. Transfer Function with Positive Offset

Rev. F | Page 14 of 28

AD5308/AD5318/AD5328

THEORY OF OPERATION

The AD5308/AD5318/AD5328 are octal resistor-string DACs fabricated on a CMOS process with resolutions of 8, 10, and 12 bits, respectively. Each contains eight output buffer amplifiers and is written to via a 3-wire serial interface. They operate from single supplies of 2.5 V to 5.5 V and the output buffer amplifiers provide rail-to-rail output swing with a slew rate of

0.7 V/µs. DAC A, DAC B, DAC C, and DAC D share a common reference input, V share a common reference input, V

ABCD. DAC E, DAC F, DAC G, and DAC H

REF

EFGH. Each reference

REF

input can be buffered to draw virtually no current from the reference source, can be unbuffered to give a reference input range from 0.25 V to V

, or can come from VDD. The devices

DD

have a power-down mode in which all DACs can be turned off individually with a high impedance output.

DIGITAL-TO-ANALOG CONVERTER

The architecture of one DAC channel consists of a resistor string DAC followed by an output buffer amplifier. The voltage at the V sponding DAC. Figure 29 shows a block diagram of the DAC architecture. Since the input coding to the DAC is straight binary, the ideal output voltage is given by

where:

D is the decimal equivalent of the binary code that is loaded to

the DAC register: 0 to 255 for AD5308 (8 bits) 0 to 1023 for AD5318 (10 bits) 0 to 4095 for AD5328 (12 bits)

N is the DAC resolution.

V

REGISTER

DAC Reference Inputs

There is a reference pin for each quad of DACs. The reference inputs can be buffered from V with the buffered input is the high impedance it presents to the voltage source driving it. However, if the unbuffered mode is used, the user can have a reference voltage as low as 0.25 V and as high as V and footroom of the reference amplifier.

pin provides the reference voltage for the corre-

REF

DV

×

V

DD

INPUT

OUT

REF

=

N

2

V

ABCD

V

DD

BUF

DAC

REGISTER

Figure 29. Single DAC Channel Architecture

since there is no restriction due to the headroom

DD

REF

REFERENCE BUFFER

RESISTOR

STRING

, or unbuffered. The advantage

DD

GAIN MODE

(GAIN = +1 OR +2)

OUTPUT

BUFFER AMPLIFIER

V

OUT

A

02812-029

If there is a buffered reference in the circuit (for example, the REF192), there is no need to use the on-chip buffers of the AD5308/AD5318/AD5328. In unbuffered mode, the input impedance is still large at typically 45 k per reference input for 0 V to V

mode and 22 k for 0 V to 2 V

REF

mode.

REF

RESISTOR STRING

The resistor-string section is shown in Figure 30. It is simply a string of resistors, each of value R. The digital code loaded to the DAC register determines at which node on the string the voltage is tapped off to be fed into the output amplifier. The voltage is tapped off by closing one of the switches connecting the string to the amplifier. Because it is a string of resistors, it is guaranteed monotonic.

R

Figure 30. Resistor String

TO OUTPUT AMPLIFIER

02812-030

OUTPUT AMPLIFIER

The output buffer amplifier is capable of generating output voltages to within 1 mV of either rail. Its actual range depends on the value of V error, and the gain error.

If a gain of 1 is selected (gain bit = 0), the output range is

0.001 V to V

If a gain of 2 is selected (gain bit = 1), the output range is

0.001 V to 2 V output is limited to V

The output amplifier is capable of driving a load of 2 k to GND or V

DD

source and sink capabilities of the output amplifier can be seen in the plot in Figure 14.

The slew rate is 0.7 V/s with a half-scale settling time to ±0.5 LSB (at 8 bits) of 6 s.

, the gain of the output amplifier, the offset

REF

.

REF

. Because of clamping, however, the maximum

REF

− 0.001 V.

DD

, in parallel with 500 pF to GND or VDD. The

Rev. F | Page 15 of 28

AD5308/AD5318/AD5328

POWER-ON RESET

The AD5308/AD5318/AD5328 are provided with a power-on reset function so that they power up in a defined state. The power-on state is

• Normal operation

• Reference inputs unbuffered

• 0 V to V

output range

REF

• Output voltage set to 0 V

•

LDAC

bits set to

LDAC

high

Both input and DAC registers are filled with 0s and remain so until a valid write sequence is made to the device. This is particularly useful in applications where it is important to know the state of the DAC outputs while the device is powering up.

POWER-DOWN MODE

The AD5308/AD5318/AD5328 have low power consumption, typically dissipating 2.4 mW with a 3 V supply and 5 mW with a 5 V supply. Power consumption can be further reduced when the DACs are not in use by putting them into power-down mode, which is described in the Serial Interface section.

When in default mode, all DACs work normally with a typical power consumption of 1 mA at 5 V (800 A at 3 V). However, when all DACs are powered down, that is, in power-down mode, the supply current falls to 400 nA at 5 V (120 nA at 3 V). Not only does the supply current drop, but the output stage is also internally switched from the output of the amplifier, making it open-circuit. This has the advantage that the output is three-state while the part is in power-down mode, and provides a defined input condition for whatever is connected to the output of the DAC amplifier. The output stage is illustrated in Figure 31.

The bias generator, the output amplifiers, the resistor string, and all other associated linear circuitry are shut down when the power-down mode is activated. However, the contents of the registers are unaffected when in power-down. In fact, it is possible to load new data to the input registers and DAC registers during power-down. The DAC outputs update as soon as the device comes out of power-down mode. The time to exit power-down is typically 2.5 s when V V

= 3 V.

DD

RESISTOR-

STRING DAC

Figure 31. Output Stage During Power-Down

= 5 V and 5 s when

DD

AMPLIFIER

POWER-DOWN

CIRCUITRY

V

OUT

02812-035

SERIAL INTERFACE

The AD5308/AD5318/AD5328 are controlled over a versatile 3-wire serial interface that operates at clock rates up to 30 MHz and is compatible with SPI, QSPI, MICROWIRE, and DSP interface standards.

Input Shift Register

The input shift register is 16 bits wide. Data is loaded into the device as a 16-bit word under the control of a serial clock input, SCLK. The timing diagram for this operation is shown in Figure 2.

SYNC

The synchronization signal and chip enable. Data can be transferred into the device only while transfer, SYNC low, serial data is shifted into the device’s input shift register on the falling edges of SCLK for 16 clock pulses.

To end the transfer, edge of the 16th SCLK pulse, observing the minimum SCLK falling edge to

After the end of the serial data transfer, data is automatically transferred from the input shift register to the input register of the selected DAC. If edge of SCLK, the data transfer is aborted and the DAC input registers are not updated.

Data is loaded MSB first (Bit 15). The first bit determines whether it is a DAC write or a control function.

DAC Write

The 16-bit word consists of 1 control bit and 3 address bits followed by 8, 10, or 12 bits of DAC data, depending on the device type. In the case of a DAC write, the MSB is a 0. The next 3 address bits determine whether the data is for DAC A, DAC B, DAC C, DAC D, DAC E, DAC F, DAC G, or DAC H. The AD5328 uses all 12 bits of DAC data. The AD5318 uses 10 bits and ignores the 2 LSBs. The AD5308 uses 8 bits and ignores the last 4 bits. These ignored LSBs should be set to 0. The data format is straight binary, with all 0s corresponding to 0 V output and all 1s corresponding to full-scale output.

Table 6. Address Bits for the AD5308/AD5318/AD5328

A2 (Bit 14) A1 (Bit 13) A0 (Bit 12) DAC Addressed

0 0 0 DAC A 0 0 1 DAC B 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 DAC H

input is a level-triggered input that acts as a frame

SYNC

is low. To start the serial data

SYNC

should be taken low, observing the minimum

to SCLK falling edge set-up time, t4. After

SYNC

must be taken high after the falling

SYNC

rising edge time, t7.

SYNC

is taken high before the 16th falling

SYNC

DAC C DAC D DAC E DAC F DAC G

goes

Rev. F | Page 16 of 28

AD5308/AD5318/AD5328

Control Functions

In the case of a control function, the MSB (Bit 15) is a 1. This is followed by two control bits, which determine the mode. There

LDAC

are four different control modes: reference and gain mode, mode, power-down mode, and reset mode. The write sequences for these modes are shown in . Tabl e 7

Reference and Gain Mode

This mode determines whether the reference for each group of DACs is buffered, unbuffered, or from V

. It also determines

DD

the gain of the output amplifier. To set up the reference of both groups, set the control bits to (00), set the GAIN bits, the BUF bits, and the V

DD

bits.

Table 7. Control Words for the AD53x8

/C

D

Control Bits

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Mode

GAIN Bits BUF Bits VDD Bits Gain of output amplifier and 1 0 0 x x x x x x x E...H A...D E...H A...D E...H A...D reference selection

1 0 1 x x x x x x x x x x x 1/0 1/0

Channels 1 1 0 x x x x x H G F E D C B A Power-down Reset 1 1 1 1/0 x x x x x x x x x x x x Reset

BIT 15 (MSB)

D/C

BIT 15 (MSB)

A1A2

A0 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0

DATA BITS

Figure 32. AD5308 Input Shift Register Contents

A1

A0

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0A2D/C

DATA BITS

Figure 33. AD5318 Input Shift Register Contents

A0

A1A2

Figure 34. AD5328 Input Shift Register Contents

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0D10D11D/C

DATA BITS

BIT 0 (LSB)

02812-031

02812-032

02812-033

VDD

These bits are set when VDD is to be used as a reference. The first group of DACs (A, B, C, and D) can be set up to use V

DD

by setting Bit 0, and the second group of DACs (E, F, G, and H) by setting Bit 1. The V

When V

is used as the reference, it is always unbuffered and

DD

has an output range of 0 V to V

bits have priority over the BUF bits.

DD

regardless of the state of the

REF

GAIN and BUF bits.

BUF

This controls whether the reference of a group of DACs is buffered or unbuffered. The reference of the first group of DACs (A, B, C, and D) is controlled by setting Bit 2, and the second group of DACs (E, F, G, and H) is controlled by setting Bit 3.

0: unbuffered reference. 1: buffered reference.

GAIN

The gain of the DACs is controlled by setting Bit 4 for the first group of DACs (A, B, C, and D) and Bit 5 for the second group of DACs (E, F, G, and H).

0: output range of 0 V to V 1: output range of 0 V to 2 V

Bits

LDAC

.

REF

.

REF

LDAC

Mode

LDAC

mode controls

LDAC

, which determines when data is transferred from the input registers to the DAC registers. There are three options when updating the DAC registers, as shown in

. Tab l e 8

Table 8.

Bit 15 Bit 14 Bit 13

1 0 1 x ... x 0 0 1 0 1 x ... x 0 1 1 0 1 x ... x 1 0

LDAC

Mode

Bits 12:2

Bit 1 Bit 0 Description

LDAC low LDAC high LDAC single

update

1 0 1 x ... x 1 1 Reserved

LDAC

Low (00): This option sets

LDAC

permanently low,

allowing the DAC registers to be updated continuously.

LDAC

High (01): This option sets

LDAC

permanently high. The DAC registers are latched and the input registers can change without affecting the contents of the DAC registers. This is the default option for this mode.

LDAC

Single Update (10): This option causes a single pulse on

LDAC

, updating the DAC registers once.

Reserved (11): reserved.

Rev. F | Page 17 of 28

AD5308/AD5318/AD5328

Power-Down Mode

The individual channels of the AD5308/AD5318/AD5328 can be powered down separately. The control mode for this is (10). On completion of this write sequence, the channels that have been set to 1 are powered down.

Reset Mode

This mode consists of two possible reset functions, as outlined in Tab l e 9 .

Table 9. Reset Mode

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 ... 0 Des cription

1 1 1 0 x ... x DAC data reset 1 1 1 1 x ... x Data and control reset

DAC Data Reset: On completion of this write sequence, all DAC registers and input registers are filled with 0s.

Data and Control Reset: This function carries out a DAC data

LDAC

,

reset and resets all the control bits (GAIN, BUF, V

DD

, and

power-down channels) to their power-on conditions.

LOW POWER SERIAL INTERFACE

To minimize the power consumption of the device, the interface powers up fully only when the device is being written to, that is,

SYNC

on the falling edge of are powered down on the rising edge of

. The SCLK and DIN input buffers

SYNC

.

LOAD DAC INPUT (LDAC) FUNCTION

LDAC

function

02812-034

mode bits

Access to the DAC registers is controlled by both the

LDAC

and the

mode bits. The operation of the

can be likened to the configuration shown in . Figure 35

EXTERNAL LDAC PIN

INTERNAL LDAC MODE

Figure 35.

LDAC

LDAC FUNCTION

Function

If the user wishes to update the DAC through software, the LDAC

pin should be tied high and the

LDAC

mode bits set as required. Alternatively, if the user wishes to control the DAC through hardware, that is, the should be set to

LDAC

high (default mode).

LDAC

pin, the

LDAC

Use of the data, and the GAIN, BUF and V which the

Synchronous data is read in on the falling edge of the 16th SCLK pulse. LDAC

Asynchronous time that the input registers are written to. When low, the DAC registers are updated with the contents of the

input register.

DOUBLE-BUFFERED INTERFACE

The AD5308/AD5318/AD5328 DACs all have double-buffered interfaces consisting of two banks of registers: input and DAC. The input registers are connected directly to the input shift register and the digital code is transferred to the relevant input register on completion of a valid write sequence. The DAC registers contain the digital code used by the resistor strings.

When the the DAC registers are latched and the input registers can change state without affecting the contents of the DAC registers. However, when the is brought low, the DAC registers become transparent and the contents of the input registers are transferred to them.

The double-buffered interface is useful if the user requires simultaneous updating of all DAC outputs. The user can write up to seven of the input registers individually and then, by bringing register, all outputs will update simultaneously.

These parts contain an extra feature whereby a DAC register is not updated unless its input register has been updated since the last time the DAC registers are filled with the contents of the input registers. In the case of the AD5308/AD5318/AD5328, the part updates the DAC register only if the input register has been changed since the last time the DAC register was updated, thereby removing unnecessary digital crosstalk.

LDAC

function enables double-buffering of the DAC

bits. There are two ways in

DD

LDAC

function can operate:

LDAC

: The DAC registers are updated after new

can be permanently low or pulsed as in . Figure 2

LDAC

: The outputs are not updated at the same

LDAC

pin is high and the

LDAC

bits are set to (00) or when the

LDAC

low when writing to the remaining DAC input

LDAC

was low. Normally, when

LDAC

bits are set to (01),

LDAC

is brought low,

goes

LDAC

Rev. F | Page 18 of 28

AD5308/AD5318/AD5328

MICROPROCESSOR INTERFACE

ADSP-2101/ADSP-2103-toAD5308/AD5318/AD5328 INTERFACE

Figure 36 shows a serial interface between the AD5308/AD5318/ AD5328 and the ADSP-2101/ADSP-2103. The ADSP-2101/ ADSP-2103 should be set up to operate in the SPORT transmit alternate framing mode. The ADSP-2101/ADSP-2103 SPORT is programmed through the SPORT control register and should be configured as follows: internal clock operation, active low framing, and 16-bit word length. Transmission is initiated by writing a word to the Tx register after the SPORT has been enabled. The data is clocked out on each rising edge of the DSP’s serial clock and clocked into the AD5308/AD5318/ AD5328 on the falling edge of the DAC’s SCLK.

ADSP-2101/ ADSP-2103*

TFS

DT

SCLK SCLK

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 36. ADSP-2101/ADSP-2103-to-AD5308/AD5318/AD5328 Interface

SYNC DIN

AD5308/ AD5318/

AD5328*

02812-036

68HC11/68L11-to-AD5308/AD5318/AD5328 INTERFACE

Figure 37 shows a serial interface between the AD5308/AD5318/ AD5328 and the 68HC11/68L11 microcontroller. SCK of the 68HC11/68L11 drives the SCLK of the AD5308/AD5318/AD5328, and the MOSI output drives the serial data line (DIN) of the DAC. The sync signal is derived from a port line (PC7). The set up conditions for the correct operation of this interface are as follows: the 68HC11/68L11 should be configured so that its CPOL bit is a 0 and its CPHA bit is a 1. When data is being transmitted to the DAC, the sync line is taken low (PC7). When the 68HC11/ 68L11 is configured as just described, data appearing on the MOSI output is valid on the falling edge of SCK. Serial data from the 68HC11/ 68L11 is transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. Data is transmitted MSB first. To load data to the AD5308/AD5318/AD5328, PC7 is left low after the first eight bits are transferred, and a second serial write operation is performed to the DAC. PC7 is taken high at the end of this procedure.

68HC11/68L11

PC7

SCK

MOSI

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 37. 68HC11/68L11-to-AD5308/AD5318/ AD5328 Interface

SYNC SCLK DIN

AD5308/ AD5318/

AD5328*

02812-037

80C51/80L51-to-AD5308/AD5318/AD5328 INTERFACE

Figure 38 shows a serial interface between the AD5308/AD5318/ AD5328 and the 80C51/80L51 microcontroller. The setup for the interface is as follows: TxD of the 80C51/80L51 drives SCLK of the AD5308/AD5318/AD5328, while RxD drives the serial data

SYNC

line of the part. The programmable pin on the port. In this case, port line P3.3 is used. When data is transmitted to the AD5308/AD5318/AD5328, P3.3 is taken low. The 80C51/80L51 transmits data only in 8-bit bytes; thus, only eight falling clock edges occur in the transmit cycle. To load data to the DAC, P3.3 is left low after the first eight bits are transmitted, and a second write cycle is initiated to transmit the second byte of data. P3.3 is taken high following the completion of this cycle. The 80C51/80L51 outputs the serial data in a format that has the LSB first. The AD5308/AD5318/AD5328 requires its data with the MSB as the first bit received. The 80C51/80L51 transmit routine should take this into account.

80C51/80L51*

P3.3

RxD

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 38. 80C51/80L51-to-AD5308/AD5318/AD5328 Interface

signal is again derived from a bit

TxD

SYNC SCLK DIN

AD5308/ AD5318/

AD5328*

02812-038

Rev. F | Page 19 of 28

AD5308/AD5318/AD5328

MICROWIRE-to-AD5308/AD5318/AD5328 INTERFACE

Figure 39 shows an interface between the AD5308/AD5318/ AD5328 and any MICROWIRE-compatible device. Serial data is shifted out on the falling edge of the serial clock, SK, and is clocked into the AD5308/AD5318/AD5328 on the rising edge of SK, which corresponds to the falling edge of the DAC’s SCLK.

MICROWIRE*

CS SK SO

AD5308/ AD5318/ AD5328*

SYNC SCLK DIN

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 39. MICROWIRE-to-AD5308/AD5318/AD5328 Interface

02812-039

Rev. F | Page 20 of 28

AD5308/AD5318/AD5328

A

W

A

V

(

)

(

APPLICATIONS INFORMATION

TYPICAL APPLICATION CIRCUIT

The AD5308/AD5318/AD5328 can be used with a wide range of reference voltages where the devices offer full, one-quadrant multiplying capability over a reference range of 0.25 V to V

DD

. More typically, these devices are used with a fixed, precision reference voltage. Suitable references for 5 V operation are the AD780, ADR381, and REF192 (2.5 V references). For 2.5 V operation, a suitable external reference is the AD589 or the AD1580 (1.2 V band gap references). Figure 40 shows a typical setup for the AD5308/AD5318/AD5328 when using an external reference.

= 2.5V TO 5.5V

V

DD

10μF

0.1μF

V

A

V

IN

V

OUT

EXT REF

D780/ADR3811/REF192

ITH VDD = 5V OR

D589/AD1580 WITH

= 2.5V

DD

1μF

INTERFACE

SERIAL

V

ABCD

REF

V

EFGH

REF

AD5308/AD5318/

AD5328

SCL DIN SYNC

GND

Figure 40. AD5308/AD5318/AD5328 Using a 2.5 V or 5 V External Reference

OUT

B

V

OUT

G

V

OUT

V

H

OUT

02812-040

DRIVING VDD FROM THE REFERENCE VOLTAGE

If an output range of 0 V to VDD is required when the reference inputs are configured as unbuffered, the simplest solution is to connect the reference input to V

. As this supply can be noisy

DD

and not very accurate, the AD5308/AD5318/AD5328 can be powered from a voltage reference. For example, using a 5 V reference, such as the REF195, works because the REF195 outputs a steady supply voltage for the AD5308/AD5318/ AD5328. The typical current required from the REF195 is a 1 A supply current and ≈ 112 A into the reference inputs (if unbuffered); this is with no load on the DAC outputs. When the DAC outputs are loaded, the REF195 also needs to supply the current to the loads. The total current required (with a10 k load on each output) is

1.22 mA + 8(5 V/10 k) = 5.22 mA

The load regulation of the REF195 is typically 2.0 ppm/mA, which results in an error of 10.4 ppm (52 V) for the 5.22 mA current drawn from it. This corresponds to a 0.003 LSB error at 8 bits and 0.043 LSB error at 12 bits.

BIPOLAR OPERATION USING THE AD5308/AD5318/AD5328

The AD5308/AD5318/AD5328 have been designed for singlesupply operation, but a bipolar output range is also possible using the circuit in Figure 41. This circuit gives an output voltage range of ±5 V. Rail-to-rail operation at the amplifier

Rev. F | Page 21 of 28

output is achievable using an AD820, the AD8519, or an OP196 as the output amplifier.

R2

10kΩ

V

IN

REF192

GND

+6V TO +16V

10μF

V

OUT

0.1μF

μ

1

+5V

R1

10kΩ

V

DD

V

OUT

AD5308/ AD5318/

AD5328

V

ABCD

F

REF

V

REF

GND

DIN

V

B

V

SCLK

SERIAL

INTERFACE

OUT OUT

OUT

SYNC

+5V

±5V

–5V

02812-041

AD820/ AD8519/ OP196

A

B C

H

Figure 41. Bipolar Operation with the AD5308/AD5318/AD5328

The output voltage for any input code can be calculated as follows:

⎡

=

V

⎢

OUT

⎢

⎣

N

R1

⎤

()

+××

RR1DREFIN

22/

⎥ ⎥

⎦

()

R1RREFIN

/2

×−

where:

D is the decimal equivalent of the code loaded to the DAC. N is the DAC resolution. REFIN is the reference voltage input.

with

REFIN = 5 V , R1 = R2 = 10 k

N

)

VDV

OUT

52/10 −×=

OPTO-ISOLATED INTERFACE FOR PROCESS CONTROL APPLICATIONS

The AD5308/AD5318/AD5328 have a versatile 3-wire serial interface, making them ideal for generating accurate voltages in process control and industrial applications. Due to noise and safety requirements, or distance, it may be necessary to isolate the AD5308/AD5318/AD5328 from the controller. This can easily be achieved by using opto-isolators that provide isolation in excess of 3 kV. The actual data rate achieved may be limited by the type of optocouplers chosen. The serial loading structure of the AD5308/AD5318/AD5328 makes them ideally suited for use in opto-isolated applications. Figure 42 shows an optoisolated interface to the AD5308/AD5318/AD5328 where DIN,

SYNC

SCLK, and supply to the part also needs to be isolated. This is done by using a transformer. On the DAC side of the transformer, a 5 V regulator provides the 5 V supply required for the AD5308/ AD5318/AD5328.

are driven from optocouplers. The power

AD5308/AD5318/AD5328

5V

POWER

SCLK

V

10kΩ

REGULATOR

DD

SCLK

10μF

0.1μF

V

DD

V

ABCD

REF

V

EFGH

REF

AD5308/AD5318/

SYNC

DIN

10kΩ

V

DD

V

DD

SYNC

DIN

AD5328

GND

V

A

OUT

V

B

OUT

V

C

OUT

V

D

OUT

V

E

OUT

V

F

OUT

V

G

OUT

V

H

OUT

02812-042

Figure 42. AD5308/AD5318/AD5328 in an Opto-Isolated Interface

DECODING MULTIPLE AD5308/AD5318/AD5328s

SYNC

The applications to decode a number of DACs. In this application, the DACs in the system receive the same serial clock and serial data but only the time, allowing access to four channels in this 16-channel system. The 74HC139 is used as a 2-to-4 line decoder to address any of the DACs in the system. To prevent timing errors from occurring, the enable input should be brought to its inactive state while the coded-address inputs are changing state. Figure 43 multiple AD5308 devices in a system.

pin on the AD5308/AD5318/AD5328 can be used in

SYNC

to one of the devices is active at any one

shows a diagram of a typical setup for decoding

SCLK

DIN

ENABLE

CODED

ADDRESS

V V

SYNC

AD5308

DIN

V

DD

V

CC

1G 1Y0 1A 1B

74HC139

DGND

1Y1 1Y2 1Y3

SCLK

SYNC DIN SCLK

V V

AD5308

V V

AD5308

V V

AD5308

V V

Figure 43. Decoding Multiple AD5308 Devices in a System

OUT OUT

A B

G H

A B

G H

A B

G H

A B

G H

02812-043

Rev. F | Page 22 of 28

AD5308/AD5318/AD5328

Table 10. Overview of AD53xx Serial Devices

Part No. Resolution DNL V SINGLES

AD5300 8 ±0.25 0 (V AD5310 10 ±0.50 0 (V AD5320 12 ±1.00 0 (V AD5301 8 ±0.25 0 (V AD5311 10 ±0.50 0 (V AD5321 12 ±1.00 0 (V

DUALS

AD5302 8 ±0.25 2 6 SPI MSOP 10 AD5312 10 ±0.50 2 7 SPI MSOP 10 AD5322 12 ±1.00 2 8 SPI MSOP 10 AD5303 8 ±0.25 2 6 SPI TSSOP 16 AD5313 10 ±0.50 2 7 SPI TSSOP 16 AD5323 12 ±1.00 2 8 SPI TSSOP 16

QUADS

AD5304 8 ±0.25 1 6 SPI MSOP 10 AD5314 10 ±0.50 1 7 SPI MSOP 10 AD5324 12 ±1.00 1 8 SPI MSOP 10 AD5305 8 ±0.25 1 6 2-Wire MSOP 10 AD5315 10 ±0.50 1 7 2-Wire MSOP 10 AD5325 12 ±1.00 1 8 2-Wire MSOP 10 AD5306 8 ±0.25 4 6 2-Wire TSSOP 16 AD5316 10 ±0.50 4 7 2-Wire TSSOP 16 AD5326 12 ±1.00 4 8 2-Wire TSSOP 16 AD5307 8 ±0.25 2 6 SPI TSSOP 16 AD5317 10 ±0.50 2 7 SPI TSSOP 16 AD5327 12 ±1.00 2 8 SPI TSSOP 16

OCTALS

AD5308 8 ±0.25 2 6 SPI TSSOP 16 AD5318 10 ±0.50 2 7 SPI TSSOP 16 AD5328 12 ±1.00 2 8 SPI TSSOP 16

Pins Settling Time (μs) Interface Package Pins

REF

= VDD) 4 SPI SOT-23, MSOP 6, 8

REF

= VDD) 6 SPI SOT-23, MSOP 6, 8

REF

= VDD) 8 SPI SOT-23, MSOP 6, 8

REF

= VDD) 6 2-Wire SOT-23, MSOP 6, 8

REF

= VDD) 7 2-Wire SOT-23, MSOP 6, 8

REF

= VDD) 8 2-Wire SOT-23, MSOP 6, 8

REF

Table 11. Overview of AD53xx Parallel Devices

Part No. Resolution DNL V SINGLES

AD5330 8 ±0.25 1 6

AD5331 10 ±0.50 1 7

AD5340 12 ±1.00 1 8

AD5341 12 ±1.00 1 8

DUALS

AD5332 8 ±0.25 2 6

AD5333 10 ±0.50 2 7

AD5342 12 ±1.00 2 8

AD5343 12 ±1.00 1 8

QUADS

AD5334 8 ±0.25 2 6

AD5335 10 ±0.50 2 7

AD5336 10 ±0.50 4 7

Pins Settling Time (μs) Additional Pin Functions Package Pins

REF

BUF GAIN HBEN

✓ ✓

✓

✓ ✓

✓ ✓ ✓ ✓

✓ ✓

✓

✓ ✓

✓

CLR

TSSOP 20

✓

TSSOP 20

✓

TSSOP 24

✓

TSSOP 20

✓

TSSOP 24

✓

TSSOP 28

✓

TSSOP 20

TSSOP 24

✓

TSSOP 24

TSSOP 28

✓

AD5344 12 ±1.00 4 8 TSSOP 28

Rev. F | Page 23 of 28

AD5308/AD5318/AD5328

OUTLINE DIMENSIONS

5.10

5.00

4.90

0.15

0.05

4.50

4.40

4.30

PIN 1

16

0.65

BSC

COPLANARITY

COMPLIANT TO JEDEC S T ANDARDS MO-153-AB

0.10

0.30

0.19

9

81

1.20 MAX

SEATING PLANE

6.40 BSC

0.20

0.09 8°

0°

0.75

0.60

0.45

Figure 44. 16-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-16)

Dimensions shown in millimeters

ORDERING GUIDE

Model1, 2 Temperature Range Package Description Package Option

AD5308ARU −40°C to +125°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16 AD5308ARU-REEL7 −40°C to +125°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16 AD5308ARUZ −40°C to +125°C 16-Lead Thin Shrink Small Outline Package (TSSOP) AD5308ARUZ-REEL7 −40°C to +125°C 16-Lead Thin Shrink Small Outline Package (TSSOP) AD5308BRU −40°C to +125°C 16-Lead Thin Shrink Small Outline Package (TSSOP) AD5308BRU-REEL −40°C to +125°C 16-Lead Thin Shrink Small Outline Package (TSSOP) AD5308BRU-REEL7 −40°C to +125°C 16-Lead Thin Shrink Small Outline Package (TSSOP) AD5308BRUZ −40°C to +125°C 16-Lead Thin Shrink Small Outline Package (TSSOP) AD5308BRUZ-REEL −40°C to +125°C 16-Lead Thin Shrink Small Outline Package (TSSOP) AD5308BRUZ-REEL7 −40°C to +125°C 16-Lead Thin Shrink Small Outline Package (TSSOP) AD5318ARU −40°C to +125°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16 AD5318ARU-REEL7 −40°C to +125°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16 AD5318ARUZ −40°C to +125°C 16-Lead Thin Shrink Small Outline Package (TSSOP) AD5318ARUZ-REEL7 −40°C to +125°C 16-Lead Thin Shrink Small Outline Package (TSSOP) AD5318BRU −40°C to +125°C 16-Lead Thin Shrink Small Outline Package (TSSOP) AD5318BRU-REEL −40°C to +125°C 16-Lead Thin Shrink Small Outline Package (TSSOP) AD5318BRU-REEL7 −40°C to +125°C 16-Lead Thin Shrink Small Outline Package (TSSOP) AD5318BRUZ −40°C to +125°C 16-Lead Thin Shrink Small Outline Package (TSSOP) AD5318BRUZ-REEL −40°C to +125°C 16-Lead Thin Shrink Small Outline Package (TSSOP) AD5318BRUZ-REEL7 −40°C to +125°C 16-Lead Thin Shrink Small Outline Package (TSSOP) AD5328ARU −40°C to +125°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16 AD5328ARU-REEL7 −40°C to +125°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16 AD5328ARUZ −40°C to +125°C 16-Lead Thin Shrink Small Outline Package (TSSOP) AD5328ARUZ-REEL7 −40°C to +125°C 16-Lead Thin Shrink Small Outline Package (TSSOP) AD5328BRU −40°C to +125°C 16-Lead Thin Shrink Small Outline Package (TSSOP) AD5328BRU-REEL −40°C to +125°C 16-Lead Thin Shrink Small Outline Package (TSSOP) AD5328BRU-REEL7 −40°C to +125°C 16-Lead Thin Shrink Small Outline Package (TSSOP) AD5328BRUZ −40°C to +125°C 16-Lead Thin Shrink Small Outline Package (TSSOP) AD5328BRUZ-REEL −40°C to +125°C 16-Lead Thin Shrink Small Outline Package (TSSOP) AD5328BRUZ-REEL7 −40°C to +125°C 16-Lead Thin Shrink Small Outline Package (TSSOP) AD5308WARUZ-REEL7 −40°C to +125°C 16-Lead Thin Shrink Small Outline Package (TSSOP) RU-16

1

Z = RoHS Compliant Part.

2

W = Qualified for Automotive Applications.

RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16 RU-16

Rev. F | Page 24 of 28

AD5308/AD5318/AD5328

AUTOMOTIVE PRODUCTS

The AD5308WARUZ-REEL7 model is available with controlled manufacturing to support the quality and reliability requirement s of automotive applications. Note that this automotive model may have specifications that differ from the commercial models; therefore, designers should review the Specifications section of this data sheet carefully. Only the automotive grade product shown is available for use in automotive applications. Contact your local Analog Devices, Inc., account representative for specific product ordering information and to obtain the specific Automotive Reliability report for this model.

Rev. F | Page 25 of 28

AD5308/AD5318/AD5328

NOTES

Rev. F | Page 26 of 28

AD5308/AD5318/AD5328

NOTES

Rev. F | Page 27 of 28

AD5308/AD5318/AD5328

NOTES

Rev. F | Page 28 of 28

Datasheet AD5308, AD5318, AD5328 Datasheet (ANALOG DEVICES)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

TABLE OF CONTENTS

REVISION HISTORY

FUNCTIONAL BLOCK DIAGRAM

SPECIFICATIONS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

TERMINOLOGY

THEORY OF OPERATION

DIGITAL-TO-ANALOG CONVERTER

DAC Reference Inputs

RESISTOR STRING

OUTPUT AMPLIFIER

POWER-ON RESET

POWER-DOWN MODE

SERIAL INTERFACE

Input Shift Register

DAC Write

Control Functions

Reference and Gain Mode

GAIN

Power-Down Mode

Reset Mode

LOW POWER SERIAL INTERFACE

DOUBLE-BUFFERED INTERFACE

MICROPROCESSOR INTERFACE

68HC11/68L11-to-AD5308/AD5318/AD5328 INTERFACE

80C51/80L51-to-AD5308/AD5318/AD5328 INTERFACE

MICROWIRE-to-AD5308/AD5318/AD5328 INTERFACE

APPLICATIONS INFORMATION

TYPICAL APPLICATION CIRCUIT

DRIVING VDD FROM THE REFERENCE VOLTAGE

BIPOLAR OPERATION USING THE AD5308/AD5318/AD5328

OPTO-ISOLATED INTERFACE FOR PROCESS CONTROL APPLICATIONS

DECODING MULTIPLE AD5308/AD5318/AD5328s

OUTLINE DIMENSIONS

ORDERING GUIDE