Datasheet AD5317R Datasheet (ANALOG DEVICES)

with 2 ppm/°C Reference, SPI Interface

AD5317R

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

Trademarks and registered trademarks are the property of their respective owners.

Fax: [phone] ©2012 Analog Devices, Inc. All rights reserved.

V

V

GNDV

10800-001

Data Sheet

FEATURES

Low drift 2.5 V reference: 2 ppm/°C typical
Tiny package: 3 mm × 3 mm, 16-lead LFCSP

Total unadjusted error (TUE): ±0.1% of FSR maximum
Offset error: ±1.5 mV maximum
Gain error: ±0.1% of FSR maximum
High drive capability: 20 mA, 0.5 V from supply rails
User selectable gain of 1 or 2 (GAIN pin)
Reset to zero scale or midscale (RSTSEL pin)

1.8 V logic compatibility
50 MHz SPI with readback or daisy chain
Low glitch: 0.5 nV-sec
Robust 4 kV HBM and 1.5 kV FICDM ESD rating
Low power: 3.3 mW at 3 V

2.7 V to 5.5 V power supply

−40°C to +105°C temperature range

APPLICATIONS

Digital gain and offset adjustment
Programmable attenuators
Industrial automation
Data acquisition systems

LOGIC

SCLK

SYNC

SDIN

SDO

Quad, 10-Bit nanoDAC

FUNCTIONAL BLOCK DIAGRAM

REF

STRING

DAC A

STRING

DAC B

STRING

DAC C

STRING

DAC D

GAIN
×1/×2

REFERENCE

AD5317R

INTERFACE LOGIC

LDAC RESET

DD

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

DAC

REGISTER

DAC

REGISTER

DAC

REGISTER

DAC

REGISTER

POWER-ON

RESET

RSTSEL GAIN

Figure 1.

2.5V

BUFFER

BUFFER

BUFFER

BUFFER

POWER-

DOWN
LOGIC

®

V

A

OUT

V

B

OUT

V

C

OUT

V

D

OUT

GENERAL DESCRIPTION

The AD5317R, a member of the nanoDAC® family, is a low
power, quad, 10-bit buffered voltage output DAC. The device
includes a 2.5 V, 2 ppm/°C internal reference (enabled by
default) and a gain select pin giving a full-scale output of 2.5 V
(gain = 1) or 5 V (gain = 2). The device operates from a single

2.7 V to 5.5 V supply, is guaranteed monotonic by design, and
exhibits less than 0.1% FSR gain error and 1.5 mV offset error
performance. The device is available in a 3 mm × 3 mm LFCSP
and a TSSOP package.

The AD5317R also incorporates a power-on reset circuit and a
RSTSEL pin that ensures that the DAC outputs power up to
zero scale or midscale and remain at that level until a valid write
takes place. Each part contains a per-channel power-down
feature that reduces the current consumption of the device to
4 µA at 3 V while in power-down mode.

The AD5317R employs a versatile SPI interface that operates at
clock rates up to 50 MHz and contains a V

1.8 V/3 V/5 V logic.

pin intended for

LOGIC

Table 1. Related Devices

Interface Reference 12-Bit 10-Bit

SPI Internal AD5684R
External AD5684 AD53171
I2C Internal AD5694R AD5316R
External AD5694 AD5316

1

The AD5317 and AD5317R are not pin-to-pin or software compatible.

PRODUCT HIGHLIGHTS

1. Precision DC Performance.

Total unadjusted error: ±0.1% of FSR maximum
Offset error: ±1.5 mV maximum
Gain error: ±0.1% of FSR maximum

2. Low Drift 2.5 V On-Chip Reference.

2 ppm/°C typical temperature coefficient
5 ppm/°C maximum temperature coefficient

3. Two Package Options.

3 mm × 3 mm, 16-lead LFCSP
16-lead TSSOP

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without n otice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]

www.analog.com

AD5317R Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications ....................................................................................... 1

Functional Block Diagram .............................................................. 1

General Description ......................................................................... 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Specifications ..................................................................................... 3

AC Characteristics ........................................................................ 5

Timing Characteristics ................................................................ 6

Daisy-Chain and Readback Timing Characteristics................ 7

Absolute Maximum Ratings ............................................................ 9

ESD Caution .................................................................................. 9

Pin Configurations and Function Descriptions ......................... 10

Typical Performance Characteristics ........................................... 11

Terminology .................................................................................... 17

Theory of Operation ...................................................................... 19

Digital-to-Analog Converter .................................................... 19

Transfer Function ....................................................................... 19

DAC Architecture ....................................................................... 19

Serial Interface ............................................................................ 20

Standalone Operation ................................................................ 21

Write and Update Commands .................................................. 21

Daisy-Chain Operation ............................................................. 21

Readback Operation .................................................................. 22

Power-Down Operation ............................................................ 22

Load DAC (Hardware
LDAC

Mask Register ................................................................. 23

Hardware Reset (

Reset Select Pin (RSTSEL) ........................................................ 24

Internal Reference Setup ........................................................... 25

Solder Heat Reflow ..................................................................... 25

Long-Term Temperature Drift ................................................. 25

Thermal Hysteresis .................................................................... 25

Applications Information .............................................................. 26

Microprocessor Interfacing ....................................................... 26

AD5317R to ADSP-BF531 Interface ....................................... 26

AD5317R to SPORT Interface .................................................. 26

Layout Guidelines....................................................................... 26

Galvanically Isolated Interface ................................................. 27

Outline Dimensions ....................................................................... 28

Ordering Guide .......................................................................... 28

LDAC

Pin) ........................................... 23

) .......................................................... 24

RESET

REVISION HISTORY

7/12—Revision 0: Initial Version

Rev. 0 | Page 2 of 28

Data Sheet AD5317R

Full-Scale Error

+0.01

±0.1

% of FSR

All 1s loaded to DAC register

REF

REF

10 nF

RL = 1 kΩ

7, 8

Output Voltage Noise Density2

240 nV/√Hz

At ambient; f = 10 kHz, CL = 10 nF

SPECIFICATIONS

VDD = 2.7 V to 5.5 V; V

Table 2.

Parameter Min Typ Max Unit Test Conditions/Comments

STATIC PERFORMANCE1

Resolution 10 Bits
Relative Accuracy ±0.12 ±0.5 LSB
Differential Nonlinearity ±0.5 LSB Guaranteed monotonic by design
Zero-Code Error 0.4 1.5 mV All 0s loaded to DAC register
Offset Error +0.1 ±1.5 mV

Gain Error ±0.02 ±0.1 % of FSR
Total Unadjusted Error ±0.01 ±0.1 % of FSR External reference; gain = 2; TSSOP
±0.2 % of FSR Internal reference; gain = 1; TSSOP
Offset Error Drift
Gain Temperature Coefficient2 ±1 ppm Of FSR/°C
DC Power Supply Rejection Ratio2 0.15 mV/V DAC code = mi dscale; VDD = 5 V ± 10%
DC Crosstalk2 ±2 µV Due to single channel, full-scale output change
±3 µV/mA Due to load current change
±2 µV Due to power-down (per channel)

OUTPUT CHARACTERISTICS2

Output Voltage Range 0 V
0 2 × V
Capacitive Load Stability 2 nF RL = ∞

= 2.5 V; 1.8 V ≤ V

REF

2

≤ 5.5 V; all specifications T

LOGIC

MIN

to T

±1 µV/°C

V Gain = 1

V Gain = 2, see Figure 29

, unless otherwise noted. RL = 2 kΩ; CL = 200 pF.

MAX

Resistive Load3 1 kΩ
Load Regulation 80 µV/mA 5 V ± 10%, DAC code = midscale; −30 mA ≤ I

+30 mA

80 µV/mA 3 V ± 10%, DAC code = midscale; −20 mA ≤ I

+20 mA
Short-Circuit Current4 40 mA
Load Impedance at Rails5 25 Ω See Figure 29
Power-Up Time 2.5 µs Coming out of power-down mode; VDD = 5 V

REFERENCE OUTPUT

Output Voltage6 2.4975 2.5025 V At ambient
Reference TC

2 5 ppm/°C See the Terminology section
Output Impedance2 0.04 Ω
Output Voltage Noise2 12 µV p-p 0.1 Hz to 10 Hz

Load Regulation, Sourcing2 20 µV/mA At ambient
Load Regulation, Sinking2 40 µV/mA At ambient
Output Current Load Capability2

±5

mA VDD ≥ 3 V
Line Regulation2 100 µV/V At ambient
Long-Term Stability/Drift2 12 ppm After 1000 hours at 125°C
Thermal Hysteresis2 125 ppm First cycle
25 ppm Additional cycles

OUT

OUT

≤

≤

Rev. 0 | Page 3 of 28

AD5317R Data Sheet

INL

LOGIC

INH

LOGIC

Pin Capacitance

2

pF

SINK

LOGIC

SOURCE

LOGIC

LOGI C

REF

Parameter Min Typ Max Unit Test Conditions/Comments

LOGIC INPUTS2

Input Current ±2 µA Per pin
Input Low Voltage, V
Input High Voltage, V

LOGIC OUTPUTS (SDO)2

Output Low Voltage, VOL 0.4 V I
Output High Voltage, VOH V
Floating State Output

Capacitance

POWER REQUIREMENTS

V
I
VDD 2.7 5.5 V Gain = 1
V
IDD VIH = VDD, VIL = G ND, VDD = 2.7 V to 5.5 V

Normal Mode9 0.59 0.7 mA Internal reference off

1.1 1.3 mA Internal reference on, at full scale
All Power-Down Modes10 1 4 µA −40°C to +85°C

6 µA −40°C to +105°C

1

DC specifications tested with the outputs unloaded, unless otherwise noted. Upper dead band = 10 mV and exists only when V

with gain = 2. Linearity calculated using a reduced code range of 4 to 1020.

V

DD

2

Guaranteed by design and characterization; not production tested.

3

Channel A and Channel B can have a combined output current of up to 30 mA. Similarly, Channel C and Channel D can have a combined output current of up to

30 mA up to a junction temperature of 110°C.

4

VDD = 5 V. The device includes current limiting that is intended to protect the device during temporary overload conditions. Junction temperature can be exceeded

during current limit. Operation above the specified maximum operation junction temperature may impair device reliability.

5

When drawing a load current at either rail, the output voltage headroom with respect to that rail is limited by the 25 Ω typical channel resistance of the output

devices. For example, when sinking 1 mA, the minimum output voltage = 25 Ω × 1 mA = 25 mV (see Figure 29).

6

Initial accuracy presolder reflow is ±750 µV; output voltage includes the effects of preconditioning drift. See the Terminology section.

7

Reference is trimmed and tested at two temperatures and is characterized from −40°C to +105°C.

8

Reference temperature coefficient calculated as per the box method. See the Terminology section for more information.

9

Interface inactive. All DACs active. DAC outputs unloaded.

10

All DACs powered down.

0.3 × V

0.7 × V

V

− 0.4 V I

4 pF

1.8 5.5 V
3 µA

+ 1.5 5.5 V Gain = 2

V

= 200 μA

= 200 μA

= VDD with gain = 1 or when V

REF

/2 =

REF

Rev. 0 | Page 4 of 28

Data Sheet AD5317R

OUT

AC CHARACTERISTICS

VDD = 2.7 V to 5.5 V; V
otherwise noted.

1

Table 3.

Parameter2 Min Typ Max Unit Test Conditions/Comments3

Output Voltage Settling Time 5 7 µs ¼ to ¾ scale settling to ±1 LSB
Slew Rate 0.8 V/µs
Digital-to-Analog Glitch Impulse 0.5 nV-sec 1 LSB change around major carry
Digital Feedthrough 0.13 nV-sec
Digital Crosstalk 0.1 nV-sec
Analog Crosstalk 0.2 nV-sec
DAC-to-DAC Crosstalk 0.3 nV-sec
Total Harmonic Distortion4 −80 dB At ambient, BW = 20 kHz, VDD = 5 V, f
Output Noise Spectral Density 300 nV/√Hz DAC code = midscale, 10 kHz, gain = 2
Output Noise 6 µV p-p 0.1 Hz to 10 Hz

1

Guaranteed by design and characterization, not production tested.

2

See the Terminology section.

3

Temperature range is −40°C to +105°C, typical @ 25°C.

4

Digitally generated sine wave @ 1 kHz.

= 2.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; 1.8 V ≤ V

REF

≤ 5.5 V; all specifications T

LOGIC

to T

MIN

= 1 kHz

MAX

, unless

Rev. 0 | Page 5 of 28

AD5317R Data Sheet

LOGIC

LOGIC

Data Setup Time

t5 8 5

ns

t

4

t

3

SCLK

SYNC

SDIN

t

1

t

2

t

5

t

6

t

7

t

8

DB23

t

9

t

10

t

11

LDAC

1

LDAC

2

t

12

1

ASYNCHRONOUS LDAC UPDATE MODE .

2

SYNCHRONOUS LDAC UPDATE MODE .

RESET

t

13

t

14

V

OUT

DB0

10800-002

TIMING CHARACTERISTICS

All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 2.
V

= 2.7 V to 5.5 V, 1.8 V ≤ V

DD

Table 4.

1.8 V ≤ V
Parameter1 Symbol Min Max Min Max Unit

SCLK Cycle Time t1 33 20 ns
SCLK High Time t2 16 10 ns
SCLK Low Time t3 16 10 ns

to SCLK Falling Edge Setup Time t4 15 10 ns

SYNC

Data Hold Time t6 8 5 ns
SCLK Falling Edge to

Minimum

Falling Edge to SCLK Fall Ignore t9 16 10 ns

SYNC

Pulse Width Low t10 25 15 ns

LDAC

High Time t8 20 20 ns

SYNC

SCLK Falling Edge to
SCLK Falling Edge to

Minimum Pulse Width Low t13 30 30 ns

RESET

Pulse Activation Time t14 30 30 ns

RESET

Rising Edge t7 15 10 ns

SYNC

Rising Edge t11 30 20 ns

LDAC

Falling Edge t12 20 20 ns

LDAC

Power-Up Time2 4.5 4.5 µs

1

Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V, 1.8 V ≤ V

2

Time to exit power-down to normal mode of AD5317R operation, 32nd clock edge to 90% of DAC midscale value, with output unloaded.

LOGIC

≤ 5.5 V; V

= 2.5 V. All specifications T

REF

≤ VDD. Guaranteed by design and characterization; not production tested.

LOGIC

MIN

to T

, unless otherwise noted.

MAX

< 2.7 V 2.7 V ≤ V

≤ 5.5 V

Figure 2. Serial Write Operation

Rev. 0 | Page 6 of 28

Data Sheet AD5317R

LOGIC

LOGIC

200µA I

OL

200µA I

OH

VOH (MIN)

TO OUTPUT

PIN

C

L

20pF

10800-003

t

4

t

5

t

6

t

8

SDO

SDIN

SYNC

SCLK

4824

DB23 DB0 DB23 DB0

DB23

INPUT WORD FOR DAC NUNDEFINED

INPUT WORD FOR DAC N + 1INPUT WORD FOR DAC N

DB0

t

11

t

12

t

10

10800-004

DAISY-CHAIN AND READBACK TIMING CHARACTERISTICS

All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 4
and Figure 5. V

Table 5.

1.8 V ≤ V
Parameter1 Symbol Min Max Min Max Unit

SCLK Cycle Time t1 66 40 ns
SCLK High Time t2 33 20 ns
SCLK Low Time t3 33 20 ns

to SCLK Falling Edge t4 33 20 ns

SYNC
Data Setup Time t5 5 5 ns

Data Hold Time t6 5 5 ns
SCLK Falling Edge to
Minimum
Minimum

SDO Data Valid from SCLK Rising Edge t10 36 25 ns
SCLK Falling Edge to

Rising Edge to SCLK Rising Edge t12 15 10 ns

SYNC

1

Maximum SCLK frequency is 25 MHz or 15 MHz at VDD = 2.7 V to 5.5 V, 1.8 V ≤ V

Circuit and Timing Diagrams

= 2.7 V to 5.5 V, 1.8 V ≤ V

DD

Rising Edge t7 15 10 ns

SYNC

High Time t8 60 30 ns

SYNC

High Time t9 60 30 ns

SYNC

Rising Edge t11 15 10 ns

SYNC

LOG IC

≤ 5.5 V; V

= 2.5 V. All specifications T

REF

< 2.7 V 2.7 V ≤ V

≤ VDD. Guaranteed by design and characterization; not production tested.

LOGIC

MIN

to T

, unless otherwise noted.

MAX

≤ 5.5 V

Figure 3. Load Circuit for Digital Output (SDO) Timing Specifications

Figure 4. Daisy-Chain Timing Diagram

Rev. 0 | Page 7 of 28

AD5317R Data Sheet

SYNC

t

8

t

6

SCLK

24

1

24

1

t

9

t

4

t

2

t

7

t

3

t

1

DB23 DB0 DB23 DB0

SDIN

NOP CONDITIONINPUT WORD SPECIFIES

REGIST E R TO BE READ

t

5

DB23 DB0 DB23 DB0

SDO

SELECTED REGISTER DATA

CLOCKED OUT

UNDEFINED

t

10

10800-005

Figure 5. Readback Timing Diagram

Rev. 0 | Page 8 of 28

Data Sheet AD5317R

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 6.

Parameter Rating

VDD to GND −0.3 V to +7 V
V

to GND −0.3 V to +7 V

LOGI C

V

to GND −0.3 V to VDD + 0.3 V

OUT

V

to GND −0.3 V to VDD + 0.3 V

REF

Digital Input Voltage to GND −0.3 V to V
Operating Temperature Range −40°C to +105°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 125°C
16-Lead TSSOP, θJA Thermal

Impedance, 0 Airflow (4-Layer Board)

16-Lead LFCSP, θJA Thermal

Impedance, 0 Airflow (4-Layer Board)

Reflow Soldering Peak

Temperature, Pb Free (J-STD-020)

ESD

HBM1 4 kV
FICDM 1.5 kV

1

Human body model (HBM) classification.

112.6°C/W

70°C/W

260°C

LOGI C

+ 0.3 V

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

Rev. 0 | Page 9 of 28

AD5317R Data Sheet

OUT

3 5 VDD

Power Supply Input. This part can be operated from 2.7 V to 5.5 V, and the supply should be

OUT

OUT

for readback. The serial data is transferred on the rising edge of SCLK and is valid on the falling

LOGIC

Power-On Reset Pin. Tying this pin to GND powers up all four DACs to zero scale. Tying this pin to
VDD powers up all four DACs to midscale.

OUT

17

N/A

EPAD

Exposed Pad. The exposed pad must be tied to GND.

12
11
10

1

3
4

SDIN
SYNC
SCLK

9

V

LOGIC

V

OUT

A

V

DD

2

GND

V

OUT

C

6

SDO

5

V

OUT

D

7

LDAC

8

GAIN

16

V

OUT

B

15

V

REF

14

RSTSEL

13

RESET

AD5317R

NOTES

1. THE EXPOSED PAD MUST BE TIED TO GND.

TOP VIEW

(Not to S cale)

10800-006

1

2

3

4

5

6

7

8

V

OUT

B

V

OUT

A

GND

V

OUT

D

V

OUT

C

V

DD

V

REF

SDO

16

15

14

13

12

11

10

9

RESET
SDIN
SYNC

GAIN
LDAC

V

LOGIC

SCLK

RSTSEL

TOP VIEW

(Not to S cale)

AD5317R

10800-007

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

Figure 6. 16-Lead LFCSP Pin Configuration

Table 7. Pin Function Descriptions

Pin No.

LFCSP TSSOP

1 3 V

Mnemonic Description

A Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.

2 4 GND Ground Reference Point for All Circuitry on the Part.

decoupled with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND.
4 6 V
5 7 V

C Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.
D Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.

6 8 SDO Serial Data Output. Can be used to daisy-chain a number of AD5317R devices together or can be

used

edge of the clock.
7 9

LDAC

can be operated in two modes, asynchronously and synchronously. Pulsing this pin low allows

LDAC

any or all DAC registers to be updated if the input registers have new data. This allows all DAC outputs

to be simultaneously updated. This pin can also be tied permanently low.
8 10 GAIN Span Set Pin. When this pin is tied to GND, all four DAC outputs have a span of 0 V to V

9 11 V

pin is tied to V

Digital Power Supply. Voltage ranges from 1.8 V to 5.5 V.

, all four DAC outputs have a span of 0 V to 2 × V

DD

10 12 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock

input. Data can be transferred at rates of up to 50 MHz.
11 13

Active Low Control Input. This is the frame synchronization signal for the input data. When

SYNC

goes low, data is transferred in on the falling edges of the next 24 clocks.
12 14 SDIN Serial Data Input. This device has a 24-bit input shift register. Data is clocked into the register on the

falling edge of the serial clock input.
13 15

Asynchronous Reset Input. The

RESET

pulses are ignored. When

input is falling edge sensitive. When

RESET

is activated, the input register and the DAC register are updated with

RESET

zero scale or midscale, depending on the state of the RSTSEL pin.
14 16 RSTSEL

15 1 V

16 2 V

Reference Voltage. The AD5317R has a common reference pin. When using the internal reference,

REF

this is the reference output pin. When using an external reference, this is the reference input pin.

The default for this pin is as a reference output.

B Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.

Rev. 0 | Page 10 of 28

Figure 7. 16-Lead TSSOP Pin Configuration

.

REF

is low, all

RESET

. When this

REF

SYNC

LDAC

Data Sheet AD5317R

–40 –20 0 20 40 60 80 100 120

V

REF

(V)

TEMPERATURE (°C)

DEVICE 1
DEVICE 2
DEVICE 3
DEVICE 4
DEVICE 5

2.4980

2.4985

2.4990

2.4995

2.5000

2.5005

2.5010

2.5015

2.5020
VDD = 5V

10800-212

90

0

10

20

30

40

50

60

70

80

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

NUMBER OF UNI TS

TEMPERAT URE DRIFT (p pm/°C)

VDD = 5V

10800-250

60

0

10

20

30

40

50

2.498 2.499 2.500 2.501 2.502

HITS

V

REF

(V)

0 HOUR
168 HOURS
500 HOURS
1000 HOURS

VDD = 5.5V

10800-251

1600

0

200

400

600

800

1000

1200

1400

10 100 1k 10k 100k 1M

NSD (nV/ Hz)

FREQUENCY ( Hz )

VDD = 5V
T

A

= 25°C

10800-111

CH1 2µV M1.0s

1

V

DD

= 5V

T

A

= 25°C

10800-112

2.5000

2.4999

2.4998

2.4997

2.4996

2.4995

2.4994

2.4993
–0.005 –0.003 –0.001 0.001 0.003 0.005

V

REF

(V)

I

LOAD

(A)

VDD = 5V
T

A

= 25°C

10800-113

TYPICAL PERFORMANCE CHARACTERISTICS

Figure 8. Internal Reference Voltage vs. Temperature (Grade B)

Figure 9. Reference Output Temperature Drift Histogram

Figure 11. Internal Reference Noise Spectral Density vs. Frequency

Figure 12. Internal Reference Noise, 0.1 Hz to 10 Hz

Figure 10. Reference Long-Term Stability/Drift

Figure 13. Internal Reference Voltage vs. Load Current

Rev. 0 | Page 11 of 28

AD5317R Data Sheet

2.5002

2.5000

2.4998

2.4996

2.4994

2.4992

2.4990

2.5 3.0 3.5 4.0 4.5 5.0 5.5

V

REF

(V)

V

DD

(V)

D1

D3

D2

T

A

= 25°C

10800-117

0.5

–0.5

–0.3

–0.1

0.1

0.3

0 156 312 468 625 781 938

INL (LSB)

CODE

10800-118

DNL (LSB)

CODE

10800-119

0.5

–0.5

–0.3

–0.1

0.1

0.3

CODE

0 156 312 468 625 781 938

10

–10

–8

–6

–4

–2

0

2

4

6

8

–40 1106010

ERROR (LSB)

TEMPERATURE (°C)

INL

DNL

V

DD

= 5V

T

A

= 25°C

INTERNAL RE FERENCE = 2.5V

10800-124

10

–10

–8

–6

–4

–2

0

2

4

6

8

0 5.04.54.03.53.02.52.01.51.00.5

ERROR (LSB)

V

REF

(V)

INL

DNL

VDD = 5V
T

A

= 25°C

INTERNAL RE FERENCE = 2.5V

10800-125

10

–10

–8

–6

–4

–2

0

2

4

6

8

2.7 5.24.74.23.73.2

ERROR (LSB)

SUPPLY VOLTAGE (V)

INL

DNL

V

DD

= 5V

T

A

= 25°C

INTERNAL RE FERENCE = 2.5V

10800-126

Figure 14. Internal Reference Voltage vs. Supply Voltage

Figure 15. INL

Figure 17. INL Error and DNL Error vs. Temperature

Figure 18. INL Error and DNL Error vs. V

REF

Figure 16. DNL

Figure 19. INL Error and DNL Error vs. Supply Voltage

Rev. 0 | Page 12 of 28

Data Sheet AD5317R

0.10

–0.10

–0.08

–0.06

–0.04

–0.02

0

0.02

0.04

0.06

0.08

–40 –20 0 20 40 60 80 100 120

ERROR (% of FSR)

TEMPERATURE (°C)

GAIN ERROR

FULL-S CALE ERROR

VDD = 5V
T

A

= 25°C

INTERNAL RE FERENCE = 2.5V

10800-127

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

–40 –20 0 20 40 60 80 100 120

ERROR (mV)

TEMPERATURE (°C)

OFFSET ERROR

ZERO-CO DE E RROR

V

DD

= 5V

T

A

= 25°C

INTERNAL RE FERENCE = 2.5V

10800-128

0.10

–0.10

–0.08

–0.06

–0.04

–0.02

0

0.02

0.04

0.06

0.08

2.7 5.24.74.23.73.2

ERROR (% of FSR)

SUPPLY VOLTAGE (V)

GAIN ERROR

FULL-S CALE ERROR

V

DD

= 5V

T

A

= 25°C

INTERNAL RE FERENCE = 2.5V

10800-129

1.5

–1.5

–1.0

–0.5

0

0.5

1.0

2.7 5.24.74.23.73.2

ERROR (mV)

SUPPLY VOLTAGE (V)

ZERO-CO DE E RROR

OFFSET ERROR

VDD = 5V
T

A

= 25°C

INTERNAL RE FERENCE = 2.5V

10800-130

0.10

0.09

0.08

0.07

0.06

0.05

0.04

0.03

0.02

0.01

0

–40 –20 0 20 40 60 80 100 120

TOTAL UNADJUS TED ERROR (% o f FSR)

TEMPERATURE (°C)

VDD = 5V
T

A

= 25°C

INTERNAL RE FERENCE = 2.5V

10800-131

0.10

0.08

0.06

0.04

0.02

0

–0.02

–0.04

–0.06

–0.08

–0.10

2.7 5.24.74.23.73.2

TOTAL UNADJUS TED ERROR (% o f FSR)

SUPPLY VOLTAGE (V)

VDD = 5V
T

A

= 25°C

INTERNAL RE FERENCE = 2.5V

10800-132

Figure 20. Gain Error and Full-Scale Error vs. Temperature

Figure 21. Zero-Code Error and Offset Error vs. Temperature

Figure 23. Zero-Code Error and Offset Error vs. Supply Voltage

Figure 24. TUE vs. Temperature

Figure 22. Gain Error and Full-Scale Error vs. Supply Voltage

Figure 25. TUE vs. Supply Voltage, Gain = 1

Rev. 0 | Page 13 of 28

AD5317R Data Sheet

0

–0.01

–0.02

–0.03

–0.04

–0.05

–0.06

–0.07

–0.08

–0.09

–0.10

0 156 312 468 624 780 936 1023

TOTAL UNADJUS TED ERROR (% of FSR)

CODE

VDD = 5V
T

A

= 25°C

INTERNAL RE FERENCE = 2.5V

10800-133

25

20

15

10

5

0

540 560 580 600 620 640

HITS

IDD (mA)

V

DD

= 5V

T

A

= 25°C
EXTERNAL
REFERENCE = 2. 5V

10800-135

30

25

20

15

10

5

0

1000 1020 1040 1060 1080 1100 1120 1140

HITS

I

DD

FULL SCALE (mA)

V

DD

= 5V

T

A

= 25°C
INTERNAL
REFERENCE = 2. 5V

10800-136

1.0

–1.0

–0.8

–0.6

–0.4

–0.2

0

0.2

0.4

0.6

0.8

0 5 10 15 20 25 30

ΔV

OUT

(V)

LOAD CURRENT ( mA)

SOURCING 2.7V

SOURCING 5V

SINKING 2.7V

SINKING 5V

10800-200

7

–2

–1

0

1

2

3

4

5

6

–0.06 –0.04 –0.02 0 0.02 0.04 0.06

V

OUT

(V)

LOAD CURRENT ( A)

0xFFFF

0x4000

0x8000

0xC000

0x0000

VDD = 5V
T

A

= 25°C
GAIN = 2
INTERNAL
REFERENCE = 2.5V

10800-138

5

–2

–1

0

1

2

3

4

–0.06 –0.04 –0.02 0 0.02 0.04 0.06

V

OUT

(V)

LOAD CURRENT ( A)

0xFFFF

0x4000

0x8000

0xC000

0x0000

VDD = 3V
T

A

= 25°C
EXTERNAL RE FERENCE = 2.5V
GAIN = 1

10800-139

Figure 26. TUE vs. Code

Figure 27. IDD Histogram with External Reference, 5 V

Figure 29. Headroom/Footroom vs. Load Current

Figure 30. Source and Sink Capability at 5 V

Figure 28. IDD Histogram with Internal Reference, V

= 2.5 V, Gain = 2

REF

Figure 31. Source and Sink Capability at 3 V

Rev. 0 | Page 14 of 28

Data Sheet AD5317R

0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

–40 1106010

CURRENT (mA)

TEMPERATURE (°C)

FULL-SCALE

ZERO CODE

EXTERNAL RE FERENCE, F ULL-SCALE

10800-140

0

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

10 32016040 8020

V

OUT

(V)

TIME (µs)

DAC A
DAC B
DAC C
DAC D

V

DD

= 5V

T

A

= 25°C
INTERNAL RE FERENCE = 2.5V
1/4 TO 3/ 4 S CALE

10800-141

–0.01

0

0.06

0.01

0.02

0.03

0.04

0.05

–1

0

6

1

2

3

4

5

–10 15100 5–5

V

OUT

(V)

V

DD

(V)

TIME (µs)

CH D
V

DD

CH A
CH B
CH C

TA = 25°C
INTERNAL RE FERENCE = 2.5V

10800-142

0

1

3

2

–5 100 5

V

OUT

(V)

TIME (µs)

CH D
SYNC

CH A
CH B
CH C

VDD = 5V
T

A

= 25°C

INTERNAL RE FERENCE = 2.5V

GAIN = 1

GAIN = 2

10800-143

2.4988

2.5008

2.5003

2.4998

2.4993

0 128 104 62

V

OUT

(V)

TIME (µs)

CHANNEL B
T

A

= 25°C

V

DD

= 5.25V
INTERNAL RE FERENCE = 2.5V
CODE = 7FF F TO 8000
ENERGY = 0. 227206nV-sec

10800-144

–0.002

–0.001

0

0.001

0.002

0.003

0 252010 155

V

OUT

AC-COUPLED ( V )

TIME (µs)

CH B
CH C
CH D

10800-145

Figure 32. Supply Current vs. Temperature

Figure 33. Settling Time, 5 V

Figure 35. Exiting Power-Down to Midscale

Figure 36. Digital-to-Analog Glitch Impulse

Figure 34. Power-On Reset to 0 V

Rev. 0 | Page 15 of 28

Figure 37. Analog Crosstalk, Channel A

AD5317R Data Sheet

CH1 10µV M1.0s A CH1 802mV

1

T

VDD = 5V
T

A

= 25°C

EXTERNAL RE FERENCE = 2.5V

10800-146

CH1 10µV M1.0s A CH1 802mV

1

T

VDD = 5V
T

A

= 25°C

INTERNAL RE FERENCE = 2.5V

10800-147

0

200

400

600

800

1000

1200

1400

1600

10 1M100k1k 10k100

NSD (nV/ Hz)

FREQUENCY ( Hz )

FULL-SCALE
MIDSCALE
ZERO-SCALE

VDD = 5V
T

A

= 25°C

INTERNAL RE FERENCE = 2.5V

10800-148

–180

–160

–140

–120

–100

–80

–60

–40

–20

0

20

0 20000160008000 1200040002000 1800010000 140006000

THD (dBV)

FREQUENCY ( Hz )

VDD = 5V
T

A

= 25°C

INTERNAL RE FERENCE = 2.5V

10800-149

4.0

V

(V)

Figure 38. 0.1 Hz to 10 Hz Output Noise Plot, External Reference

Figure 39. 0.1 Hz to 10 Hz Output Noise Plot, 2.5 V Internal Reference

OUT

Figure 41. Total Harmonic Distortion @ 1 kHz

3.9

3.8

3.7

3.6

3.5

3.4

3.3

3.2

3.1

3.0

1.590 1.6301.6201.600 1.610 1.6251.605 1.6151.595

0nF

0.1nF
10nF

0.22nF

4.7nF

VDD = 5V

= 25°C

T

A

INTERNAL RE FERENCE = 2.5V

TIME (ms)

Figure 42. Settling Time vs. Capacitive Load

10800-150

Figure 40. Noise Spectral Density

Rev. 0 | Page 16 of 28

Data Sheet AD5317R

TERMINOLOGY

Relative Accuracy or Integral Nonlinearity (INL)

For the DAC, relative accuracy or integral nonlinearity is a
measurement of the maximum deviation, in LSBs, from a
straight line passing through the endpoints of the DAC transfer
function. A typical INL vs. code plot is shown in Figure 15.

Differential Nonlinearity (DNL)

Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ±1 LSB maximum
ensures monotonicity. This DAC is guaranteed monotonic by
design. A typical DNL vs. code plot can be seen in Figure 16.

Zero-Code Error

Zero-code error is a measurement of the output error when
zero code (0x0000) is loaded to the DAC register. Ideally, the
output should be 0 V. The zero-code error is always positive in
the AD5317R because the output of the DAC cannot go below
0 V due to a combination of the offset errors in the DAC and
the output amplifier. Zero-code error is expressed in mV. A plot
of zero-code error vs. temperature can be seen in Figure 21.

Full-Scale Error

Full-scale error is a measurement of the output error when full­scale code (0xFFFF) is loaded to the DAC register. Ideally, the
output should be V

− 1 LSB. Full-scale error is expressed in

DD

percent of full-scale range (% of FSR). A plot of full-scale error
vs. temperature can be seen in Figure 20.

Gain Error

Gain error is a measurement of the span error of the DAC. It is
the deviation in slope of the DAC transfer characteristic from
the ideal expressed as % of FSR.

Offset Error Drift

Offset error drift is a measurement of the change in offset error
with a change in temperature. It is expressed in µV/°C.

Gain Temperature Coefficient

Gain temperature coefficient is a measurement of the change in
gain error with changes in temperature. It is expressed in ppm
of FSR/°C.

Offset Error

Offset error is a measurement of the difference between V
(actual) and V

(ideal) expressed in mV in the linear region of

OUT

OUT

the transfer function. Offset error is measured on the AD5317R
with Code 4 loaded to the DAC register. It can be negative or
positive.

DC Power Supply Rejection Ratio (PSRR)

DC PSRR indicates how the output of the DAC is affected by
changes in the supply voltage. PSRR is the ratio of the change
in V

to a change in VDD for full-scale output of the DAC. It

OUT

is measured in mV/V. V

is held at 2.5 V, a nd VDD is varied

REF

by ±10%.

Output Voltage Settling Time

This is the amount of time it takes for the output of a DAC to
settle to a specified level for a ¼ to ¾ full-scale input change
and is measured from the rising edge of

SYNC

.

Digital-to-Analog Glitch Impulse

Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV-sec
and is measured when the digital input code is changed by
1 LSB at the major carry transition (0x7FFF to 0x8000) (see
Figure 36).

Digital Feedthrough

Digital feedthrough is a measurement of the impulse injected into
the analog output of the DAC from the digital inputs of the
DAC, but is measured when the DAC output is not updated. It
is specified in nV-sec and measured with a full-scale code
change on the data bus, that is, from all 0s to all 1s and vice
versa.

Noise Spectral Density

This is a measurement of the internally generated random
noise. Random noise is characterized as a spectral density
(nV/√Hz). It is measured by loading the DAC to midscale
and measuring noise at the output. It is measured in nV/√Hz.
A plot of noise spectral density is shown in Figure 40.

DC Crosstalk

DC crosstalk is the dc change in the output level of one DAC
in response to a change in the output of another DAC. It is
measured with a full-scale output change on one DAC (or soft
power-down and power-up) while monitoring another DAC
kept at midscale. It is expressed in μV.

DC crosstalk due to load current change is a measurement of
the impact that a change in load current on one DAC has on
another DAC kept at midscale. It is expressed in μV/mA.

Digital Crosstalk

Digital crosstalk is the glitch impulse transferred to the output
of one DAC at midscale in response to a full-scale code change
(all 0s to all 1s and vice versa) in the input register of another
DAC. It is measured in standalone mode and is expressed in
nV-sec.

Rev. 0 | Page 17 of 28

AD5317R Data Sheet

6

10×















×

−

=

TempRangeV

VV

TC

REFnom

REFminREFmax

Analog Crosstalk

Analog crosstalk is the glitch impulse transferred to the output
of one DAC due to a change in the output of another DAC. It is
measured by loading one of the input registers with a full-scale
code change (all 0s to all 1s and vice versa). Then execute a
software LDAC and monitor the output of the DAC whose
digital code was not changed. The area of the glitch is expressed
in nV-sec.

DAC-to-DAC Crosstalk

DAC-to-DAC crosstalk is the glitch impulse transferred to
the output of one DAC in response to a digital code change
and subsequent analog output change of another DAC. It is
measured by loading one channel with a full-scale code change
(all 0s to all 1s and vice versa) using the write to and update
commands while monitoring the output of another channel that
is at midscale. The energy of the glitch is expressed in nV-sec.

Total Harmonic Distortion (THD)

THD is the difference between an ideal sine wave and its
attenuated version using the DAC. The sine wave is used as the
reference for the DAC, and the THD is a measurement of the
harmonics present on the DAC output. It is measured in dB.

Voltage Reference TC

Voltage reference TC is a measurement of the change in the
reference output voltage with a change in temperature. The
reference TC is calculated using the box method, which defines
the TC as the maximum change in the reference output over a
given temperature range expressed in ppm/°C, as follows:

where:

V

is the maximum reference output measured over the

REFmax

total temperature range.

V

is the minimum reference output measured over the total

REFmin

temperature range.

V

is the nominal reference output voltage, 2.5 V.

REFno m

TempRange is the specified temperature range of −40°C to

+105°C.

Rev. 0 | Page 18 of 28

Data Sheet AD5317R













×=

N

REF

OUT

D

GainVV

2

V

R

R

R

R

R

TO OUTPUT
AMPLIFIER

V

REF

10800-053

THEORY OF OPERATION

DIGITAL-TO-ANALOG CONVERTER

The AD5317R is a quad, 10-bit, serial input, voltage output
DAC with an internal reference. The part operates from supply
voltages of 2.7 V to 5.5 V. Data is written to the AD5317R in a
24-bit word format via a 3-wire serial interface. The AD5317R
incorporates a power-on reset circuit to ensure that the DAC
output powers up to a known output state. The device also has
a software power-down mode that reduces the typical current
consumption to typically 4 µA.

TRANSFER FUNCTION

The internal reference is on by default. Because the input
coding to the DAC is straight binary, the ideal output voltage
when using an external reference is given by

where:
D is the decimal equivalent of the binary code that is loaded to
the DAC register as follows: 0 to 1023 for the 10-bit device.

N is the DAC resolution (10-bits).
Gain is the gain of the output amplifier and is set to 1 by default.

The gain can be set to ×1 or ×2 using the gain select pin. When
this pin is tied to GND, all four DAC outputs have a span from
0 V to V
have a span of 0 V to 2 × V

. When this pin is tied to VDD, all four DAC outputs

REF

.

REF

DAC ARCHITECTURE

The DAC architecture consists of a string DAC followed by an
output amplifier. Figure 43 shows a block diagram of the DAC
architecture.

REF

2.5V
REF

INPUT

REGISTER

Figure 43. Single DAC Channel Architecture Block Diagram

DAC

REGISTER

REF (+)

RESISTOR

STRING

REF (–)

GND

GAIN

(GAIN = 1 O R 2)

V

X

OUT

10800-052

The resistor string structure is shown in Figure 44. It is a string
of resistors, each of Value R. The code loaded to the DAC register
determines the node on the string where the voltage is to be
tapped off and fed into the output amplifier. The voltage is
tapped off by closing one of the switches connecting the
string to the amplifier. Because the DAC is a string of resistors,
it is guaranteed monotonic.

Figure 44. Resistor String Structure

Output Amplifiers

The output buffer amplifier can generate rail-to-rail voltages on
its output, which gives an output range of 0 V to V
range depends on the value of V

, the GAIN pin, offset error,

REF

. The actual

DD

and gain error. The GAIN pin selects the gain of the output.

• If this pin is tied to GND, all four outputs have a gain of 1,

and the output range is 0 V to V

• If this pin is tied to V

, all four outputs have a gain of 2,

DD

and the output range is 0 V to 2 × V

REF

.

.

REF

The output amplifiers are capable of driving a load of 1 kΩ in
parallel with 2 nF to GND. The slew rate is 0.8 V/µs with a ¼
to ¾ scale settling time of 5 µs.

Rev. 0 | Page 19 of 28

AD5317R Data Sheet

0 0 0 0 No operation

0 0 0

1

DAC D

DAC C

DAC B

DAC A

1 0 0 0 DAC D

ADDRESS BITSCOMMAND BIT S

DACDDACCDACBDAC

A

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X

C3 C2 C1 C0

DB23 (MSB) DB0 (LSB)

DATA BITS

10800-054

SERIAL INTERFACE

The AD5317R has a 3-wire serial interface (
SDIN) that is compatible with SPI, QSPI™, and MICROWIRE¬
interface standards as well as most DSPs. See Figure 2 for a
timing diagram of a typical write sequence. The AD5317R
contain an SDO pin to allow the user to daisy-chain multiple
devices together (see the Daisy-Chain Operation section) or for
readback.

Input Shift Register

The input shift register of the AD5317R is 24 bits wide. Data is
loaded MSB first (DB23) and the first four bits are the command
bits, C3 to C0 (see Table 8), followed by the 4-bit DAC address
bits, DAC A, DAC B, DAC C, DAC D (see Table 9), and finally
the data-word.

The data-word comprises the 10-bit input code, followed by six
don’t care bits (see Figure 45). These data bits are transferred to
the input register on the 24 falling edges of SCLK and are
updated on the rising edge of

SYNC

Commands can be executed on individual DAC channels,
combined DAC channels, or on all DAC channels, depending on
the address bits selected (see Table 9).

SYNC

, SCLK, and

.

Table 8. Command Bit Definitions

Command

C3 C2 C1 C0 Description

Write to Input Register n (dependent on

0 0 1 0

0 0 1 1 Write to and update DAC Channel n
0 1 0 0 Power down/power up DAC
0 1 0 1
0 1 1 0 Software reset (power-on reset)
0 1 1 1 Internal reference setup register
1 0 0 0 Set up DCEN register (daisy-chain enable)
1 0 0 1 Set up readback register (readback enable)
1 0 1 0 Reserved
… … … … Reserved
1 1 1 1 Reserved

Update DAC Register n with contents of Input
Register n

LDAC

Hardware

mask register

LDAC

Table 9. Address Bits and Selected DACs

Address Bits

Selected DAC Channel

0 0 0 1 DAC A
0 0 1 0 DAC B
0 1 0 0 DAC C

0 0 1 1 DAC A and DAC B
1 1 1 1 All DACs

1

Any combination of DAC channels can be selected using the address bits.

)

1

Figure 45. AD5317R Input Shift Register Contents

Rev. 0 | Page 20 of 28

68HC11*

MISO

SDIN
SCLK

MOSI

SCK

PC7
PC6

SDO

SCLK

SDO

SCLK

SDO

SDIN

SDIN

SYNC

SYNC

SYNC
LDAC

LDAC

LDAC

AD5317R

AD5317R

AD5317R

*ADDITIONAL PINS OMITTED FOR CLARITY.

10800-057

Data Sheet AD5317R

STANDALONE OPERATION

The write sequence begins by bringing the
from the SDIN line is clocked into the 24-bit input shift register
on the falling edge of SCLK. After the last of the 24 data bits is
clocked in,

SYNC

should be brought high. The programmed
function is then executed, that is, an
in DAC register contents and/or a change in the mode of

SYNC

operation. If
data may be loaded to the DAC.

is taken high before the 24th clock, invalid

SYNC
for a minimum of 20 ns (single channel, see t
before the next write sequence so that a falling edge of
can initiate the next write sequence.
the rails between write sequences for even lower power opera-

SYNC

tion of the part. The

line is kept low for 24 falling edges

of SCLK, and the DAC is updated on the rising edge of
After the data is transferred into the input register of the

addressed DAC, all DAC registers and outputs can be updated
by taking

LDAC

low while the

SYNC

WRITE AND UPDATE COMMANDS

Write to Input Register n (Dependent on

Command 0001 allows the user to write to each DAC’s
dedicated input register individually. When
the input register is transparent (if not controlled by the
LDAC

mask register).

Update DAC Register n with Contents of Input Register n

Command 0010 loads the DAC registers/outputs with the
contents of the input registers selected and updates the DAC
outputs directly.

Write to and Update DAC Channel n (Independent of

)

LDAC

Command 0011 allows the user to write to the DAC registers
and update the DAC outputs directly.

DAISY-CHAIN OPERATION

For systems that contain several DACs, the SDO pin can be
used to daisy-chain several devices together. This function
is enabled through a software executable daisy-chain enable
(DCEN) command. Command 1000 is reserved for this DCEN
function (see Table 8). The daisy-chain mode is enabled by
setting Bit DB0 in the DCEN register. The default setting is
standalone mode, where DB0 = 0. Table 10 shows how the state
of the bit corresponds to the mode of operation of the device.

Table 10. Daisy-Chain Enable (DCEN) Register

DB0 Description

0 Standalone mode (default)
1 DCEN mode

SYNC

line low. Data

LDAC

-dependent change

must be brought high

in Figure 2)

8

SYNC

should be idled at

line is high.

)

LDAC

LDAC

is low,

SYNC

SYNC

.

Rev. 0 | Page 21 of 28

Figure 46. Daisy-Chaining the AD5317R

The SCLK pin is continuously applied to the input shift register

SYNC

when

is low. If more than 24 clock pulses are applied, the
data ripples out of the input shift register and appears on the
SDO line. This data is clocked out on the rising edge of SCLK
and is valid on the falling edge. By connecting the SDO line to
the SDIN input on the next DAC in the chain, a daisy-chain
interface is constructed. Each DAC in the system requires 24
clock pulses. Therefore, the total number of clock cycles must
equal 24 × N, where N is the total number of devices that are
updated. If

SYNC

is taken high at a clock that is not a multiple
of 24, invalid data may be loaded to the DAC. When the serial
transfer to all devices is complete,

SYNC

is taken high. This
latches the input data in each device in the daisy chain and
prevents any further data from being clocked into the input
shift register. The serial clock can be a continuous or a gated clock.
A continuous SCLK source can be used only if

SYNC

can be
held low for the correct number of clock cycles. In gated clock
mode, a burst clock containing the exact number of clock cycles
must be used, and

SYNC

must be taken high after the final clock

to latch the data.

AD5317R Data Sheet

RESISTOR
NETWORK

V

OUT

X

DAC

POWER-DOWN

CIRCUITRY

AMPLIFIER

10800-058

READBACK OPERATION

Readback mode is invoked through a software executable
readback command. If the SDO output is disabled via the daisy­chain mode disable bit in the control register, it is automatically
enabled for the duration of the read operation, after which it is
disabled again. Command 1001 is reserved for the readback
function. This command, in association with selecting one of
the address bits, DAC A to DAC D, selects the register to read.
Note that only one DAC register can be selected during
readback. The remaining three address bits must be set to Logic

0. The remaining data bits in the write sequence are don’t care
bits. If more than one or no bits are selected, DAC Channel A is
read back by default. During the next SPI write, the data
appearing on the SDO output contains the data from the
previously addressed register.

For example, to read back the DAC register for Channel A, the
following sequence should be implemented:

1. Write 0x900000 to the AD5317R input register. This

configures the part for read mode with the DAC register of
Channel A selected. Note that all data bits, DB15 to DB0,
are don’t care bits.

2. Follow this with a second write, a NOP condition,

0x000000. During this write, the data from the register is
clocked out on the SDO line. DB23 to DB20 contain
undefined data, and the last 16 bits contain the DB19 to
DB4 DAC register contents.

Table 11. Modes of Operation

Operating Mode PDx1 PDx0

Normal Operation 0 0
Power-Down Modes

1 kΩ to GND 0 1
100 kΩ to GND 1 0
Three-State 1 1

Any or all DACs (DAC A to DAC D) can be powered down to
the selected mode by setting the corresponding bits. See
Table 12 for the contents of the input shift register during the
power-down/power-up operation.

When both Bit PDx1 and Bit PDx0 (where x is the channel
selected) in the input shift register are set to 0, the part works
normally with its normal power consumption of 1.1 mA at 5 V.
However, for the three power-down modes, the supply current
falls to 4 μA at 5 V. Not only does the supply current fall, but the
output stage is also internally switched from the output of the
amplifier to a resistor network of known values. This has the
advantage that the output impedance of the part is known while
the part is in power-down mode. There are three different
power-down options (see Tabl e 11). The output is connected
internally to GND through either a 1 kΩ or a 100 kΩ resistor, or
it is left open-circuited (three-state). The output stage is
illustrated in Figure 47.

POWER-DOWN OPERATION

The AD5317R provides three separate power-down modes.
Command 0100 is designated for the power-down function (see
Table 8). These power-down modes are software programmable
by setting eight bits, Bit DB7 to Bit DB0, in the input shift register.
There are two bits associated with each DAC channel. Table 11
shows how the state of the two bits corresponds to the mode of
operation of the device.

The bias generator, output amplifier, resistor string, and other
associated linear circuitry are shut down when the power-down

Figure 47. Output Stage During Power-Down

mode is activated. However, the contents of the DAC registers
are unaffected when in power-down. The DAC registers can be
updated while the device is in power-down mode. The time
required to exit power-down is typically 4.5 µs for V

Table 12. 24-Bit Input Shift Register Contents for Power-Down/Power-Up Operation

1

DD

DB15
to

DB23 DB22 DB21 DB20 DB19 to DB16

DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1

0 1 0 0 X X PDD1 PDD0 PDC1 PDC0 PDB1 PDB0 PDA1 PDA0

Command bits (C3 to C0) Address bits

(don’t care)

1

X = don’t care.

Power-Down

Select DAC D

Power-Down
Select DAC C

Power-Down
Select DAC B

Power-Down
Select DAC A

= 5 V.

DB0
(LSB)

Rev. 0 | Page 22 of 28

Data Sheet AD5317R

LOGIC

contents

LOGIC

SYNC

SCLK

V

OUT

X

DAC

REGISTER

INTERFACE

LOGIC

OUTPUT

AMPLIFIER

LDAC

SDO

SDIN

V

REF

INPUT

REGISTER

10-BIT

DAC

10800-059

LOAD DAC (HARDWARE

The AD5317R DAC has double buffered interfaces consisting
of two banks of registers: input registers and DAC registers.
The user can write to any combination of the input registers.
Updates to the DAC register are controlled by the

LDAC

PIN)

LDAC

pin.

MASK REGISTER

LDAC

Command 0101 is reserved for the software

LDAC

function.

Address bits are ignored. Writing to the DAC using Command

LDAC

0101 loads the 4-bit
for each channel is 0; that is, the

register (DB3 to DB0). The default

LDAC

pin works normally.
Setting the bits to 1 forces this DAC channel to ignore transitions
on the

LDAC

pin, regardless of the state of the hardware

LDAC

pin. This flexibility is useful in applications where the user

LDAC

wishes to select which channels respond to the

LDAC

The
control over the hardware
the

mask register gives the user extra flexibility and

LDAC

pin (see Table 13). Setting

LDAC

bits (DB3 to DB0) to 0 for a DAC channel means that

this channel’s update is controlled by the hardware

pin.

LDAC

pin.

Figure 48. Simplified Diagram of Input Loading Circuitry for a Single DAC

Instantaneous DAC Updating (

LDAC

is held low while data is clocked into the input register

LDAC

Held Low)

using Command 0001. Both the addressed input register and

SYNC

the DAC register are updated on the rising edge of
the output begins to change (see

Deferred DAC Updating (

LDAC

is held high while data is clocked into the input register

Table 14).

LDAC

Is Pulsed Low)

and

using Command 0001. All DAC outputs are asynchronously

LDAC

updated by taking

low after

The update now occurs on the falling edge of

Table 14. Write Commands and

SYNC

has been taken high.

LDAC

LDAC

Pin Truth Table1

.

Command Description

0001 Write to Input Register n (dependent on

LDAC

0010 Update DAC Register n with contents of Input

Register n

Load

Bits

LDAC

LDAC

Overwrite Definition

Register

LDAC

Pin

LDAC

Operation

LDAC

Table 13.

LDAC
(DB3 to DB0)

0 1 or 0 Determined by the
1 X1 DAC channels are updated and

) V

1

X = don’t care.

Hardware
Pin State

LDAC

override the
channels see

Input Register
Contents DAC Register Contents

Data update No change (no update)

LDAC

LDAC

pin. DAC

as 1.

GND2 Data update Data update
V

LOGIC

No change Updated with input register

contents

GND No change Updated with input register

pin.

0011 Write to and update DAC Channel n V

1

A high to low hardware

(blocked) by the

2

When LDAC is permanently tied low, the LDAC mask bits are ignored.

LDAC

mask register.

LDAC

pin transition always updates the contents of the DAC register with the contents of the input register on channels that are not masked

Data update Data update

GND Data update Data update

Rev. 0 | Page 23 of 28

AD5317R Data Sheet

HARDWARE RESET (

RESET

is an active low reset that allows the outputs to be
cleared to either zero scale or midscale. The clear code value is
user selectable via the

RESET

keep
operation (see Figure 2). When the
high, the output remains at the cleared value until a new value is

programmed. The outputs cannot be updated with a new value
while the
reset function that resets the DAC to the power-on reset code.
Command 0110 is designated for this software reset function
(see
reset are ignored.

low for a minimum of 30 ns to complete the

RESET

pin is low. There is also a software executable

Table 8). Any events on

RESET

RESET

)

select pin. It is necessary to

RESET

signal is returned

LDAC

or

RESET

during power-on

RESET SELECT PIN (RSTSEL)

The AD5317R contains a power-on reset circuit that controls
the output voltage during power-up. By connecting the RSTSEL
pin low, the output powers up to zero scale. Note that this is
outside the linear region of the DAC. By connecting the
RSTSEL pin high, V
remains powered up at this level until a valid write sequence is
made to the DAC.

powers up to midscale. The output

OUT

Rev. 0 | Page 24 of 28

Data Sheet AD5317R

60

0

10

20

30

40

50

2.498 2.499 2.500 2.501 2.502

HITS

V

REF

(V)

POSTSOLDER
HEAT REFLOW

PRESOLDER
HEAT REFLOW

10800-060

60

0

10

20

30

40

50

2.498 2.499 2.500 2.501 2.502

HITS

V

REF

(V)

0 HOUR
168 HOURS
500 HOURS
1000 HOURS

10800-061

9

8

7

6

5

4

3

2

1

0

500–50–100–150–200

HITS

DISTORTION (ppm)

FIRST TEMPERATURE SWEEP
SUBSEQUENT TEMPERATURE SWEEPS

10800-062

INTERNAL REFERENCE SETUP

By default, the internal reference is on at power-up. To reduce
the supply current, the on-chip reference can be turned off.
Command 0111 is reserved for setting up the internal reference.
To turn off the internal reference, set the software programmable
bit, DB0, in the input shift register using Command 0111, as
shown in Tabl e 16. Table 15 shows how the state of the DB0 bit
corresponds to the mode of operation.

Table 15. Internal Reference Setup Register

Internal Reference
Setup Register (Bit DB0) Action

0 Reference on (default)
1 Reference off

SOLDER HEAT REFLOW

As with all IC reference voltage circuits, the reference value
experiences a shift induced by the soldering process. Analog
Devices, Inc., performs a reliability test called precondition to
mimic the effect of soldering a device to a board. The output
voltage specification in Table 2 includes the effect of this
reliability test.

Figure 49 shows the effect of solder heat reflow (SHR) as
measured through the reliability test (precondition).

LONG-TERM TEMPERATURE DRIFT

Figure 50 shows the change in the V
in life test at 150°C.

Figure 50. Reference Drift to 1000 Hours

value after 1000 hours

REF

THERMAL HYSTERESIS

Thermal hysteresis is the voltage difference induced on the
reference voltage by sweeping the temperature from ambient
to cold, to hot, and then back to ambient.

Thermal hysteresis data is shown in Figure 51. It is measured by
sweeping the temperature from ambient to −40°C, then to +105°C,
and then back to ambient. The V
the two ambient measurements (shown in blue in Figure 51). The
same temperature sweep and measurements were immediately
repeated, and the results are shown in red in Figure 51.

delta is then measured between

REF

Figure 49. SHR Reference Voltage Shift

Table 16. 24-Bit Input Shift Register Contents for Internal Reference Setup Command1

DB23 (MSB) DB22 DB21 DB20 DB19 to DB16 DB15 to DB1 DB0 (LSB)

0 1 1 1 X X 1 or 0

Command bits (C3 to C0) Address bits (don’t care) Don’t care Reference setup register

1

X = don’t care.

Figure 51. Thermal Hysteresis

Rev. 0 | Page 25 of 28

AD5317R Data Sheet

ADSP-BF531

SYNCSPISELx
SCLKSCK
SDINMOSI

LDACPF9
RESET

PF8

AD5317R

10800-164

ADSP-BF527

SYNCSPORT_TFS
SCLKSPORT_TSCK
SDINSPORT_DTO

LDACGPIO0
RESETGPIO1

AD5317R

10800-165

AD5317R

GND

PLANE

BOARD

10800-166

APPLICATIONS INFORMATION

MICROPROCESSOR INTERFACING

Microprocessor interfacing to the AD5317R is via a serial bus
that uses a standard protocol that is compatible with DSP
processors and microcontrollers. The communications channel
requires a 3- or 4-wire interface consisting of a clock signal, a
data signal, and a synchronization signal. The device requires a
24-bit data-word with data valid on the rising edge of

SYNC

.

AD5317R TO ADSP-BF531 INTERFACE

The SPI interface of the AD5317R is designed to be easily
connected to industry-standard DSPs and microcontrollers.
Figure 52 shows the AD5317R connected to the Analog
Devices, Inc., Blackfin® DSP. The Blackfin has an integrated SPI
port that can be connected directly to the SPI pins of the

AD5317R.

Figure 52. ADSP-BF531 Interface

AD5317R TO SPORT INTERFACE

The Analog Devices ADSP-BF527 has one SPORT serial port.
Figure 53 shows how one SPORT interface can be used to
control the AD5317R.

LAYOUT GUIDELINES

In any circuit where accuracy is important, careful consider­ation of the power supply and ground return layout helps to
ensure the rated performance. The PCB on which the AD5317R is
mounted should be designed so that the AD5317R lies on the
analog plane.

The AD5317R should have ample supply bypassing of 10 µF in
parallel with 0.1 µF on each supply, located as close to the
package as possible, ideally right up against the device. The
10 µF capacitors are the tantalum bead type. The 0.1 µF
capacitor should have low effective series resistance (ESR) and
low effective series inductance (ESI), such as the common
ceramic types, which provide a low impedance path to ground
at high frequencies to handle transient currents due to internal
logic switching.

In systems where there are many devices on one board, it is
often useful to provide some heat sinking capability to allow
the power to dissipate easily.

The AD5317R LFCSP model has an exposed pad beneath the
device. Connect this pad to the GND supply for the part. For
optimum performance, use special considerations to design the
motherboard and to mount the package. For enhanced thermal,
electrical, and board level performance, solder the exposed pad
on the bottom of the package to the corresponding thermal land
pad on the PCB. Design thermal vias into the PCB land pad
area to further improve heat dissipation.

The GND plane on the device can be increased (as shown in
Figure 54) to provide a natural heat sinking effect.

Figure 53. SPORT Interface

Figure 54. Pad Connection to Board

Rev. 0 | Page 26 of 28

Data Sheet AD5317R

ENCODE

SERIAL

CLOCK IN

CONTROLLER

ADuM1400

1

SERIAL

DATA OUT

SYNC OUT

LOAD DAC

OUT

DECODE

TO
SCLK

TO
SDIN

TO
SYNC

TO
LDAC

V

IA

V

OA

ENCODE DECODE

V

IB

V

OB

ENCODE DECODE

V

IC

V

OC

ENCODE DECODE

V

ID

V

OD

1

ADDITIONAL PINS OMITTED FOR CLARITY.

10800-167

GALVANICALLY ISOLATED INTERFACE

In many process control applications, it is necessary to
provide an isolation barrier between the controller and
the unit being controlled to protect and isolate the controlling
circuitry from any hazardous common-mode voltages that
may occur. iCoupler® products from Analog Devices provide
voltage isolation in excess of 2.5 kV. The serial loading struc­ture of the AD5317R makes the part ideal for isolated interfaces
because the number of interface lines is kept to a minimum.
Figure 55 shows a 4-channel isolated interface to the AD5317R
using an ADuM1400. For further information, visit

http://www.analog.com/icouplers.

Figure 55. Isolated Interface

Rev. 0 | Page 27 of 28

AD5317R Data Sheet

C

OUTLINE DIMENSIONS

PIN 1

INDI

ATOR

0.80

0.75

0.70

SEATING

PLANE

3.10

3.00 SQ

2.90

0.50

BSC

0.50

0.40

0.30

0.05 MAX

0.02 NOM

0.20 REF

COMPLIANTTOJEDEC STANDARDS MO-220-W E E D - 6.

0.30

0.23

0.18

13

12

9

BOTTOM VIEWTOP VIEW

COPLANARITY

0.08

P

N

I

16

1

EXPOSED

PAD

4

58

FOR PROP ER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPT IONS
SECTION OF THIS DATA SHEET.

Figure 56. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

3 mm × 3 mm Body, Very Very Thin Quad

(CP-16-22)

Dimensions shown in millimeters

5.10

5.00

4.90

N

1

I

D

C

I

A

1.75

1.60 SQ

1.45

0.25 MIN

R

O

T

08-16-2010-E

0.15

0.05

4.50

4.40

4.30

PIN 1

16

0.65

BSC

COPLANARITY

COMPLI ANT TO JEDE C S TANDARDS MO-153 - AB

0.10

0.30

0.19

9

81

1.20
MAX

6.40
BSC

SEATING
PLANE

0.20

0.09
8°

0°

0.75

0.60

0.45

Figure 57. 16-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-16)

Dimensions shown in millimeters

ORDERING GUIDE

Reference

Temperature

Model1 Resolution

Range

AD5317RBCPZ-RL7 10 Bits −40°C to +105°C ±0.12 LSB INL 5 (max) 16-Lead LFCSP_WQ CP-16-22 DG6
AD5317RBRUZ 10 Bits −40°C to +105°C ±0.12 LSB INL 5 (max) 16-Lead TSSOP RU-16
AD5317RBRUZ-RL7 10 Bits −40°C to +105°C ±0.12 LSB INL 5 (max) 16-Lead TSSOP RU-16

1

Z = RoHS Compliant Part.

Accuracy
(Typ)

Tempco
(ppm/°C)

Package
Description

Package
Option

Branding

©2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10800-0-7/12(0)

Rev. 0 | Page 28 of 28