Datasheet AD5307 Datasheet (Analog Devices)

2.5 V to 5.5 V, 400 ␮A, Quad Voltage Output
8-/10-/12-Bit DACs in 16-Lead TSSOP

FEATURES
AD5307: 4 Buffered 8-Bit DACs in 16-Lead TSSOP

A Version: ⴞ1 LSB INL, B Version: ⴞ0.625 LSB INL

AD5317: 4 Buffered 10-Bit DACs in 16-Lead TSSOP

A Version: ⴞ4 LSB INL, B Version: ⴞ2.5 LSB INL

AD5327: 4 Buffered 12-Bit DACs in 16-Lead TSSOP

A Version: ⴞ16 LSB INL, B Version: ⴞ10 LSB INL

Low Power Operation: 400 ␮A @ 3 V, 500 ␮A @ 5 V

2.5 V to 5.5 V Power Supply
Guaranteed Monotonic by Design over All Codes
Power-Down to 90 nA @ 3 V, 300 nA @ 5 V (PD Pin)
Double-Buffered Input Logic
Buffered/Unbuffered Reference Input Options
Output Range: 0 V to V

or 0 V to 2 V

REF

REF

Power-On Reset to 0 V
Simultaneous Update of Outputs (LDAC Pin)
Asynchronous Clear Facility (CLR Pin)
Low Power, SPI

®

, QSPI™, MICROWIRE™, and DSP

Compatible 3-Wire Serial Interface
SDO Daisy-Chaining Option
On-Chip Rail-to-Rail Output Buffer Amplifiers
Temperature Range –40ⴗC to +105ⴗC

APPLICATIONS
Portable Battery-Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources

AD5307/AD5317/AD5327

*

Programmable Attenuators
Industrial Process Control

GENERAL DESCRIPTION

The AD5307/AD5317/AD5327 are quad 8-, 10-, and 12-bit
buffered voltage-output DACs in a 16-lead TSSOP package that
operate from a single 2.5 V to 5.5 V supply, consuming 400 mA
at 3 V. Their on-chip output amplifiers allow the outputs to
swing rail-to-rail with a slew rate of 0.7 V/ms. The AD5307/
AD5317/AD5327 utilize a versatile 3-wire serial interface that
operates at clock rates up to 30 MHz and is compatible with
standard SPI, QSPI, MICROWIRE, and DSP interface standards.

The references for the four DACs are derived from two refer­ence pins (one per DAC pair). These reference inputs can be
configured as buffered or unbuffered inputs. The parts incorpo­rate a power-on reset circuit, which ensures that the DAC outputs
power up to 0 V and remain there until a valid write to the device
takes place. There is also an asynchronous active low CLR pin
that clears all DACs to 0 V. The outputs of all DACs may be
updated simultaneously using the asynchronous LDAC input.
The parts contain a power-down feature that reduces the cur­rent consumption of the devices to 300 nA @ 5 V (90 nA @
3 V). The parts may also be used in daisy-chaining applications
using the SDO pin.

All three parts are offered in the same pinout, which allows users
to select the amount of resolution appropriate for their applica­tion without redesigning their circuit board.

FUNCTIONAL BLOCK DIAGRAM

AD5307/AD5317/AD5327

LDAC

INPUT

REGISTER

SCLK

SYNC

DIN

SDO

*Protected by U.S. Patent No. 5,969,657; other patents pending.

INTERFACE

LOGIC

DCEN

LDAC PD

CLR

INPUT

REGISTER

INPUT

REGISTER

INPUT

REGISTER

POWER-ON

RESET

REV. A

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.

V

V

DD

DAC

REGISTER

DAC

REGISTER

DAC

REGISTER

DAC

REGISTER

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2003 Analog Devices, Inc. All rights reserved.

REF

STRING

DAC A

STRING

DAC B

STRING

DAC C

STRING

DAC D

V

REF

AB

CD

GAIN-SELECT

BUFFER

BUFFER

BUFFER

BUFFER

POWER-DOWN

LOGIC

LOGIC

GND

V

A

OUT

V

B

OUT

V

C

OUT

V

D

OUT

AD5307/AD5317/AD5327–SPECIFICATIONS

= 200 pF to GND; all specifications T

GND; C

L

Parameter

DC PERFORMANCE

1

3, 4

A Version
Min Typ Max Min Typ Max Unit Conditions/Comments

MIN

to T

, unless otherwise noted.)

MAX

2

B Version

2

(VDD = 2.5 V to 5.5 V; V

= 2 V; RL = 2 k⍀ to

REF

AD5307

Resolution 8 8 Bits
Relative Accuracy ± 0.15 ± 1 ± 0.15 ± 0.625 LSB
Differential Nonlinearity ± 0.02 ± 0.25 ± 0.02 ± 0.25 LSB Guaranteed Monotonic by Design

over All Codes

AD5317

Resolution 10 10 Bits
Relative Accuracy ± 0.5 ± 4 ± 0.5 ± 2.5 LSB
Differential Nonlinearity ± 0.05 ± 0.5 ± 0.05 ± 0.5 LSB Guaranteed Monotonic by Design

over All Codes

AD5327

Resolution 12 12 Bits
Relative Accuracy ± 2 ± 16 ± 2 ± 10 LSB
Differential Nonlinearity ± 0.2 ± 1 ± 0.2 ± 1 LSB Guaranteed Monotonic by Design

over All Codes

Offset Error ± 5 ± 60 ± 5 ± 60 mV V

= 4.5 V, Gain = 2;

DD

See Figures 4 and 5

Gain Error ± 0.3 ± 1.25 ± 0.3 ± 1.25 % of FSR V

Lower Deadband

Upper Deadband

Offset Error Drift

Gain Error Drift

6

5

5

6

10 60 10 60 mV See Figure 4. Lower deadband exists

10 60 10 60 mV See Figure 5. Upper deadband exists

–12 –12 ppm of

FSR/∞C

–5 –5 ppm of

= 4.5 V, Gain = 2;

DD

See Figures 4 and 5.

only if offset error is negative.

only if V

= VDD and offset plus

REF

gain error is positive.

FSR/∞C

DC Power Supply Rejection

6

Ratio

DC Crosstalk

DAC REFERENCE INPUTS

V

Input Range 1 V

REF

6

6

0.25 V

Input Impedance (R

V

REF

) >10 >10 MW Buffered Reference Mode and

DAC

–60 –60 dB ⌬VDD = ± 10%
200 200 mVR

1V

DD

0.25 V

DD

V Buffered Reference Mode

DD

V Unbuffered Reference Mode

DD

= 2 kW to GND or V

L

DD

Power-Down Mode

74 90 74 90 kW Unbuffered Reference Mode.

0 V to V

Output Range

REF

37 45 37 45 kW Unbuffered Reference Mode.

0 V to 2 V

Output Range

REF

Reference Feedthrough –90 –90 dB Frequency = 10 kHz
Channel-to-Channel Isolation –75 –75 dB Frequency = 10 kHz

OUTPUT CHARACTERISTICS

Minimum Output Voltage
Maximum Output Voltage

6

7

7

0.001 0.001 V This is a measure of the minimum
VDD – 0.001 VDD – 0.001 V and maximum drive capability of the

output amplifier.

DC Output Impedance 0.5 0.5 W
Short Circuit Current 25 25 mA V

16 16 mA V

DD

DD

= 5 V
= 3 V

Power-Up Time 2.5 2.5 ms Coming out of Power-Down Mode.

= 5 V

V

DD

55ms Coming out of Power-Down Mode.

VDD = 3 V

REV. A–2–

AD5307/AD5317/AD5327

Parameter

1

LOGIC INPUTS

A Version

2

B Version

Min Typ Max Min Typ Max Unit Conditions/Comments

6

2

Input Current ± 1 ± 1 mA

, Input Low Voltage 0.8 0.8 V VDD = 5 V ± 10%

V

IL

, Input High Voltage

V

IH

(Excluding DCEN) 1.7 1.7 V V

0.6 0.6 V V

0.5 0.5 V V

= 3 V ± 10%

DD

= 2.5 V

DD

= 2.5 V to 5.5 V; TTL and 1.8 V

DD

CMOS Compatible

, Input High Voltage

V

IH

(DCEN) 2.4 2.4 V V

2.1 2.1 V V

2.0 2.0 V V

= 5 V ± 10%

DD

= 3 V ± 10%

DD

= 2.5 V

DD

Pin Capacitance 3 3 pF

LOGIC OUTPUT (SDO)

6

VDD = 4.5 V to 5.5 V

Output Low Voltage, V
Output High Voltage, V

V

= 2.5 V to 3.6 V

DD

Output Low Voltage, V
Output High Voltage, V

OL

OL

OH

OH

0.4 0.4 V I

VDD – 1 VDD – 1 V I

0.4 0.4 V I

VDD – 0.5 VDD – 0.5 V I

= 2 mA

SINK

SOURCE

= 2 mA

SINK

SOURCE

= 2 mA

= 2 mA

Floating State Leakage Current ± 1 ± 1 mA DCEN = GND
Floating State Output

Capacitance 3 3 pF DCEN = GND

POWER REQUIREMENTS

V

DD

(Normal Mode)

I

DD

V

= 4.5 V to 5.5 V 500 900 500 900 mA All DACs in Unbuffered Mode.

DD

8

2.5 5.5 2.5 5.5 V
VIH = VDD and VIL = GND

In Buffered Mode, extra current is
typically x mA per DAC

= 2.5 V to 3.6 V 400 750 400 750 mA where x = 5 mA + V

V

DD

(Power-Down Mode) VIH = VDD and VIL = GND

I

DD

= 4.5 V to 5.5 V 0.3 1 0.3 1 mA

V

DD

VDD = 2.5 V to 3.6 V 0.09 1 0.09 1 mA

NOTES

1

See the Terminology section.

2

Temperature range (A, B Versions): –40∞C to +105∞C; typical at +25∞C.

3

DC specifications tested with the outputs unloaded, unless stated otherwise.

4

Linearity is tested using a reduced code range: AD5307 (Code 8 to 255); AD5317 (Code 28 to 1023); AD5327 (Code 115 to 4095).

5

This corresponds to x codes. x = Deadband Voltage/LSB size.

6

Guaranteed by design and characterization; not production tested.

7

For the amplifier output to reach its minimum voltage, offset error must be negative; for the amplifier output to reach its maximum voltage, V
plus gain error must be positive.

8

Interface inactive. All DACs active. DAC outputs unloa-ded.

Specifications subject to change without notice.

REF/RDAC

REF

.

= VDD and offset

REV. A

–3–

AD5307/AD5317/AD5327

(VDD = 2.5 V to 5.5 V; RL = 2 k⍀ to GND; CL = 200 pF to GND; all specifications T

AC CHARACTERISTICS

Parameter

2

1

otherwise noted.)

A, B Versions

3

Min Typ Max Unit Conditions/Comments

Output Voltage Settling Time V

= VDD = 5 V

REF

MIN

to T

, unless

MAX

AD5307 6 8 ms 1/4 Scale to 3/4 Scale Change (0x40 to 0xC0)
AD5317 7 9 ms 1/4 Scale to 3/4 Scale Change (0x100 to 0x300)
AD5327 8 10 ms 1/4 Scale to 3/4 Scale Change (0x400 to 0xC00)

Slew Rate 0.7 V/ms
Major-Code Change Glitch Energy 12 nV-s 1 LSB Change around Major Carry
Digital Feedthrough 0.5 nV-s
SDO Feedthrough 4 nV-s Daisy-Chain Mode; SDO Load is 10 pF
Digital Crosstalk 0.5 nV-s
Analog Crosstalk 1 nV-s
DAC-to-DAC Crosstalk 3 nV-s
Multiplying Bandwidth 200 kHz V
Total Harmonic Distortion –70 dB V

NOTES

1

Guaranteed by design and characterization; not production tested.

2

See the Terminology section.

3

Temperature range (A, B Versions): –40∞C to +105∞C; typical at +25∞C.

Specifications subject to change without notice.

1, 2, 3

TIMING CHARACTERISTICS

(VDD = 2.5 V to 5.5 V; all specifications T

= 2 V ± 0.1 V p-p. Unbuffered Mode

REF

= 2.5 V ± 0.1 V p-p. Frequency = 10 kHz

REF

to T

MIN

, unless otherwise noted.)

MAX

A, B Versions

Parameter Limit at T

t

1

t

2

t

3

t

4

t

5

t

6

t

7

t

8

t

9

t

10

t

11

t

12

4, 5

t

13

5

t

14

5

t

15

5

t

16

NOTES

1

Guaranteed by design and characterization; not production tested.

2

All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.

3

See Figures 2 and 3.

4

This is measured with the load circuit of Figure 1. t13 determines maximum SCLK frequency in Daisy-Chain mode.

5

Daisy-chain mode only.

Specifications subject to change without notice.

33 ns min SCLK Cycle Time
13 ns min SCLK High Time
13 ns min SCLK Low Time
13 ns min SYNC to SCLK Falling Edge Setup Time
5 ns min Data Setup Time

4.5 ns min Data Hold Time
0 ns min SCLK Falling Edge to SYNC Rising Edge
50 ns min Minimum SYNC High Time
20 ns min LDAC Pulsewidth
20 ns min SCLK Falling Edge to LDAC Rising Edge
20 ns min CLR Pulsewidth
0 ns min SCLK Falling Edge to LDAC Falling Edge
20 ns max SCLK Rising Edge to SDO Valid (VDD = 3.6 V to 5.5 V)
25 ns max SCLK Rising Edge to SDO Valid (V
5 ns min SCLK Falling Edge to SYNC Rising Edge
8 ns min SYNC Rising Edge to SCLK Rising Edge
0 ns min SYNC Rising Edge to LDAC Falling Edge

MIN

, T

MAX

Unit Conditions/Comments

= 2.5 V to 3.5 V)

DD

REV. A–4–

2mA

AD5307/AD5317/AD5327

I

OL

Figure 1. Load Circuit for Digital Output (SDO) Timing Specifications

SCLK

t

t

8

SYNC

DIN

1

LDAC

2

LDAC

CLR

NOTES

ASYNCHRONOUS LDAC UPDATE MODE.

1

SYNCHRONOUS LDAC UPDATE MODE.

2

DB15

TO OUTPUT

PIN

C

L

50pF

I

2mA

OH

t

1

t

2

DB0

t

7

t

9

t

12

t

4

t

5

3

t

6

Figure 2. Serial Interface Timing Diagram

V

OH (MIN)

t

10

t

11

REV. A

SCLK

SYNC

LDAC

DIN

SDO

t

1

t

t

t

t

4

8

t

5

DB15

INPUT WORD FOR DAC N INPUT WORD FOR DAC (N+1)

3

t

6

UNDEFINED INPUT WORD FOR DAC N

2

DB0 DB15' DB0'

t

13

DB15

t

14

DB0

t

15

t

16

t

9

Figure 3. Daisy-Chaining Timing Diagram

–5–

AD5307/AD5317/AD5327

ABSOLUTE MAXIMUM RATINGS

(TA = 25∞C, unless otherwise noted.)

VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

Digital Input Voltage to GND . . . . . . . –0.3 V to V

Digital Output Voltage to GND . . . . . –0.3 V to V

Reference Input Voltage to GND . . . . –0.3 V to V

V

OUT

A–V

D to GND . . . . . . . . . . . –0.3 V to VDD + 0.3 V

OUT

Operating Temperature Range

Industrial (A, B Versions) . . . . . . . . . . . . –40∞C to +105∞C

Storage Temperature Range . . . . . . . . . . . . –65∞C to +150∞C

Junction Temperature (T

max) . . . . . . . . . . . . . . . . . . . 150∞C

J

1, 2

+ 0.3 V

DD

+ 0.3 V

DD

+ 0.3 V

DD

16-Lead TSSOP

Power Dissipation . . . . . . . . . . . . . . . . . . (T

max – TA)/␪

J

␪JA Thermal Impedance . . . . . . . . . . . . . . . . . . . 150.4∞C/W

Reflow Soldering

Peak Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . 220∞C

Time at Peak Temperature . . . . . . . . . . . . . 10 sec to 40 sec

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.

2

Transient currents of up to 100 mA will not cause SCR latch-up.

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD5307ARU –40∞C to +105∞CThin Shrink Small Outline Package (TSSOP) RU-16
AD5307ARU-REEL 7 –40∞C to +105∞CThin Shrink Small Outline Package (TSSOP) RU-16
AD5307BRU –40∞C to +105∞CThin Shrink Small Outline Package (TSSOP) RU-16
AD5307BRU-REEL –40∞C to +105∞CThin Shrink Small Outline Package (TSSOP) RU-16
AD5307BRU-REEL7 –40∞C to +105∞CThin Shrink Small Outline Package (TSSOP) RU-16
AD5317ARU –40∞C to +105∞CThin Shrink Small Outline Package (TSSOP) RU-16
AD5317ARU-REEL7 –40∞C to +105∞CThin Shrink Small Outline Package (TSSOP) RU-16
AD5317BRU –40∞C to +105∞CThin Shrink Small Outline Package (TSSOP) RU-16
AD5317BRU-REEL –40∞C to +105∞CThin Shrink Small Outline Package (TSSOP) RU-16
AD5317BRU-REEL7 –40∞C to +105∞CThin Shrink Small Outline Package (TSSOP) RU-16
AD5327ARU –40∞C to +105∞CThin Shrink Small Outline Package (TSSOP) RU-16
AD5327ARU-REEL7 –40∞C to +105∞CThin Shrink Small Outline Package (TSSOP) RU-16
AD5327BRU –40∞C to +105∞CThin Shrink Small Outline Package (TSSOP) RU-16
AD5327BRU-REEL –40∞C to +105∞CThin Shrink Small Outline Package (TSSOP) RU-16
AD5327BRU-REEL7 –40∞C to +105∞CThin Shrink Small Outline Package (TSSOP) RU-16

JA

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD5307/AD5317/AD5327 feature proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions
are recommended to avoid performance degradation or loss of functionality.

REV. A–6–

PIN CONFIGURATION

AD5307/AD5317/AD5327

V

V

LDAC

V

OUT

V

OUT

V

OUT

REF

REF

CLR

V

AB

CD

DD

1

2

3

4

A

5

B

(Not to Scale)

6

C

7

8

AD5307/
AD5317/

AD5327

TOP VIEW

16

SDO

15

SYNC

14

SCLK

13

DIN

12

GND

11

V

D

OUT

10

PD

DCEN

9

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Function

1 CLR Active Low Control Input that Loads All Zeros to All Input and DAC Registers. Therefore, the outputs

also go to 0 V.

2 LDAC Active Low Control Input that Transfers the Contents of the Input Registers to their Respective DAC

Registers. Pulsing this pin low allows any or all DAC registers to be updated if the input registers have
new data. This allows simultaneous update of all DAC outputs. Alternatively, this pin can be tied
permanently low.

3V

DD

Power Supply Input. These parts can be operated from 2.5 V to 5.5 V, and the supply should be decoupled
with a 10 mF capacitor in parallel with a 0.1 mF capacitor to GND.

4V

5V

6V

7V

ABuffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.

OUT

BBuffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.

OUT

CBuffered Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.

OUT

AB Reference Input Pin for DACs A and B. It may be configured as a buffered or an unbuffered input to each or

REF

both of the DACs, depending on the state of the BUF bits in the serial input words to DACs A and B. It

in unbuffered mode and from 1 V to VDD in buffered mode.

DD

8V

CD Reference Input Pin for DACs C and D. It may be configured as a buffered or an unbuffered input to each or

REF

has an input range from 0.25 V to V

both of the DACs, depending on the state of the BUF bits in the serial input words to DACs C and D. It
has an input range from 0.25 V to V

in unbuffered mode and from 1 V to VDD in buffered mode.

DD

9 DCEN This pin is used to enable the daisy-chaining option. This should be tied high if the part is being used in a

daisy chain. The pin should be tied low if it is being used in standalone mode.

10 PD Active low control input that acts as a hardware power-down option. All DACs go into power-down

mode when this pin is tied low. The DAC outputs go into a high impedance state and the current con­sumption of the part drops to 300 nA @ 5 V (90 nA @ 3 V).

11 V

DBuffered Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.

OUT

12 GND Ground Reference Point for All Circuitry on the Part.

13 DIN Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling

edge of the serial clock input. The DIN input buffer is powered down after each write cycle.

14 SCLK Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock

input. Data can be transferred at rates up to 30 MHz. The SCLK input buffer is powered down after
each write cycle.

15 SYNC Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes

low, it powers on the SCLK and DIN buffers and enables the input shift register. Data is transferred in
on the falling edges of the following 16 clocks. If SYNC is taken high before the 16th falling edge, the
rising edge of SYNC acts as an interrupt and the write sequence is ignored by the device.

16 SDO Serial Data Output. Can be used for daisy-chaining a number of these devices together or for reading

back the data in the shift register for diagnostic purposes. The serial data is transferred on the rising edge
of SCLK and is valid on the falling edge of the clock.

REV. A

–7–

AD5307/AD5317/AD5327

TERMINOLOGY
Relative Accuracy

For the DAC, relative accuracy or integral nonlinearity (INL) is
a measure of the maximum deviation, in LSB, from a straight
line passing through the endpoints of the DAC transfer function.
Typical INL versus code plots can be seen in TPCs 1, 2, and 3.

Differential Nonlinearity

Differential nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A specified differential nonlinearity of ± 1 LSB
maximum ensures monotonicity. This DAC is guaranteed
monotonic by design. Typical DNL versus code plots can be
seen in TPCs 4, 5, and 6.

Offset Error

This is a measure of the offset error of the DAC and the output
amplifier. (See Figures 4 and 5.) It can be negative or positive.
It is expressed in mV.

Gain Error

This is a measure of the span error of the DAC. It is the devia­tion in slope of the actual DAC transfer characteristic from the
ideal expressed as a percentage of the full-scale range.

Offset Error Drift

This is a measure of the change in offset error with changes in
temperature. It is expressed in (ppm of full-scale range)/∞C.

Gain Error Drift

This is a measure of the change in gain error with changes in
temperature. It is expressed in (ppm of full-scale range)/∞C.

DC Power Supply Rejection Ratio (PSRR)

This indicates how the output of the DAC is affected by changes
in the supply voltage. PSRR is the ratio of the change in V

OUT

to a change in VDD for full-scale output of the DAC. It is mea­sured in dB. V

DC Crosstalk

is held at 2 V and VDD is varied ± 10%.

REF

This is the dc change in the output level of one DAC in response
to a change in the output of another DAC. It is measured with a
full-scale output change on one DAC while monitoring another
DAC. It is expressed in mV.

Reference Feedthrough

This is the ratio of the amplitude of the signal at the DAC output
to the reference input when the DAC output is not being updated
(i.e., LDAC is high). It is expressed in dB.

Channel-to-Channel Isolation

This is the ratio of the amplitude of the signal at the output of
one DAC to a sine wave on the reference input of another DAC.
It is measured in dB.

Major-Code Transition Glitch Energy

Major-code transition glitch energy is the energy of the impulse
injected into the analog output when the code in the DAC
register changes state. It is normally specified as the area of the
glitch in nV-s and is measured when the digital code is changed
by 1 LSB at the major carry transition (011 . . . 11 to 100 . . .
00 or 100 . . . 00 to 011 . . . 11).

Digital Feedthrough

Digital feedthrough is a measure of the impulse injected into the
analog output of a DAC from the digital input pins of the device,
but is measured when the DAC is not being written to the (SYNC
held high). It is specified in nV-s and is measured with a full­scale change on the digital input pins, i.e., from all 0s to all 1s
or vice versa.

Digital Crosstalk

This is the glitch impulse transferred to the output of one DAC
at midscale in response to a full-scale code change (all 0s to all
1s and vice versa) in the input register of another DAC. It is
measured in standalone mode and is expressed in nV-s.

Analog Crosstalk

This is the glitch impulse transferred to the output of one DAC
due to a change in the output of another DAC. It is measured
by loading one of the input registers with a full-scale code change
(all 0s to all 1s and vice versa) while keeping LDAC high. Then
pulse LDAC low and monitor the output of the DAC whose
digital code was not changed. The area of the glitch is expressed
in nV-s.

DAC-to-DAC Crosstalk

This is the glitch impulse transferred to the output of one DAC
due to a digital code change and subsequent output change of
another DAC. This includes both digital and analog crosstalk. It
is measured by loading one of the DACs with a full-scale code
change (all 0s to all 1s and vice versa) with LDAC low and
monitoring the output of another DAC. The energy of the glitch
is expressed in nV-s.

Multiplying Bandwidth

The amplifiers within the DAC have a finite bandwidth. The
multiplying bandwidth is a measure of this. A sine wave on the
reference (with full-scale code loaded to the DAC) appears on
the output. The multiplying bandwidth is the frequency at which
the output amplitude falls to 3 dB below the input.

Total Harmonic Distortion

This is the difference between an ideal sine wave and its attenuated
version using the DAC. The sine wave is used as the reference
for the DAC, and the THD is a measure of the harmonics present
on the DAC output. It is measured in dB.

REV. A–8–

OUTPUT

VOLTAGE

NEGATIVE

OFFSET

ERROR

AMPLIFIER

FOOTROOM

NEGATIVE

OFFSET

ERROR

LOWER

DEADBAND

CODES

DAC CODE

GAIN ERROR

OFFSET ERROR

ACTUAL

IDEAL

AD5307/AD5317/AD5327

GAIN ERROR

+

+

OUTPUT

VOLTAGE

POSITIVE

OFFSET

ERROR

DAC CODE

Figure 5. Transfer Function with Positive Offset
(V

= VDD)

REF

OFFSET ERROR

UPPER
DEADBAND
CODES

ACTUAL

IDEAL

FULL SCALE

Figure 4. Transfer Function with Negative Offset

REV. A

–9–

AD5307/AD5317/AD5327–Typical Performance Characteristics

GAIN ERROR

TEMPERATURE (ⴰC)

ERROR (% FSR)

1.0

0.5

–1.0

ⴚ40 0 40

0

–0.5

VDD = 5V
V

REF

= 2V

OFFSET ERROR

80 120

1.0

TA = 25ⴗC
V

= 5V

DD

0.5

0

INL ERROR (LSB)

–0.5

–1.0

050 250100 150 200

CODE

TPC 1. AD5307 Typical INL Plot

0.3
TA = 25ⴗC

= 5V

V

DD

0.2

0.1

0

–0.1

DNL ERROR (LSB)

–0.2

3

TA = 25ⴗC
V

= 5V

DD

2

1

0

–1

INL ERROR (LSB)

–2

–3

0 200 1000

400 600 800

CODE

TPC 2. AD5317 Typical INL Plot

0.6
TA = 25ⴗC

= 5V

V

DD

0.4

0.2

0

–0.2

DNL ERROR (LSB)

–0.4

12

TA = 25ⴗC

= 5V

V

DD

8

4

0

–4

INL ERROR (LSB)

–8

–12

0 40001000 2000 3000

CODE

TPC 3. AD5327 Typical INL Plot

1.0
TA = 25ⴗC

= 5V

V

DD

0.5

0

DNL ERROR (LSB)

–0.5

–0.3

050 250100 150 200

CODE

TPC 4. AD5307 Typical DNL Plot

0.50

VDD = 5V

= 25ⴗC

T

A

0.25

0

ERROR (LSB)

–0.25

–0.50

01 5234

MAX INL

MIN DNL

MIN INL

V

REF

(V)

TPC 7. AD5307 INL and DNL
Error vs. V

REF

MAX DNL

–0.6

2000

CODE

600400

800 1000

TPC 5. AD5317 Typical DNL Plot

0.5

VDD = 5V

0.4

0.3

0.2

0.1

–0.1

ERROR (LSB)

–0.2

–0.3

–0.4

–0.5

= 3V

V

REF

0

ⴚ40 0 40

MAX INL

MAX DNL

TEMPERATURE (ⴰC)

MIN DNL

MIN INL

80 120

TPC 8. AD5307 INL Error and
DNL Error vs. Temperature

–1.0

10000

2000

CODE

3000 4000

TPC 6. AD5327 Typical DNL Plot

TPC 9. AD5307 Offset Error and
Gain Error vs. Temperature

REV. A–10–

AD5307/AD5317/AD5327

0.2
TA = 25ⴗC

0.1

–0.1

–0.2

–0.3

ERROR (% FSR)

–0.4

–0.5

–0.6

= 2V

V

REF

0

01 3

GAIN ERROR

OFFSET ERROR

25

VDD (V)

46

TPC 10. Offset Error and Gain
Error vs. V

600

500

400

300

(␮A)

DD

I

200

DD

–40ⴗC

+25ⴗC

+105ⴗC

5

5V SOURCE

3V SOURCE

3

(V)

OUT

V

2

1

0

01 3446

SINK/SOURCE CURRENT (mA)

TPC 11. V

5V SINK

25

Source and Sink

OUT

3V SINK

Current Capability

0.5

0.4

0.3

(␮A)

DD

I

0.2

–40ⴗC

+25ⴗC

600

500

400

300

(␮A)

DD

I

200

100

0

ZERO SCALE

CODE

TPC 12. Supply Current vs.
DAC Code

800

DECREASING

700

INCREASING

600

(␮A)

DD

I

500

VDD = 5V

TA = 25ⴗC

= 5V

V

DD

= 2V

V

REF

FULL SCALE

TA = 25ⴗC

100

0

3.0 3.5 4.0 4.5 5.0 5.5

2.5
VDD (V)

TPC 13. Supply Current vs.
Supply Voltage

T

= 25ⴗC

A

5µs

= 5V

V

DD

= 5V

V

REF

CH1

V

A

OUT

SCLK

CH2

CH1 1V, CH2 5V, TIME BASE= 1␮s/DIV

TPC 16. Half-Scale Settling (1/4 to
3/4 Scale Code Change)

0.1

0

2.5 3.0

4.0

VDD (V)

+105ⴗC

4.5 5.53.5 5.0

TPC 14. Power-Down Current vs.
Supply Voltage

TA = 25ⴗC

= 5V

V

DD

= 2V

V

REF

CH1

V

DD

V

CH2

CH1 2.00V, CH2 200mV, TIME BASE = 200␮s/DIV

OUT

A

TPC 17. Power-On Reset to 0 V

400

300

01

INCREASING

DECREASING

VDD = 3V

23 4
V

(V)

LOGIC

TPC 15. Supply Current vs. Logic
Input Voltage for SCLK and DIN
Increasing and Decreasing

TA = 25ⴗC

= 5V

V

DD

= 2V

V

REF

CH1

V

A

OUT

CH2

PD

CH1 500mV, CH2 5.00V, TIME BASE = 1␮s/DIV

TPC 18. Exiting Power-Down to
Midscale

5

REV. A

–11–

AD5307/AD5317/AD5327

V

= 3V

DD

V

FREQUENCY

350 400 500 550450 600

IDD (␮A)

TPC 19. IDD Histogram with
V

= 3 V and VDD = 5 V

DD

0.02

VDD = 5V

= 25ⴗC

T

A

0.01

0

DD

= 5V

2.50

2.49

(V)

OUT

V

2.48

2.47
1␮s/DIV

TPC 20. AD5327 Major-Code
Transition Glitch Energy

1mV/DIV

10

0

–10

–20

dB

–30

–40

–50

–60

10

100 1k 10k 100k 1M 10M

FREQUENCY (Hz)

TPC 21. Multiplying Bandwidth
(Small-Signal Frequency Response)

–0.01

FULL-SCALE ERROR (V)

–0.02

01 3

25

V

46

(V)

REF

TPC 22. Full-Scale Error vs. V

REF

150ns/DIV

TPC 23. DAC-to-DAC Crosstalk

REV. A–12–

AD5307/AD5317/AD5327

TO OUTPUT
AMPLIFIER

R

R

R

R

R

FUNCTIONAL DESCRIPTION

The AD5307/AD5317/AD5327 are quad resistor-string DACs
fabricated on a CMOS process with resolutions of 8, 10, and
12 bits respectively. Each contains four output buffer amplifiers
and is written to via a 3-wire serial interface. They operate from

impedance it presents to the voltage source driving it. How­ever, if the unbuffered mode is used, the user can have a
reference voltage as low as 0.25 V and as high as V

DD

since
there is no restriction due to headroom and footroom of the
reference amplifier.

single supplies of 2.5 V to 5.5 V, and the output buffer amplifiers
provide rail-to-rail output swing with a slew rate of 0.7 V/ms.
DACs A and B share a common reference input, V
DACs C and D share a common reference input, V

REF

REF

AB.

CD.
Each reference input may be buffered to draw virtually no
current from the reference source, or unbuffered to give a
reference input range from 0.25 V to V

. The devices have a

DD

power-down mode in which all DACs may be turned off
completely with a high impedance output.

Digital-to-Analog Section

The architecture of one DAC channel consists of a resistor-string
DAC followed by an output buffer amplifier. The voltage at the

pin provides the reference voltage for the corresponding

V

REF

DAC. Figure 6 shows a block diagram of the DAC architecture.
Since the input coding to the DAC is straight binary, the ideal
output voltage is given by

VD

¥

V

OUT

REF

=

N

2

where:

D = decimal equivalent of the binary code that is loaded to the
DAC register:

0–255 for AD5307 (8 bits)
0–1023 for AD5317 (10 bits)
0–4095 for AD5327 (12 bits)

N = DAC resolution

V

AB

REF

REFERENCE

BUF

BUFFER

GAIN MODE

(GAIN = 1 OR 2)

If there is a buffered reference in the circuit (e.g., REF192), there
is no need to use the on-chip buffers of the AD5307/AD5317/
AD5327. In unbuffered mode, the input impedance is still large
at typically 90 kW per reference input for 0 V to V
45 kW for 0 V to 2 V

The buffered/unbuffered option is controlled by the BUF bit in
the data-word. The BUF bit setting applies to whichever DAC
is selected.

Output Amplifier

The output buffer amplifier is capable of generating output
voltages to within 1 mV of either rail. Its actual range depends
on the value of V

If a gain of 1 is selected (GAIN = 0), the output range is 0.001 V
to V

.

REF

If a gain of 2 is selected (GAIN = 1), the output range is 0.001 V
to 2 V

. Because of clamping, however, the maximum output

REF

is limited to V

The output amplifier is capable of driving a load of 2 kW to
GND or V

DD

Figure 7. Resistor String

mode and

mode.

REF

, GAIN, offset error, and gain error.

REF

– 0.001 V.

DD

REF

, in parallel with 500 pF to GND or VDD. The

source and sink capabilities of the output amplifier can be seen

INPUT

REGISTER

DAC

REGISTER

RESISTOR

STRING

OUTPUT

BUFFER AMPLIFIER

V

OUT

Figure 6. Single DAC Channel Architecture

Resistor String

The resistor string section is shown in Figure 7. It is simply a
string of resistors, each of value R. The digital code loaded to
the DAC register determines at which node on the string the
voltage is tapped off to be fed into the output amplifier. The
voltage is tapped off by closing one of the switches connecting
the string to the amplifier. Because it is a string of resistors, it is
guaranteed monotonic.

DAC Reference Inputs

There is a reference pin for each pair of DACs. The reference
inputs are buffered but can also be individually configured as
unbuffered. The advantage with the buffered input is the high

in the plot in TPC 11.

A

The slew rate is 0.7 V/ms with a half-scale settling time to ±0.5 LSB
(at eight bits) of 6 ms.

POWER-ON RESET

The AD5307/AD5317/AD5327 are provided with a power-on
reset function so that they power up in a defined state. The
power-on state is

∑ Normal operation
∑ Reference inputs unbuffered
∑ 0 V to V

output range

REF

∑ Output voltage set to 0 V

Both input and DAC registers are filled with zeros and remain
so until a valid write sequence is made to the device. This is
particularly useful in applications where it is important to know
the state of the DAC outputs while the device is powering up.

REV. A

–13–

AD5307/AD5317/AD5327

SERIAL INTERFACE

The AD5307/AD5317/AD5327 are controlled over a versatile
3-wire serial interface that operates at clock rates up to 30 MHz
and is compatible with SPI, QSPI, MICROWIRE, and DSP
interface standards.

Input Shift Register

The input shift register is 16 bits wide. Data is loaded into the
device as a 16-bit word under the control of a serial clock input,
SCLK. The timing diagram for this operation is shown in
Figure 2. The 16-bit word consists of four control bits followed
by 8, 10, or 12 bits of DAC data, depending on the device type.
Data is loaded MSB first (Bit 15), and the first two bits determine
whether the data is for DAC A, DAC B, DAC C, or DAC D.
Bits 13 and 12 control the operating mode of the DAC. Bit 13
is GAIN, which determines the output range of the part. Bit 12
is BUF, which controls whether the reference inputs are
buffered or unbuffered.

Table I. Address Bits for the AD53x7

A1 (Bit 15) A0 (Bit 14) DAC Addressed

00 DAC A
01 DAC B
10 DAC C
11 DAC D

Control Bits

GAIN Controls the output range of the addressed DAC.

0: Output range of 0 V to V
1: Output range of 0 V to 2 V

REF

.

REF

.

BUF Controls whether reference of the addressed DAC

is buffered or unbuffered.
0: Unbuffered reference.
1: Buffered reference.

The AD5327 uses all 12 bits of DAC data; the AD5317 uses 10
bits and ignores the 2 LSB. The AD5307 uses eight bits and
ignores the last four bits. The data format is straight binary,
with all 0s corresponding to 0 V output and all 1s corresponding
to full-scale output (V

– 1 LSB).

REF

The SYNC input is a level-triggered input that acts as a frame
synchronization signal and chip enable. Data can be transferred
into the device only while SYNC is low. To start the serial data
transfer, SYNC should be taken low, observing the minimum
SYNC to SCLK falling edge setup time, t

. After SYNC goes low,

4

serial data will be shifted into the device’s input shift register on
the falling edges of SCLK for 16 clock pulses. In standalone
mode (DCEN = 0), any data and clock pulses after the 16th falling
edge of SCLK will be ignored and no further serial data transfer
will occur until SYNC is taken high and low again.

SYNC may be taken high after the falling edge of the 16th SCLK
pulse, observing the minimum SCLK falling edge to SYNC
rising edge time, t

.

7

After the end of serial data transfer, data will automatically be
transferred from the input shift register to the input register of
the selected DAC. If SYNC is taken high before the 16th falling
edge of SCLK, the data transfer will be aborted and the DAC
input registers will not be updated.

BIT 15
(MSB)

A1 BUF

GAINA0

D7 D6 D5 D4 D3 D2 D1 D0 XXXX

DATA BITS

Figure 8. AD5307 Input Shift Register Contents

BIT 15
(MSB)

A1 BUF

GAINA0

D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

DATA BITS

Figure 9. AD5317 Input Shift Register Contents

BIT 15
(MSB)

A1 BUF

GAINA0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0D10D11

DATA BITS

Figure 10. AD5327 Input Shift Register Contents

BIT 0
(LSB)

BIT 0
(LSB)

XX

BIT 0
(LSB)

REV. A–14–

AD5307/AD5317/AD5327

When data has been transferred into the input register of a
DAC, the corresponding DAC register and DAC output can be
updated by taking LDAC low. CLR is an active low, asynchro­nous clear that clears the input registers and DAC registers to
all 0s.

Low Power Serial Interface

To minimize the power consumption of the device, the interface
powers up fully only when the device is being written to, i.e., on
the falling edge of SYNC. The SCLK and DIN input buffers
are powered down on the rising edge of SYNC.

Daisy-Chaining

For systems that contain several DACs, or where the user wishes
to read back the DAC contents for diagnostic purposes, the
SDO pin may be used to daisy-chain several devices together
and provide serial readback.

By connecting the DCEN (daisy-chain enable) pin high, the
daisy-chain mode is enabled. It is tied low in the case of stand­alone mode. In daisy-chain mode, the internal gating on SCLK is
disabled. The SCLK is continuously applied to the input shift
register when SYNC is low. If more than 16 clock pulses are
applied, the data ripples out of the shift register and appears on
the SDO line. This data is clocked out on the rising edge of
SCLK and is valid on the falling edge. By connecting this line to
the DIN input on the next DAC in the chain, a multi-DAC
interface is constructed. Sixteen clock pulses are required for
each DAC in the system. Therefore, the total number of clock
cycles must equal 16N, where N is the total number of devices
in the chain. When the serial transfer to all devices is complete,
SYNC should be taken high. This prevents any further data
from being clocked into the input shift register.

A continuous SCLK source may be used if it can be arranged
that SYNC is held low for the correct number of clock cycles.
Alternatively, a burst clock containing the exact number of
clock cycles may be used and SYNC may be taken high some
time later.

When the transfer to all input registers is complete, a common
LDAC signal updates all DAC registers and all analog outputs
are updated simultaneously.

Double-Buffered Interface

The AD5307/AD5317/AD5327 DACs have double-buffered
interfaces consisting of two banks of registers: input registers and
DAC registers. The input registers are connected directly to the
input shift register and the digital code is transferred to the relevant
input register on completion of a valid write sequence. The DAC
registers contain the digital code used by the resistor strings.

Access to the DAC registers is controlled by the LDAC pin.
When the LDAC pin is high, the DAC registers are latched and
the input registers may change state without affecting the contents
of the DAC registers. When LDAC is brought low, however, the
DAC registers become transparent and the contents of the input
registers are transferred to them.

The double-buffered interface is useful if the user requires simulta­neous updating of all DAC outputs. The user may write to three
of the input registers individually and then, by bringing LDAC
low when writing to the remaining DAC input register, all outputs
will update simultaneously.

These parts contain an extra feature whereby a DAC register is
not updated unless its input register has been updated since the
last time LDAC was brought low. Normally, when LDAC is
brought low, the DAC registers are filled with the contents of the
input registers. In the case of the AD5307/AD5317/AD5327,
the part will update the DAC register only if the input register
has been changed since the last time the DAC register was
updated, thereby removing unnecessary digital crosstalk.

Load DAC Input (LDAC)

LDAC transfers data from the input registers to the DAC registers
(and, therefore, updates the outputs). Use of the LDAC function
enables double-buffering of the DAC data, GAIN, and BUF.
There are two LDAC modes:

Synchronous Mode: In this mode, the DAC registers are
updated after new data is read in on the falling edge of the 16th
SCLK pulse. LDAC can be tied permanently low or pulsed as
in Figure 2.

Asynchronous Mode: In this mode, the outputs are not updated
at the same time that the input registers are written to. When
LDAC goes low, the DAC registers are updated with the con­tents of the input register.

POWER-DOWN MODE

The AD5307/AD5317/AD5327 have low power consumption,
typically dissipating 1.2 mW with a 3 V supply and 2.5 mW
with a 5 V supply. Power consumption can be further reduced
when the DACs are not in use by putting them into power­down mode, which is selected by taking the PD pin low.

When the PD pin is high, all DACs work normally with a typical
power consumption of 500 mA at 5 V (400 mA at 3 V). However,
in power-down mode, the supply current falls to 300 nA at 5 V
(90 nA at 3 V) when all DACs are powered down. Not only
does the supply current drop, but the output stage is also inter­nally switched from the output of the amplifier, making it an
open circuit. This has the advantage that the output is three­state while the part is in power-down mode and provides a defined
input condition for whatever is connected to the output of the
DAC amplifier. The output stage is illustrated in Figure 11.

The bias generator, the output amplifiers, the resistor string,
and all other associated linear circuitry are shut down when the
power-down mode is activated. However, the contents of the
registers are unaffected when in power-down. In fact, it is pos­sible to load new data to the input registers and DAC registers
during power-down. The DAC outputs will update as soon as
PD goes high. The time to exit power-down is typically 2.5 ms

= 5 V and 5 ms when VDD = 3 V. This is the time from

for V

DD

the rising edge of PD to when the output voltage deviates from
its power-down voltage. See TPC 18 for a plot.

AMPLIFIER

RESISTOR

STRING DAC

POWER-DOWN

CIRCUITRY

Figure 11. Output Stage during Power-Down

V

OUT

REV. A

–15–

AD5307/AD5317/AD5327

MICROPROCESSOR INTERFACING
ADSP-2101/ADSP-2103 to AD5307/AD5317/AD5327 Interface

Figure 12 shows a serial interface between the AD5307/AD5317/
AD5327 and the ADSP-2101/ADSP-2103. The ADSP-2101/
ADSP-2103 should be set up to operate in the SPORT transmit
alternate framing mode. The ADSP-2101/ADSP-2103 sport
is programmed through the SPORT control register and should
be configured as follows: internal clock operation, active low
framing, 16-bit word length. Transmission is initiated by writing
a word to the Tx register after the SPORT has been enabled.
The data is clocked out on each rising edge of the DSP’s serial
clock and clocked into the AD5307/AD5317/AD5327 on the
falling edge of the DAC’s SCLK.

ADSP-2101/

ADSP-2103*

TFS

DT

SCLK

*ADDITIONAL PINS OMITTED FOR CLARITY

AD5307/
AD5317/

AD5327*

SYNC

DIN

SCLK

Figure 12. ADSP-2101/ADSP-2103 to AD5307/
AD5317/AD5327 Interface

68HC11/68L11 to AD5307/AD5317/AD5327 Interface

Figure 13 shows a serial interface between the AD5307/AD5317/
AD5327 and the 68HC11/68L11 microcontroller. SCK of the
68HC11/68L11 drives the SCLK of the AD5307/AD5317/
AD5327, while the MOSI output drives the serial data line
(DIN) of the DAC. The SYNC signal is derived from a port
line (PC7). The setup conditions for correct operation of this
interface are as follows: the 68HC11/68L11 should be config­ured so that its CPOL bit is a 0 and its CPHA bit is a 1. When
data is being transmitted to the DAC, the SYNC line is taken
low (PC7). When the 68HC11/68L11 is configured as above,
data appearing on the MOSI output is valid on the falling edge
of SCK. Serial data from the 68HC11/68L11 is transmitted in
8-bit bytes with only eight falling clock edges occurring in the
transmit cycle. Data is transmitted MSB first. To load data to the
AD5307/AD5317/AD5327, PC7 is left low after the first eight bits
are transferred, and a second serial write operation is performed
to the DAC; PC7 is taken high at the end of this procedure.

80C51/80L51 to AD5307/AD5317/AD5327 Interface

Figure 14 shows a serial interface between the AD5307/AD5317/
AD5327 and the 80C51/80L51 microcontroller. The setup for
the interface is as follows: TxD of the 80C51/80L51 drives
SCLK of the AD5307/AD5317/AD5327, while RxD drives the
serial data line of the part. The SYNC signal is again derived
from a bit programmable pin on the port. In this case, port line
P3.3 is used. When data is to be transmitted to the AD5307/
AD5317/AD5327, P3.3 is taken low. The 80C51/80L51 trans­mits data only in 8-bit bytes; thus only eight falling clock edges
occur in the transmit cycle. To load data to the DAC, P3.3 is
left low after the first eight bits are transmitted, and a second
write cycle is initiated to transmit the second byte of data. P3.3
is taken high following the completion of this cycle. The 80C51/
80L51 outputs the serial data in a format that has the LSB first.
The AD5307/AD5317/AD5327 requires its data with the MSB
as the first bit received. The 80C51/80L51 transmit routine
should take this into account.

80C51/80L51*

P3.3

TxD

RxD

*ADDITIONAL PINS OMITTED FOR CLARITY

AD5307/
AD5317/

AD5327*

SYNC

SCLK

DIN

Figure 14. 80C51/80L51 to AD5307/AD5317/AD5327
Interface

MICROWIRE to AD5307/AD5317/AD5327 Interface

Figure 15 shows an interface between the AD5307/AD5317/
AD5327 and any MICROWIRE compatible device. Serial data
is shifted out on the falling edge of the serial clock, SK, and is
clocked into the AD5307/AD5317/AD5327 on the rising edge
of SK, which corresponds to the falling edge of the DAC’s SCLK.

MICROWIRE*

CS

SK

SO

AD5307/
AD5317/

AD5327*

SYNC

SCLK

DIN

68HC11/68L11*

PC7

SCK

MOSI

*ADDITIONAL PINS OMITTED FOR CLARITY

AD5307/
AD5317/

AD5327*

SYNC

SCLK

DIN

Figure 13. 68HC11/68L11 to AD5307/AD5317/
AD5327 Interface

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 15. MICROWIRE to AD5307/AD5317/AD5327
Interface

REV. A–16–

AD5307/AD5317/AD5327

APPLICATIONS
Typical Application Circuit

The AD5307/AD5317/AD5327 can be used with a wide range
of reference voltages where the devices offer full, one-quadrant
multiplying capability over a reference range of 0.25 V to V

DD

.
More typically, these devices are used with a fixed, precision
reference voltage. Suitable references for 5 V operation are the
AD780 and REF192 (2.5 V references). For 2.5 V operation, a
suitable external reference would be the AD589, a 1.23 V band
gap reference. Figure 16 shows a typical setup for the AD5307/
AD5317/AD5327 when using an external reference.

= 2.5V TO 5.5V

V

DD

V

IN

V

OUT

EXT
REF

AD780/REF192
WITH VDD = 5V

OR AD589 WITH

= 2.5V

V

DD

0.1␮F

1␮F

SERIAL

INTERFACE

10␮F

V

AB

REF

V

REF

AD5307/AD5317/

SCLK

DIN

SYNC

CD

AD5327

GND

V

V

A

OUT

B

OUT

V

C

OUT

V

D

OUT

Figure 16. AD5307/AD5317/AD5327 Using a 2.5 V
External Reference

Driving VDD from the Reference Voltage

If an output range of 0 V to VDD is required when the reference
inputs are configured as unbuffered, the simplest solution is to
connect the reference input to V

. As this supply may be noisy

DD

and not very accurate, the AD5307/AD5317/AD5327 may be
powered from the reference voltage, for example, using a 5 V
reference such as the REF195. The REF195 will output a steady
supply voltage for the AD5307/AD5317/AD5327. The typical
current required from the REF195 is 500 mA supply current and
ª 112 mA into the reference inputs (if unbuffered). This is with
no load on the DAC outputs. When the DAC outputs are loaded,
the REF195 also needs to supply the current to the loads. The
total current required (with a 10 kW load on each output) is

612 4 5 10 2 6mAVk mA+

()

=/.W

The load regulation of the REF195 is typically 2 ppm/mA, which
results in an error of 5.2 ppm (26 mV) for the 2.6 mA current
drawn from it. This corresponds to a 0.0013 LSB error at eight
bits and 0.021 LSB error at 12 bits.

Bipolar Operation Using the AD5307/AD5317/AD5327

The AD5307/AD5317/AD5327 have been designed for single­supply operation, but a bipolar output range is also possible
using the circuit in Figure 17. This circuit will give an output
voltage range of ± 5 V. Rail-to-rail operation at the amplifier
output is achievable using an AD820 or an OP295 as the output
amplifier.

The output voltage for any input code can be calculated as
follows:

È

REFIN D R R

()

OUT

Í

=

Í

R REFIN R R

121–/

Î

V

N

¥

¥+

212

()

¥

()

˘
˙
˙

˚

where:

D is the decimal equivalent of the code loaded to the DAC.
N is the DAC resolution.
REFIN is the reference voltage input.

with
REFIN = 5 V, R1 = R2 = 10 kW:

5V

V

DD

AD5327

AB

CD

SCLK

SERIAL

INTERFACE

N

R1

10k⍀

V

OUT

V

OUT

V

OUT

V

OUT

SYNC

R2

10k⍀

+5V

A

–5V

B

C

D

AD820/
OP295

ⴞ5V

V

IN

REF195

V

GND

6V TO 16V

10␮F

OUT

VDV

=¥

10 2 5/–

()

OUT

0.1␮F

AD5307/AD5317/

V

1␮F

REF

V

REF

GND

DIN

Figure 17. Bipolar Operation with the AD5307/
AD5317/AD5327

REV. A

–17–

AD5307/AD5317/AD5327

Opto-Isolated Interface for Process Control Applications

The AD5307/AD5317/AD5327 have a versatile 3-wire serial
interface, making them ideal for generating accurate voltages in
process control and industrial applications. Due to noise, safety
requirements, or distance, it may be necessary to isolate the
AD5307/AD5317/AD5327 from the controller. This can easily
be achieved by using opto-isolators that will provide isolation in
excess of 3 kV. The actual data rate achieved may be limited by
the type of optocouplers chosen. The serial loading structure of
the AD5307/AD5317/AD5327 makes them ideally suited for use
in opto-isolated applications. Figure 18 shows an opto-isolated
interface to the AD5307/AD5317/AD5327 where DIN, SCLK,
and SYNC are driven from optocouplers. The power supply to the
part also needs to be isolated. This is done by using a transformer.
On the DAC side of the transformer, a 5 V regulator provides
the 5 V supply required for the AD5307/AD5317/AD5327.

5V

POWER

SCLK

SYNC

DIN

10k⍀

10k⍀

10k⍀

REGULATOR

V

DD

SCLK

V

DD

SYNC

V

DD

DIN

DCEN

AD5307

V

DD

GND

10␮F

0.1␮F

V

AB

REF

V

CD

REF

A

V

OUT

V

B

OUT

V

C

OUT

V

D

OUT

Figure 18. AD5307 in an Opto-Isolated Interface

Decoding Multiple AD5307/AD5317/AD5327s

The SYNC pin on the AD5307/AD5317/AD5327 can be used
in applications to decode a number of DACs. In this application,
all the DACs in the system receive the same serial clock and
serial data, but only the SYNC to one of the devices will be
active at any one time, allowing access to four channels in this
16-channel system. The 74HC139 is used as a 2-to-4 line decoder
to address any of the DACs in the system. To prevent timing
errors from occurring, the enable input should be brought to
its inactive state while the coded address inputs are changing
state. Figure 19 shows a diagram of a typical setup for decoding
multiple AD5307 devices in a system.

AD5307

V

SCLK

DIN

ENABLE

CODED

ADDRESS

1G

1A

1B

V

DD

V

CC

74HC139

DGND

1Y0

1Y1

1Y2
1Y3

SYNC

DIN
SCLK

SYNC

DIN
SCLK

SYNC

DIN
SCLK

AD5307

AD5307

A

OUT

V

B

OUT

V

C

OUT

V

D

OUT

V

A

OUT

V

B

OUT

V

C

OUT

V

D

OUT

V

A

OUT

V

B

OUT

V

C

OUT

V

D

OUT

AD5307

V

A

OUT

V

B

SYNC

DIN
SCLK

OUT

V

C

OUT

V

D

OUT

Figure 19. Decoding Multiple AD5307 Devices in a System

AD5307/AD5317/AD5327 as a Digitally Programmable Window Detector

A digitally programmable upper/lower limit detector using two
of the DACs in the AD5307/AD5317/AD5327 is shown in
Figure 20. The upper and lower limits for the test are loaded to
DACs A and B, which, in turn, set the limits on the CMP04. If
the signal at the V

input is not within the programmed window,

IN

an LED will indicate the fail condition. Similarly, DACs C and D
can be used for window detection on a second V

V

REF

SYNC

DIN

SCLK

5V

0.1␮F 10␮F

V

AB

REF

V

CD

REF

AD5307/AD5317/

AD5327

SYNC

DIN

SCLK

GND

V

IN

V

DD

A

V

OUT

1/2

CMP04

B

V

OUT

signal.

IN

1k⍀

FAIL

PASS/FAIL

1/6 74HC05

1k⍀

PASS

Figure 20. Window Detection

REV. A–18–

AD5307/AD5317/AD5327

Daisy-Chaining

For systems that contain several DACs, or where the user wishes
to read back the DAC contents for diagnostic purposes, the
SDO pin may be used to daisy-chain several devices together
and provide serial readback. Figure 3 shows the timing diagram
for daisy-chain applications. The daisy-chain mode is enabled by
connecting DCEN high. See Figure 21.

68HC11*

MOSI

SCK

PC7

PC6

MISO

DIN

SCLK

SYNC

LDAC

SCLK

SYNC

LDAC

SCLK

SYNC

LDAC

AD5307*

DCEN

SDO

DIN

AD5307*

DCEN

SDO

DIN

AD5307*

DCEN

SDO

Power Supply Bypassing and Grounding

In any circuit where accuracy is important, careful consideration
of the power supply and ground return layout helps to ensure
the rated performance. The printed circuit board on which the
AD5307/AD5317/AD5327 is mounted should be designed so
that the analog and digital sections are separated and confined
to certain areas of the board. If the AD5307/AD5317/AD5327
is in a system where multiple devices require an AGND-to-DGND
connection, the connection should be made at one point only.
The star ground point should be established as close as possible
to the device. The AD5307/AD5317/AD5327 should have
ample supply bypassing of 10 mF in parallel with 0.1 mF on the
supply located as close to the package as possible, ideally right
up against the device. The 10 mF capacitors are the tantalum
bead type. The 0.1 mF capacitor should have low effective series
resistance (ESR) and effective series inductance (ESI), like the
common ceramic types that provide a low impedance path to
ground at high frequencies to handle transient currents due to
internal logic switching.

The power supply lines of the AD5307/AD5317/AD5327 should
use as large a trace as possible to provide low impedance paths
and reduce the effects of glitches on the power supply line. Fast
switching signals such as clocks should be shielded with digital
ground to avoid radiating noise to other parts of the board, and
should never be run near the reference inputs. Avoid crossover
of digital and analog signals. Traces on opposite sides of the
board should run at right angles to each other. This reduces the
effects of feedthrough through the board. A microstrip technique is
by far the best, but is not always possible with a double-sided
board. In this technique, the component side of the board is
dedicated to ground plane while signal traces are placed on the
solder side.

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 21. AD5307 in Daisy-Chain Mode

REV. A

–19–

AD5307/AD5317/AD5327

Table II. Overview of AD53xx Serial Devices

No. of Settling

Part No. Resolution DACs DNL Interface Time (␮s) Package Pins

SINGLES

AD5300 8 1 ± 0.25 SPI 4 SOT-23, MSOP 6, 8
AD5310 10 1 ± 0.5 SPI 6 SOT-23, MSOP 6, 8
AD5320 12 1 ± 1.0 SPI 8 SOT-23, MSOP 6, 8

AD5301 8 1 ± 0.25 2-Wire 6 SOT-23, MSOP 6, 8
AD5311 10 1 ± 0.5 2-Wire 7 SOT-23, MSOP 6, 8
AD5321 12 1 ± 1.0 2-Wire 8 SOT-23, MSOP 6, 8

DUALS

AD5302 8 2 ± 0.25 SPI 6 MSOP 8
AD5312 10 2 ± 0.5 SPI 7 MSOP 8
AD5322 12 2 ± 1.0 SPI 8 MSOP 8

AD5303 8 2 ± 0.25 SPI 6 TSSOP 16
AD5313 10 2 ± 0.5 SPI 7 TSSOP 16
AD5323 12 2 ± 1.0 SPI 8 TSSOP 16

QUADS

AD5304 8 4 ± 0.25 SPI 6 MSOP 10
AD5314 10 4 ± 0.5 SPI 7 MSOP 10
AD5324 12 4 ± 1.0 SPI 8 MSOP 10

AD5305 8 4 ± 0.25 2-Wire 6 MSOP 10
AD5315 10 4 ± 0.5 2-Wire 7 MSOP 10
AD5325 12 4 ± 1.0 2-Wire 8 MSOP 10

AD5306 8 4 ± 0.25 2-Wire 6 TSSOP 16
AD5316 10 4 ± 0.5 2-Wire 7 TSSOP 16
AD5326 12 4 ± 1.0 2-Wire 8 TSSOP 16

AD5307 8 4 ± 0.25 SPI 6 TSSOP 16
AD5317 10 4 ± 0.5 SPI 7 TSSOP 16
AD5327 12 4 ± 1.0 SPI 8 TSSOP 16

OCTALS

AD5308 8 8 ± 0.25 SPI 6 TSSOP 16
AD5318 10 8 ± 0.5 SPI 7 TSSOP 16
AD5328 12 8 ± 1.0 SPI 8 TSSOP 16

Visit www.analog.com/support/standard_linear/selection_guides/AD53xx.html for more information.

Table III. Overview of AD53xx Parallel Devices

Part No. Resolution DNL V
SINGLES BUF GAIN HBEN CLR

AD5330 8 ± 0.25 1 6 ✓✓ ✓ TSSOP 20
AD5331 10 ± 0.5 1 7 ✓✓TSSOP 20
AD5340 12 ± 1.0 1 8 ✓✓ ✓ TSSOP 24
AD5341 12 ± 1.0 1 8 ✓✓ ✓ ✓ TSSOP 20

DUALS

AD5332 8 ± 0.25 2 6 ✓ TSSOP 20
AD5333 10 ± 0.5 2 7 ✓✓ ✓ TSSOP 24
AD5342 12 ± 1.0 2 8 ✓✓ ✓ TSSOP 28
AD5343 12 ± 1.0 1 8 ✓✓ TSSOP 20

QUADS

AD5334 8 ± 0.25 2 6 ✓✓TSSOP 24
AD5335 10 ± 0.5 2 7 ✓✓ TSSOP 24
AD5336 10 ± 0.5 4 7 ✓✓TSSOP 28
AD5344 12 ± 1.0 4 8 TSSOP 28

Pins Settling Time (␮s) Additional Pin Functions Package Pins

REF

REV. A–20–

AD5307/AD5317/AD5327

OUTLINE DIMENSIONS

16-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-16)

Dimensions shown in millimeters

5.10

5.00

4.90

0.15

0.05

4.50

4.40

4.30

PIN 1

16

0.65

BSC

COPLANARITY

COMPLIANT TO JEDEC STANDARDS MO-153AB

0.10

0.30

0.19

9

81

1.20
MAX

6.40
BSC

SEATING

PLANE

0.20

0.09

0.75

8ⴗ
0ⴗ

0.60

0.45

Revision History

Location Page

8/03—Data Sheet changed from REV. 0 to REV. A.

Added A Version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal

Changes to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Changes to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Changes to TPC 21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Added OCTALS section to Table II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

REV. A

–21–

–22–

–23–

C02067–0–8/03(A)

–24–