Datasheet AD53042 Datasheet (Analog Devices)

a

2.8V

0.2V

3.0V

0V

0V

3.0V

MIN. POSITIVE

INPUT PULSE

MIN. NEGATIVE

INPUT PULSE

High Speed Window Comparator

AD53042

FEATURES
–2 V to +7 V Input Voltage Range
Low V

Bias Current (<100 nA)

IN

Up to 5 V/ns Input Signal Tracking
Low Dispersion of ⴞ100 ps
28-Lead PLCC Package

APPLICATIONS
Automatic Test Equipment
Semiconductor Test Systems
Board Test Systems

PRODUCT DESCRIPTION

The AD53042 is an ultrahigh speed window comparator
with latch. It uses a high speed monolithic process to provide
high dc accuracy without sacrificing input voltage range.
On-chip connection of the common input eliminates the
contributions of a second bonding pad and package pin to
the input capacitance, resulting in a maximum input
capacitance of 2 pF.

The AD53042 employs a high precision differential input
stage with a common mode range of 9 V. Its complementary
digital outputs are fully ECL-compatible. The output stage is

capable of driving a 50 Ω line terminated to –2 V. The device

also provides a latch function, allowing operation in track-hold
mode and can also be used to generate hysteresis.

FUNCTIONAL BLOCK DIAGRAM

GND

GND

V

A

NC

V

IN

NC

V

B

GND

NOTE:
NOT THE ACTUAL PHYSICAL LAYOUT OF DEVICE.
NC = NO CONNECTION INSIDE PACKAGE.

LEA

LATCH/OUTPUT

AD53042

LATCH/OUTPUT

LEB

LEA NC

A

B

LEB

NC

+V

S

–V

NC GNDGND

Figure 1. Typical Application Circuit

NC

GND

GND

QA

QA

DGND

QB

QB
GND

S

REV. A

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reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
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Fax: [phone] © Analog Devices, Inc., 1999

(All specifications apply with TC = 40ⴗC to 100ⴗC and +VS = +7.75 V to +11.5 V;

AD53042–SPECIFICATIONS

–VS = –3.95 V to –7.7 V unless otherwise noted.)

Parameter Min Typ Max Units Test Conditions

POWER SUPPLIES

Positive Supply Currents 65 mA No Load
Negative Supply Current –85 mA No Load
Power Dissipation 1.19 W No Load, +VS = +10 V, –VS = –5.2 V

DC INPUT CHARACTERISTICS

Offset Voltage (V

Bias Current –0.5 <0.1 0.5 µAV

V

IN

, V

Bias Current –20 20 µAV

V

A

B

Capacitance V
Voltage Range (V
Differential Voltage (V

) –10 10 mV CMV = 0 V

OS

, VA, V

IN

B

)–V

CM

)9V

DIFF

+ 2.7 +VS – 2.5 V

S

2pF

= 0 V

IN

= 0 V

IN

Nonlinearity –5 5 mV See Note 1
VA/VB Interaction 0.1 mV/V

BIAS CURRENT

Change vs. Comparator State –1 1 µA
Nonlinearity –2 2 µA
Tempco ±0.1 µA/°C

LATCH ENABLE INPUTS

Common-Mode Range –2 1 V
Differential Voltage 0.4 3 V
Logic “1” Current (L
Logic “0” Current (L

) 200 µA

IH

) –10 µA

IL

DIGITAL OUTPUTS

Logic “1” Voltage (V
Logic “0” Voltage (V

) –0.98 V Q or Q, 50 Ω to –2 V

OH

) –1.5 V Q or Q, 50 Ω to –2 V

OL

SWITCHING PERFORMANCE

Propagation Delay

Input to Output 2 ns V

= 2 V p-p, t

IN

PDR

, t

, Figure 1, Note 2

PDF

Latch Enable to Output 1.2 ns
Part-to-Part Skew 1 ns

Change vs. Temperature ±1 ps/°C

DISPERSION

5 V p-p Input (All Edges) ±100 ps 10%, 90% 0.5 V/ns, 3 V/ns
5 V p-p Input (All Edges) ±175 ps 10%, 90% 5 V/ns
V Slew = 1 V/ns (All Edges) ±50 ps 10%, 90% 3 V, 5 V
V Slew = 1 V/ns (All Edges) ±50 ps 20%, 80% 1 V

Minimum Pulsewidth <1 ns See Note 3
Edge Interaction <200 ps See Note 4
Duty Ratio <100 ps See Note 5
Comparator Interaction <100 ps

NOTES

1

Defined as change in VOS from –VS + 2.95 V to +VS – 2.75 V (throughout the range) after VA and VB are corrected for gain and offset using 0 V and 5 V.

2

Propagation delay is measured from the input threshold crossing at the 50% point of a 0 V to 5 V input to the output Q and Q crossing.

3

The minimum input pulsewidth that will maintain a 600 mV ECL swing on the output. The input is a 0 V to 3 V signal with a 3 V/ns rise and fall times. The input
pulsewidth is measured between the 2.8 V point of a positive input pulse and the 0.2 V of a negative input pulse. See Figure 2.

4

Maximum Change in propagation delay as the input pulse is reduced from 50 ns to a 2 ns pulsewidth. 0 V to 3 V swing with 3 V/ns rise/fall time and 25% duty cycle.

5

Maximum Change in propagation delay as the input pulse is reduced from 99% to a 1% duty cycle. 0 V to 3 V swing with 3 V/ns rise/fall time and 50 ns to 4.95 µs
pulsewidth, period = 5 µs.

Specifications subject to change without notice.

–2–

REV. A

AD53042

7
8

9
10
11

5

6

28 27 261234

121314 15 16 17 18

TOP VIEW

(Not to Scale)

PIN 1
IDENTIFIER

21

22

23

24

25

19

20

GND

VINA

NC

VINAB

NC

GND

QA

QA
DGND

QB

NC = NO CONNECT

AD53042

VINB

GND

QB
GND

VNEG

GND

LEB

LEB

NC

NC

GND

GND

LEA

NC

VPOS

LEA

NC

GND

WARNING!

ESD SENSITIVE DEVICE

V

A

V

B

V

IN

QA

QA

QB

QB

LEA, LEB

LEA, LEB

~1.2ns

ABSOLUTE MAXIMUM RATINGS*

Power Supply Voltage

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +12 V

+V

S

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –8 V

–V

S

to –VS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +17 V

+V

S

Inputs

, VA, VB . . . . . . . . . . . . . . . +VS – 13.5 V, –VS + 13.7 V

V

IN

LEA, LEA, LEB, LEB . . . . . . . . . +V

– 14 V, –VS +10 V

S

Currents

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 mA

+V

S

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .–75 mA

–V

S

QA, QA, QB, QB . . . . . . . . . . . . . . . . . . –40 mA to +2 mA

Environmental

Operating Temperature (Ambient) . . . . . . . . 0°C to +70°C

Storage Temperature . . . . . . . . . . . . . . . . –65°C to +125°C

Lead Temperature (Soldering, 20 sec) . . . . . . . . . . .+300°C

*Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Absolute maximum limits apply
individually, not in combination. Exposure to absolute maximum rating condi­tions for extended periods may affect device reliability.

The device must suffer no reliability degradation if any supply pin is either shorted
to ground or left floating for an indefinite periods of time during normal operation.

ORDERING GUIDE

Shipment Method,
Quantity

Package Per Shipping Package

Model Description Container Option

AD53042KRP 28-Lead PLCC Tube, 36 Pieces P-28A

PIN CONFIGURATION

V

A

V

B

V

IN

QA

QA

QB

QB

t

PDR t

t

PDR

PDF

t

PDF

Figure 2. Timing Diagram I

Figure 3. Timing Diagram II

If either of the latch enables, LEA or LEB are low, the output
follows the input. If LEA or LEB are high, the comparator out­puts will be latched and they won’t change.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD53042 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

–3–

REV. A

AD53042

0.048 (1.21)

0.042 (1.07)

0.020
(0.50)

MAX

(3) PLACES

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

28-Lead Plastic Leaded Chip Carrier

(P-28A)

0.180 (4.57)

0.050
(1.27)
BSC

0.165 (4.19)

0.110 (2.79)

0.085 (2.16)

0.048 (1.21)

0.042 (1.07)

4

5

11

12

0.456 (11.58)

0.450 (11.43)

0.495 (12.57)

0.485 (12.32)

PIN 1

IDENTIFIER

TOP VIEW

(PINS DOWN)

0.056 (1.42)

0.042 (1.07)

26

25

19

18

SQ

SQ

0.025 (0.63)

0.015 (0.38)

0.021 (0.53)

0.013 (0.33)

0.032 (0.81)

0.026 (0.66)

0.040 (1.01)

0.025 (0.64)

C3120a–0–5/99

0.430 (10.92)

0.390 (9.91)

–4–

PRINTED IN U.S.A.

REV. A