Datasheet AD5301, AD5321, AD5311 Datasheet (Analog Devices)

+2.5 V to +5.5 V, 120 ␮A, 2-Wire Interface,

a

FEATURES
AD5301: Buffered Voltage Output 8-Bit DAC
AD5311: Buffered Voltage Output 10-Bit DAC
AD5321: Buffered Voltage Output 12-Bit DAC
6-Lead SOT-23 and 8-Lead ␮SOIC Packages
Micropower Operation: 120 ␮A @ 3 V
2-Wire (I
Data Readback Capability
+2.5 V to +5.5 V Power Supply
Guaranteed Monotonic By Design Over All Codes
Power-Down to 50 nA @ 3 V
Reference Derived from Power Supply
Power-On-Reset to Zero Volts
On-Chip Rail-to-Rail Output Buffer Amplifier
Three Power-Down Functions

APPLICATIONS
Portable Battery Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Programmable Attenuators

2C®

Compatible) Serial Interface

Voltage Output 8-/10-/12-Bit DACs

AD5301/AD5311/AD5321*

GENERAL DESCRIPTION

The AD5301/AD5311/AD5321 are single 8-, 10- and 12-bit
buffered voltage-output DACs that operate from a single +2.5 V

to +5.5 V supply consuming 120 µA at 3 V. The on-chip output

amplifier allows rail-to-rail output swing with a slew rate of

0.7 V/µs. It uses a 2-wire (I

operates at clock rates up to 400 kHz. Multiple devices can
share the same bus.

The reference for the DAC is derived from the power supply
inputs and thus gives the widest dynamic output range. These
parts incorporate a power-on-reset circuit, which ensures that
the DAC output powers-up to zero volts and remains there until
a valid write takes place. The parts contain a power-down feature
which reduces the current consumption of the device to 50 nA
at 3 V and provides software-selectable output loads while in
power-down mode.

The low power consumption in normal operation make these
DACs ideally suited to portable battery-operated equipment.
The power consumption is 0.75 mW at 5 V, 0.36 mW at 3 V

reducing to 1 µW in all power-down modes.

2

C compatible) serial interface that

FUNCTIONAL BLOCK DIAGRAM

SCL

SDA

A0

A1*

I2C is a registered trademark of Philips Corporation.
*Protected by U.S. Patent No. 5684481, other patent pending.

INTERFACE

LOGIC

POWER-ON

RESET

GND

*AVAILABLE ON 8-LEAD VERSION ONLY

REGISTER

DAC

V

DD

REF

8-/10-/12-BIT
DAC

AD5301/AD5311/AD5321

BUFFER

POWER-DOWN

LOGIC

RESISTOR
NETWORK

PD*

V

OUT

REV. 0

Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] World Wide Web Site: http://www.analog.com
Fax: [phone] © Analog Devices, Inc., 1999

AD5301/AD5311/AD5321–SPECIFICATIONS

CL = 200 pF to GND; All specifications T

Parameter

DC PERFORMANCE

1

3, 4

to T

MIN

unless otherwise noted.)

MAX

B Version

2

Min Typ Max Units Conditions/Comments

(VDD = +2.5 V to +5.5 V; RL = 2 k⍀ to GND;

AD5301

Resolution 8 Bits

Relative Accuracy ±0.15 ±1 LSB
Differential Nonlinearity ±0.02 ±0.25 LSB Guaranteed Monotonic by Design Over All Codes

AD5311

Resolution 10 Bits

Relative Accuracy ±0.5 ±4 LSB
Differential Nonlinearity ±0.05 ±0.5 LSB Guaranteed Monotonic by Design Over All Codes

AD5321

Resolution 12 Bits

Relative Accuracy ±2 ±16 LSB
Differential Nonlinearity ±0.3 ±0.8 LSB Guaranteed Monotonic by Design Over All Codes

Zero Code Error +5 +20 mV All Zeros Loaded to DAC, See Figure 9

Full-Scale Error ±0.15 ±1.25 % of FSR All Ones Loaded to DAC, See Figure 9
Gain Error ±0.15 ±1 % of FSR

Zero Code Error Drift
Gain Error Drift

OUTPUT CHARACTERISTICS

5

5

5

–20 µV/°C
–5 ppm of FSR/°C

Minimum Output Voltage 0.001 V min This is a measure of the minimum and maximum drive
Maximum Output Voltage VDD– 0.001 V max capability of the output amplifier.

DC Output Impedance 1 Ω

Short Circuit Current 50 mA VDD = +5 V

20 mA VDD = +3 V

Power-Up Time 2.5 µs Coming Out of Power-Down Mode. V

6 µs Coming Out of Power-Down Mode. V

LOGIC INPUTS (A0, A1, PD)

5

= +5␣ V

DD

= +3␣ V

DD

Input Current ±1 µA

VIL, Input Low Voltage 0.8 V V

0.6 V V

= +5 V ± 10%

DD

= +3 V ± 10%

DD

0.5 V VDD = +2.5 V

VIH, Input High Voltage 2.4 V V

2.1 V V

= +5 V ± 10%

DD

= +3 V ± 10%

DD

2.0 V VDD = +2.5 V

Pin Capacitance 3 pF

LOGIC INPUTS (SCL, SDA)

VIH, Input High Voltage 0.7 V
VIL, Input Low Voltage –0.3 0.3 V
I

, Input Leakage Current ±1 µAV

IN

V

, Input Hysteresis 0.05 V

HYST

CIN, Input Capacitance 6 pF
Glitch Rejection

6

LOGIC OUTPUT (SDA)

VOL, Output Low Voltage 0.4 V I

5

DD

DD

VDD + 0.3 V

DD

V

= 0 V to V

IN

DD

V

50 ns Pulsewidth of Spike Suppressed

5

= 3 mA

0.6 V I

SINK

SINK

= 6 mA

Three-State Leakage Current ±1 µA

Three-State Output Capacitance 6 pF

POWER REQUIREMENTS

V

DD

2.5 5.5 V IDD Specification Is Valid for All DAC Codes

IDD (Normal Mode) DAC Active and Excluding Load Current

V

= +4.5 V to +5.5 V 150 250 µAV

DD

V

= +2.5 V to +3.6 V 120 220 µAV

DD

= VDD and VIL = GND

IH

= VDD and VIL = GND

IH

IDD (Power-Down Mode)

V

= +4.5 V to +5.5 V 0.2 1 µAV

DD

V

= +2.5 V to +3.6 V 0.05 1 µAV

DD

NOTES

1

See Terminology.

2

Temperature ranges are as follows: B Version: –40°C to +105°C.

3

DC specifications tested with the outputs unloaded.

4

Linearity is tested using a reduced code range: AD5301 (Code 7 to 250); AD5311 (Code 28 to 1000); AD5321 (Code 112 to 4000).

5

Guaranteed by Design and Characterization, not production tested.

6

Input filtering on both the SCL and SDA inputs suppress noise spikes that are less than 50 ns.

= VDD and VIL = GND

IH

= VDD and VIL = GND

IH

Specifications subject to change without notice.

REV. 0–2–

AD5301/AD5311/AD5321

(VDD = +2.5 V to +5.5 V; R

AC CHARACTERISTICS

Parameter

2

1

otherwise noted.)

B Version
Min Typ Max Units Conditions/Comments

Output Voltage Settling Time V

= 2 kΩ to GND; C

L

3

= 200 pF to GND; All specifications T

L

= +5 V

DD

MIN

to T

MAX

unless

AD5301 6 8 µs 1/4 Scale to 3/4 Scale Change (40 Hex to C0 Hex)
AD5311 7 9 µs 1/4 Scale to 3/4 Scale Change (100 Hex to 300 Hex)
AD5321 8 10 µs 1/4 Scale to 3/4 Scale Change (400 Hex to C00 Hex)

Slew Rate 0.7 V/µs

Major-Code Change Glitch Impulse 12 nV-s 1 LSB Change Around Major Carry
Digital Feedthrough 0.3 nV-s

NOTES

1

See Terminology

2

Guaranteed by design and characterization, not production tested.

3

Temperature ranges are as follows: B Version: –40°C to +105°C.

Specifications subject to change without notice.

1

TIMING CHARACTERISTICS

Limit at T

MIN

, T

MAX

(VDD = +2.5 V to +5.5 V. All specifications T

MIN

to T

unless otherwise noted.)

MAX

Parameter2(B Version) Units Conditions/Comments

f
t
t
t
t
t
t

SCL

1

2

3

4

5

3

6

400 kHz max SCL Clock Frequency

2.5 µs min SCL Cycle Time

0.6 µs min t

1.3 µs min t

0.6 µs min t

100 ns min t

0.9 µs max t

, SCL High Time

HIGH

, SCL Low Time

LOW

, Start/Repeated Start Condition Hold Time

HD,STA

, Data Setup Time

SU,DAT

, Data Hold Time

HD,DAT

0 µs min

t

7

t

8

t

9

t

10

0.6 µs min t

0.6 µs min t

1.3 µs min t

300 ns max tR, Rise Time of Both SCL and SDA when Receiving

, Setup Time for Repeated Start

SU,STA

, Stop Condition Setup Time

SU,STO

, Bus Free Time Between a STOP Condition and a START Condition

BUF

0 ns min May be CMOS Driven

t

11

C

b

NOTES

1

See Figure 1.

2

Guaranteed by design and characterization, not production tested.

3

A master device must provide a hold time of at least 300 ns for the SDA signal (referred to the V
SCL’s falling edge.

4

Cb is the total capacitance of one bus line in pF. tR and tF measured between 0.3 VDD and 0.7 VDD.

Specifications subject to change without notice.

250 ns max tF, Fall Time of SDA when Receiving
300 ns max t
20 + 0.1C

4

b

ns min

, Fall Time of Both SCL and SDA when Transmitting

F

400 pF max Capacitive Load for Each Bus Line

of the SCL signal) in order to bridge the undefined region of

IH MIN

REV. 0

–3–

AD5301/AD5311/AD5321

WARNING!

ESD SENSITIVE DEVICE

SDA

SCL

t

9

t

4

START

CONDITION

t

3

t

10

t

6

t

t

11

2

t

5

REPEATED
CONDITION

t

7

START

t

4

t

1

t

8

STOP

CONDITION

Figure 1. 2-Wire Serial Interface Timing Diagram

ABSOLUTE MAXIMUM RATINGS

(T

= +25°C unless otherwise noted)

A

1, 2

VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V

SCL, SDA to GND . . . . . . . . . . . . . . . . –0.3 V to V

PD, A1, A0 to GND . . . . . . . . . . . . . . . –0.3 V to V

to GND . . . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V

V

OUT

+ 0.3 V

DD

+ 0.3 V

DD

Operating Temperature Range

Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +105°C

Storage Temperature Range . . . . . . . . . . . . . –65°C to +150°C

Junction Temperature (T

max) . . . . . . . . . . . . . . . . . . .+150°C

J

SOT-23 Package

Power Dissipation . . . . . . . . . . . . . . . . . . . (T

max – T

J

)/θ

A

µSOIC Package

Power Dissipation . . . . . . . . . . . . . . . . . . . (T

max – T

J

θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 206°C/W

Lead Temperature, Soldering

Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . +215°C

Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . +220°C

NOTES

1

Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute maximum rating condi­tions for extended periods may affect device reliability.

2

Transient currents of up to 100 mA will not cause SCR latch-up.

JA

θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 229.6°C/W

ORDERING GUIDE

Temperature Package Package Branding

Model Range Description Option Information

AD5301BRT –40°C to +105°C SOT-23 RT-6 D8B
AD5301BRM –40°C to +105°C µSOIC RM-8 D8B
AD5311BRT –40°C to +105°C SOT-23 RT-6 D9B
AD5311BRM –40°C to +105°C µSOIC RM-8 D9B
AD5321BRT –40°C to +105°C SOT-23 RT-6 DAB
AD5321BRM –40°C to +105°C µSOIC RM-8 DAB

)/θ

A

JA

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD5301/AD5311/AD5321 features proprietary ESD protection circuitry, perma nent
damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper
ESD precautions are recommended to avoid performance degradation or loss of functionality.

–4–

REV. 0

AD5301/AD5311/AD5321

PIN FUNCTION DESCRIPTION

␮SOIC SOT-23
Pin No. Pin No. Mnemonic Function

16V

DD

2 5 A0 Address Input. Sets the Least Significant Bit of the 7-bit slave address.
3 N/A A1 Address Input. Sets the 2nd Least Significant Bit of the 7-bit slave address.
44V

OUT

5 N/A PD Active low control input that acts as a hardware power-down option. This pin overrides any

6 3 SCL Serial Clock Line. This is used in conjunction with the SDA line to clock data into the 16-bit

7 2 SDA Serial Data Line. This is used in conjunction with the SCL line to clock data into the 16-bit

8 1 GND Ground reference point for all circuitry on the part.

Power Supply Input. These parts can be operated from +2.5 V to +5.5 V and the supply

should be decoupled with a 10 µF in parallel with a 0.1 µF capacitor to GND.

Buffered analog output voltage from the DAC. The output amplifier has rail-to-rail operation.

software power-down option. The DAC output goes three-state and the current consumption
of the part drops to 50 nA @ 3 V (200 nA @ 5 V).

input shift register. Clock rates of up to 400 kbit/s can be accommodated in the I

2

C compat-

ible interface. SCL may be CMOS/TTL driven.

input shift register during the write cycle and used to read back one or two bytes of data
(one byte for the AD5301, two bytes for the AD5311/AD5321) during the read cycle. It is
a bidirectional open-drain data line that should be pulled to the supply with an external
pull-up resistor. If not used in readback mode, SDA may be CMOS/TTL driven.

PIN CONFIGURATIONS

6-Lead SOT-23 8-Lead ␮SOIC

(RT-6) (RM-8)

AD5301/AD5311/AD5321 AD5301/AD5311/AD5321

GND

SDA
SCL

1

TOP VIEW

2

(Not to Scale)

3

V

6

DD

5

A0

4

V

OUT

V

V

OUT

DD

A0
A1

1

2

TOP VIEW

(Not to Scale)

3

4

8

GND

7

SDA

6

SCL

5

PD

REV. 0

–5–

AD5301/AD5311/AD5321

TERMINOLOGY
RELATIVE ACCURACY

For the DAC, Relative Accuracy or Integral Nonlinearity (INL)
is a measure of the maximum deviation, in LSBs, from a straight
line passing through the actual endpoints of the DAC transfer
function. Typical INL vs. Code plots can be seen in Figures 2
to 4.

DIFFERENTIAL NONLINEARITY

Differential Nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two

adjacent codes. A specified differential nonlinearity of ±1 LSB

maximum ensures monotonicity. These DACs are guaranteed
monotonic by design over all codes. Typical DNL vs. Code
plots can be seen in Figures 5 to 7.

ZERO CODE ERROR

Zero Code Error is a measure of the output error when zero
code (00H) is loaded to the DAC register. Ideally, the output
should be 0 V. The Zero Code Error of the AD5301/AD5311/
AD5321 is always positive because the output of the DAC can­not go below 0 V. It is due to a combination of the offset errors
in the DAC and output amplifier. It is expressed in mV, see
Figure 9.

FULL-SCALE ERROR

Full-Scale Error is a measure of the output error when full scale
is loaded to the DAC register. Ideally, the output should be V
– 1 LSB. Full-scale error is expressed in percent of FSR (full­scale range). A plot can be seen in Figure 9.

DD

GAIN ERROR

This is a measure of the span error of the DAC. It is the devia­tion in slope of the actual DAC transfer characteristic from the
ideal expressed as a percentage of the full-scale range.

ZERO CODE ERROR DRIFT

This is a measure of the change in zero code error with a

change in temperature. It is expressed in µV/°C.

GAIN ERROR DRIFT

This is a measure of the change in gain error with changes in tem-

perature. It is expressed in (ppm of full-scale range)/°C.

MAJOR CODE TRANSITION GLITCH ENERGY

Major Code Transition Glitch Energy is the energy of the im­pulse injected into the analog output when the code in the DAC
register changes state. It is normally specified as the area of the
glitch in nV-secs and is measured when the digital code is
changed by 1 LSB at the major carry transition (011 . . . 11 to
100 . . . 00 or 100 . . . 00 to 011 . . . 11).

DIGITAL FEEDTHROUGH

Digital Feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital input pins of the
device but is measured when the DAC is not being written to. It
is specified in nV-secs and is measured with a full-scale change
on the digital input pins, i.e., from all 0s to all 1s and vice versa.

–6–

REV. 0

Typical Performance Characteristics–

CODE

INL ERROR – LSBs

12

0

1000

4000

2000 3000

0

–4

–8

–12

8

4

TA = +258C
VDD = +5V

IDD – mA

FREQUENCY

120 200190

VDD = +5V

VDD = +3V

1801701601501401301101009080

AD5301/AD5311/AD5321

1.0
TA = +258C
V

= +5V

DD

0.5

0

INL ERROR – LSBs

–0.5

–1.0

50 250100 150 200

0

CODE

Figure 2. AD5301 Typical INL Plot

0.3

TA = +258C
V

= +5V

DD

0.2

0.1

0

–0.1

DNL ERROR – LSBs

–0.2

3

TA = +258C
VDD = +5V

2

1

0

–1

INL ERROR – LSBs

–2

–3

0

200 1000

400 600 800

CODE

Figure 3. AD5311 Typical INL Plot

0.6
TA = +258C

VDD = +5V

0.4

0.2

0

–0.2

DNL ERROR – LSBs

–0.4

Figure 4. AD5321 Typical INL Plot

1.0
TA = +258C

= +5V

V

DD

0.5

0

DNL ERROR – LSBs

–0.5

–0.3

0 50 250

100 150 200

CODE

Figure 5. AD5301 Typical DNL Plot

1.00
VDD = +5V

0.75

0.50

0.25

0

–0.25

ERROR – LSBs

–0.50

–0.75

–1.00

–40 0 120

TEMPERATURE – 8C

MAX INLMAX DNL

MIN DNLMIN INL

40 80

Figure 8. AD5301 INL Error and
DNL Error vs. Temperature

–0.6

0

400 600 800

200 1000

CODE

Figure 6. AD5311 Typical DNL Plot

10

8
6
4
2
0

–2

ERROR –

–4
–6
–8

–10

–40 0 10040 80

ZERO SCALE

FULL SCALE

TEMPERATURE – 8C

VDD = +5V

6020–20

Figure 9. Zero-Code Error and Full­Scale Error vs. Temperature

–1.0

0 1000 40002000 3000

CODE

Figure 7. AD5321 Typical DNL Plot

Figure 10. IDD Histogram with VDD =
+3 V and V

= +5 V

DD

REV. 0

–7–

AD5301/AD5311/AD5321

VDD – Volts

I

DD

– mA

200

0

2.7 3.2

3.7 4.2

100

50

4.7

5.2

150

–408C

+258C

+1058C

CH1 1V, TIME BASE = 5ms/DIV

CH1

V

OUT

VDD = +5V
T

A

= +258C

LOAD = 2kV AND
200pF TO GND

2.48

2.49

V

OUT

– Volts

2.47

2.50

5

5V SOURCE

4

3

– V

OUT

V

2

1

0

03

6

I – mA

3V SOURCE

3V SINK

5V SINK

912

Figure 11. Source and Sink Current
Capability

1.0

0.8

0.6

– mA

DD

I

0.4

0.2

0

2.7 3.2 5.2

–408C +258C

+1058C

3.7 4.2 4.7
VDD – Volts

Figure 14. Power-Down Current vs.
Supply Voltage␣

200
180
160

140
120
100

– mA

DD

I

80
60
40
20

0

15

ZERO-SCALE FULL-SCALE

VDD = 5V

VDD = 3V

Figure 12. Supply Current vs. Code

TA = +258C

CODE

Figure 13. Supply Current vs. Supply
Voltage

300

TA = +258C

250

VDD = +5V

200

DECREASING

150

– mA

DD

I

100

50

0

VDD = +3V

0

1.0 2.0 3.0 4.0 5.0
V – Volts

Figure 15. Supply Current vs. Logic
Input Voltage for SDA and SCL Volt-

INCREASING

Figure 16. Half-Scale Settling (1/4 to
3/4 Scale Code Charge)

age Increasing and Decreasing

TA = +258C

CH1

CH2

CH1 1V, CH2 1V, TIME BASE = 20ms/DIV

Figure 17. Power-On Reset to 0 V

V

TA = +258C

DD

V

OUT

CH1

V

OUT

CH2

SCL

CH1 1V, CH2 5V, TIME BASE = 1ms/DIV

Figure 18. Exiting Power-Down to

VDD = +5V

Figure 19. Major-Code Transition

Midscale

–8–

REV. 0

AD5301/AD5311/AD5321

2.440

2.445

V – Volts

2.450

2.455
1ns/DIV

Figure 20. Digital Feedthrough

GENERAL DESCRIPTION

The AD5301/AD5311/AD5321 are single resistor-string DACs
fabricated on a CMOS process with resolutions of 8, 10 and 12
bits respectively. Data is written via a 2-wire serial interface.
They operate from single supplies of +2.5 V to +5.5 V and the
output buffer amplifiers provide rail-to-rail output swing with a

slew rate of 0.7 V/µs. The power-supply (V

) acts as the refer-

DD

ence to the DAC. The devices have three programmable power­down modes, in which the DAC may be turned off completely
with a high-impedance output, or the output may be pulled low
by an on-chip resistor. See Power-Down section.

V

DD

REF(+)

DAC

REGISTER

RESISTOR

STRING

REF(–)

OUTPUT BUFFER

AMPLIFIER

V

OUT

Figure 21. DAC Channel Architecture

RESISTOR STRING

The resistor string section is shown in Figure 22. It is simply a
string of resistors, each of value R. The digital code loaded to
the DAC register determines at what node on the string the
voltage is tapped off to be fed into the output amplifier. The
voltage is tapped off by closing one of the switches connecting
the string to the amplifier. Because it is a string of resistors, it is
guaranteed monotonic over all codes.

R

R

R

TO OUTPUT
AMPLIFIER

DIGITAL-TO-ANALOG SECTION

The architecture of the DAC channel consists of a resistor­string DAC followed by an output buffer amplifier. The voltage
at the V

pin provides the reference voltage for the DAC.

DD

Figure 21 shows a block diagram of the DAC architecture.
Since the input coding to the DAC is straight binary, the ideal
output voltage is given by:

VD

×

V

OUT

DD

=

N

2

where:

N = DAC resolution
D = decimal equivalent of the binary code which is loaded to the

DAC register:

0–255 for AD5301 (8 Bits)
0–1023 for AD5311 (10 Bits)
0–4095 for AD5321 (12 Bits)

R

R

Figure 22. Resistor String

OUTPUT AMPLIFIER

The output buffer amplifier is capable of generating output
voltages to within 1 mV from either rail, which gives an output
range of 0.001 V to V

load of 2 kΩ to GND and V

– 0.001 V. It is capable of driving a

DD

, in parallel with 500 pF to GND.

DD

The source and sink capabilities of the output amplifier can be
seen in Figure 11.

The slew rate is 0.7 V/µs with a half-scale settling time to
±0.5 LSB (at 8 bits) of 6 µs with the output unloaded.

POWER-ON RESET

The AD5301/AD5311/AD5321 are provided with a power-on
reset function, ensuring that they power up in a defined state.

The DAC register is filled with zeros and remains so until a
valid write sequence is made to the device. This is particularly
useful in applications where it is important to know the state of
the DAC output while the device is powering up.

REV. 0

–9–

AD5301/AD5311/AD5321

SERIAL INTERFACE

2-WIRE SERIAL BUS

The AD5301/AD5311/AD5321 are controlled via an I2C­compatible serial bus. The DACs are connected to this bus as
slave devices (no clock is generated by the AD5301/AD5311/
AD5321 DACs).

The AD5301/AD5311/AD5321 has a 7-bit slave address. In the
case of the 6-pin device, the 6 MSBs are 000110 and the LSB is
determined by the state of the A0 pin. In the case of the 8-pin
device, the 5 MSBs are 00011 and the 2 LSBs are determined
by the state of the A0 and A1 pins. A1 and A0 allow the user to
use up to four of these DACs on one bus.

The 2-wire serial bus protocol operates as follows:

1. The master initiates data transfer by establishing a START
condition, which is when a high to low transition on the SDA
line occurs while SCL is high. The following byte is the ad­dress byte which consists of the 7-bit slave address followed
by an R/W bit (this bit determines whether data will be read
from or written to the slave device).

The slave whose address corresponds to the transmitted
address responds by pulling the SDA line low during the
ninth clock pulse (this is termed the Acknowledge bit). At
this stage, all other devices on the bus remain idle while the
selected device waits for data to be written to or read from its
serial register. If the R/W bit is high, the master will read
from the slave device. However, if the R/W bit is low, the
master will write to the slave device.

2. Data is transmitted over the serial bus in sequences of nine
clock pulses (eight data bits followed by an Acknowledge
bit). The transitions on the SDA line must occur during the
low period of SCL and remain stable during the high period
of SCL.

3. When all data bits have been read or written, a STOP condi­tion is established by the master. A STOP condition is de­fined as a low-to-high transition on the SDA line while SCL
is high. In Write mode, the master will pull the SDA line
high during the 10th clock pulse to establish a STOP condi­tion. In Read mode, the master will issue a No Acknowledge
for the 9th clock pulse (i.e., the SDA line remains high). The
master will then bring the SDA line low before the 10th clock
pulse and then high during the 10th clock pulse to establish a
STOP condition.

In the case of the AD5301/AD5311/AD5321, a write operation
contains two bytes whereas a read operation may contain one or
two bytes. See Figures 24 to 29 below for a graphical explana­tion of the serial interface.

A repeated write function gives the user flexibility to update the
DAC output a number of times after addressing the part only
once. During the write cycle, each multiple of two data bytes
will update the DAC output. For example, after the DAC has
acknowledged its address byte, and receives two data bytes, the
DAC output will update after the two data bytes, if another two
data bytes are written to the DAC while it is still the addressed
slave device, these data bytes will also cause an output update.
Repeat read of the DAC is also allowed.

INPUT SHIFT REGISTER

The input shift register is 16 bits wide. Figure 23 illustrates the
contents of the input shift register for each part. Data is loaded
into the device as a 16-bit word under the control of a serial
clock input, SCL. The timing diagram for this operation is
shown in Figure 1. The 16-bit word consists of four control bits
followed by 8, 10 or 12 bits of data, depending on the device
type. MSB (Bit 15) is loaded first. The first two bits are “don’t
cares.” The next two are control bits that control the mode of
operation of the device (normal mode or any one of three
power-down modes). See Power Down Modes section for a
complete description. The remaining bits are left-justified DAC
data bits, starting with the MSB and ending with the LSB.

DB0 (LSB)DB15 (MSB)

X

PD1 PD0 D7 D6 D5 D4 D3 D2 D1 D0 X X X X

X

DATA BITS

Figure 23a. AD5301 Input Shift Register Contents

DB0 (LSB)DB15 (MSB)

X

PD1 PD0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X

X

DATA BITS

Figure 23b. AD5311 Input Shift Register Contents

DB0 (LSB)DB15 (MSB)

X

PD1 PD0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

X

DATA BITS

Figure 23c. AD5321 Input Shift Register Contents

–10–

REV. 0

AD5301/AD5311/AD5321

WRITE OPERATION

When writing to the AD5301/AD5311/AD5321 DACs, the user
must begin with an address byte, after which the DAC will
acknowledge that it is prepared to receive data by pulling SDA

SCL

SDA

START

COND

BY

MASTER

SCL

SDA D3D2D1D0XXXX

*THIS BIT MUST BE 0 IN THE 6-PIN SOT-23 VERSION.

ADDRESS BYTE MOST SIGNIFICANT CONTROL BYTE

LEAST SIGNIFICANT CONTROL BYTE

ACK

BY

AD5301

Figure 24. AD5301 Write Sequence

SCL

SDA

START

COND

BY

MASTER

ADDRESS
BYTE

ACK

BY

AD5311

low. This address byte is followed by the 16-bit word in the
form of two control bytes. The write operations for the three
DACs are shown in the figures below.

X X PD1 PD0 D7 D6 D5 D400011A1*A0R/W

ACK

BY

AD5301

STOP

ACK

COND

BY

AD5301

BY

MASTER

X X PD1 PD0 D9 D8 D7 D60 0 0 1 1 A1* A0 R/W

MOST SIGNIFICANT CONTROL BYTE

ACK

BY

AD5311

SCL

SDA D5 D4 D3 D2 D1 D0 X X

LEAST SIGNIFICANT CONTROL BYTE

*THIS BIT MUST BE 0 IN THE 6-PIN SOT-23 VERSION.

Figure 25. AD5311 Write Sequence

SCL

SDA

START

COND

BY

MASTER

SCL

SDA D7 D6 D5 D4 D3 D2 D1 D0

*THIS BIT MUST BE 0 IN THE 6-PIN SOT-23 VERSION.

ADDRESS BYTE MOST SIGNIFICANT CONTROL BYTE

LEAST SIGNIFICANT CONTROL BYTE

Figure 26. AD5321 Write Sequence

ACK

BY

AD5321

ACK

BY

AD5311

ACK

BY

AD5321

X X PD1 PD0 D11 D10 D9 D80 0 0 1 1 A1* A0 R/W

MASTER

STOP

COND

BY

MASTER

STOP
COND

BY

ACK

BY

AD5321

REV. 0

–11–

AD5301/AD5311/AD5321

READ OPERATION

When reading data back from the AD5301/AD5311/AD5321
DACs, the user must begin with an address byte after which the
DAC will acknowledge that it is prepared to transmit data by
pulling SDA low. There are two different read operations. In the
case of the AD5301, the readback is a single byte that consists

SCL

SDA 0 0 0 1 1 A1* A0 R/W

START

COND

BY

MASTER

*THIS BIT MUST BE 0 IN THE 6-PIN SOT-23 VERSION.

ADDRESS BYTE

D7 D6 D5 D4 D3 D2 D1 D0

ACK

BY

AD5301

Figure 27. AD5301 Readback Sequence

SCL

SDA

SCL

START

COND

BY

MASTER

ADDRESS BYTE MOST SIGNIFICANT BYTE

ACK

BY

AD5311

of the eight data bits in the DAC register. However, in the
case of the AD5311 and AD5321, the readback consists of two
bytes that contain both the data and the power-down mode bits.
The read operations for the three DACs are shown in the figures
below.

BY

MASTER

MASTER

ACK

BY

STOP
COND

BY

DATA BYTE

X X PD1 PD0 D9 D8 D7 D60 0 0 1 1 A1* A0 R/W

NO ACK

MASTER

SDA D5 D4 D3 D2 D1 D0 X X

LEAST SIGNIFICANT BYTE

*THIS BIT MUST BE 0 IN THE 6-PIN SOT-23 VERSION.

Figure 28. AD5311 Readback Sequence

SCL

SDA

START

COND

BY

MASTER

SCL

SDA D7 D6 D5 D4 D3 D2 D1 D0

*THIS BIT MUST BE 0 IN THE 6-PIN SOT-23 VERSION.

ADDRESS BYTE MOST SIGNIFICANT BYTE

LEAST SIGNIFICANT BYTE

Figure 29. AD5321 Readback Sequence

NO ACK

MASTER

ACK

BY

AD5321

NO ACK

MASTER

BY

BY

STOP

COND

MASTER

X X PD1 PD0 D11 D10 D9 D8000 11A1*A0R/W

COND

MASTER

BY

STOP

BY

ACK

BY

MASTER

–12–

REV. 0

AD5301/AD5311/AD5321

AD5301/
AD5311/

AD5321

2-WIRE
SERIAL

INTERFACE

SDA

SCL

+15V

+5V

150mA TYP

V

OUT

= 0V TO 5V

REF195

V

DD

+5V

–5V

AD820/
OP295

2-WIRE
SERIAL

INTERFACE

+5V

AD5301/
AD5311/

AD5321

10mF

0.1mF

V

DD

V

OUT

R1 = 10kV

65V

R2 = 10kV

POWER-DOWN MODES

The AD5301/AD5311/AD5321 have very low power consump­tion, dissipating typically 0.36 mW with a 3 V supply and

0.75 mW with a 5 V supply. Power consumption can be further
reduced when the DAC is not in use by putting it into one of
three power-down modes, which are selected by Bits 13 and 12
(PD1 and PD0) of the control word. Table I shows how the state
of the bits corresponds to the mode of operation of the DAC.

Table I. PD1/PD0 Operating Modes

PD1 PD0 Operating Mode

0 0 Normal Operation

0 1 Power-Down (1 kΩ Load to GND)
1 0 Power-Down (100 kΩ Load to GND)

1 1 Power-Down (Three-State Output)

The software power-down modes programmed by PD0 and
PD1 may be overridden by the PD pin on the 8-pin version.
Taking this pin low puts the DAC into three-state power-down
mode. If PD is not used it should be tied high.

When both bits are set to 0, the DAC works normally with its

normal power consumption of 150 µA at 5 V, while for the three

power-down modes, the supply current falls to 200 nA at
5 V (50 nA at 3 V). Not only does the supply current drop, but
the output stage is also internally switched from the output of
the amplifier to a resistor network of known values. This has the
advantage that the output impedance of the part is known while
the part is in power-down mode and provides a defined input
condition for whatever is connected to the output of the DAC
amplifier. There are three different options. The output is con-

nected internally to GND through a 1 kΩ resistor, a 100 kΩ

resistor or it is left open-circuited (Three-State). Resistor toler-

ance = ±20%. The output stage is illustrated in Figure 30.

RESISTOR-

STRING DAC

AMPLIFIER

POWER-DOWN

CIRCUITRY

RESISTOR
NETWORK

V

OUT

APPLICATIONS

USING REF19x AS A POWER SUPPLY

Because the supply current required by the AD5301/AD5311/
AD5321 is extremely low, the user has an alternative option
to use a REF19x voltage reference (REF195 for +5 V or REF193
for +3 V) to supply the required voltage to the part, see Fig­ure 31.

Figure 31. REF195 as Power Supply to AD5301/AD5311/
AD5321

This is especially useful if the power supply is quite noisy or if
the system supply voltages are at some value other than +5 V or
+3 V (e.g., +15 V). The REF19x will output a steady supply
voltage for the AD5301/AD5311/AD5321. If the low dropout
REF195 is used, the current it needs to supply to the AD5301/

AD5311/AD5321 is 150 µA. This is with no load on the output

of the DAC. When the DAC output is loaded, the REF195 also
needs to supply the current to the load.

The total current required (with a 2 kΩ load on the DAC

output and full scale loaded to the DAC) is:

150 µA + (5 V/2 kΩ) = 2.65 mA

The load regulation of the REF195 is typically 2 ppm/mA which

results in an error of 5.3 ppm (26.5 µV) for the 2.65 mA current

drawn from it. This corresponds to a 0.00136 LSB error.

BIPOLAR OPERATION USING THE AD5301/AD5311/
AD5321

The AD5301/AD5311/AD5321 has been designed for single­supply operation but a bipolar output range is also possible
using the circuit in Figure 32. The circuit below will give an

output voltage range of ±5 V. Rail-to-rail operation at the am-

plifier output is achievable using an AD820 or an OP295 as the
output amplifier.

Figure 30. Output Stage During Power-Down

The bias generator, the output amplifier, the resistor string and
all other associated linear circuitry are all shut down when the
power-down mode is activated. However, the contents of the
DAC register are unchanged when in power-Down. The time to

exit power-down is typically 2.5 µs for V

= 3 V. See Figure 18 for a plot.

V

DD

REV. 0

= 5 V and 6 µs when

DD

Figure 32. Bipolar Operation with the AD5301/AD5311/
AD5321

–13–

AD5301/AD5311/AD5321

The output voltage for any input code can be calculated as
follows:

V

OUT

= [(V

× (D/2N) × (R1 + R2)/R1) – VDD × (R2/R1)]

DD

where D is the decimal equivalent of the code loaded to the
DAC.

N is the DAC resolution.

With V

= 5 V, R1 = R2 = 10 kΩ:

DD

V

= (10 × D/2

OUT

N

) – 5 V

MULTIPLE DEVICES ON ONE BUS

Figure 33 shows four AD5301 devices on the same serial bus.
Each has a different slave address since the state of their A0 and
A1 pins is different. This allows each DAC to be written to or
read from independently. The master device output bus line
drivers are open-drain pull downs in a fully I

2

C-compatible

interface.

CMOS DRIVEN SCL AND SDA LINES

For single or multisupply systems where the minimum SCL
swing requirements allow it, a CMOS SCL driver may be used,
the SCL pull-up resistor can be removed, making the SCL bus
line fully CMOS compatible. This will reduce power consump­tion in both the SCL driver and receiver devices. The SDA line
remains open-drain, I

2

C-compatible.

Further changes, in the SDA line driver, may be made to make
the system more CMOS-compatible and save more power. As
the SDA line is bidirectional, it cannot be made fully CMOS­compatible. A switched pull-up resistor can be combined with
a CMOS device with an open-circuit (three-state) input such
that the CMOS SDA driver is enabled during write cycles and

2

C mode is enabled during shared cycles, i.e., readback, ac-

I
knowledge bit cycles, start and stop conditions.

POWER SUPPLY DECOUPLING

In any circuit where accuracy is important, careful consider­ation of the power supply and ground return layout helps to
ensure the rated performance. The AD5301/AD5311/AD5321

should be decoupled to GND with a 10 µF in parallel with 0.1 µF
capacitor, located as close to the package as possible. The 10 µF

capacitor should be the tantalum bead type, while a ceramic

0.1 µF capacitor will provide sufficient low impedance path to

ground at high frequencies. The power supply lines of the
AD5301/AD5311/AD5321 should use as large a trace as pos­sible to provide low impedance paths. A ground line routed
between the SDA and SCL lines will help reduce crosstalk
between them (not required on a multilayer board as there will
be a ground plane layer, but separating the lines will help).

MASTER

SDA SCL

A1
A0

V

AD5301

+5V

R

OUT

R

P

V

DD

P

SDA SCL

A1
A0

AD5301

V

DD

SDA SCL

V

OUT

A1
A0

V

OUT

V

AD5301

Figure 33. Multiple AD5301 Devices on One Bus

DD

SDA SCL

A1
A0

AD5301

SDA
SCL

V

OUT

–14–

REV. 0

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

6-Lead SOT-23

(RT-6)

0.122 (3.10)

0.106 (2.70)

AD5301/AD5311/AD5321

0.071 (1.80)

0.059 (1.50)

0.051 (1.30)

0.035 (0.90)

0.122 (3.10)

0.114 (2.90)

0.006 (0.15)

0.002 (0.05)

PIN 1

0.006 (0.15)

0.000 (0.00)

PIN 1

1

2

0.075 (1.90)
BSC

0.020 (0.50)

0.010 (0.25)

8-Lead ␮SOIC

0.122 (3.10)

0.114 (2.90)

85

41

0.0256 (0.65) BSC

0.016 (0.40)

0.010 (0.25)

4 5 6

0.118 (3.00)

0.098 (2.50)

3

0.037 (0.95) BSC

0.057 (1.45)

0.035 (0.90)

SEATING
PLANE

(RM-8)

0.193
(4.90)

BSC

0.043
(1.10)
MAX

SEATING
PLANE

0.009 (0.23)

0.003 (0.08)

0.009 (0.23)

0.005 (0.13)

68
08

10°

0.022 (0.55)

0°

0.014 (0.35)

0.037 (0.95)

0.030 (0.75)

0.028 (0.70)

0.016 (0.40)

C3531–8–7/99

REV. 0 –15–

PRINTED IN U.S.A.