Datasheet AD5280 Datasheet (Analog Devices)

15 V, I2C Compatible

256-Position Digital Potentiometers

FEATURES 256 Position AD5280: 1-Channel AD5282: 2-Channel (Independently Programmable) Potentiometer Replacement 20 k, 50 k, 200 k Low Temperature Coefficient 30 ppm/°C Internal Power-On Midscale Preset 5 V to 15 V Single-Supply; 5.5 V Dual-Supply Operation

C Compatible Interface

APPLICATIONS Multimedia, Video, and Audio Communications Mechanical Potentiometer Replacement Instrumentation: Gain, Offset Adjustment Programmable Voltage Source Programmable Current Source Line Impedance Matching

GENERAL DESCRIPTION

The AD5280/AD5282 provides a single-/dual-channel, 256-position digitally controlled variable resistor (VR) device.

These devices perform the same electronic adjustment function as a potentiometer, trimmer, or variable resistor. Each VR offers a completely programmable value of resistance between the A terminal and the wiper or the B terminal and the wiper. The fixed A-to-B terminal resistance of 20 kΩ, 50 kΩ, or 200 kΩ has a 1% channel-to-channel matching tolerance. Nominal temperature coefficient of both parts is 30 ppm/°C. Another key feature of these parts is that they can operate up to +15 V or ±5 V.

Wiper position programming defaults to midscale at system power-on. Once powered, the VR wiper position is programmed

by an I

C compatible 2-wire serial data interface. Both parts have additional programmable logic outputs that enable users to drive digital loads, logic gates, LED drivers, and analog switches in their system.

The AD5280/AD5282 are available in thin surface-mount 14-lead and 16-lead TSSOP packages. All parts are guaranteed to operate over the extended industrial temperature range of –40°C to +85°C. For 3-wire SPI compatible interface appli- cations, see AD5260/AD5262 products.

SHDN

SCL

SDA

GND

AD5280/AD5282

FUNCTIONAL BLOCK DIAGRAMS

AW B O

SHDN

SCL

SDA

GND

ADDRESS

DECODE

RDAC REGISTER

ADDRESS

DECODE

SERIAL INPUT REGISTER

AD0

AD1

A1W1B

RDAC1 REGISTER

SERIAL INPUT REGISTER

AD0

AD1

OUTPUT REGISTER

A2W2B

RDAC2 REGISTER

PWR ON

RESET

AD5280

PWR ON

RESET

OUTPUT

AD5282

Patent Pending.

NOTE

The terms digital potentiometer, VR, and RDAC are used interchangeably.

REV. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2002

AD5280/AD5282–SPECIFICATIONS

ELECTRICAL CHARACTERISTICS 20 k, 50 k, 200 k VERSION

(VDD = +15 V, VSS = 0 V or VDD = +5 V, VSS = –5 V; V

Parameter Symbol Conditions Min Typ

DC CHARACTERISTICS–RHEOSTAT MODE Specifications apply to all VRs

Resistor Differential NL Resistor Nonlinearity Nominal Resistor Tolerance Resistance Temperature Coefficient R Wiper Resistance R

R-DNL RWB, VA = NC –1 ± 1/4 +1 LSB R-INL RWB, VA = NC –1 ± 1/4 +1 LSB ⌬R

/⌬TV

DC CHARACTERISTICS–POTENTIOMETER DIVIDER MODE Specifications apply to all VRs

Resolution N 8 Bits Integral Nonlinearity Differential Nonlinearity Voltage Divider Temperature ⌬V

INL –1 ± 1/4 +1 LSB DNL –1 ± 1/4 +1 LSB

Coefficient

Full-Scale Error V Zero-Scale Error V

RESISTOR TERMINALS

Voltage Range Capacitance

A, B C

Capacitance6 WC

Common-Mode Leakage I Shutdown Current I

WFSE

WZSE

A,B,W

A,B

SHDN

DIGITAL INPUTS AND OUTPUTS

Input Logic High V Input Logic Low V Input Logic High V Input Logic Low V Output Logic High (SDO) V Output Logic Low (SDO) V Input Current I Input Capacitance

POWER SUPPLIES

Logic Supply V Power Single-Supply Range V Power Dual-Supply Range V Logic Supply Current I Positive Supply Current I Negative Supply Current I Power Dissipation

LOGIC

DD RANGE

DD/SS RANGE

LOGIC

DISS

Power Supply Sensitivity PSS 0.002 0.01 %/%

DYNAMIC CHARACTERISTICS

6, 8, 9

Bandwidth –3 dB BW_20K RAB = 20 kΩ, Code = 80

BW_50K R BW_200K R

Total Harmonic Distortion THD

Settling Time t

Crosstalk CT V

Analog Crosstalk CTA Measure V

Resistor Noise Voltage e

N_WB

= 5 V, VA = +VDD, VB = 0 V; –40C < TA < +85C, unless otherwise noted.)

LOGIC

TA = 25°C –30 +30 %

= VDD, Wiper = No Connect 30 ppm/°C

IW = VDD /R, VDD = 3 V or 5 V 60 150 Ω

/⌬TCode = 80

Code = FF Code = 00

–2 –1 0 LSB 0+1+2LSB

5 ppm/°C

f = 5 MHz, measured to 25 pF GND, Code = 80

f = 1 MHz, measured to 55 pF GND, Code = 80 VA = VB = V

1nA

2.4 V

= 3 V, VSS = 0 2.1 V

LOGIC

= 3 V, VSS = 0 0.6 V

LOGIC

4.9 V

VIN = 0 V or 5 V ±1 µA

5pF

2.7 5.5 V

VSS = 0 V 5 15 V

±4.5 ±5.5 V

= 5 V 60 µA

LOGIC

VIH = 5 V or VIL = 0 V 0.1 1 µA

0.1 1 µA

VIH = 5 V or VIL = 0 V, VDD = +5 V, 0.2 0.3 mW V

= –5 V

= 50 kΩ, Code = 80

= 200 kΩ, Code = 80

VA = 1 V rms, RAB = 20 kΩ 0.014 % V

= 0 V DC, f = 1 kHz

310 kHz 150 kHz 35 kHz

VA = 5 V, VB = 5 V, 5 µs ±1 LSB error band

= VDD, VB = 0 V, Measure 15 nV-s

VW1 with Adjacent RDAC Making Full-Scale Code Change

with VW2 = 5 V p-p –62 dB

@ f = 10 kHz RWB = 20 kΩ, f = 1 kHz 18 nV/√Hz

Max Unit

5 µA

0.8 V

0.4 V

REV. 0–2–

AD5280/AD5282

Parameter Symbol Conditions Min Typ

INTERFACE TIMING CHARACTERISTICS Applies to all parts SCL Clock Frequency f

Bus Free Time between STOP and START t

BUF

Hold Time (Repeated START) t

HD:STA

SCL

6, 10

1.3 µs

After this period, the first 0.6 µs

Max Unit

400 kHz

clock pulse is generated

Low Period of SCL Clock t

LOW

High Period of SCL Clock t

HIGH

Setup Time for START Condition t

SU:STA

Data Hold Time t

HD:DAT

Data Setup Time t

SU:DAT

tF Fall Time of Both SDA and SCL Signals t

Rise Time of Both SDA and SCL Signals t

Setup Time for STOP Condition t

SU:STO

NOTES

Typicals represent average readings at 25°C, VDD = +5 V, VSS = –5 V.

Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.

VAB = VDD, Wiper (VW) = No connect.

INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V. DNL specification limits of ± 1 LSB maximum are guaranteed monotonic operating conditions.

Resistor terminals A, B, W have no limitations on polarity with respect to each other.

Guaranteed by design and not subject to production test.

is calculated from (IDD ⫻ VDD). CMOS logic level inputs result in minimum power dissipation.

DISS

Bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest bandwidth. The highest R value results in the minimum overall power consumption.

All dynamic characteristics use VDD = 5 V.

See timing diagram for location of measured values.

Speciﬁcations subject to change without notice.

1.3 µs

0.6 50 µs

0.6 µs

0.9 µs

100 ns

300 ns 300 ns

0.6 µs

REV. 0

–3–

AD5280/AD5282

ABSOLUTE MAXIMUM RATINGS

(TA = 25°C, unless otherwise noted.)

VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +15 V

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, –7 V

to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V

, VB, VW to GND . . . . . . . . . . . . . . . . . . . . . . . . . . VSS, V

AX – BX, AX – WX, BX – W

Intermittent2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA

Continuous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±5 mA

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, 7 V

LOGIC

Output Voltage to GND . . . . . . . . . . . . . . . . . . . . . . 0 V, 7 V

Operating Temperature Range . . . . . . . . . . . –40°C to +85°C

Thermal Resistance

␪JA,

TSSOP-14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206°C/W

TSSOP-16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C/W

Maximum Junction Temperature (TJ MAX) . . . . . . . . . 150°C

Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C

Lead Temperature

RU-14, RU-16 (Vapor Phase, 60 sec) . . . . . . . . . . . . 215°C

RU-14, RU-16 (Infrared, 15 sec) . . . . . . . . . . . . . . . . 220°C

NOTES

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Maximum terminal current is bound by the maximum current handling of the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the A, B, and W terminals at a given resistance.

Package Power Dissipation (TJ MAX – TA)/␪

ORDERING GUIDE

Number of R

Package Package Parts Per Branding

Model Channels (k) Temp Description Option Container Information*

AD5280BRU20 1 20 –40°C to +85°CTSSOP-14 RU-14 96 AD5280B20 AD5280BRU20-REEL7 1 20 –40°C to +85°CTSSOP-14 RU-14 1000 AD5280B20 AD5280BRU50 1 50 –40°C to +85°CTSSOP-14 RU-14 96 AD5280B50 AD5280BRU50-REEL7 1 50 –40°C to +85°CTSSOP-14 RU-14 1000 AD5280B50 AD5280BRU200 1 200 –40°C to +85°CTSSOP-14 RU-14 96 AD5280B200 AD5280BRU200-REEL7 1 200 –40°C to +85°CTSSOP-14 RU-14 1000 AD5280B200 AD5282BRU20 2 20 –40°C to +85°CTSSOP-16 RU-16 96 AD5282B20 AD5282BRU20-REEL7 2 20 –40°C to +85°CTSSOP-16 RU-16 1000 AD5282B20 AD5282BRU50 2 50 –40°C to +85°CTSSOP-16 RU-16 96 AD5282B50 AD5282BRU50-REEL7 2 50 –40°C to +85°CTSSOP-16 RU-16 1000 AD5282B50 AD5282BRU200 2 200 –40°C to +85°CTSSOP-16 RU-16 96 AD5282B200 AD5282BRU200-REEL7 2 200 –40°C to +85°CTSSOP-16 RU-16 1000 AD5282B200

The AD5280/AD5282 die size is 75 mm ⫻ 120 mm, 9,000 sq. mm. Contains 3077 transistors. *Line 1 contains model number, Line 2 contains ADI logo followed by the end-to-end resistance value, and line 3 contains date code YYWW.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD5280/AD5282 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

REV. 0–4–

PIN CONFIGURATION

AD5280/AD5282

AD5280 PIN CONFIGURATION

HDN

SCL

SDA

AD5280

TOP VIEW

(Not to Scale)

GND

AD1

AD0

AD5280 PIN FUNCTION DESCRIPTION

Pin Mnemonic Description

1A Resistor Terminal A 2W Wiper Terminal W 3B Resistor Terminal B 4V

Positive Power Supply. Specified for operation from 5 V to 15 V (Sum of |V

| + |VSS| ≤ 15 V).

5 SHDN Active Low, Asynchronous Connection of the

Wiper W to Terminal B and Open Circuit of Terminal A. RDAC Register contents unchanged. SHDN should tie to V

if not used.

6 SCL Serial Clock Input 7 SDA Serial Data Input/Output 8AD0 Programmable Address Bit 0 for Multiple

Package Decoding. Bits AD0 and AD1 provide four possible addresses.

9AD1 Programmable Address Bit 1 for Multiple

Package Decoding. Bits AD0 and AD1 provide

four possible addresses. 10 GND Common Ground 11 V

12 O 13 V

Negative Power Supply. Specified for operation

from 0 V to –5 V (Sum of |V

Logic Output Terminal O

| + |VSS| ≤ 15 V).

Logic Supply Voltage. Needs to be the same

voltage as the digital logic controlling the

AD5280. 14 O

Logic Output Terminal O

AD5282 PIN CONFIGURATION

HDN

SCL

SDA

(Not to Scale)

AD5282

TOP VIEW

GND

AD1

AD0

AD5282 PIN FUNCTION DESCRIPTION

Pin Mnemonic Description

Logic Output Terminal O Resistor Terminal A Wiper Terminal W Resistor Terminal B

Positive Power Supply. Specified for operation from 5 V to 15 V (Sum of |V

| + |VSS|≤ 15 V).

6 SHDN Active Low, Asynchronous Connection of the

Wiper W to Terminal B and Open Circuit of Terminal A. RDAC Register contents unchanged. SHDN should tie to V

if not used.

7 SCL Serial Clock Input 8 SDA Serial Data Input/Output 9 AD0 Programmable Address Bit 0 for Multiple

Package Decoding. Bits AD0 and AD1 provide four possible addresses.

10 AD1 Programmable Address Bit 1 for Multiple

Package Decoding. Bits AD0 and AD1 provide

four possible addresses. 11 GND Common Ground 12 V

13 V

Negative Power Supply. Specified for operation

from 0 V to –5 V (Sum of |V

| + |VSS| ≤ 15 V).

Logic Supply Voltage. Needs to be the same

voltage as the digital logic controlling the

AD5282. 14 B 15 W 16 A

Resistor Terminal B

Wiper Terminal W

Resistor Terminal A

REV. 0

–5–

AD5280/AD5282

–Typical Performance Characteristics

0.8

0.6

0.4

0.2

–0.2

–0.4

–0.6

RHEOSTAT MODE INL – LSB

–0.8

–1

0 32 160 256

+5V

ⴞ5V

64 96 128 192 224

CODE – Decimal

+15V

RAB = 20k⍀

= 25ⴗC

TPC 1. R-INL vs. Code vs. Supply Voltages

0.5

0.4

0.3

0.2

TA = –40ⴗC

0.1

–0.1

–0.2

–0.3

POTENTIOMETER MODE DNL – LSB

–0.4

–0.5

0 32 160 256

TA = +125ⴗC

64 96 128 192 224

CODE – Decimal

RAB = 20k⍀

TA = +85ⴗC

TA = +25ⴗC

TPC 4. DNL vs. Code, VDD/VSS = ±5 V

0.5

0.4

0.3

0.2

ⴞ5V

0.1

–0.1

–0.2

–0.3

RHEOSTAT MODE DNL – LSB

–0.8

–0.5

0 32 160 256

+15V

64 96 128 192 224

CODE – Decimal

+5V

RAB = 20k⍀

= 25ⴗC

TPC 2. R-DNL vs. Code vs. Supply Voltages

0.8

0.6

0.4

0.2

–0.2

–0.4

–0.6

POTENTIOMETER MODE INL – LSB

–0.8

–1

0 32 160 256

ⴞ5V

64 96 128 192 224

CODE – Decimal

+5V

RAB = 20k⍀ TA = 25ⴗC

+15V

TPC 5. INL vs. Code vs. Supply Voltages

0.8

0.6 TA = +85ⴗC

0.4

0.2

–0.2

TA = –40ⴗC

–0.4

–0.6

POTENTIOMETER MODE INL – LSB

–0.8

–1

0 32 160 256

TA = +125ⴗC

TA = +25ⴗC

64 96 128 192 224

CODE – Decimal

RAB = 20k⍀

TPC 3. INL vs. Code, VDD/VSS = ±5 V

0.5

0.4

0.3

0.2

ⴞ5V

0.1

–0.1

–0.2

–0.3

POTENTIOMETER MODE DNL – LSB

–0.4

–0.5

0 32 160 256

+5V

64 96 128 192 224

CODE – Decimal

RAB = 20k⍀

= 25ⴗC

+15V

TPC 6. DNL vs. Code vs. Supply Voltages

1.0

Avg + 3␴

0.5

INL – LSB

–0.5

–1.0

0 20

Avg

Avg – 3␴

51015

|VDD – VSS| – V

RAB = 20k⍀

= 25ⴗC

TPC 7. INL Over Supply Voltage

2.0

1.5

1.0

0.5

RINL – LSB

–0.5

–1.0

–1.5

–2.0

0 20

Avg + 3␴

Avg

Avg – 3␴

51015

|VDD – VSS| – V

RAB = 20k⍀ T

= 25ⴗC

TPC 8. RINL Over Supply Voltage

–0.2

–0.4

–0.6

–0.8

–1.0

–1.2

–1.4

–1.6

FULL-SCALE ERROR – LSB

–1.8

–2.0

–40 100

VDD/VSS = 15V/0V

VDD/VSS = ⴞ5V

200–20

TEMPERATURE – ⴗC

RAB = 20k⍀

VDD/VSS = 5V/0V

40 60 80

TPC 9. Full-Scale Error

REV. 0–6–

AD5280/AD5282

CODE – Decimal

POTENTIOMETER MODE TEMPCO – ppm/ⴗC

256

–40

966432

–20

TA = 25ⴗC

128 192 224

50k⍀

120

100



200k⍀

20k⍀

2.0

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

ZERO-SCALE ERROR – LSB

0.2

0 –40 100

VDD/VSS = 5V/0V

VDD/VSS = ⴞ5V

200–20

TEMPERATURE – ⴗC

RAB = 20k⍀

VDD/VSS = 15V/0V

40 60 80

TPC 10. Zero-Scale Error

1000



– ␮A

100

LOGIC

VDD/VSS = 5V/0V

0 534

TPC 13. V

Supply Current

LOGIC

VIH – V

RAB = 20k⍀

= 25ⴗC

VDD/VSS = 5V/0V

= 5V

LOGIC

= 3V

vs. Digital Input Voltage

1000

@ VDD/VSS = 15V/0V

100

ISS @ VDD/VSS = ⴞ5V

IDD @ VDD/VSS = ⴞ5V

SUPPLY CURRENT – nA

1 –40 125

RAB = 20k

26–7

TEMPERATURE – ⴗC

LOGIC

= 5V

= 0V

59 92

= 5V

TPC 11. Supply Current vs. Temperature

–100

RHEOSTAT MODE TEMPCO – ppm/ C

–200

700

600

500

400

300

200

100

20k⍀ 50k⍀

200k⍀



966432

CODE – Decimal

TA = 25ⴗC

128 192 224

TPC 14. Rheostat Mode Tempco

⌬

RWB/⌬T vs. Code, VDD/VSS = ±5 V

256

26.0

25.5

VDD/VSS = 15V/0V

25.0

– ␮A

24.5

LOGIC

24.0

23.5

23.0 –40 125

TPC 12. V

26–7

TEMPERATURE – ⴗC

LOGIC

DD/VSS

59 92

Supply

RAB = 20k⍀

= ⴞ5V

Current vs. Temperature

TPC 15. Potentiometer Mode Tempco

⌬

VWB/⌬T vs. Code, VDD/VSS = ±5 V



–6

–12

–18

–24

–30

–36

GAIN – dB

–42

–48

–54

–60

80H

40H

20H

10H

08H

04H

02H

01H

FREQUENCY – Hz

TA = 25ⴗC V V

100k10k

= 50mV rms

= ⴞ5V

DD/VSS

TPC 16. Gain vs. Frequency

= 20 k

vs. Code, R

REV. 0

Ω



–6

–12

–18

–24

–30

GAIN – dB

–36

–42

–48

–54

–60

80H

40H

20H

10H

08H

04H

02H

01H

TA = 25ⴗC V V

100k10k

FREQUENCY – Hz

TPC 17. Gain vs. Frequency vs. Code, RAB = 50 k

–7–

= 50mV rms

= ⴞ5V

DD/VSS

Ω



–6

–12

–18

–24

–30

–36

GAIN – dB

–42

–48

–54

–60

80H

40H

20H

10H

08H

04H

02H

01H

FREQUENCY – Hz

TPC 18. Gain vs. Frequency vs. Code, RAB = 200 k

TA = 25ⴗC

= 50mV rms

VDD/VSS = ⴞ5V

Ω

100k10k

AD5280/AD5282



–6

–12

–18

–24

–30

–36

GAIN – dB

–42

–48

–54

–60

R = 50k⍀ 150kHz

R = 200k⍀ 35kHz

TA = 25ⴗC VDD/VSS = ⴞ5V V

FREQUENCY – Hz

100k10k

TPC 19. –3 dB Bandwidth



PSRR – –dB

+PSRR @ VDD/VSS = ⴞ5V

DC ⴞ 10% p-p AC

100

CODE = 80H, VA = VDD, VB = 0V

–PSRR @ VDD/VSS = ⴞ5V DC ⴞ 10% p-p AC

100000100001000

FREQUENCY – MHz

TPC 22. PSRR vs. Frequency

R = 20k⍀ 310kHz

= 50mV rms

1000000



–6dB

R = 200k⍀

NOMALIZED GAIN FLATNESS – 0.1dB/DIV

FREQUENCY – Hz

TA = 25ⴗC V

DD/VSS

R = 20k⍀

R = 50k⍀

10k1k100

= ⴞ5V

TPC 20. Normalized Gain Flatness vs. Frequency

852.0␮s1.2VA2

2.04␮s

TPC 23. Midscale Glitch Energy Code 80H to 7F

100k

– ␮A

LOGIC

500

400

300

200

100



FREQUENCY – Hz

TPC 21. V

LOGIC

VDD/VSS = ⴞ5V

= 25ⴗC

CODE = 55

100000010000010000

Supply

CODE = FF

10000000

Current vs. Frequency

TPC 24. Large Signal Settling Time

33.41␮s1.0VA2

1.50␮s

TPC 25. Digital Feedthrough vs. Time

100

– mA

WB_MAX

0.1

THEORETICAL I



0.01 0

TPC 26. I

VA = VB = OPEN T

RAB = 200k⍀

966432

128 192 224

CODE – Decimal

vs. Code

MAX

= 25ⴗC

RAB = 20k⍀

RAB = 50k⍀

256

CODES SET TO



MIDSCALE 3 LOTS SAMPLE SIZE = 135

FREQUENCY – MHz

–0.5

–0.4

–0.45

LONG TERM CHANNEL-TO-CHANNEL RAB

–0.35

–0.3

–0.2

–0.25

–0.15

MATCH – %

–0.1

–0.05

0.1

0.05

TPC 27. Channel-to-Channel Resistance Matching (AD5282)

0.15

0.2

REV. 0–8–

TEST CIRCUITS

Test Circuits 1 to 11 define the test conditions used in the product specification table.

AD5280/AD5282

V+ = V

1LSB = V+/2

V

DUT

Test Circuit 1. Potentiometer Divider Nonlinearity Error (INL, DNL)

NO CONNECT

DUT

Test Circuit 2. Resistor Position Nonlinearity Error (Rheostat Operation; R-INL, R-DNL)

DUT

MS2

= VDD/R

NOMINAL

MS1

RW = [V

MS1

– V

MS2

]/I

OFFSET

GND

DUT

2.5V

+15V

AD8610

–15V

OUT

Test Circuit 7. Gain vs. Frequency

0.1V

DUT

CODE =

0.1V

TO V

Test Circuit 8. Incremental On Resistance

DUT

GND

NC = NO CONNECT

Test Circuit 3. Wiper Resistance

V+

V+ = V

10%

PSRR (dB) = 20 LOG

PSS (%/ %) =

VMS%

V

( )

V

Test Circuit 4. Power Supply Sensitivity (PSS, PSSR)

OFFSET

GND

DUT

OFFSET BIAS

OP279

OUT

Test Circuit 5. Inverting Gain

OFFSET

GND

DUT

OFFSET BIAS

OP279

OUT

Test Circuit 9. Common-Mode Leakage Current

DIGITAL INPUT VOLTAGE

LOGIC

RDAC

OUT

VIN]

Test Circuit 10. V

LOGIC

SCL

SDA

Current vs. Digital Input Voltage

LOGIC

RDAC W

N/C

= 20 log [V

Test Circuit 11. Analog Crosstalk (AD5282 Only)

REV. 0

Test Circuit 6. Noninverting Gain

–9–

AD5280/AD5282

SDA

SCL

S P

Figure 1. Detailed Timing Diagram

Data of AD5280/AD5282 is accepted from the I2C bus in the following serial format: S 01011AD1AD0R/W A A/B RS SD O1 O2 X X X A D7 D6 D5 D4 D3 D2 D1 D0 A P

Slave Address Byte Instruction Byte Data Byte

Where:

S = Start Condition P = Stop Condition A = Acknowledge

A = No Acknowledge

X = Don’t Care AD1, AD0 = Package Pin Programmable Address Bits R/W = Read Enable at High and Write Enable at Low

A/B = RDAC Subaddress Select. “Zero” for RDAC1 and “One” for RDAC2 RS = Midscale Reset, Active High (only affects selected channel) SD = Shutdown. Same as SHDN pin operation except inverse logic (only affects

selected channel)

O2, O1 = Output Logic Pin Latched Values, Default Logic 0 D7, D6, D5, D4, D3, D2, D1, D0 = Data Bits

SCL

SDA

START BY

MASTER

SLAVE ADDRESS BYTE

1AD1AD0R/W

FRAME 1

91 199

RS SD O1 O2 X X X D7 D6 D5 D4D3D2D1D0

A/B

ACK. BY

AD5280/AD5282

FRAME 2

INSTRUCTION BYTE

ACK. BY

AD5280/AD5282

Figure 2. Writing to the RDAC Register

SCL

SDA

START BY

MASTER

SLAVE ADDRESS BYTE

FRAME 1

1AD1AD0

91 9

R/W

AD5280/AD5282

D7 D6 D5 D4 D3 D2 D1 D0

ACK. BY

DATA BYTE FROM PREVIOUSLY SELECTED

RDAC REGISTER IN WRITE MODE

FRAME 2

NO ACK. BY

MASTER

Figure 3. Reading Data from a Previously Selected RDAC Register in Write Mode

FRAME 3

DATA BYTE

STOP BY MASTER

ACK. BY

AD5280/AD5282

STOP BY MASTER

REV. 0–10–

AD5280/AD5282

OPERATION

The AD5280/AD5282 provides a single-/dual-channel, 256position, digitally controlled variable resistor (VR) device.

To program the VR settings, refer to the Digital Interface section. Both parts have an internal power-on preset that places the wiper at midscale during power-on, which simplifies the fault condition recovery at power-up. Operation of the power-on preset function also depends on the state of the V

pin. In addition, the shutdown

SHDN pin of the AD5280/AD5282 places the RDAC in an almost zero power consumption state where terminal A is open circuited and the wiper W is connected to terminal B, resulting in only leakage currents being consumed in the VR structure. During shutdown, the VR latch settings are maintained or new settings can be programmed. When the part is returned from shutdown, the corresponding VR setting will be applied to the RDAC.

HDN

string will not be accessed; therefore, there is 1 LSB less of the nominal resistance at full scale in addition to the wiper resistance.

The general equation determining the digitally programmed output resistance between W and B is:

WB AB W

256

=×+

()

(1)

where: D is the decimal equivalent of the binary code loaded in the

8-bit RDAC Register.

is the nominal end-to-end resistance.

is the wiper resistance contributed by the on resistance of

the internal switch.

Again, if R following output resistance values, R

= 20 kΩ and the A terminal is open circuited, the

, will be set for the fol-

lowing RDAC latch codes.

Table I. Codes and Corresponding Resistances

D7 D6 D5 D4 D3 D2 D1 D0

RDAC

LATCH

AND

DECODER

D (DEC) R

(⍀)Output State

255 19982 Full Scale (RAB – 1 LSB + RW) 128 10060 Midscale 1 138 1 LSB 060Zero-Scale (Wiper Contact Resistance)

Note that in the zero-scale condition, a finite wiper resistance of 60 Ω is present. Care should be taken to limit the current flow between W and B in this state to a maximum pulse current of no more than 20 mA. Otherwise, degradation or possible destruction of the internal switch contact can occur.

Similar to the mechanical potentiometer, the resistance of the RDAC between the wiper W and terminal A also produces a digitally controlled complementary resistance, R

. When these

terminals are used, the B terminal can be opened. Setting the

Figure 4. AD5280/AD5282 Equivalent RDAC Circuit

PROGRAMMING THE VARIABLE RESISTOR Rheostat Operation

The nominal resistance of the RDAC between terminals A and B is available in 20 kΩ, 50 kΩ, and 200 kΩ. The final two or three digits of the part number determine the nominal resistance value, e.g., 20 kΩ = 20; 50 kΩ = 50; 200 kΩ = 200. The nominal resistance (R

) of the VR has 256 contact points accessed by

the wiper terminal, plus the B terminal contact. The 8-bit data in the RDAC latch is decoded to select one of the 256 possible settings. Assuming a 20 kΩ part is used, the wiper’s first connection starts at the B terminal for data 00

. Since there is a 60 Ω

wiper contact resistance, such a connection yields a minimum of 60 Ω resistance between terminals W and B. The second connection is the first tap point that corresponds to 138 Ω

= RAB/256 + RW = 78 Ω + 60 Ω) for data 01H. The third

connection is the next tap point representing 216 Ω (78 ⫻ 2 + 60) for data 02

, and so on. Each LSB data value increase moves

the wiper up the resistor ladder until the last tap point is reached at 19982 Ω [R

– 1 LSB + RW]. Figure 4 shows a simplified

diagram of the equivalent RDAC circuit where the last resistor

resistance value for R and decreases as the data loaded in the latch increases in value. The general equation for this operation is:

WA AB W

For R

= 20 kΩ and B terminal open circuited, the following

256

=×+

()

output resistance, R latch codes.

Table II. Codes and Corresponding Resistances

D (DEC) R

255 138 Full Scale 128 10060 Midscale 1 19982 1 LSB 0 20060 Zero Scale

The typical distribution of the nominal resistance, R channel-to-channel matches within ±1%. Device-to-device matching is process lot dependent and is possible to have ±30% variation. Since the resistance element is processed in thin film technology, the change in R

starts at a maximum value of resistance

–

256

, will be set for the following RDAC

(⍀)Output State

with temperature has a very low

(2)

, from

30 ppm/°C temperature coefficient.

REV. 0

–11–

AD5280/AD5282

PROGRAMMING THE POTENTIOMETER DIVIDER Voltage Output Operation

The digital potentiometer easily generates a voltage divider at wiper-to-B and wiper-to-A to be proportional to the input voltage at A-to-B. Unlike the polarity of V

, which must be positive,

DD–VSS

voltage across A–B, W–A, and W–B can be at either polarity provided that V

is powered by a negative supply.

If ignoring the effect of the wiper resistance for approximation, connecting A terminal to 5 V and B terminal to ground produces an output voltage at the wiper-to-B starting at 0 V up to 1 LSB less than 5 V. Each LSB of voltage is equal to the voltage applied across A–B divided by the 256 positions of the potentiometer divider. Since AD5280/AD5282 can be supplied by dual supplies, the general equation defining the output voltage at V

with respect to ground for any valid input voltage applied to terminals A and B is:

256

VDDV

()

WA B

256

–

(3)

For a more accurate calculation, which includes the effect of wiper resistance, V

()

can be found as:

()

(4)

Operation of the digital potentiometer in the Divider Mode results in a more accurate operation overtemperature. Unlike the Rheostat Mode, the output voltage is dependent mainly on the ratio of the internal resistors R

and RWB and not on the absolute

values; therefore, the temperature drift reduces to 5 ppm/°C.

DIGITAL INTERFACE 2-Wire Serial Bus

The AD5280/AD5282 are controlled via an I2C compatible serial bus. The RDACs are connected to this bus as slave devices.

Referring to Figures 2 and 3, the first byte of AD5280/AD5282 is a Slave Address Byte. It has a 7-bit slave address and an R/W bit. The 5 MSBs are 01011 and the following two bits are determined by the state of the AD0 and AD1 pins of the device. AD0 and AD1 allow the user to place up to four of the I

C compatible

devices on one bus.

The 2-wire I

C serial bus protocol operates as follows:

1. The master initiates data transfer by establishing a START condition, which is when a high-to-low transition on the SDA line occurs while SCL is high (see Figure 2). The following byte is the Slave Address Byte which consists of the 7-bit slave address followed by an R/W bit (this bit determines whether data will be read from or written to the slave device).

The slave whose address corresponds to the transmitted address responds by pulling the SDA line low during the ninth clock pulse (this is termed the Acknowledge bit). At this stage, all other devices on the bus remain idle while the selected device waits for data to be written to or read from its serial register. If the R/W bit is high, the master will read from the slave device. On the other hand, if the R/W bit is low, the master will write to the slave device.

2. A write operation contains an extra Instruction Byte more than a read operation. Such an Instruction Byte in Write Mode follows the Slave Address Byte. The MSB of the Instruction

Byte labeled A/B is the RDAC subaddress select. A “low” selects RDAC1 and a “high” selects RDAC2 for the dualchannel AD5282. Set A/B to low for the AD5280.

The second MSB, RS, is the midscale reset. A logic high on this bit moves the wiper of a selected channel to the center tap where R

= RWB. This feature effectively writes over

the contents of the register, and thus when taken out of reset mode, the RDAC will remain at midscale.

The third MSB SD is a shutdown bit. A logic high causes the selected channel to open circuit at terminal A while shorting the wiper to terminal B. This operation yields almost 0 Ω in Rheostat Mode or 0 V in Potentiometer Mode. This SD bit serves the same function as the SHDN pin except that the SHDN pin reacts to active low. Also, the SHDN pin affects both channels (AD5282) as opposed to the SD bit, which only affects the channel that is being written to. It is important to note that the shutdown operation does not disturb the contents of the register. When brought out of shutdown, the previous setting will be applied to the RDAC.

The following two bits are O1 and O2. They are extra programmable logic outputs that can be used to drive other digital loads, logic gates, LED drivers, analog switches, and so on. The three LSBs are Don’t Care (see Figure 2).

3. After acknowledging the Instruction Byte, the last byte in Write Mode is the Data Byte. Data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an Acknowledge bit). The transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL (see Figure 2).

4. In the Read Mode, the Data Byte follows immediately after the acknowledgment of the Slave Address Byte. Data is transmitted over the serial bus in sequences of nine clock pulses (a slight difference with the Write Mode, where there are eight data bits followed by an Acknowledge bit). Similarly, the transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL (see Figure 3).

5. When all data bits have been read or written, a Stop condition is established by the master. A Stop condition is defined as a low-to-high transition on the SDA line while SCL is high. In Write Mode, the master will pull the SDA line high during the tenth clock pulse to establish a Stop condition, (see Figure 2). In Read Mode, the master will issue a No Acknowledge for the ninth clock pulse (i.e., the SDA line remains high). The master will then bring the SDA line low before the tenth clock pulse, which goes high to establish a Stop condition (see Figure 3).

A repeated write function gives the user flexibility to update the RDAC output a number of times after addressing and instructing the part only once. During the write cycle, each data byte will update the RDAC output. For example, after the RDAC has acknowledged its slave address and instruction bytes, the RDAC output will update after these two bytes. If another byte is written to the RDAC while it is still addressed to a specific slave device with the same instruction, this byte will update the output of the selected slave device. If different instructions are needed, the Write Mode has to start with a new Slave Address, Instruction, and Data Byte again. Similarly, a repeated read function of the RDAC is also allowed.

REV. 0–12–

AD5280/AD5282

RPR

3.3V

PROM

RPR

AD5282

SCL2

SDA2

DD2

= 5V

SCL1

SDA1

DD1

= 3.3V

READBACK RDAC VALUE

AD5280/AD5282 allows the user to read back the RDAC values in the Read Mode. However, for the AD5282 dual-channel device, the channel of interest is the one that is previously selected in the Write Mode. In the case where users need to read the RDAC values of both channels in AD5282, they can program the first subaddress in Write Mode and then change to Read Mode to read the first channel value. After that, they can change back to Write Mode with the second subaddress and finally read the second channel value in Read Mode again. Note that it is not necessary for users to issue the Frame 3 data byte in Write Mode for subsequent readback operation. Users should refer to Figures 2 and 3 for the programming format.

ADDITIONAL PROGRAMMABLE LOGIC OUTPUT

AD5280/AD5282 features additional programmable logic outputs, O1 and O2, which can be used to drive a digital load, analog switches, and logic gates. O logic states of O

and O2 can be programmed in Frame 2 under

and O2 default to Logic 0. The

the Write Mode (see Figure 2). These logic outputs have adequate current driving capability to sink/source milliamperes of load.

Users can also activate O

and O2 in three different ways without

affecting the wiper settings. They may do the following:

1. Start, Slave Address Byte, Acknowledge, Instruction Byte with O

and O2 specified, Acknowledge, Stop.

2. Complete the write cycle with Stop, then Start, Slave Address Byte, Acknowledge, Instruction Byte with O

and O2 specified,

Acknowledge, Stop.

3. Do not complete the write cycle by not issuing the Stop, then Start, Slave Address Byte, Acknowledge, Instruction Byte with O

and O2 specified, Acknowledge, Stop.

MULTIPLE DEVICES ON ONE BUS

Figure 6 shows four AD5282 devices on the same serial bus. Each has a different slave address since the states of their AD0 and AD1 pins are different. This allows each RDAC within each device to be written to or read from independently. The master device output bus line drivers are open-drain pull-downs in a

C compatible interface.

fully I

RPR

MASTER

SDA SCL

AD1

AD0

AD5282

SDA SCL

AD1

AD0

AD5282

SDA SCL

AD1

AD0

AD5282

SDA SCL

AD1

AD0

SDA

SCL

AD5282

Figure 6. Multiple AD5282 Devices on One Bus

LEVEL SHIFT FOR BIDIRECTIONAL INTERFACE

While most old systems may be operated at one voltage, a new component may be optimized at another. When two systems operate the same signal at two different voltages, proper level shifting is needed. For instance, one can use a 3.3 V E

PROM to interface with a 5 V digital potentiometer. A level shift scheme is needed to enable a bidirectional communication so that the setting of the digital potentiometer can be stored to and retrieved from

PROM. Figure 7 shows one of the implementations.

the E M1 and M2 can be any N-Ch signal FETs or low threshold FDV301N if V

falls below 2.5 V.

SELF-CONTAINED SHUTDOWN FUNCTION

Shutdown can be activated by strobing the SHDN pin or pro- gramming the SD bit in the Write Mode Instruction Byte. In addition, shutdown can even be implemented with the device digital output as shown in Figure 5. In this configuration, the device will be shut down during power-up, but users are allowed to program the device. Thus when O

is programmed high, the

device will exit from Shutdown Mode and respond to the new setting. This self-contained shutdown function allows absolute shutdown during power-up, which is crucial in hazardous environments, without adding extra components.

SHDN

SDA

SCL

Figure 5. Shutdown by Internal Logic Output

REV. 0

Figure 7. Level Shift for Different Potential Operation

LEVEL SHIFT FOR NEGATIVE VOLTAGE OPERATION

The digital potentiometer is popular in laser diode driver and certain telecommunications equipment level-setting applications. These applications are sometimes operated between ground and some negative supply voltage such that the systems can be biased at ground to avoid large bypass capacitors that may significantly impede the ac performance. Like most digital potentiometers, AD5280/AD5282 can be configured with a negative supply (see Figure 8).

–5V

LEVEL SHIFTED

GND

SDA

SCL

Figure 8. Biased at Negative Voltage

–13–

AD5280/AD5282

However, the digital inputs must also be level shifted to allow proper operation since the ground is now referenced to the negative potential. As a result, Figure 9 shows one implementation with a few transistors and a few resistors. When V

is below

Q3’s threshold value, Q3 is off, Q1 is off, and Q2 is on. In this state, V Q1 is on, and Q2 is turned off. In this state, V

approaches 0 V. When VIN is above 2 V, Q3 is on,

OUT

is pulled down to VSS. Beware that proper time shifting is also needed for successful communication with the device.

+5V

VSS = –5V

R2 10k⍀

R3 10k⍀

OUT

–5V

Figure 9. Level Shift for Bipolar Potential Operation

ESD PROTECTION

All digital inputs are protected with a series input resistor and parallel Zener ESD structures shown in Figure 10; applies to digital input pins, SDA, SCL, and SHDN.

340⍀

LOGIC

Figure 10a. ESD Protection of Digital Pins

POWER-UP SEQUENCE

Since there are ESD protection diodes that limit the voltage compliance at terminals A, B, and W (see Figure 11), it is important to power V

before applying any voltage to

DD/VSS

terminals A, B, and W. Otherwise, the diode will be forward biased such that V

will be powered unintentionally and

DD/VSS

may affect the rest of the user’s circuit. The ideal power-up sequence is in the following order: GND, V inputs, and V

. The order of powering VA, VB, VW, and

A/B/W

, VSS, digital

digital inputs is not important as long as they are powered

DD/VSS

after V

LAYOUT AND POWER SUPPLY BYPASSING

It is a good practice to employ compact, minimum lead length layout design. The leads to the input should be as direct as possible with a minimum conductor length. Ground paths should have low resistance and low inductance.

Similarly, it is also a good practice to bypass the power supplies with quality capacitors for optimum stability. Supply leads to the device should be bypassed with 0.01 µF to 0.1 µF disc or chip ceramics capacitors. Low ESR 1 µF to 10 µF tantalum or electrolytic capacitors should also be applied at the supplies to minimize any transient disturbance and filter low frequency ripple (see Figure 12). Notice the digital ground should also be joined remotely to the analog ground at one point to minimize the digital ground bounce.

AD5280/AD5282

10␮F

0.1␮F

VSSGND

A, B, W

Figure 10b. ESD Protection of Resistor Terminals

TERMINAL VOLTAGE OPERATING RANGE

The AD5280/AD5282 positive VDD and negative VSS power supply defines the boundary conditions for proper 3-terminal digital potentiometer operation. Supply signals present on terminals A, B, and W that exceed V

or VSS will be clamped by

the internal forward biased diodes (see Figure 11).

A W B

Figure 11. Maximum Terminal Voltages Set by

and V

Figure 12. Power Supply Bypassing

APPLICATIONS Bipolar DC or AC Operation from Dual Supplies

The AD5280/AD5282 can be operated from dual supplies enabling control of ground referenced ac signals or bipolar operation. The ac signal, as high as V

, can be applied

DD/VSS

directly across terminals A–B with the output taken from terminal W. See Figure 13 for a typical circuit connection.

+5.0V

␮C

SCLK

MOSI

GND

SCL

SDA

GND

AD5282

ⴞ2.5V p-p

D = 80

ⴞ5V p-p

–5.0V

Figure 13. Bipolar Operation from Dual Supplies

REV. 0–14–

AD5280/AD5282

Gain Control Compensation

The digital potentiometer is commonly used in gain control such as the noninverting gain amplifier shown in Figure 14.

200k

4.7pF

47k

25pF

Figure 14. Typical Noninverting Gain Amplifier

Notice the RDAC B terminal parasitic capacitance is connected to the op amp noninverting node. It introduces a zero for the 1/␤

␱

term with 20 dB/dec, whereas a typical op amp GBP has –20 dB/dec characteristics. A large R2 and finite C1 can cause this zero’s frequency to fall well below the crossover frequency. Thus the rate of closure becomes 40 dB/dec and the system has 0° phase margin at the crossover frequency. The output may ring or oscillate if the input is a rectangular pulse or step function. Similarly, it is also likely to ring when switching between two gain values because this is equivalent to a step change at the input.

Depending on the op amp GBP, reducing the feedback resistor may extend the zero’s frequency far enough to overcome the problem. A better approach is to include a compensation capacitor C2 to cancel the effect caused by C1. Optimum compensation occurs when R1 × C1 = R2 × C2. This is not an option because of the variation of R2. As a result, one may use the relationship above and scale C2 as if R2 is at its maximum value. Doing so may overcompensate and compromise the performance slightly when R2 is set at low values. However, it will avoid the gain peaking, ringing, or oscillation at the worst case. For critical applications, C2 should be found empirically to suit the need. In general, C2 in the range of a few pF to no more than a few tenths of pF is usually adequate for the compensation.

Similarly, there are W and A terminal capacitances connected to the output (not shown); fortunately their effect at this node is less significant and the compensation can be avoided in most cases.

Programmable Voltage Reference

For Voltage Divider Mode operation, Figure 15, it is common to buffer the output of the digital potentiometer unless the load is much larger than R

. Not only does the buffer serve the

purpose of impedance conversion, it also allows a heavier load to be driven.

GND

OUT

AD1582

AD5280

AD8601

V+

V–

Figure 15. Programmable Voltage Reference

8-Bit Bipolar DAC

Figure 16 shows a low cost, 8-bit, bipolar DAC. It offers the same number of adjustable steps but not the precision as compared to the conventional DACs. The linearity and temperature coefficients, especially at low value codes, are skewed by the effects of the digital potentiometer wiper resistance. The output of this circuit is:





O REF

256



TRIM

GND

OUT

ADR425

1–

+5V

 



REF

R R

+15V

OP2177

–15V

+15V

OP2177

–15V

5V

REF

U2 = AD5280

(5)

Figure 16. 8-Bit Bipolar DAC

Bipolar Programmable Gain Amplifier

For applications that require bipolar gain, Figure 17 shows one implementation similar to the previous circuit. The digital potentiometer, U

can therefore be programmed between Vi and –KVi at a

given U

, sets the adjustment range. The wiper voltage at

setting. Configuring A2 in the Noninverting Mode

allows linear gain and attentuation. The transfer function is:

where K is the ratio of R



 

AD5282





××+





12256





WB1/RWA1

V+

OP2177

1()–

set by U1.

V–

–kVi

 



OP2177

(6)

V+

V–

Figure 17. Bipolar Programmable Gain Amplifier

Similar to the previous example, in the simpler (and much more usual) case, where K = 1, a single digital potentiometer AD5280 is used and U apply V

is replaced by a matched pair of resistors to

and –Vi at the ends of the digital potentiometer. The

relationship becomes:

2122















256







×1

1–

 

(7)

If R2 is large, a few pF compensation capacitor may be needed to avoid any gain peaking.

REV. 0

–15–

AD5280/AD5282

Table III shows the result of adjusting D, with A2 configured as a unity gain, a gain of 2, and a gain of 10. The result is a bipolar amplifier with linearly programmable gain and 256-step resolution.

Table III. Result of Bipolar Gain Amplifier

DR1 = , R2 = 0 R1 = R2 R2 = 9R1

0–1 –2 –10

64 –0.5 –1 –5

128 0 0 0

192 0.5 1 5

255 0.968 1.937 9.680

Programmable Voltage Source with Boosted Output

For applications that require high current adjustments such as a laser diode driver or tunable laser, a boosted voltage source can be considered (see Figure 18).

V+

V–

SIGNAL

U1 = AD5280

= AD8601, AD8605, AD8541

= FDV301N, 2N7002

BIAS

Figure 18. Programmable Booster Voltage Source

In this circuit, the inverting input of the op amp forces the V

BIAS

to be equal to the wiper voltage set by the digital potentiometer. The load current is then delivered by the supply via the N-Ch FET N1. N1’s power handling must be adequate to dissipate

) × IL power. This circuit can source a maximum of

i–VO

100 mA with a 5 V supply. A1 needs to be a rail-to-rail input type. Fore precision applications, a voltage reference such as ADR423, ADR292, or AD1584 can be applied at the input of the digital potentiometer.

Programmable 4 to 20 mA Current Source

A programmable 4 to 20 mA current source can be implemented with the circuit shown in Figure 19. REF191 is a unique, low supply headroom and high current handling precision reference that can deliver 20 mA at 2.048 V. The load current is simply the voltage across terminals B to W of the digital potentiometer divided by R

REF

× 2

(8)

+5V

SLEEP

REF191

GND

–2.048V TO V

OUT

AD5280

0 TO (2.048 + VL)

1F

+5V

V+

OP8510

V–

–5V

–

100

102

Figure 19. Programmable 4 to 20 mA Current Source

The circuit is simple, but beware of two things. First, dual supply op amps are ideal because the ground potential of REF191 can swing from –2.048 V at zero scale to V

at full scale of the

potentiometer setting. Although the circuit works under single supply, the programmable resolution of the system will be reduced.

For applications that demand higher current capabilities, a few changes to the circuit in Figure 19 will produce an adjustable current in the range of hundreds of mA. First, the voltage reference needs to be replaced with a high current, low dropout regulator, such as the ADP3333, and the op amp needs to be swapped with a high current dual-supply model, such as the AD8532. Depending on the desired range of current, an appropriate value for RS must be calculated. Because of the high current flowing to the load, the user must pay attention to the load impedance so as not to drive the op amp beyond the positive rail.

Programmable Bidirectional Current Source

For applications that require bidirectional current control or higher voltage compliance, a Howland current pump can be a solution (see Figure 20). If the resistors are matched, the load current is:

()22

AD5280

+5V

–5V

+15V

V+

OP2177

V–

–

–15V

15k

+15V

–

V+

OP2177

V–

–15V

14.95k



10pF



150k



R2 50

R 500

(9)



Figure 20. Programmable Bidirectional Current Source

REV. 0–16–

AD5280/AD5282

or f

R2B in theory can be made as small as needed to achieve the

current needed within A

’s output current driving capability. In

this circuit, OP2177 can deliver ±5 mA in either direction, and the voltage compliance approaches 15 V. It can be shown that the output impedance is:

RRRR

×+

1212

RR RR R

12 12 2

()

′

–( )

′′

(10)

This output impedance can be infinite if resistors R1' and R2' match precisely with R1 and R2A + R2B, respectively. On the other hand, it can be negative if the resistors are not matched. As a result, C1 in the range of 1 pF to 10 pF, is needed to prevent the oscillation.

Programmable Low-Pass Filter

In A/D conversion applications, it is common to include an antialiasing filter to band-limit the sampling signal. Dual-channel digital potentiometers can be used to construct a second order Sallen Key low-pass filter (see Figure 21). The design equations are:

RC R C

11122

RRCC

1212

(11)

(12)

(13)

Users can first select some convenient values for the capacitors. To achieve maximally flat bandwidth where Q = 0.707, let C1 be twice the size of C2 and let R1 = R2. As a result, the user can adjust R1 and R2 to the same settings to achieve the desirable bandwidth.

+2.5V

R2R1

ADJUSTED TO

SAME SETTING

V+

AD8601

V–

–2.5V

Figure 21. Sallen Key Low-Pass Filter

PROGRAMMABLE OSCILLATOR

In a classic Wien-bridge oscillator (Figure 22), the Wien network (R, R', C, C') provides positive feedback, while R1 and R2 provide negative feedback. At the resonant frequency, fo, the overall phase shift is zero, and the positive feedback causes the circuit to oscillate. With R = R', C = C', and R2 = R2

), the oscillation frequency is:

diode

//(R2B +

(14)

where R is equal R

256

–

256

such that:

(15)

At resonance, setting:

RR2

(16)

balances the bridge. In practice, R2/R1 should be set slightly larger than 2 to ensure the oscillation can start. On the other hand, the alternate turn-on of the diodes D1 and D2 ensures that R2/R1 are smaller than 2 momentarily, and therefore stabilizes the oscillation.

Once the frequency is set, the oscillation amplitude can be tuned by R2

2 3

, ID, and VD are interdependent variables. With proper

selection of R2

since:

ODBD

2VIR V

, an equilibrium will be reached such that V

(17)

converges. R2B can be in series with a discrete resistor to increase the amplitude, but the total resistance cannot be too large to prevent saturation of the output.

FREQUENCY

ADJUSTMENT

10k

2.2nF

R1 = R1' = R2B = AD5282 D1 = D2 = 1N4148

1k

2.2nF

+2.5V

OP1177

–2.5V

10k

V+

V–

2.1k

AMPLITUDE ADJUSTMENT

Figure 22. Programmable Oscillator with Amplitude Control

REV. 0

–17–

AD5280/AD5282

Resistance Scaling

AD5280/AD5282 offers 20 kΩ, 50 kΩ, and 200 kΩ nominal resistance. Users who need a lower resistance and the same number of step adjustments can place multiple devices in parallel. For example, Figure 23 shows a simple scheme of paralleling both channels of the AD5282. To adjust half of the resistance linearly per step, users need to program both channels to the same settings.

Figure 23. Reduce Resistance by Half with Linear Adjustment Characteristics

Applicable only to the Voltage Divider Mode, by paralleling a discrete resistor as shown in Figure 24, a proportionately lower voltage appears at terminal A. This translates into a finer degree of precision because the step size at terminal W will be smaller. The voltage can be found as:

=×

()

256 3 //

 



R2 R1

VDD



RR2

(//)





(18)

RDAC CIRCUIT SIMULATION MODEL

RDAC

25pF

20k

55pF

25pF

Figure 26. RDAC Circuit Simulation Model for RDAC = 20 k

Ω

The internal parasitic capacitances and the external capacitive loads dominate the ac characteristics of the RDACs. Configured as a potentiometer divider, the –3 dB bandwidth of the AD5280 (20 kΩ resistor) measures 310 kHz at half scale. TPC 19 provides the large signal BODE plot characteristics of the three available resistor versions—20 kΩ, 50 kΩ, and 200 kΩ. A parasitic simulation model is shown in Figure 26. A macro model net list for the 20 kΩ RDAC is provided.

Macro Model Net List for RDAC

.PARAM D=256, RDAC=20E3

.SUBCKT DPOT (A,W,B)

CA A 0 25E-12 RWA A W {(1-D/256)*RDAC+60} CW W 0 55E-12 RWB W B {D/256*RDAC+60} CB B 0 25E-12

.ENDS DPOT

Figure 24. Lowering the Nominal Resistance

Figures 23 and 24 show that the digital potentiometers change steps linearly. On the other hand, log taper adjustment is usually preferred in applications like volume control. Figure 25 shows another way of resistance scaling. In this circuit, the smaller the R2 with respect to R

, the more the pseudo log

taper characteristic behaves.

Figure 25. Resistor Scaling with Log Adjustment Characteristics

REV. 0–18–

AD5280/AD5282

AD8601

Resistance Tolerance, Drift, and Temperature Coefficient Mismatch Considerations

In a Rheostat Mode operation such as gain control, Figure 27, the tolerance mismatch between the digital potentiometer and the discrete resistor can cause repeatability issues among various systems. Because of the inherent matching of the silicon process, it is practical to apply the dual-channel device in this type of application. As such, R1 should be replaced by one of the channels of the digital potentiometer. R1 should be programmed to a specific value while R2 can be used for the adjustable gain. Although it adds cost, this approach minimizes the tolerance and temperature coefficient mismatch between R1 and R2. In addition, this approach also tracks the resistance drift over time. As a result, these nonideal parameters become less sensitive to the system variations.

R1*

*REPLACED WITH ANOTHER CHANNEL OF RDAC

AD8601

Figure 27. Linear Gain Control with Tracking Resistance Tolerance and Drift

Notice the circuit in Figure 28 can also be used to track the tolerance, temperature coefficient, and drift in this particular application. However, the characteristics of the transfer function change from a linear to pseudo-logarithmic gain function.

Figure 28. Nonlinear Gain Control with Tracking Resistance Tolerance and Drift

REV. 0

–19–

AD5280/AD5282

OUTLINE DIMENSIONS

14-Lead Thin Shrink Small Outline Package (TSSOP)

(RU-14)

Dimensions shown in millimeters

5.10

5.00

4.90

1.05

1.00

0.80

4.50

4.40

4.30

PIN 1

0.65

BSC

0.15

0.05

COMPLIANT TO JEDEC STANDARDS MO-153AB-1

0.30

0.19

6.40 BSC

1.20 MAX

SEATING PLANE

0.20

0.09

COPLANARITY

0.10

8 0

16-Lead Thin Shrink Small Outline Package (TSSOP)

(RU-16)

Dimensions shown in millimeters

5.10

5.00

4.90

0.15

0.05

4.50

4.40

4.30

PIN 1

0.65 BSC

COPLANARITY

COMPLIANT TO JEDEC STANDARDS MO-153AB

0.10

0.30

0.19

1.20 MAX

6.40

BSC

SEATING

PLANE

0.20

0.09

0.75

8 0

0.60

0.45

C02929–0–10/02(0)

0.75

0.60

0.45

–20–

PRINTED IN U.S.A.

REV. 0

Datasheet AD5280 Datasheet (Analog Devices)

Specifications and Main Features

Frequently Asked Questions

User Manual

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAMS

ABSOLUTE MAXIMUM RATINGS

ORDERING GUIDE

PIN CONFIGURATION

AD5280 PIN CONFIGURATION

AD5280 PIN FUNCTION DESCRIPTION

AD5282 PIN CONFIGURATION

AD5282 PIN FUNCTION DESCRIPTION

TEST CIRCUITS

OPERATION

READBACK RDAC VALUE

ADDITIONAL PROGRAMMABLE LOGIC OUTPUT

MULTIPLE DEVICES ON ONE BUS

LEVEL SHIFT FOR BIDIRECTIONAL INTERFACE

SELF-CONTAINED SHUTDOWN FUNCTION

LEVEL SHIFT FOR NEGATIVE VOLTAGE OPERATION

ESD PROTECTION

POWER-UP SEQUENCE

LAYOUT AND POWER SUPPLY BYPASSING

TERMINAL VOLTAGE OPERATING RANGE

Gain Control Compensation

Programmable Voltage Reference

8-Bit Bipolar DAC

Bipolar Programmable Gain Amplifier

Programmable Voltage Source with Boosted Output

Programmable 4 to 20 mA Current Source

Programmable Bidirectional Current Source

Programmable Low-Pass Filter

PROGRAMMABLE OSCILLATOR

Resistance Scaling

RDAC CIRCUIT SIMULATION MODEL

Macro Model Net List for RDAC

Resistance Tolerance, Drift, and Temperature Coefficient Mismatch Considerations

OUTLINE DIMENSIONS