Page 1
Quad, 15 V, 256-Position, Digital
Potentiometer with Pin Selectable SPI/I
FEATURES
256-position, 4-channel
End-to-end resistance 20 kΩ, 50 kΩ, 200 kΩ
Pin selectable SPI® or I
Power-on preset to midscale
Two package address decode pins AD0 and AD1
Rheostat mode temperature coefficient 30 ppm/°C
Voltage divider temperature coefficient 5 ppm/°C
Wide operating temperature range –40°C to +125°C
5 V to 15 V single supply; ±5 V dual supply
APPLICATIONS
Mechanical potentiometer replacement
Optical network adjustment
Instrumentation: gain, offset adjustment
Stereo channel audio level control
Automotive electronics adjustment
Programmable power supply
Programmable filters, delays, time constants
Line impedance matching
Low resolution DAC/trimmer replacement
Base station power amp biasing
Sensor calibration
GENERAL DESCRIPTION
The AD5263 is the industry’s first quad-channel, 256-position,
digital potentiometer
device performs the same electronic adjustment function as
mechanical potentiometers or variable resistors, with enhanced
resolution, solid-state reliability, and superior low temperature
coefficient performance.
Each channel of the AD5263 offers a completely programmable
value of resistance between the A terminal and the wiper, or
between the B terminal and the wiper. The fixed A-to-B
terminal resistance of 20 kΩ, 50 kΩ, or 200 kΩ has a nominal
temperature coefficient of ±30 ppm/°C and a ±1% channel-to-
2
C® compatible interface
1
with a selectable digital interface. This
2
AD5263
channel matching tolerance. Another key feature of this part is
the ability to operate from +4.5 V to +15 V, or at ±5 V.
Wiper position programming presets to midscale upon poweron. Once powered, the VR wiper position is programmed by
either the 3-wire SPI or 2-wire I
2
I
C mode, additional programmable logic outputs enable users
to drive digital loads, logic gates, and analog switches in their
systems.
The AD5263 is available in a narrow body TSSOP-24. All parts
are guaranteed to operate over the automotive temperature
range of –40°C to +125°C.
For single- or dual-channel applications, refer to the
AD5260/AD5280 or AD5262/AD5282.
FUNCTIONAL BLOCK DIAGRAM
A1
V
DD
V
SS
SHDN
RES/AD1
V
L
CLK/SCL
SDI/SDA
CS/AD0
GND
1
The terms digital potentiometer, VR, and RDAC are used interchangeably.
Purchase of licensed I2C components of Analog Devices or one of its sublicensed
Associated Companies conveys a license for the purchaser under the Philips I
Patent Rights to use these components in an I
conforms to the I
W1 B1 A2
RDAC 1
REGISTER
2
C Standard Specification as defined by Philips.
REGISTER
ADDRESS
DECODER
2
SPI/I
C
SELECT
LOGIC
DIS
2
C compatible interface. In the
W2 B2
RDAC 2
SERIAL INPUT
Figure 1.
REGISTER
A3
RDAC 3
REGISTER
8
NC/O2
W3
B3 A4
SDO/O1
2
C system, provided that the system
W4 B4
RDAC 4
REGISTER
AD5263
2
C
C
03142-0-001
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.326.8703 © 2003 Analog Devices, Inc. All rights reserved.
Page 2
AD5263
TABLE OF CONTENTS
Electrical Characteristics—20 kΩ, 50 kΩ, 200 kΩ Versions ....... 3
Applications..................................................................................... 20
Timing Characteristics—20 kΩ, 50 kΩ, 200 kΩ Versions........... 4
Absolute Maximum Ratings............................................................ 5
Typical Performance Characteristics ............................................. 6
Test Circuits..................................................................................... 11
SPI Compatible Digital Interface (DIS = 0)................................ 12
I2C Compatible Digital Interface (DIS = 1).................................13
Operation......................................................................................... 14
Programming the Variable Resistor .........................................14
Programming the Potentiometer Divider ............................... 15
Pin Selectable Digital Interface................................................. 15
SPI Compatible 3-Wire Serial Bus (DIS = 0).......................... 15
I2C Compatible 2-Wire Serial Bus (DIS = 1) .......................... 16
Additional Programmable Logic Output ................................17
Self-Contained Shutdown Function ........................................ 17
Multiple Devices on One Bus ...................................................17
Level Shift for Negative Voltage Operation............................. 17
ESD Protection ........................................................................... 18
Terminal Voltage Operating Range.......................................... 18
Power-Up Sequence ................................................................... 18
V
Power Supply ................................................................... 18
LOGIC
Layout and Power Supply Bypassing ....................................... 18
Bipolar DC or AC Operation from Dual Supplies................. 20
Gain Control Compensation.................................................... 20
Programmable Voltage Reference ............................................ 20
8-Bit Bipolar DAC ...................................................................... 21
Bipolar Programmable Gain Amplifier................................... 21
Programmable Voltage Source with Boosted Output............ 21
Programmable 4–20 mA Current Source ............................... 22
Programmable Bidirectional Current Source......................... 22
Programmable Low-Pass Filter ................................................ 23
Programmable Oscillator.......................................................... 23
Resistance Scaling ...................................................................... 24
Resistance Tolerance, Drift, and Temperature Coefficient
Mismatch Considerations
Pin Configuration and Pin Function Descriptions.................... 25
Pin Configuration ...................................................................... 25
Pin Function Descriptions........................................................ 25
Outline Dimensions....................................................................... 26
ESD Caution................................................................................ 26
Ordering Guide............................................................................... 26
......................................................... 24
RDAC Circuit Simulation Model ............................................. 19
REVISION HISTORY
Revision 0: Initial Version
Rev. 0 | Page 2 of 28
Page 3
AD5263
ELECTRICAL CHARACTERISTICS—20 kΩ, 50 kΩ, 200 kΩ VERSIONS
(VDD = +5 V, VSS = –5 V, VL = +5 V, VA = +VDD, VB = 0 V, –40°C < TA < +125°C, unless otherwise noted.)
Table 1.
Parameter Symbol Conditions Min Typ1 Max Unit
DC CHARACTERISTICS—RHEOSTAT MODE (Specifications apply to all VRs.)
Resistor Differential NL2 R-DNL RWB, VA=NC –1 ±1/4 +1 LSB
Resistor Nonlinearity2 R-INL RWB, VA=NC –1 ±1/2 +1 LSB
Nominal Resistor Tolerance3 ∆RAB T
∆RWB/∆T 30 ppm/°C Resistance Mode Temperature
Coefficient
∆RWA/∆T 30 ppm/°C
Wiper Resistance RW I
DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE (Specifications apply to all VRs.)
Resolution N 8 Bits
Differential Nonlinearity4 DNL –1 ±1/4 +1 LSB
Integral Nonlinearity4 INL –1 ±1/2 +1 LSB
Voltage Divider Temperature Coefficient ∆VW/∆T Code = 0x80 5 ppm/°C
Full-Scale Error V
Zero-Scale Error V
Code = 0xFF –2 –1 +0 LSB
WFSE
Code = 0x00 0 +1 +2 LSB
WZSE
RESISTOR TERMINALS
Voltage Range5 V
Capacitance6 Ax, Bx C
V
A,B,W
f = 1 MHz, measured to GND, Code = 0x80 25 pF
A,B
Capacitance6 Wx CW f = 1 MHz, measured to GND, Code = 0x80 55 pF
Common-Mode Leakage ICM V
Shutdown Current
7
I
0.02 5 µA
SHDN
DIGITAL INPUTS
Input Logic High VIH 2.4 V
Input Logic Low VIL 0.8 V
Input Logic High (SDA and SCL) VIH V
Input Logic Low (SDA and SCL) VIL V
Input Current IIL V
Input Capacitance6 C
5 pF
IL
DIGITAL OUTPUTS
SDA VOL I
VOL I
O1, O2 VOH I
O1, O2 VOL I
SDO VOH R
SDO VOL I
Three-State Leakage Current IOZ V
Output Capacitance6 C
3 8 pF
OZ
POWER SUPPLIES
Logic Supply
Power Single-Supply Range V
Power Dual-Supply Range V
Logic Supply Current
8
9
VL 2.7 5.5 V
DD RANGE
DD/SS RANGE
I
L
Positive Supply Current IDD V
Negative Supply Current ISS V
Power Dissipation10 P
V
DISS
Power Supply Sensitivity PSS ∆VDD = +5 V ± 10% 0.002 0.01 %/%
DYNAMIC CHARACTERISTICS
6, 11
Bandwidth (3 dB) BW RAB = 20 kΩ/50 kΩ/200 kΩ 300/150/35 kHz
Total Harmonic Distortion THDW V
VW Settling Time
Resistor Noise Voltage e
12
tS V
RWB = 10 kΩ, f = 1 kHz, RS = 0 9
N_WB
= 25°C –30 30 %
A
= 1 V/RAB 60 150 Ω
W
V
SS
= VB = VDD/2 1 nA
A
= 0 V 0.7 × VL VL + 0.5 V
SS
= 0 V –0.5 0.3 × VL V
SS
= 0 V or +5 V ±1 µA
IN
= 3 mA 0.4 V
SINK
= 6 mA 0.6 V
SINK
= 40 µA 4 V
SOURCE
= 1.6 mA 0.4 V
SINK
= 2.2 kΩ to VDD V
L
= 3 mA 0.4 V
SINK
= 0 V or +5 V ±1 µA
IN
– 0.1 V
DD
V
DD
VSS = 0 V VL 16.5 V
±4.5 ±7.5 V
V
= +5 V 25 60 µA
L
= +5 V or VIL = 0 V 1 µA
IH
= –5 V 1 µA
SS
= +5 V or VIL = 0 V, VDD = +5 V, VSS = –5 V 0.6 mW
IH
= 1 V rms, VB = 0 V, f = 1 kHz, RAB = 20 kΩ 0.05 %
A
= 10 V, VB = 0 V, ±1 LSB error band 2 µs
A
Hz
nV/√
Rev. 0 | Page 3 of 28
Page 4
AD5263
TIMING CHARACTERISTICS—20 kΩ, 50 kΩ, 200 kΩ VERSIONS
(V
= +5 V, V
DD
Table 2.
Parameter Symbol Conditions Min Typ1 Max Unit
SPI INTERFACE TIMING CHARACTERISTICS (Specifications Apply to All Parts
Clock Frequency f
Input Clock Pulsewidth tCH,tCL Clock level high or low 20 ns
Data Setup Time tDS 10 ns
Data Hold Time tDH 10 ns
CS Setup Time
CS High Pulsewidth
CLK Fall to CS Fall Hold Time
CLK Fall to CS Rise Hold Time
CS Rise to Clock Rise Setup
Reset Pulsewidth t
I2C INTERFACE TIMING CHARACTERISTICS (Specifications Apply to All Parts
SCL Clock Frequency f
t
Bus Free Time between STOP and START t1 1.3 µs
BUF
t
t
t
t
t
t
Hold Time (Repeated START) t2
HD;STA
Low Period of SCL Clock t3 1.3 µs
LOW
High Period of SCL Clock t4 0.6 50 µs
HIGH
Setup Time for START Condition t5 0.6 µs
SU;STA
HD;DAT
Data Setup Time t7 100 ns
SU;DAT
tF Fall Time of both SDA and SCL Signals t8 300 ns
tR Rise Time of Both SDA and SCL Signals t9 300 ns
t
NOTES
1
2
3
4
5
6
7
8
9
10
11
12
13
Setup Time for STOP Condition t10 0.6 µs
SU;STO
Typicals represent average readings at 25°C and VDD = +5 V, VSS = –5 V.
Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. IW = VDD/R for both VDD = +5 V and
VSS = –5 V.
VAB = VDD, Wiper (VW) = no connect.
INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
Resistor Terminals A, B, and W have no limitations on polarity with respect to each other.
Guaranteed by design and not subject to production test.
Measured at the Ax terminals. All Ax terminals are open circuited in shutdown mode.
VL is limited to VDD or 5.5 V, whichever is less.
Worst-case supply current consumed when all logic-input levels set at 2.4 V, standard characteristic of CMOS logic.
P
is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
DISS
All dynamic characteristics use VDD = +5 V, VSS = –5 V, VL = +5 V.
Settling time depends on value of VDD, RL, and CL.
See timing diagrams for location of measured values. All input control voltages are specified with tR = tF = 2 ns (10% to 90% of +3 V) and timed from a voltage level
of 1.5 V. Switching characteristics are measured using V
= –5 V, VL = +5 V, VA = +VDD, VB = 0 V, –40°C < TA < +125°C unless otherwise noted.)
SS
6, 13
)
25 MHz
CLK
15 ns
t
CSS
t
20 ns
CSW
t
0 ns
CSH0
t
0 ns
CSH1
10 ns
t
CS1
RS
400 kHz
SCL
6, 13
)
After this period, the first clock
5 ns
0.6 µs
pulse is generated.
Data Hold Time t6 0.9 µs
= +5 V.
L
Rev. 0 | Page 4 of 28
Page 5
AD5263
ABSOLUTE MAXIMUM RATINGS
(TA = +25°C, unless otherwise noted.)
Table 3.
Parameter Value
VDD to GND –0.3 V to +16.5 V
VSS to GND 0 V to +7.5 V
VDD to VSS +16.5 V
VL to GND –0.3 V to +6.5 V
VA, VB, VW to GND VSS to V
DD
Terminal Current, Ax-Bx, Ax-Wx, Bx-Wx
Pulsed1 ±20 mA
Continuous ±3 mA
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Digital Inputs and Output Voltage to GND 0 V to +7 V
Operating Temperature Range –40°C to +85°C
Maximum Junction Temperature (T
) 150°C
J MAX
Storage Temperature –65°C to +150°C
Lead Temperature (Soldering, 10 sec) 300°C
Vapor Phase (60 sec) 215°C
Infrared (15 sec) 220°C
Thermal Resistance2 θJA
TSSOP-24 143°C/W
1
Maximum terminal current is bounded by the maximum current handling of
the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.
2
Package power dissipation: (T
JMAX
– TA)/θJA.
Rev. 0 | Page 5 of 28
Page 6
AD5263
TYPICAL PERFORMANCE CHARACTERISTICS
(RAB = 20 kΩ unless otherwise noted.)
1
±5V
15/0V
03142-0-073
RHEOSTAT MODE DNL (LSB)
0.6
0.4
0.2
–0.2
–0.4
–0.6
–0.8
0.8
0
–1
32
64 96 1280
CODE (Decimal)
Figure 2. R-DNL vs. Code vs. Supply Voltage
160 192 224 256
1
0.8
0.6
0.4
0.2
0
–0.2
–0.4
RHEOSTAT MODE INL (LSB)
–0.6
–0.8
–1
32
64 96 1280
Figure 5. R-INL vs. Code; V
CODE (Decimal)
–40°C
25°C
85°C
125°C
160 192 224 256
= ±5 V
DD
03142-0-004
1
0.8
0.6
0.4
0.2
0
–0.2
–0.4
RHEOSTAT MODE INL (LSB)
–0.6
–0.8
–1
32
64 96 1280
Figure 3. R-INL vs. Code vs. Supply Voltage
1
0.8
0.6
0.4
0.2
0
–0.2
–0.4
RHEOSTAT MODE DNL (LSB)
–0.6
–0.8
–1
32
64 96 1280
Figure 4. R-DNL vs. Code; V
CODE (Decimal)
CODE (Decimal)
±5V
15/0V
160 192 224 256
–40°C
25°C
85°C
125°C
160 192 224 256
= ±5 V
DD
03142-0-002
03142-0-003
1
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
POTENTIOMETER MODE INL (LSB)
–0.8
–1
32
64 96 1280
CODE (Decimal)
160 192 224 256
±5V
15/0V
03142-0-005
Figure 6. INL vs. Code vs. Supply Voltage
1
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
POTENTIOMETER MODE DNL (LSB)
–0.8
–1
32
64 96 1280
CODE (Decimal)
160 192 224 256
±5V
15/0V
03142-0-006
Figure 7. DNL vs. Code vs. Supply Voltage
Rev. 0 | Page 6 of 28
Page 7
AD5263
POTENTIOMETER MODE INL (LSB)
0.8
0.6
0.4
0.2
–0.2
–0.4
–0.6
–0.8
1
–40°C
25°C
85°C
125°C
0
–1
32
64 96 1280
CODE (Decimal)
Figure 8. INL vs. Code; V
160 192 224 256
= ±5 V
DD
03142-0-007
2
VDD/VSS = 4.5/0V
1.8
1.6
1.4
1.2
1
0.8
ZSE (LSB)
0.6
0.4
0.2
0
–20
0
VDD/VSS = ±5V
VDD/VSS = 16.5/0V
40 100
20 60 80–40
TEMPERATURE (°C)
03142-0-010
120
Figure 11. Zero-Scale Error vs. Temperature
1
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
POTENTIOMETER MODE DNL (LSB)
–0.8
–1
0
–0.5
–1
–1.5
FSE (LSB)
–2
32
64 96 1280
Figure 9. DNL vs. Code; V
VDD/VSS = 4.5/0V
CODE (Decimal)
VDD/VSS = ±5V
–40°C
25°C
85°C
125°C
160 192 224 256
= ±5 V
DD
VDD/VSS = 16.5/0V
03142-0-008
SUPPLY CURRENT (µA)
SS
/I
DD
I
0.001
SHUTDOWN CURRENT (µA)
0.01
0.1
0.01
10
1
0.1
ISS@ VDD/VSS = ±5V
IDD @ VDD/VSS = 15/0V
0
40
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 12. Supply Current vs. Temperature
10
1
VDD/VSS = ±5V
VDD/VSS = 15/0V
V
= 5V
LOGIC
= 5V
V
IH
= 0V
V
IL
IDD@VDD/VSS = ±5V
80–40
120
03142-0-011
–2.5
20 60 80–40
–20
0
40 100
TEMPERATURE (°C)
Figure 10. Full-Scale Error vs. Temperature
03142-0-009
120
Rev. 0 | Page 7 of 28
0.001
0
40
TEMPERATURE (°C)
80–40
Figure 13. Shutdown Current vs. Temperature
03142-0-012
120
Page 8
AD5263
27
26
25
(µA)
LOGIC
24
I
VDD/VSS = 15/0V
VDD/VSS = ±5V
150
100
–50
–100
20k
Ω
50k
Ω
200k
50
0
Ω
23
22
0
Figure 14. I
85
80
75
70
65
60
WIPER RESISTANCE (Ω)
55
50
45
0
40
TEMPERATURE (°C)
vs. Temperature
LOGIC
RON @ VDD/VSS = 15/0V
510–5 15
V
(V)
BIAS
Figure 15. Wiper ON Resistance vs. Bias Voltage
80–40
RON @ VDD/VSS = 5/0V
RON @ VDD/VSS = ±5V
120
03142-0-013
03142-0-014
–150
–200
POTENTIOMETER MODE TEMPCO (ppm/°C)
–250
32
64 96 1280
CODE (Decimal)
Figure 17. Potentiometer Mode Tempco ∆R
0
–6
–12
–18
–24
–30
–36
GAIN (dB)
–42
–48
–54
–60
1k
0x80
0x40
0x20
0x10
0x08
0x04
0x02
0x01
FREQUENCY (Hz)
Figure 18. Gain vs. Frequency vs. Code; R
160 192 224 256
/∆T vs. Code
WB
= 25°C
T
A
= 50mV rms
V
A
=±5V
V
DD/VSS
100k10k
= 20 kΩ
AB
1M
03142-0-016
03142-0-017
700
500
300
100
–100
–300
RHEOSTAT MODE TEMPCO (ppm/°C)
–500
–700
32
64 96 1280
CODE (Decimal)
Figure 16. Rheostat Mode Tempco ∆R
20kΩ
50kΩ
200kΩ
160 192 224 256
/∆T vs. Code
WB
03142-0-015
Rev. 0 | Page 8 of 28
0
–6
–12
–18
–24
–30
–36
GAIN (dB)
–42
–48
–54
–60
1k
0x80
0x40
0x20
0x10
0x08
0x04
0x02
0x01
FREQUENCY (Hz)
Figure 19. Gain vs. Frequency vs. Code; R
TA = 25°C
=50mVrms
V
A
=±5V
V
DD/VSS
100k10k
03142-0-018
1M
= 50 kΩ
AB
Page 9
AD5263
0
–6
–12
–18
–24
–30
–36
GAIN (dB)
–42
–48
–54
–60
1k
Figure 20. Gain vs. Frequency vs. Code; R
0x80
0x40
0x20
0x10
0x08
0x04
0x02
0x01
FREQUENCY (Hz)
TA = 25°C
= 50mV rms
V
A
V
DD/VSS
= 200 kΩ
AB
=±5V
Code = 0x80
VDD/VSS = ±5.5V
=±5V
V
B/VA
V
1
03142-0-019
100k10k
Ch 1 50.0mV M 100ns A CH2 2.70 V
Figure 23. Digital Feedthrough
W
03142-0-022
GAIN (dB)
PSRR (–dB)
–12
–18
–24
–30
–36
–42
–48
–54
–60
–6
80
60
40
20
0
0
1k
100
Figure 21. –3 db Bandwidth
+PSRR @
V
= ±5V DC ± 10% p-p AC
DD/VSS
Figure 22. PSRR v s. Frequency
R = 50kΩ
150kHz
R = 200kΩ
35kHz
TA = 25°C
V
V
FREQUENCY (Hz)
CODE = 0x80, VA = VDD, VB = 0V
–PSRR @
V
DD/VSS
FREQUENCY (Hz)
100k10k
= ±5V DC ± 10% p-p AC
10k1k
100k
R = 20kΩ
300kHz
= ±5V
DD/VSS
= 50mV rms
A
1M
1M
03142-0-020
03142-0-021
T
1
Ch 1 50.0mV T 20.00% M 2.00µs A CH2 2.00 V
VDD/VSS = 5/0V
= 5V
V
A
= 0V
V
B
Figure 24. Midscale Glitch; Code 0x80–ox7F
(4.7 nF Capacitor Used from Wiper to Ground)
VDD/VSS = ±5.5V
=±5V
V
A/VB
1
2
Ch 1 5.00V Ch 2 5.00 V M 400ns A CH1 2.70 V
Figure 25. Large Signal Settling Time; Code 0x00–0xFF
V
W
03142-0-023
V
W
CS
03142-0-024
Rev. 0 | Page 9 of 28
Page 10
AD5263
1
RAB = 20k
TA = 25°C
1.5
2
RAB = 20k
TA = 25°C
Ω
Ω
INL (LSB)
–0.5
0.5
–1
Avg – 3
σ
Avg
σ
Avg – 3
0
5
10 15 200
|VDD– VSS| (–V)
03142-0-025
Figure 26. INL vs. Supply Voltage
R-INL (LSB)
–0.5
–1.5
0.5
1
Avg + 3
σ
0
–1
–2
5
10 15 200
|VDD– VSS| (V)
Avg
Avg – 3
σ
03142-0-026
Figure 27. R-INL vs. Supply Voltage
Rev. 0 | Page 10 of 28
Page 11
AD5263
TEST CIRCUITS
DUT
DUT
W
B
DD
GND
SS
V
LOGIC
A1
W1
N/C
CTA = 20 log[V
A
B
+15V
W
AD8610
–15V
0.1V
RSW=
I
SW
CODE = 0x00
I
SW
VSS TO V
0.1V
DD
NC
I
A
CM
W
B
V
CM
NC
03142-0-036
I
LOGIC
+
–
03142-0-037
Current vs. Digital Input Voltage
LOGIC
RDAC1
V
V
B1
DD
SS
OUT/VIN
RDAC2
W2
B2
]
A2
V
OUT
03142-0-035
03142-0-038
V
OUT
03142-0-034
Figure 28 to Figure 38 define the test conditions used in the
product specification table.
DUT
A
V+
W
B
Figure 28. Test Circuit for Potentiometer Divider Nonlinearity Error (INL, DNL)
NO CONNECT
DUT
A
W
B
Figure 29. Test Circuit for Resistor Position Nonlinearity Error
(Rheostat Operation; R-INL, R-DNL)
DUT
V
MS2
A
B
V
W
W
Figure 30. Test Circuit for Wiper Resistance
V
A
V
DD
A
V+
W
B
Figure 31. Test Circuit for Power Supply Sensitivity (PSS, PSSR)
A
DUT
V
IN
OFFSET
GND
OFFSET
BIAS
Figure 32. Test Circuit for Inverting Gain
V
IN
OFFSET
GND
A
DUT
OFFSET
BIAS
Figure 33. Test Circuit for Noninverting Gain
V+ = V
1LSB = V+/2
V
MS
V
MS
IW= VDD/R
V
RW= [V
MS1
V+ = V
DD
PSRR (dB) = 20 LOG
PSS (%/ %) =
V
MS
B
5V
W
OP279
5V
OP279
W
B
DD
I
W
NOMINAL
MS1
10%
∆
∆
V
V
N
03142-0-028
03142-0-029
– V
%
MS
%
DD
V
V
OUT
]/I
MS2
∆
V
( )
∆
V
OUT
03142-0-033
W
MS
DD
03142-0-032
03142-0-030
03142-0-031
V
IN
OFFSET
GND
2.5V
Figure 34. Test Circuit for Gain vs Frequency
Figure 35. Test Circuit for Incremental ON Resistance
V
DUT
V
Figure 36. Test Circuit for Common Mode Leakage Current
SCL
SCA
Figure 37. Test Circuit for V
V
IN
Figure 38. Test Circuit for Analog Crosstalk
Rev. 0 | Page 11 of 28
Page 12
AD5263
V
SPI COMPATIBLE DIGITAL INTERFACE (DIS = 0)
Table 4. AD5263 Serial Data-Word Format
Addr Data
B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
MSB LSB
29 27 2
1
SDI
(DATA IN)
CLK
CS
V
OUT
0
1
0
t
CSHO
1
0
V
DD
0
Dx
t
CH
t
CSS
Figure 40. Detailed SPI Timing Diagram (V
0
Dx
t
DS
t
CL
t
SDI
CLK
CS
OUT
1
0
1
0
1
0
1
0
A0
A1
D7 D6
Figure 39. AD5263 Timing Diagram (V
CH
t
CSH1
= 5 V, VB = 0 V, VW = V
A
OUT
)
D5
t
CS1
D3
D4
D2 D1
RDAC REGISTER LOAD
= 5 V, VB = 0 V, VW = V
A
t
C-SW
t
S
D0
±LSB
OUT
03142-0-039
)
03142-0-040
Rev. 0 | Page 12 of 28
Page 13
AD5263
SDA
Y
S
Y
I2C COMPATIBLE DIGITAL INTERFACE (DIS = 1)
Table 5. I2C Write Mode Data-Word Format
S 0 1 0 1 1 AD1 AD0 W
Slave Address Byte Instruction Byte Data Byte
Table 6. I
S 0 1 0 1 1 AD1 AD0 R A D7 D8 D5 D4 D3 D2 D1 D0 A P
Slave Address Byte Data Byte
2
C Read Mode Data-Word Format
S = Start condition.
P = Stop condition.
A = Acknowledge.
A X A1 A0 RS SD O1 O2 X A D7 D6 D5 D4 D3 D2 D1 D0 A P
2
O1, O2 = Data to digital output pins O1, O2 in I
C mode, used
to drive external logic. The logic high level is determined by V
and the logic low level is GND.
L
AD1, AD0 = I2C device address bits. Must match with the logic
states at pins AD1, AD0. Refer to Figure 48.
A1, A0 = RDAC channel select.
RS = Software reset wiper (A1, A0) to midscale position.
SD = Shutdown active high; ties wiper (A1, A0) to Terminal A,
opens Terminal B, RDAC register contents are not disturbed. To
exit shutdown, the command SD = 0 must be executed for each
RDAC (A1, A0).
SCL
START B
MASTER
t
1
PS
SCL
0
SDA
t
8
t
2
1
0
FRAME 1 FRAME 2
SLAVE ADDRESS BYTE
TART B
MASTER
t
3
t
9
t
8
1
1 AD1 AD0 R/W
ACK BY
AD5263
1 919
SCL
0 1 0 1 1 AD1 AD0 R/W
SDA
FRAME 1
SLAVE ADDRESS BYTE
Figure 43. Reading Data from a Previously Selected RDAC Register in Write Mode
t
9
t
4
Figure 41. Detailed I
1 919
XA1 RSSDO1O2X
Figure 42
A0
INSTRUCTION BYTE
. Writing to the RDAC Register
W
= Write = 0.
R = Read = 1.
D7, D6, D5, D4, D3, D2, D1, D0 = Data Bits.
X = Don’t Care.
t
7
S
2
C Timing Diagram
ACK BY
AD5263
D7 D6 D5 D4 D3 D2 D1 D0
ACK BY
AD5263
FRAME 2
RDAC REGISTER
t
2
t
5
19
D7 D6 D5 D4 D3 D2 D1 D0
FRAME 3
DATA BYTE
NO ACK
BY MASTER
STOP BY
MASTER
ACK BY
AD5263
03142-0-043
P
STOP BY
MASTER
t
10
03142-0-041
03142-0-042
Rev. 0 | Page 13 of 28
Page 14
AD5263
−
OPERATION
The AD5263 is a quad-channel, 256-position, digitally
controlled, variable resistor (VR) device.
To program the VR settings, refer to the interface sections of the
previous pages. The part has an internal power-on preset that
places the wiper at midscale during power-on, which simplifies
the fault condition recovery at power-up. In addition, the shut-
SHDN
down
power consumption state where Terminal A is open circuited
and the wiper W is connected to Terminal B, resulting in only
leakage current consumption in the VR structure. During shutdown, the VR latch settings are maintained or new settings can
be programmed. When the part is returned from shutdown, the
corresponding VR setting will be applied to the RDAC.
PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation
The nominal resistance of the RDAC between Terminals A and
B is available in 20 kΩ, 50 kΩ, and 200 kΩ. The final two or
three digits of the part number determine the nominal
resistance value, e.g., 20 kΩ = 20; 50 kΩ = 50; 200 kΩ = 200. The
nominal resistance (R
accessed by the wiper terminal, plus the B terminal contact. The
8-bit data in the RDAC latch is decoded to select one of the 256
possible settings. Assuming a 20 kΩ part is used, the wiper's first
connection starts at the B terminal for data 0x00. Since there is a
60 Ω wiper contact resistance, such a connection yields a
minimum of 2 × 60 Ω resistance between Terminals W and B.
The second connection is the first tap point, and corresponds to
198 Ω (R
The third connection is the next tap point representing 216 Ω
= 78 Ω × 2 + 2 × 60 Ω) for data 0x02, and so on. Each LSB
(R
WB
data value increase moves the wiper up the resistor ladder until
the last tap point is reached at 19,982 Ω (R
Figure 44 shows a simplified diagram of the equivalent RDAC
circuit, where the last resistor string will not be accessed;
pin of AD5263 places the RDAC in an almost zero
Ax
SD BIT
R
S
D7
D6
D5
D4
D3
D2
D1
D0
DECODER
Figure 44. AD5263 Equivalent RDAC Circuit
= RAB/256 + RW = 78 Ω + 2 × 60 Ω) for data 0x01.
WB
R
S
R
S
RDAC
LATCH
AND
R
S
) of the VR has 256 contact points
AB
Wx
Bx
– 1 LSB + 2 × RW).
AB
03142-0-044
therefore, there is 1 LSB less of the nominal resistance at full
scale in addition to the wiper resistance.
The general equation determining the digitally programmed
output resistance between Terminals W and B is
WB
D
DR
)(
256
AB
(1)
RR
×+×= 2
W
where:
D
is the decimal equivalent of the binary code loaded in the
8-bit RDAC register.
is the end-to-end resistance.
R
AB
R
is the wiper resistance contributed by the ON resistance of
W
one internal switch.
In summary, if R
= 20 kΩ and the A terminal is open-
AB
circuited, the following RDAC latch codes result in the
corresponding output resistance, R
Table 7. Codes and Corresponding R
D (dec) R
(Ω) Output State
WB
WB
.
Resistances
WB
255 19,982 Full-Scale (RAB – 1 LSB + RW)
128 10,120 Midscale
1 198 1 LSB
0 120 Zero-Scale (Wiper Contact Resistance)
Note that in the zero-scale condition a finite wiper resistance of
120 Ω is present. Care should be taken to limit the current flow
between W and B in this state to a maximum pulse current of
no more than 20 mA. Otherwise, degradation or possible
destruction of the internal switch contact can occur.
Similar to the mechanical potentiometer, the resistance of the
RDAC between the wiper W and Terminal A also produces a
digitally controlled complementary resistance, R
. When these
WA
terminals are used, the B terminal can be opened. Setting the
resistance value for R
starts at a maximum value of resistance
WA
and decreases as the data loaded in the latch increases in value.
The general equation for this operation is
256
256
D
ABWA
DR
= 2
)(
= 20 kΩ and the B terminal open-circuited, the
For R
AB
(2)
RR
×+×
W
following RDAC latch codes result in the corresponding output
resistance RWA:
Table 8. Codes and Corresponding R
D (dec) R
(Ω) Output State
WA
Resistances
WA
255 198 Full-Scale
128 10,120 Midscale
1 19,982 1 LSB
0 20,060 Zero-Scale
Rev. 0 | Page 14 of 28
Page 15
AD5263
The typical distribution of the end-to-end resistance RAB from
channel to channel matches within ±1%. Device to device
matching is process lot dependent and is possible to have ±30%
variation. Since the resistance element is processed in thin film
technology, the change in R
with temperature has a very low
AB
temperature coefficient of 30 ppm/°C.
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates a voltage divider at
wiper-to-B and wiper-to-A proportional to the input voltage
from Terminals A to B. Unlike the polarity from V
which must be positive, the voltage across A-B, W-A, and W-B
can be at either polarity, provided that V
is powered by a
SS
negative supply.
to VSS,
DD
Standard logic families work well. If mechanical switches are
used for product evaluation, they should be debounced by a
flip-flop or other suitable means. When
CS
is low, the clock
loads data into the serial register on each positive clock edge
(see Figure 39).
Table 9. AD5263 Address Decode Table
A1 A0 Latch Loaded
0 0 RDAC 1
0 1 RDAC 2
1 0 RDAC 3
1 1 RDAC 4
If ignoring the effect of the wiper resistance for approximation,
connecting the A terminal to 5 V and the B terminal to ground
produces an output voltage from the wiper to B starting at 0 V
up to 1 LSB below 5 V. Each LSB step of voltage is equal to the
voltage applied across Terminals A-B divided by the 256
positions of the potentiometer divider. Since the AD5263 can be
powered by dual supplies, the general equation defining the
output voltage V
with respect to ground for any valid input
W
voltages applied to Terminals A and B is
−
D
)(
256
V
A
DV
W
D
256
+=
256
(3)
V
B
For a more accurate calculation, which includes the effect of
wiper resistance, V
DV
)( +=
W
can be found as
W
DR
)(
WB
V
A
256
WA
256
DR
)(
V
(4)
B
Operation of the digital potentiometer in the divider mode
results in a more accurate operation over temperature. Unlike
the rheostat mode, the output voltage is dependent mainly on
the ratio of the internal resistances R
and RWB, and not their
WA
absolute values; therefore, the temperature drift reduces to
5 ppm/°C.
PIN SELECTABLE DIGITAL INTERFACE
The AD5263 provides the flexibility of a selectable interface.
When the digital interface select (DIS) pin is tied low, the SPI
mode is engaged. When the DIS pin is tied high to the V
supply, the I
2
C mode is engaged.
L
SPI COMPATIBLE 3-WIRE SERIAL BUS (DIS = 0)
The AD5263 contains a 3-wire SPI compatible digital interface
CS
(SDI,
address bits A1 and A0, followed by the data byte, MSB first.
The format of the word is shown in Table 4.
The positive-edge sensitive CLK input requires clean transitions
to avoid clocking incorrect data into the serial input register.
, and CLK). The 10-bit serial word must be loaded with
The data setup and data hold times in the specification table
determine the valid timing requirements. The AD5263 uses a
10-bit serial input data register word that is transferred to the
CS
internal RDAC register when the
line returns to logic high.
Note that only the last 10-bits that are clocked into the register
CS
are latched into the decoder. As
goes high, it activates the
address decoder and updates the corresponding channel
according to Table 9.
SHDN
During shutdown (
), the serial data output (SDO) pin is
forced to logic high in order to avoid power dissipation in the
external pull-up resistor. For an equivalent SDO output circuit
schematic, see Figure 45.
SHDN
CS
SERIAL
SDI
REGISTER
CLK
RES
Figure 45. Detailed SDO Output Schematic of the AD5263
Q
D
CK
RS
SDO
03142-0-045
During reset (
unlike
remain at midscale and will not revert to its pre-reset setting.
RES
), the wiper is set to midscale. Note that
SHDN
, when the part is taken out of reset, the wiper will
Daisy-Chain Operation
The serial data output (SDO) pin contains an open drain
N-channel FET. This output requires a pull-up resistor in order
to transfer data to the next package’s SDI pin. This allows for
daisy chaining several RDACs from a single processor serial
data line. The pull-up resistor termination voltage can be
greater than the V
increase the clock period when using a pull-up resistor to the
SDI pin of the following device because capacitive loading at the
daisy-chain node (SDO-SDI) between devices may induce time
delay to subsequent devices. Users should be aware of this
potential problem to achieve data transfer successfully (see
supply voltage. It is recommended to
DD
Rev. 0 | Page 15 of 28
Page 16
AD5263
Figure 46). If two AD5263s are daisy-chained, a total of 20 bits
of data is required. The first 10 bits, complying with the format
shown in Table 4, go to U2 and the second 10 bits, with the
CS
same for mat, go to U1.
are clocked into their respective serial registers. After this,
pulled high to complete the operation and load the RDAC latch.
Note that data appears on SDO on the negative edge of the
clock, thus making it available to the input of the daisy-chained
device on the rising edge of the next clock.
SPI
MOSI
CLK
CS
Figure 46. Daisy-Chain Configuration
I2C COMPATIBLE 2-WIRE SERIAL BUS (DIS = 1)
In the I2C compatible mode, the RDACs are connected to the
bus as slave devices.
Referring to Table 5 and Table 6, the first byte of the AD5263 is
a slave address byte, consisting of a 7-bit slave address and a
W
R/
bit. The five MSBs are 01011 and the following two bits are
determined by the state of the AD0 and AD1 pins of the device.
AD0 and AD1 allow the user to place up to four of the I
compatible devices on one bus.
The 2-wire I
1. The master initiates a data transfer by establishing a
2. In the write mode, the second byte is the instruction byte.
2
C serial bus protocol operates as follows:
START condition, which is when a high-to-low transition
on the SDA line occurs while SCL is high (see Figure 42).
The following byte is the slave address byte, which consists
of the 7-bit slave address followed by an R/
bit determines whether data will be read from or written to
the slave device.
The slave whose address corresponds to the transmitted
address responds by pulling the SDA line low during the
ninth clock pulse (this is termed the acknowledge bit). At
this stage, all other devices on the bus remain idle while the
selected device waits for data to be written to or read from
its serial register. If the R/
from the slave device. If the R/
write to the slave device.
The first bit (MSB) of the instruction byte is a don’t care.
The following two bits, labeled A1 and A0, are the RDAC
subaddress select bits.
should be kept low until all 20 bits
V
L
AD5263 AD5263
U1
SDI
CS
CLK
SDO
R
P
2.2kΩ
SDI
W
bit is high, the master will read
W
bit is low, the master will
U2
SDO
CLK
CS
W
bit. This R/
CS
is
03142-0-046
2
C
W
The fourth MSB (RS) is the midscale reset. A logic high on
this bit moves the wiper of the selected channel to the
center tap where R
= RWB. This feature effectively writes
WA
over the contents of the register, so that when taken out of
reset mode, the RDAC will remain at midscale.
The fifth MSB (SD) is the shutdown bit. A logic high causes
the selected channel to open circuit at Terminal A while
shorting the wiper to Terminal B. This operation yields
almost 0 Ω in rheostat mode or 0 V in potentiometer
mode. This SD bit serves the same function as the
SHDN
pin except that the
SHDN
pin affects all channels, as opposed to the SD bit,
pin reacts to active low. Also, the
SHDN
which affects only the channel being written to. It is
important to note that the shutdown operation does not
disturb the contents of the register. When brought out of
shutdown, the previous setting will be applied to the
RDAC.
The next two bits are O2 and O1. They are extra
programmable logic outputs that can be used to drive other
digital loads, logic gates, LED drivers, analog switches, etc.
The LSB is a don’t care (see Table 5).
After acknowledging the instruction byte, the last byte in
write mode is the data byte. Data is transmitted over the
serial bus in sequences of nine clock pulses (eight data bits
followed by an acknowledge bit). The transitions on the
SDA line must occur during the low period of SCL and
remain stable during the high period of SCL (see
Figure 42).
3. In the read mode, the data byte follows immediately after
the acknowledgment of the slave address byte. Data is
transmitted over the serial bus in sequences of nine clock
pulses (a slight difference with the write mode, where there
are eight data bits followed by an acknowledge bit).
Similarly, the transitions on the SDA line must occur
during the low period of SCL and remain stable during the
high period of SCL (see Figure 43).
Note that the channel of interest is the one that was
previously selected in the write mode. In the case where
users need to read the RDAC values of both channels, they
need to program the first channel in the write mode and
then change to the read mode to read the first channel
value. After that, they need to change back to the write
mode with the second channel selected and read the
second channel value in the read mode again. It is not
necessary for users to issue the Frame 3 data byte in the
write mode for subsequent readback operation. Refer to
Figure 43 for the programming format.
Rev. 0 | Page 16 of 28
Page 17
AD5263
+5V
O1
SHDN
AD5263
SDA
SCL
03142-0-047
4. After all data bits have been read or written, a STOP
condition is established by the master. A STOP condition is
defined as a low-to-high transition on the SDA line while
SCL is high. In write mode, the master will pull the SDA
line high during the tenth clock pulse to establish a STOP
condition (see Figure 42). In read mode, the master will
issue a no acknowledge for the ninth clock pulse (i.e., the
SDA line remains high). The master will then bring the
SDA line low before the tenth clock pulse, which goes high
to establish a STOP condition (see Figure 43).
A repeated write function gives the user flexibility to update the
RDAC output a number of times after addressing and
instructing the part only once. For example, after the RDAC has
acknowledged its slave address and instruction bytes in the
write mode, the RDAC output will update on each successive
byte. If different instructions are needed, the write/read mode
has to start again with a new slave address, instruction, and data
byte. Similarly, a repeated read function of the RDAC is also
allowed.
R
PULL-DOWN
Figure 47. Shutdown by Internal Logic Output
MULTIPLE DEVICES ON ONE BUS
Figure 48 shows four AD5263 devices on the same serial bus.
Each has a different slave address since the states of their AD0
and AD1 pins are different. This allows each RDAC within each
device to be written to or read from independently. The master
device output bus line drivers are open-drain pull-downs in a
2
fully I
C compatible interface.
R
R
P
P
ADDITIONAL PROGRAMMABLE LOGIC OUTPUT
The AD5263 features additional programmable logic outputs,
O1 and O2, which can be used to drive a digital load, analog
switches, and logic gates. O1 and O2 default to Logic 0. The
voltage level can swing from GND to V
. The logic states of O1
L
and O2 can be programmed in Frame 2 under write mode (see
Figure 42). These logic outputs have adequate current driving
capability to sink/source milliamperes of load.
Users can also activate O1 and O2 in three different ways
without affecting the wiper settings. They may do the following:
1. START, slave address byte, acknowledge, instruction byte with
O1 and O2 specified, acknowledge, STOP.
2. Complete the write cycle with STOP, then START, slave
address byte, acknowledge, instruction byte with O1 and O2
specified, acknowledge, STOP.
3. Do not complete the write cycle by not issuing the STOP, then
START, slave address byte, acknowledge, instruction byte with
O1 and O2 specified, acknowledge, STOP.
SELF-CONTAINED SHUTDOWN FUNCTION
Shutdown can be activated by strobing the
programming the SD bit in the write mode instruction byte. In
addition, shutdown can even be implemented with the device’s
digital output as shown in Figure 47. In this configuration, the
device will be shut down during power-up, but users are allowed
to program the device. Thus, when O1 is programmed high, the
device will exit from the shutdown mode and respond to the
new setting. This self-contained shutdown function allows
absolute shutdown during power-up, which is crucial in
hazardous environments, without adding extra components.
SHDN
pin or
SDA
MASTER
SDA SCL
AD1 AD1 AD1 AD1
AD0
AD5263
Figure 48. Multiple AD5263 Devices on One I
+5V
SDA SCL
AD0
AD5263
+5V
SDA SCL
AD0
AD5263
+5V
2
C Bus
SDA SCL
AD0
AD5263
SCL
LEVEL SHIFT FOR NEGATIVE VOLTAGE OPERATION
The digital potentiometer is popular in laser diode driver and
certain telecommunication equipment level-setting applications.
These applications are sometimes operated between ground and
some negative supply voltage so that the systems can be biased
at ground to avoid large bypass capacitors that may significantly
impede the ac performance. Like most digital potentiometers,
the AD5263 can be configured with a negative supply (see
Figure 49).
V
V
–5V
LEVEL SHIFTED
LEVEL SHIFTED
Figure 49. Biased at Negative Voltage
GND
SDA
SCL
However, the digital inputs must also be level shifted to allow
proper operation since the ground is now referenced to the
negative potential. As a result, Figure 50 shows one
implementation with a couple transistors and a few resistors.
AD5263
DD
SS
03142-0-050
03142-0-048
Rev. 0 | Page 17 of 28
Page 18
AD5263
+
V
V
When VIN is high, Q1 is turned on and its emitter is clamped at
one threshold above ground. This threshold appears at the base
of Q2, which causes Q2 to turn off. In this state, V
approaches –5 V. When V
is low, Q1 is turned off and the base
IN
OUT
of Q2 is pulled low, which in turn causes Q2 to turn on. In this
state, V
also needed for successful communication with the device.
5V
0V
approaches 0 V. Beware that proper time shifting is
OUT
R3
V
IN
1kΩ
R1
–5V
Q1
2N3906
10kΩ
2N3906
Q2
V
OUT
R2
10kΩ
0V
–5V
–5V
Figure 50. Level Shift for Bipolar Potential Operation
03142-0-051
ESD PROTECTION
All digital inputs are protected with a series input resistor and
parallel Zener ESD structures shown in Figure 51 and Figure 52.
This protection applies to digital input pins SDI/SDA,
CLK/SCL,
/AD0,
RES
/AD1, and
340Ω
V
SS
CS
Figure 51. ESD Protection of Digital Pins
A,B,W
LOGIC
SHDN
.
03142-0-052
V
DD
A
W
B
V
SS
03142-0-054
Figure 53. Maximum Terminal Voltages Set by V
and VSS
DD
POWER-UP SEQUENCE
Since the ESD protection diodes limit the voltage compliance at
Terminals A, B, and W (see Figure 53), it is important to power
V
and VSS before applying any voltage to Terminals A, B, and
DD
W; otherwise, the diodes will be forward biased such that V
will be powered unintentionally and may affect the rest
and V
SS
DD
of the circuit. The ideal power-up sequence is in the following
order: GND, V
order of powering V
, VSS, VL, digital inputs, and V
DD
, VB, VW, and digital inputs is not
A
important as long as they are powered after V
V
POWER SUPPLY
LOGIC
. The relative
A/B/W
and VSS.
DD
The AD5263 is capable of operating at high voltages beyond the
internal logic levels, which are limited to operation at 5 V. As a
result, V
always needs to be tied to a separate 2.7 V to 5.5 V
L
source to ensure proper digital signal levels. Logic levels must
be limited to V
be less than or equal to V
, regardless of VDD. In addition, VL should always
L
.
DD
LAYOUT AND POWER SUPPLY BYPASSING
It is a good practice to employ compact, minimum-lead length
layout design. The leads to the input should be as direct as
possible with a minimum conductor length. Ground paths
should have low resistance and low inductance.
V
SS
Figure 52. ESD Protection of Resistor Terminals
TERMINAL VOLTAGE OPERATING RANGE
The AD5263 positive VDD and negative VSS power supply defines
the boundary conditions for proper 3-terminal digital
potentiometer operation. Supply signals present on Terminals A,
B, and W that exceed V
forward biased diodes shown in Figure 53.
or VSS will be clamped by the internal
DD
03142-0-053
with quality capacitors for optimum stability. Supply leads to the
device should be bypassed with 0.01 µF to 0.1 µF ceramic disc
or chip capacitors. Low ESR 1 µF to 10 µF tantalum or
electrolytic capacitors should also be applied at the supplies to
minimize any transient disturbance and low frequency ripple
(see Figure 54). Notice the digital ground should also be joined
remotely to the analog ground at one point to minimize the
ground bounce.
Rev. 0 | Page 18 of 28
DD
+
10µF
+
10µF
C1
0.1µF
C2
0.1µF
C3
C4
SS
Figure 54. Power Supply Bypassing
V
DD
AD5263
V
SS
GND
03142-0-055
Similarly, it is also a good practice to bypass the power supplies
Page 19
AD5263
A
RDAC CIRCUIT SIMULATION MODEL
The internal parasitic capacitances and the external capacitive
loads dominate the ac characteristics of the RDACs. Configured
as a potentiometer divider, the –3 dB bandwidth of the AD5263
(20 kΩ resistor) measures 300 kHz at half scale. Figure 21
provides the large signal BODE plot characteristics of the three
available resistor versions: 20 kΩ, 50 kΩ, and 200 kΩ. A parasitic
simulation model is shown in Figure 55. The following code
provides a macro model net list for the 20 kΩ RDAC.
RDAC
C
25pF
20kΩ
A
C
55pF
B
C
B
25pF
W
Listing 1. Macro Model Net List for RDAC
.PARAM D=256, RDAC=20E3
*
.SUBCKT DPOT (A,W,B)
*
CA A 0 25E-12
RWA A W {(1-D/256)*RDAC+60}
CW W 0 55E-12
RWB W B {D/256*RDAC+60}
CB B 0 25E-12
*
.ENDS DPOT
W
Figure 55. RDAC Circuit Simulation Model for RDAC = 20 k
03142-0-069
Ω
Rev. 0 | Page 19 of 28
Page 20
AD5263
APPLICATIONS
BIPOLAR DC OR AC OPERATION FROM DUAL SUPPLIES
The AD5263 can be operated from dual supplies, enabling
control of ground referenced ac signals or bipolar operation.
The ac signal, as high as V
Terminals A-B with the output taken from Terminal W. See
Figure 56 for a typical circuit connection.
V
DD
µC
SCLK
MCSI
GND
Figure 56. Bipolar Operation from Dual Supplies
GAIN CONTROL COMPENSATION
The digital potentiometer is commonly used in gain control
such as the noninverting gain amplifier shown in Figure 57.
R1
47kΩ
C1
25pF
, can be applied directly across
DD/VSS
V
DD
SCL
SDA
GND
AD5263
A1
W1
B1
A2
W2
B2
V
SS
C2
4.7pF
R2
200kΩ
B
A
W
U1
VI
2
.
5
V
p
D = 0x90
V
O
+5.0V
5Vp-p
-
p
_
5.0V
03142-0-056
problem. A better approach is to include a compensation
capacitor C2 to cancel the effect caused by C1. Optimum
compensation occurs when R1 × C1 = R2 × C2 . This is not an
option, because of the variation of R2. As a result, one may use
the relationship above and scale C2 as if R2 is at its maximum
value. Doing so may overcompensate and compromise the
performance slightly when R2 is set at low values. However, it
will avoid the gain peaking, ringing, or oscillation in the worst
case. For critical applications, C2 should be found empirically to
suit the need. In general, C2 in the range of few pF to no more
than a few tenths of pF is usually adequate for the
compensation.
Similarly, there are W and A terminal capacitances connected to
the output (not shown); fortunately their effect at this node is
less significant and the compensation can be disregarded in
most cases.
PROGRAMMABLE VOLTAGE REFERENCE
For voltage divider mode operation (Figure 58), it is common to
buffer the output of the digital potentiometer unless the load is
much larger than R
purpose of impedance conversion, but also allows a heavier load
to be driven.
+5V
1
VIN
GND
. Not only does the buffer serve the
WB
U1
AD1582
VOUT
AD5263
3
+5V
A
W
AD8601
B
A1
V
O
Figure 58. Programmable Voltage Reference
03142-0-058
03142-0-057
Figure 57. Typical Noninverting Gain Amplifier
Notice the RDAC B terminal parasitic capacitance is connected
to the op amp noninverting node. It introduces a zero for the
1/βo term with +20 dB/dec, whereas a typical op amp GBP has
–20 dB/dec characteristics. A large R2 and finite C1 can cause
this zero's frequency to fall well below the crossover frequency.
Thus, the rate of closure becomes 40 dB/dec and the system has
o
phase margin at the crossover frequency. The output may
0
ring or oscillate if the input is a rectangular pulse or step
function. Similarly, it is also likely to ring when switching
between two gain values, because this is equivalent to a step
change at the input.
Depending on the op amp GBP, reducing the feedback resistor
may extend the zero's frequency far enough to overcome the
Rev. 0 | Page 20 of 28
Page 21
AD5263
I
V
8-BIT BIPOLAR DAC
Figure 59 shows a low cost, 8-bit, bipolar DAC. It offers the
same number of adjustable steps but not the precision as
compared to conventional DACs. The linearity and temperature
coefficient, especially at low values codes, are skewed by the
effects of the digital potentiometer wiper resistance. The output
of this circuit is
2
D
V
O
V
1
VIN
ADR425
GND
I
U1
VOUT
TRIM
256
−= 1
+5VREF
(5)
V
×
REF
AD5263
W
A
B
+15V
V+
OP2177
V–
A1
Figure 59. 8-Bit Bipolar DAC
–5VREF
+15V
V+
OP2177
V–
A2
–15V
V
O
03142-0-059
BIPOLAR PROGRAMMABLE GAIN AMPLIFIER
For applications requiring bipolar gain, Figure 60 shows one
implementation similar to the previous circuit. The digital
potentiometer U1 sets the adjustment range. The wiper voltage
at W2 can therefore be programmed between V
given U2 setting. Configuring A2 in the noninverting mode
allows linear gain and attenuation. The transfer function is
V
V
where
I
O
+=
1 (6)
K
is the ratio of R
AD5263
AD5263
Figure 60. Bipolar Programmable Gain Amplifier
R2
R1
D2
()
256
1
WB1/RWA 1
V
DD
V+
OP2177
_
V
A1
V
SS
U2
W2
B2
A2
A1
B1
W1
U1
−+××
KK
set by U1.
–KV
V+
OP2177
V
A2
I
V
_
V
and –KVI at a
I
DD
V
C1
SS
R2
R1
O
03142-0-060
Similar to the previous example, in the simpler (and much more
usual) case where K = 1, a single channel is used and U1 is
V
and –
V
replaced by a matched pair of resistors to apply
I
at
I
the ends of the digital potentiometer. The relationship becomes
2
×
R2
1
+= 1
O
R1
is large, a compensation capacitor of a few pF may be
If
V
R2
D2
×
256
−
(7)
V
×
I
needed to avoid any gain peaking.
Table 10 shows the result of adjusting D, with A2 configured
with unity gain, gain of 2, and gain of 10. The result is a bipolar
amplifier with linearly programmable gain and 256-step
resolution.
Table 10. Result of Bipolar Gain Amplifier
D
R1 = ∞, R2 = 0
R1 = R2 R2 = 9 × R1
0 –1 –2 –10
64 –0.5 –1 –5
128 0 0 0
192 0.5 1 5
255 0.968 1.937 9.680
PROGRAMMABLE VOLTAGE SOURCE WITH BOOSTED OUTPUT
For applications that require high current adjustment, such as a
laser diode driver or tunable laser, a boosted voltage source can
be considered. See Figure 61.
AD8601
+V
U2
–V
U3 2N7002
SIGNAL
V
U1
AD5263
IN
A
W
B
Figure 61. Programmable Booster Voltage Source
In this circuit, the inverting input of the op amp forces the V
to be equal to the wiper voltage set by the digital potentiometer.
The load current is then delivered by the supply via the Nchannel FET N1. N1 power handling must be adequate to
– V
dissipate power equal to (V
IN
) × IL . This circuit can
OUT
source a maximum of 100 mA with a 5 V supply. For precision
applications, a voltage reference such as ADR421, ADR03, or
ADR370 can be applied at the A terminal of the digital
potentiometer.
V
OUT
R
BIAS
C
C
I
L
LD
03142-0-061
OUT
Rev. 0 | Page 21 of 28
Page 22
AD5263
S
D
V
B
+
+×′
PROGRAMMABLE 4–20 mA CURRENT SOURCE PROGRAMMABLE BIDIRECTIONAL CURRENT
A programmable 4–20 mA current source can be implemented
with the circuit shown in Figure 62. The REF191 is a unique low
supply headroom and high current handling precision reference
that can deliver 20 mA at +2.048 V. The load current is simply
the voltage across Terminals B-W of the digital potentiometer
divided by R
I
L
:
S
×
REF
= (8)
R
2×
+5V
2
VIN
VOUT
3
SLEEP
REF191
GND
4
–2.048V to V
N
U1
6
L
0 to (2.048V + VL)
C1
1µF
AD5263
+5V
U2
V+
OP8510
V–
–5V
B
W
A
R
102Ω
S
I
V
L
L
R
100Ω
L
03142-0-062
Figure 62. Programmable 4–20 mA Current Source
The circuit is simple, but beware of two things. First, dualsupply op amps are ideal because the ground potential of the
REF191 can swing from –2.048 V at zero scale to V
at full scale
L
of the potentiometer setting. Although the circuit works with a
single supply, the programmable resolution of the system will be
reduced.
For applications that demand higher current capabilities, a few
changes to the circuit in Figure 62 will produce an adjustable
current in the range of hundreds of mA. First, the voltage reference needs to be replaced with a high current, low dropout
regulator, such as the ADP3333, and the op amp needs to be
swapped with a high current, dual-supply model, such as the
AD8532. Depending on the desired range of current, an appropriate value for R
must be calculated. Because of the high
S
current flowing to the load, the user must pay attention to the
load impedance so as not to drive the op amp past the positive rail.
SOURCE
For applications that require bidirectional current control or
higher voltage compliance, a Howland current pump can be a
solution (see Figure 63). If the resistors are matched, the load
current is
R1R2BR2A
I
=
+5V
A
AD5263
W
–5V
Figure 63. Programmable Bidirectional Current Source
R2B, in theory, can be made as small as needed to achieve the
current needed within A2’s output current driving capability. In
this circuit, OP2177 can deliver ±5 mA in either direction, and
the voltage compliance approaches +15 V. It can be shown that
the output impedance is
Z
= (10)
o
×
This output impedance can be infinite if resistors R1′ and R2′
match precisely with R1 and R2A+R2B, respectively. On the
other hand, it can be negative if the resistors are not matched.
As a result, C1 in the range of 1 pF to 10 pF is needed to prevent
oscillation.
R2
+15V
OP2177
–15V
A1
)(
V
×
(9)
WL
+15V
OP2177
–15V
R2A
R2
15kΩ
C1
10pF
A2
V+
V–
14.95kΩ
R
L
R1
150kΩ
C2
10pF
V+
V–
′
′
−
R1
150kΩ
)(2
R2AR1BR1R
)(
R2BR2A1R2RR1
+
R2B
50Ω
500Ω
03142-0-063
V
L
I
L
Rev. 0 | Page 22 of 28
Page 23
AD5263
C
C
2R2C1R1
−
1
PROGRAMMABLE LOW-PASS FILTER PROGRAMMABLE OSCILLATOR
In A/D conversion applications, it is common to include an
antialiasing filter to band-limit the sampling signal. Dualchannel digital potentiometers can be used to construct a
second order Sallen-Key low-pass filter (see Figure 64). The
design equations are
In a classic Wien-bridge oscillator (Figure 65), the Wien
network (R, R
R2 provide negative feedback. At the resonant frequency,
′, C, C′) provides positive feedback, while R1 and
f
, the
O
overall phase shift is zero, and the positive feedback causes the
circuit to oscillate.
V
O
=
V
ω
Q
2
I
S
=
O
=
×
2
ω
O
ω
O
S
Q
1
+
(11)
2
ω
++
O
(12)
C2C1R2R1
×××
11
(13)
C
×
Users can first select some convenient values for the capacitors.
To achieve maximally flat bandwidth where Q = 0.707, let C1 be
twice the size of C2, and let R1 = R2. As a result, the user can
adjust R1 and R2 to the same settings to achieve the desired
bandwidth.
C1
R1
ABWAB
V
I
RR
ADJUSTED TO
SAME SETTING
R2
C2
Figure 64. Sallen-Key Low-Pass Filter
C
W
C
V+
AD8601
V–
+2.5V
U1
–2.5V
V
O
03142-0-064
With R = R
′, C = C′, and R2 = R2A||(R2B + R
DIODE
), the
oscillation frequency is
ω
where
R
1
, or
=
O
R
R
is equal to RWA, such that
256
=
256
f
D
R
AB
1
=
O
(14)
R
π
2
(15)
At resonance, setting
R2
(16)
2=
R
R2/R1
balances the bridge. In practice,
should be set slightly
greater than 2 to ensure that the oscillation can start. On the
other hand, the alternating turn-on of the diodes D1 and D2
R2/R1
ensures that
is momentarily less than 2, thereby
stabilizing the oscillation.
Once the frequency is set, the oscillation amplitude can be
R2B
O
, and
, since
(17)
VR2BIV
+×=
DD
VD
are interdependent variables. With proper
R2B
, an equilibrium will be reached such that
R2B
can be in series with a discrete resistor to
V
O
tuned by
2
3
V
,
I
O
D
selection of
converges.
increase the amplitude, but the total resistance should not be so
large that it saturates the output.
FREQUENCY
ADJUSTMENT
2.2nF
R1 = R1' = R2B = AD5263
D1 = D2 = 1N4148
Figure 65. Programmable Oscillator with Amplitude Control
B
R
A
VP
W
10kΩ
VN
R1
1kΩ
C
2.2nF
+2.5V
OP1177
–2.5V
R2B
B
W
V+
V–
R2A
2.1kΩ
A
10kΩ
A
10kΩ
U1
R'
B
W
D1
D2
AMPLITUDE
ADJUSTMENT
V
O
03142-0-065
Rev. 0 | Page 23 of 28
Page 24
AD5263
RESISTANCE SCALING RESISTANCE TOLERANCE, DRIFT, AND
The AD5263 offers 20kΩ, 50kΩ, and 200kΩ nominal
resistances. Users who need a lower resistance and the same
number of step adjustments can place multiple devices in
parallel. For example, Figure 66 shows a simple scheme of using
two channels in parallel. To adjust half of the resistance linearly
per step, users need to program both channels to the same
settings.
V
DD
A1
B1
LED
W1
A2
W2
B2
03142-0-066
Figure 66. Reduce Resistance by Half with Linear Adjustment Characteristics
Applicable only to the voltage divider mode, by connecting a
discrete resistor in parallel as shown in Figure 67, a
proportionately lower voltage appears at Terminal A. This
translates into a finer degree of precision because the step size at
Terminal W will be smaller. The voltage can be found as
VD
DV
)( ×
W
×=
DD
()
+
AB
V
R2
R1
R1 << R
Figure 67. Decreasing Step Size by Lowering the Nominal Resistance
(
R1RR2
||256
DD
A
W
B
AB
AB
03142-0-067
||
)
(18)
R1R
Figure 66 and Figure 67 show applications in which the digital
potentiometers change steps linearly. On the other hand, log
taper adjustment is usually preferred in applications such as
volume control. Figure 68 shows another method of resistance
scaling which produces a pseudo-log taper output. In this
circuit, the smaller the value of R2 with respect to R
, the more
AB
the output approaches log type behavior.
V
I
A
R1
B
V
O
R2
TEMPERATURE COEFFICIENT MISMATCH
CONSIDERATIONS
In the rheostat mode operation, such as the gain control circuit
of Figure 69, the tolerance mismatch between the digital
potentiometer and the discrete resistor can cause repeatability
issues among various systems. Because of the inherent matching
of the silicon process, it is practical to apply the multichannel
device in this type of application. As such, R1 should be
replaced by one of the channels of the digital potentiometer. R1
should be programmed to a specific value while R2 can be used
for the adjustable gain. Although it adds cost, this approach
minimizes the tolerance and temperature coefficient mismatch
between R1 and R2. In addition, this approach also tracks the
resistance drift over time. As a result, these non-ideal
parameters become less sensitive to system variations.
R2
AB
W
AD8601
AD8601
U1
Drift
C1
V
O
U1
C1
V
O
03142-0-071
R1
V
I
*REPLACED WITH ANOTHER CHANNEL OF RDAC
Figure 69. Linear Gain Control with Tracking Resistance Tolerance and Drift
Notice that the circuit in Figure 70 can also be used to track the
tolerance, temperature coefficient, and drift in this particular
application. However, the characteristics of the transfer function
change from a linear to a pseudo-logarithmic gain function.
ARB
W
V
I
Figure 70. Nonlinear Gain Control with Tracking Resistance Tolerance and
03142-0-070
03142-0-068
Figure 68. Resistor Scaling with Log Adjustment Characteristics
Rev. 0 | Page 24 of 28
Page 25
AD5263
PIN CONFIGURATION AND PIN FUNCTION DESCRIPTIONS
PIN CONFIGURATION
1
B1
2
A1
AD5263
3
W1
TSSOP-24
4
B3
5
A3
6
W3
7
V
DD
TOP VIEW
8
GND
(Not to Scale)
9
DIS
10
V
LOGIC
11
SDI/SDA
CLK/SCL
12
Figure 71. 24-Lead TSSOP
PIN FUNCTION DESCRIPTIONS
Table 11.
Pin Name Description
1 B1 Resistor Terminal B1
2 A1 Resistor Terminal A1 (ADDR = 00)
3 W1 Wiper Terminal W1
4 B3 Resistor Terminal B3
5 A3 Resistor Terminal A3
6 W3 Wiper Terminal W3 (ADDR = 10)
7
V
DD
Positive Power Supply, specified for +5 V to +15 V operation.
8 GND Ground
9
DIS Digital Interface Select (SPI/I
10 V
2.7 V to 5.5 V Logic Supply Voltage. The logic supply voltage should always be less than or equal to VDD. In addition, logic
LOGIC
levels must be limited to the logic supply voltage regardless of V
11 SDI/SDA SDI = 3-Wire Serial Data Input. SDA = 2-Wire Serial Data Input/Output.
12 CLK/SCL Serial Clock Input
13
CS
/AD0
14
RES
/AD1
15
SHDN
16 SDO/O1 Serial Data Output in SPI Mode, open-drain transistor requires pull-up resistor.
Chip Select in SPI Mode. Device Address Bit 0 in I
RESET in SPI Mode. Device Address Bit 1 in I
Shutdown. Shorts wiper to Terminal B, opens Terminal A. Tie to +5 V supply if not used. Do not tie to V
Digital Output O1 in I
2
C Mode, can be used to drive external logic.
17 NC/O2 No Connection in SPI Mode. Digital Output O2 in I2C Mode, can be used to drive external logic.
18
V
SS
Negative Power Supply, specified for operation from 0 V to –5 V.
19 W4 Wiper Terminal W4 (ADDR = 11)
20 A4 Resistor Terminal A4
21 B4 Resistor Terminal B4
22 W2 Wiper Terminal W2 (ADDR = 01)
23 A2 Resistor Terminal A2
24 B2 Resistor Terminal B2
2
C Select). SPI when DIS = 0, I2C when DIS = 1
2
2
C Mode.
C Mode.
24
B2
23
A2
22
W2
21
B4
20
A4
19
W4
18
17
NC/O2
16
SDO/O1
15
SHDN
14
RES/AD1
13
CS/AD0
V
SS
03142-0-072
.
DD
if VDD > 5 V.
DD
Rev. 0 | Page 25 of 28
Page 26
AD5263
OUTLINE DIMENSIONS
7.90
7.80
7.70
24
PIN 1
0.15
0.05
0.10 COPLANARITY
0.65
BSC
0.30
0.19
COMPLIANT TO JEDEC STANDARDS MS-153AD
13
121
1.20
MAX
SEATING
PLANE
4.50
4.40
4.30
6.40 BSC
0.20
0.09
8°
0°
0.75
0.60
0.45
Figure 72. 24-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-24)
Dimensions shown in millimeters
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
ORDERING GUIDE
Table 12. Ordering Guide
Model1 R
AD5263BRU20 20 –40°C to +125°C TSSOP-24 RU-24 62
AD5263BRU20-REEL7 20 –40°C to +125°C TSSOP-24 RU-24 1,000
AD5263BRU50 50 –40°C to +125°C TSSOP-24 RU-24 62
AD5263BRU50-REEL7 50 –40°C to +125°C TSSOP-24 RU-24 1,000
AD5263BRU200 200 –40°C to +125°C TSSOP-24 RU-24 62
AD5263BRU200-REEL7 200 –40°C to +125°C TSSOP-24 RU-24 1,000
AD5263EVAL See Note 2 Evaluation Board
1
Package branding: Line 1 contains the model number, Line 2 contains the end-to-end resistance, and Line 3 contains the date code YYWW.
2
The evaluation board is shipped with the 20 kΩ RAB resistor option; however, the board is compatible with all available resistor value options.
The AD5263 contains 5,184 transistors. Die size: 108 mil × 198 mil = 21,384 sq. mil.
(kΩ) Temperature Package Description Package Option Parts per Container
AB
Rev. 0 | Page 26 of 28
Page 27
AD5263
NOTES
Rev. 0 | Page 27 of 28
Page 28
AD5263
NOTES
© 2003 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective companies.
C03142-0-6/03(0)
Rev. 0 | Page 28 of 28
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