Datasheet AD5260 Datasheet (ANALOG DEVICES)

S

A

1-/2-Channel 15 V Digital Potentiometer

FEATURES

256 positions AD5260: 1 channel AD5262: 2 channels (independently programmable) Potentiometer replacement

20 kΩ, 50 kΩ, 200 kΩ Low temperature coefficient: 35 ppm/°C 4-wire, SPI-compatible serial data input 5 V to 15 V single-supply; ±5.5 V dual-supply operation Power on midscale preset

APPLICATIONS

Mechanical potentiometer replacement Instrumentation: gain, offset adjustment Stereo channel audio level control Programmable voltage-to-current conversion Programmable filters, delays, time constants Line impedance matching Low resolution DAC replacement

GENERAL DESCRIPTION

The AD5260/AD5262 provide a single- or dual-channel, 256position, digitally controlled variable resistor (VR) device. These devices perform the same electronic adjustment function as a potentiometer or variable resistor. Each channel of the AD5260/AD5262 contains a fixed resistor with a wiper contact that taps the fixed resistor value at a point determined by a digital code loaded into the SPI-compatible serial-input register. The resistance between the wiper and either end point of the fixed resistor varies linearly with respect to the digital code transferred into the VR latch. The variable resistor offers a completely programmable value of resistance, between the A terminal and the wiper or the B terminal and the wiper. The fixed A-to-B terminal resistance of 20 Ω, 50 Ω, or 200 Ω has a nominal temperature coefficient of 35 ppm/°C. Unlike the majority of the digital potentiometers in the market, these devices can operate up to 15 V or ±5 V provided proper supply voltages are furnished.

Each VR has its own VR latch that holds its programmed resistance value. These VR latches are updated from an internal serial-to-parallel shift register, which is loaded from a standard 3-wire serial-input digital interface. The AD5260 contains an 8-bit serial register whereas the AD5262 contains a 9-bit serial register. Each bit is clocked into the register on the positive

1

AD5260/AD5262

FUNCTIONAL BLOCK DIAGRAMS

WB

HDN

V V

CS

CLK

SDI

GND

DD

SS

V

L

LOGIC

RDAC

REGISTER

SERIAL INPUT REGISTER

Figure 1. AD5260

1W1B1 A2W2B2

SHDN

V

CS

CLK

SDI

GND

DD

SS

V

L

LOGIC

RDAC1

REGISTER

SERIAL INPUT REGIST ER

AD5262

Figure 2. AD5262

edge of the CLK pin. The AD5262 address bit determines the corresponding VR latch to be loaded with the last eight bits of the data word during the positive edging of data output pin at the opposite end of the serial register enables simple daisy-chaining in multiple VR applications without additional external decoding logic. An optional reset pin ( forces the wiper to the midscale position by loading 0x80 into the VR latch.

The AD5260/AD5262 are available in thin surface-mount 14-lead TSSOP and 16-lead TSSOP packages. All parts are guaranteed to operate over the extended industrial temperature range of −40°C to +85°C.

1

The terms digital potentiometers, VR, and RDAC are used interchangeably.

AD5260

8

POWER-ON

RESET

RDAC2

REGISTER

POWER-ON

RESET

8

CS

strobe. A serial

PR

SDO

PR

SDO

PR

02695-001

02695-002

)

Rev. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Anal og Devices for its use, nor for any infringements of patents or ot her rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

AD5260/AD5262

REVISION HISTORY

8/10—Rev. 0 to Rev. A

Updated Format..................................................................Universal

Deleted Figure 1; Renumbered Sequentially................................. 1

Changes to General Description Section ...................................... 1

Changes to Conditions of Channel Resistance Matching (AD5262 only) Parameter, Voltage Divider Temperature Coefficient Parameter, Full-Scale Error Parameter, and Zero-

Scale Error Parameter, Table 1........................................................ 3

Changes to Table 2 and Table 3....................................................... 5

Changes to Table 4............................................................................ 6

Changes to Table 5............................................................................ 7

Changes to Table 6............................................................................ 8

Changes to Figure 11 Caption and Figure 12 ................................9

Changes to Figure 31...................................................................... 12

Changes to Figure 35 Caption ...................................................... 13

Changes to Figure 43 and Figure 46............................................. 14

Deleted Potentiometer Family Selection Guide ......................... 18

Change to Programmable Voltage Source with Boosted Output

Section.............................................................................................. 20

Changes to Figure 64...................................................................... 21

Updated Outline Dimensions....................................................... 23

Changes to Ordering Guide.......................................................... 24

3/02—Revision 0: Initial Version

Rev. A | Page 2 of 24

AD5260/AD5262

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—20 kΩ, 50 kΩ, 200 kΩ VERSIONS

VDD = +15 V, VSS = 0 V, or VDD = +5 V, VSS = –5 V; VL = +5 V; VA = +5 V, VB = 0 V, −40°C < TA < +85°C, unless otherwise noted. The AD5260/AD5262 contain 1968 transistors. Die size: 89 mil × 105 mil (9345 sq mil).

Table 1.

Parameter Symbol Conditions Min Typ1 Max Unit

DC CHARACTERISTICS RHEOSTAT MODE Specifications apply to all VRs

Resistor Differential Nonlinearity2 R-DNL RWB, VA = no connect −1 ±¼ +1 LSB

Resistor Nonlinearity2 R-INL RWB, VA = no connect −1 ±½ +1 LSB

Nominal Resistor Tolerance3 ΔRAB TA = 25°C −30 30 %

Resistance Temperature Coefficient ΔRAB/ΔT Wiper = no connect 35 ppm/°C

Wiper Resistance RW IW = 1 V/RAB 60 150 Ω

Channel Resistance Matching (AD5262 only) ΔRWB/RWB Channel 1 and Channel 2 RWB,

= 0x80

D

X

Resistance Drift ΔRAB 0.05 %

DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE Specifications apply to all VRs

Resolution N 8 Bits

Differential Nonlinearity4 DNL −1 ±1/4 +1 LSB

Integral Nonlinearity4 INL −1 ±1/2 +1 LSB

Voltage Divider Temperature Coefficient ΔVW/ΔT Code = half scale 5 ppm/°C

Full-Scale Error W

Zero-Scale Error V

Code = full scale −2 −1 +0 LSB

FSE

Code = zero scale 0 1 2 LSB

WZSE

RESISTOR TERMINALS

Voltage Range5 V

Ax and Bx Capacitance6 C

VSS VDD V

A, B, W

f = 5 MHz, measured to GND,

A,B

code = half scale

Wx Capacitance6 CW f = 1 MHz, measured to GND,

code = half scale Common-Mode Leakage Current ICM VA = VB = VDD/2 1 nA Shutdown Current7 I

5 μA

SHDN

DIGITAL INPUTS and OUTPUTS

Input Logic High VIH 2.4 V Input Logic Low VIL 0.8 V Input Logic High VIH VL = 3 V, VSS = 0 V 2.1 V Input Logic Low VIL VL = 3 V, VSS = 0 V 0.6 V Output Logic High (SDO) VOH R Output Logic Low (SDO) VOL IOL = 1.6 mA, V

= 2 kΩ to 5 V 4.9 V

PULL-UP

= 5 V 0.4 V

LOGIC

Input Current8 IIL VIN = 0 V or 5 V ±1 μA Input Capacitance6 CIL 5 pF

POWER SUPPLIES

Logic Supply VL 2.7 5.5 V Power Single-Supply Range V Power Dual-Supply Range V

VSS = 0 V 4.5 16.5 V

DD RANGE

DD/SS RANGE

±4.5 ±5.5 V

Logic Supply Current IL VL = 5 V 60 μA Positive Supply Current IDD VIH = 5 V or VIL = 0 V 1 μA Negative Supply Current ISS VSS= −5 V 1 μA Power Dissipation9 P

V

DISS

= 5 V or VIL = 0 V,

IH

V

DD

= +5 V, VSS = –5 V

Power Supply Sensitivity PSS ΔVDD= +5 V, ±10% 0.003 0.01 %/%

0.1 %

25 pF

55 pF

0.3 mW

Rev. A | Page 3 of 24

AD5260/AD5262

Parameter Symbol Conditions Min Typ1 Max Unit

DYNAMIC CHARACTERISTICS

Bandwidth –3 dB BW RAB = 20 kΩ/50 kΩ/200 kΩ 310/130/30 kHz Total Harmonic Distortion THDW VA = 1 V

VW Settling Time tS VA = +5 V, VB = −5 V, ±1 LSB

Crosstalk11 CT VA = VDD, VB = 0 V, measure VW

Analog Crosstalk CTA VA1 = VDD, VB1 = 0 V, measure VW1

Resistor Noise Voltage e

INTERFACE TIMING CHARACTERISTICS

Clock Frequency f Input Clock Pulse Width tCH, tCL Clock level high or low 20 ns Data Setup Time tDS 10 ns Data Hold Time tDH 10 ns CLK to SDO Propagation Delay13 tPD RL = 1 kΩ, CL< 20 pF 1 160 ns CS

Setup Time

CS

High Pulse Width

Reset Pulse Width tRS 50 ns CLK Fall to CS Rise Hold Time

CS

Rise to Clock Rise Setup

1

Typical values represent average readings at 25°C and VDD = +5 V, VSS = −5 V.

2

Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper

positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. IW = VDD/R for both VDD = +5 V and VSS = −5V.

3

VAB = VDD, wiper = no connect.

4

INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output digital-to-analog converter. VA = VDD and VB = 0 V.

DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.

5

Resistor Terminal A, Terminal B, and Terminal W have no limitations on polarity with respect to each other.

6

Guaranteed by design and not subject to production test.

7

Measured at the Ax terminals. All Ax terminals are open-circuit in shutdown mode.

8

Worst-case supply current consumed when all logic-input levels set at 2.4 V, which is the standard characteristic of CMOS logic.

9

P

is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.

DISS

10

All dynamic characteristics use VDD = +5 V, VSS = −5 V, VL = +5 V.

11

Measured at VW where an adjacent VW is making a full-scale voltage change.

12

See Figure 5 for location of measured values. All input control voltages are specified with tR = tF = 2 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. Switching characteristics are measured using VL = 5 V.

13

Propagation delay depends on value of VDD, RL, and CL.

6, 10

= 20 kΩ

R

AB

, VB = 0 V, f = 1 kHz,

RMS

0.014 %

5 μs

error band, R

= 20 kΩ

AB

1 nV-sec with adjacent RDAC making full-scale code change (AD5262 only)

–64 dB

= 5 V p-p at f = 10 kHz,

with V

W2

= 20 kΩ/200 kΩ (AD5262

R

AB

only)

RWB = 20 kΩ, f = 1 kHz 13

6, 12

Specifications apply to all parts

N_WB

25 MHz

CLK

t

5 ns

CSS

t

20 ns

CSW

t

0 ns

CSH

t

10 ns

CS1

nV/√Hz

Rev. A | Page 4 of 24

AD5260/AD5262

V

TIMING DIAGRAMS

Table 2. AD5260 8-Bit Serial Data Word Format

Data

B7 (MSB) B6 B5 B4 B3 B2 B1 B0 (LSB)

D7 D6 D5 D4 D3 D2 D1 D0 27 26 2

Table 3. AD5262 9-Bit Serial Data Word Format

ADDR Data B8 B7 (MSB) B6 B5 B4 B3 B2 B1 B0 (LSB)

A0 D7 D6 D5 D4 D3 D2 D1 D0

8

2

7

26 2

5

2

5

2

SDI

CLK

CS

OUT

1

0 1

0

D7 D6 D5 D4 D3 D2 D1 D0

Figure 3. AD5260 Timing Diagram

SDI

CLK

CS

OUT

1

0 1

0

D7A0 D6 D5 D4 D3 D2 D1 D0

Figure 4. AD5262 Timing Diagram

4

2

3

2

4

2

RDAC REGIST ER L O AD

RDAC REGISTE R L OAD

3

2

1

2

1

2

2695-004

02695-005

0

SDI

(DATA IN)

SDO

(DATA OUT)

CLK

CS

V

OUT

V 0V

1

0

1

0

1

0

1

0

DD

Ax OR Dx

A'x OR D'x

Dx

t

DS

t

DH

D'x

t

CH

t

CL

t

CSS

±1 LSB ERROR BRAND

Figure 5. Detailed Timing Diagram

t

1

PR

0

V

DD

±1 LSB ERRO R B AND

0V

RS

t

S

Figure 6. Preset Timing Diagram

Rev. A | Page 5 of 24

t

PD

t

±1 LSBD

CS1

t

CSH

t

CSW

t

S

±1 LSB

02695-006

02695-007

AD5260/AD5262

ABSOLUTE MAXIMUM RATINGS

TA =25°C, unless otherwise noted.

Table 4.

Parameter Rating

VDD to GND −0.3 V to +17 V VSS to GND 0 V to −7 V VDD to VSS 17 V VL to GND 0 V to +7 V VA, VB, VW to GND VSS, V AX to BX, AX to WX, BX to W

X

DD

Intermittent1 ±20 mA Continuous ±5 mA

Digital Inputs and Output Voltage

to GND

−0.3 V to VL + 0.3 V, or

+7 V (whichever is less) Operating Temperature Range −40°C to +85°C Maximum Junction Temperature

)

(T

J MAX

150°C

Storage Temperature Range −65°C to +150°C Lead Temperature (Soldering,10 sec) 300°C

Vapor Phase (60 sec) 215°C Infrared (15 sec) 220°C

Thermal Resistance2 θ

JA

14-Lead TSSOP 206°C/W 16-Lead TSSOP 150°C/W

1

Maximum terminal current is bounded by the maximum current handling of

the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the A, B, and W terminals at a given resistance setting.

2

Package power dissipation = (T

J MAX

− TA)/θJA.

Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ESD CAUTION

Rev. A | Page 6 of 24

AD5260/AD5262

S

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

1

A

2

W

3

B

4

V

DD

5

HDN

6

CLK

7

SDI

NC = NO CONNECT

AD5260

TOP VIEW

(Not to S cale)

14

SDO

13

NC

12

V

L

11

V

SS

10

GND

9

PR

8

CS

2695-008

Figure 7. AD5260 Pin Configuration

Table 5. AD5260 Pin Function Descriptions

Pin No. Mnemonic Description

1 A A Terminal. 2 W Wiper Terminal. 3 B B Terminal. 4 VDD Positive Power Supply. Specified for operation at both 5 V or 15 V (sum of |VDD| + |VSS| ≤ 15 V). 5

SHDN

Active Low Input. Terminal A, open-circuit. Shutdown controls variable resistor. 6 CLK Serial Clock Input, Positive Edge Triggered. 7 SDI Serial Data Input. 8 9

CS PR

Chip Select Input, Active Low. When CS

returns high, data is loaded into the RDAC register.

Active Low Preset to Midscale. Sets RDAC registers to 0x80. 10 GND Ground. 11 VSS Negative Power Supply. Specified for operation from 0 V to −5 V. 12 VL Logic Supply Voltage. Needs to be the same voltage as the digital logic controlling the AD5260. 13 NC No Connect. Users should not connect anything other than a dummy pad on this pin. 14 SDO Serial Data Output. Open-drain transistor requires a pull-up resistor.

Rev. A | Page 7 of 24

AD5260/AD5262

SDO

W1

V

SHDN

CLK

SDI

A1

B1

DD

1

2

3

AD5262

TOP VIEW

4

(Not to Scale)

5

6

7

8

16

A2

15

W2

14

B2 V

13

L

12

V

SS

11

GND

10

PR

9

CS

02695-009

Figure 8. AD5262 Pin Configuration

Table 6. AD5262 Pin Function Descriptions

Pin No. Mnemonic Description

1 SDO Serial Data Output. Open-drain transistor requires a pull-up resistor. 2 A1 A Terminal RDAC 1. 3 W1 Wiper RDAC 1, Address A0 = 0. 4 B1 B Terminal RDAC 1. 5 VDD Positive Power Supply. Specified for operation at both 5 V or 15 V. (Sum of |VDD| + |VSS| ≤ 15 V) 6

SHDN

Active Low Input. Terminal A, open-circuit. Shutdown controls variable Resistor 1 through Resistor R2.

7 CLK Serial Clock Input, Positive Edge Triggered. 8 SDI Serial Data Input. 9

CS

Chip Select Input, Active Low. When CS

returns high, data in the serial input register is decoded, based on the

Address Bit A0, and loaded into the target RDAC register.

10

PR

Active Low Preset to Midscale. Sets RDAC registers to 0x80.

11 GND Ground. 12 VSS Negative Power Supply. Specified for operation at either 0 V or −5 V (sum of |VDD| + |VSS| < 15 V). 13 VL Logic Supply Voltage. Needs to be same voltage as the digital logic controlling the AD5262. 14 B2 B Terminal RDAC 2. 15 W2 Wiper RDAC 2, Address A0 = 1. 16 A2 A Terminal RDAC 2.

Rev. A | Page 8 of 24

AD5260/AD5262

TYPICAL PERFORMANCE CHARACTERISTICS

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

RHEOST A T MODE INL (LSB)

0

–0.1

–0.2

0 32 64 96 128 160 192 224 256

±5V

CODE (Decimal)

+5V

+12V

+15V

Figure 9. R-INL vs. Code vs. Supply Voltages

0.10

0.05

0

02695-010

0.5

0.4

0.3

0.2

0.1

0

–0.1

–0.2 –0.3

POTENT IOMET ER M O DE DNL (LSB)

–0.4

–0.5

= +85°C

T

A

T

= +125°C

A

= +25°C

T

A

TA = –40°C

0 32 64 96 128 160 192 224 256

CODE (Decimal)

VDD = +5V V

SS

R

AB

Figure 12. DNL vs. Code

0.3

0.2

0.1

+5V ±5V +15V

= –5V = 20kΩ

02695-013

–0.05

–0.10

–0.15

RHEOSTAT MODE DNL (LSB)

–0.20

–0.25

+5V ±5V +12V +15V

0 32 64 96 128 160 192 224 256

CODE (Decimal)

Figure 10. R-DNL vs. Code vs. Supply Voltages

1.0

0.8

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

POTENT I OMETER MO D E I NL (LSB)

–0.8

–1.0

0 32 64 96 128 160 192 224 256

T

= +125°C

A

T

A

CODE (Decimal )

TA = +85°C

= +25°C

VDD = +5V V

SS

R

AB

T

A

Figure 11. INL vs. Code

= –5V = 20kΩ

= –40°C

0

–0.1

–0.2

POTENTIOMETER MODE INL (LSB)

–0.3

–0.4

0 32 64 96 128 160 192 224 256

02695-011

CODE (Decimal)

02695-014

Figure 13. INL vs. Code vs. Supply Voltages

0.5

0.4

0.3

0.2

0.1

0

–0.1

–0.2

–0.3

POTENT IOMET E R M ODE DNL (LSB)

–0.4

–0.5

02695-012

±5V +15V +5V

0 32 64 96 128 160 192 224 256

CODE (Decim al)

02695-015

Figure 14. DNL vs. Code vs. Supply Voltages

Rev. A | Page 9 of 24

AD5260/AD5262

A

1.0

2.5

0.5

0

–0.5

POTENTIOMETER MODE INL (LSB)

–1.0

0 5 10 15 20

AVG + 3σ

AVG

AVG – 3σ

|V

– VSS| (V)

DD

Figure 15. INL vs. Supply Voltages

2.0

1.5

AVG + 3σ

1.0

0.5

T MODE INL (LSB)

–0.5

–1.0

RHEOST

–1.5

–2.0

AVG

AVG – 3σ

0

05

|V

10

– VSS| (V)

DD

15 20

Figure 16. R-INL vs. Supply Voltages

124

104

84

64

RON @ VDD/VSS = +5V/0V

RON @ VDD/VSS = +5V/–5V

2.0 VDD/VSS=+15/0V

1.5

FSE (LSB)

1.0

VDD/VSS=+5V/0V

0.5

0 –40 –20 0 20 40 60 80 100

02695-016

TEMPERATURE (°C)

V

DD/VSS

=±5V

02695-019

Figure 18. Full-Scale Error vs. Temperature

2.5

2.0

VDD/VSS=+5V/0V

1.5

ZSE (LSB)

1.0

0.5

0

–40 –20 0 20 40 60 80 100

02695-017

VDD/VSS=±5V

VDD/VSS=+15/0V

TEMPERATURE (°C)

02695-020

Figure 19. Zero-Scale Error vs. Temperature

1

V

= 5V

LOGIC

V

= 5V

IH

= 0V

V

0.1

IL

44

WIPER RESISTANCE (Ω)

24

4

–5 –1 3 7 11 15

R

@ VDD/VSS = +15V/0V

ON

V

(V)

DD

Figure 17. Wiper On Resistance vs. Bias Voltage

02695-018

SUPPLY CUR RE NT (µA)

0.01

SS

/I

DD

I

0.001

–40–726599212

VDD/VSS = +15/0V

VDD/VSS = ±5V

TEMPERATURE (°C)

Figure 20. Supply Current vs. Temperature

5

02695-021

Rev. A | Page 10 of 24

AD5260/AD5262

A

28.0

27.5

27.0

Figure 21. I

Figure 22. I

20kΩ

50kΩ

200kΩ

VDD/VSS = +15/0V

VDD/VSS = ±5V

TEMPERATURE (° C)

vs. Temperature

LOGIC

VDD/VSS = 5V/0V V

= 3V

LOGIC

(V)

V

IH

vs. Digital Input Voltage

LOGIC

CODE (Decimal)

VDD/VSS = 5V/0V V

= 5V

LOGIC

/ΔT vs. Code

WB

26.5

(µA)

26.0

LOGIC

I

25.5

25.0

24.5

–40–726599212

1000

(µA)

100

LOGIC

I

10

0 1.0 2.0 3.0 4.00.5 1.5 2.5 3.5 4.5 5.0

80

70

60

50

40

30

20

T MODE TEMPCO (ppm/°C)

10

0

RHEOST

–10 –20

0 32 64 96 128 160 192 224 256

Figure 23. Rheostat Mode Tempco ΔR

5

2695-022

02695-023

02695-024

120

100

80

60

40

20

0

–20

–40

POTENTIOMETER MODE TEMPCO (ppm/°C)

–60

Figure 24. Potentiometer Mode Tempco ΔV

6

0

–6

–12

–18

–24

GAIN (dB)

–30

–36

–42

–48

–54

1k 1M

6

0

–6

–12

–18

–24

GAIN (dB)

–30

–36

–42

–48

–54

1k 1M

20kΩ

50kΩ

200kΩ

0 32 64 96 128 160 192 224 256

T

= 25°C

A

Figure 25. Gain vs. Frequency vs. Code, R

T

= 25°C

A

Figure 26. Gain vs. Frequency vs. Code, R

CODE (Decim al )

CODE = 0xFF

0x80

0x40

0x20 0x10 0x08

0x04 0x02

0x01

10k 100k

FREQUENCY (Hz)

CODE = 0xFF

0x80

0x40

0x20 0x10 0x08

0x04 0x02 0x01

10k 100k

FREQUENCY (Hz)

/ΔT vs. Code

WB

= 20 kΩ

AB

= 50 kΩ

AB

02695-025

02695-026

02695-027

Rev. A | Page 11 of 24

AD5260/AD5262

6

TA = 25°C

0

–6

–12

–18

–24

GAIN (dB)

–30

–36

–42

–48

–54

1k 1M

Figure 27. Gain vs. Frequency vs. Code, R

6

0

–6

–12

–18

–24

GAIN (dB)

–30

–36

–42

–48

–54

f

–3dB

–3dB BANDWIDTHS

1k 1M10k 100k

CODE = 0xFF

0x80

0x40

0x20 0x10

0x08

0x04

0x02 0x01

10k 100k

FREQUENCY (Hz)

f

= 131kHz, R = 50kΩ

–3dB

= 30kHz, R = 200 kΩ

FREQUENCY (Hz)

f

= 310kHz, R = 20kΩ

–3dB

= 200 kΩ

AB

VIN = 50mV rms V

DD/VSS

Figure 28. −3 dB Bandwidth

0.3 CODE = 0x80

0.2

V

= ±5V

DD/VSS

T

= 25°C

A

0.1

0

–0.1

–0.2

–0.3

–0.4

–0.5

NORMALI Z E D G AI N FLATNESS ( d B)

–0.6

–0.7

100 100k1k

R = 200kΩ

FREQUENCY ( Hz)

R = 50kΩ

10k

Figure 29. Normalized Gain Flatness vs. Frequency

= ±5V

R = 20kΩ

02695-028

02695-029

02695-030

600

500

400

(µA)

300

LOGIC

I

200

100

0

10k 10M100k

FREQUENCY (Hz)

Figure 30. I

60

50

40

30

PSRR (dB)

20

10

0

100 1M

–PSRR @ VDD = ±5V DC ± 10% p-p AC

+PSRR @ V

DD

1k

FREQUENC Y ( Hz)

VDD/VSS = ±5V

V

= +5V/0V

DD/VSS

vs. Frequency

LOGIC

CODE = 0x80, V

= ±5V DC ± 10% p-p AC

10k

CODE 0xFF

CODE 0x55

1M

= VDD, VB = 0V

A

100k

Figure 31. PSRR vs. Frequency

20mV/DIV

5V/DIV

1µs/DIV

Figure 32. Midscale Glitch Energy, Code 0x80 to 0x7F

02695-031

02695-032

02695-033

Rev. A | Page 12 of 24

AD5260/AD5262

S

A

0.10 CODE = 0x80

= ±5V

V

DD/VSS

SAMPLE SIZE = 135 UNITS

0.05

TAN CE (% )

0

AVG – 3σ

5V/DIV

10mV/DIV

100

20µs/DIV

Figure 33. Large Signal Settling Time

40ns/DIV

Figure 34. Digital Feedthrough vs. Time

VA = VB = OPEN

= 25°C

T

A

–0.05

–0.10

–0.15

CHANGE IN T E RM INAL RESI

–0.20

05

02695-034

100 200 250 300 350 400 450

50 150

HOURS OF OPE RATION AT 150°C

AVG

AVG + 3σ

00

2695-037

Figure 36. Long-Term Resistance Drift

40

CODE SET TO MIDS CA LE T

= 150°C

A

3 LOTS SAMPLE SIZE = 135 UNITS

30

20

FREQUENCY

10

0

02695-035

–0.40 –0.30 –0.20 –0.10 0 0.10 0.20

–0.50

CHANNEL-TO-CHANNEL RAB MATCH (%)

02695-038

Figure 37. Channel-to-Channel Resistance Matching (AD5262)

10

(mA)

WB_MAX

1

L I

= 50kΩ

R

0.1

THEORETIC

0.01 02

32 64 96 128 160 192 224

AB

CODE (Decimal)

R

AB

= 20kΩ

R

AB

= 200kΩ

56

02695-036

Figure 35. Theoretical Maximum Current vs. Code

Rev. A | Page 13 of 24

AD5260/AD5262

V

TEST CIRCUITS

Figure 38 to Figure 46 define the test conditions used in Ta b le 1 .

0.1V

RW=

I

W

CODE = 0x00

DD

I

CM

I

LOGIC

0.1V

02695-044

V

CM

02695-045

+ = V

DUT

A

V+

W

B

DD

1LSB = V+/2

N

V

MS

02695-039

Figure 38. Potentiometer Divider Nonlinearity Error (INL, DNL)

NC

NC = NO CONNECT

DUT

A

B

W

I

W

V

MS

02695-040

Figure 39. Resistor Position Nonlinearity Error

(Rheostat Operation; R-INL, R-DNL)

DUT

W

B

I

W

A = NC

VSS TO V

Figure 43. Incremental On Resistance

NC

V

DD

DUT V

SS

GND

NC

A

W

B

Figure 44. Common-Mode Leakage Current

LOGIC

CS

CLK

DIGIT AL INPUT

VOLTAGE

Figure 45. V

V

IN

SDI

Current vs. Digital Input Voltage

LOGIC

V

W1

DD

A2

W2

B2

V

SS

B1

)

OUT/VIN

A1

RDAC1 RDAC2

NC

CTA = 20 log (V NC = NO CONNECT

Figure 46. Analog Crosstalk

02695-046

V

OUT

02695-047

MS2

DUT A

B

W

V

W

IW= VDD/R

V

MS1

Figure 40. Wiper Resistance

A

V

DD

A

V+

W

B

V+ = V

PSRR (dB) = 20 log

PSS (%/%) =

V

MS

Figure 41. Power Supply Sensitivity (PSS, PSSR)

A

W

B

OFFSET

GND

V

DUT

IN

NOMINAL

RW= (V

± 10%

DD

+13V

AD8610

–13V

MS1

∆VMS% ∆V

DD

– V

)/I

MS2

W

∆V

MS

()

∆V

DD

%

V

OUT

02695-041

02695-042

2695-043

Figure 42. Gain vs. Frequency

Rev. A | Page 14 of 24

AD5260/AD5262

THEORY OF OPERATION

The AD5260/AD5262 provide a single- or dual-channel, 256position, digitally controlled variable resistor (VR) device and operate up to 15 V maximum voltage. Changing the programmed VR settings is accomplished by clocking an 8-/9-bit serial data word into the SDI (serial data input) pin. For the AD5262, the format of this data word is one address bit. A0 represents the first bit, B8, followed by eight data bits, B7 to B0, with MSB first. Table 2 and Tab l e 3 provide the serial register data word format. See Tabl e 7 for the AD5262 address assignment to decode the location of the VR latch receiving the serial register data in Bit B7 through Bit B0. VR outputs can be changed one at a time in random sequence. The AD5260/AD5262 preset to a midscale, simplifying fault condition recovery at power-up. Midscale can also be achieved at any time by asserting the

PR

pin. Both parts have an internal power-on preset that places the wiper in a midscale preset condition at power-on. Operation of the poweron preset function depends only on the state of the V

The AD5260/AD5262 contain a power shutdown

pin.

L

SHDN

pin that places the RDAC in an almost zero power consumption state where Terminals Ax are open circuited and the Wiper W is connected to B, resulting in only leakage currents being consumed in the VR structure. In the shutdown mode, the VR latch settings are maintained so that, when returning to operational mode from power shutdown, the VR settings return to their previous resistance values.

Table 7. AD5262 Address Decode Table

A0 Latch Loaded

0 RDAC1 1 RDAC2

DIGITAL INTERFACING

The AD5260/AD5262 contain a 4-wire SPI-compatible digital

CS

interface (SDI, SDO, serial word must be loaded with the MSB first. The format of the word is shown in . For the AD5262, the 9-bit serial word must be loaded with Address Bit A0 first, then the MSB of the data. The format of the word is shown in .

, and CLK). For the AD5260, the 8-bit

Tabl e 2

Tabl e 3

V

CS

CLK

SDI

SDO

PR

GND

L

RDAC

LATCH

1

PR

EN

ADDR

A0

SER

REG

POWER-

ON

PRESET

DEC

D7 D6 D5 D4 D3 D2 D1 D0

Figure 47. AD5262 Block Diagram

RDAC

LATCH

2

PR

V

DD

A1 W1 B1

A2 W2 B2

SHDN

V

SS

02695-048

The positive-edge sensitive CLK input requires clean transitions to avoid clocking incorrect data into the serial input register. Standard logic families work well. If mechanical switches are used for product evaluation, they should be debounced by a flip-flop or other suitable means. Figure 47 shows more detail of the internal digital circuitry. When

CS

is low, the clock loads data into

the serial input register on each positive clock edge (see ). Tabl e 8

Table 8. Truth Table

CS

CLK

1

PR SHDN

Register Activity

Low Low High High No SR effect, enables SDO pin.

Low High High

↑

Shift one bit in from the SDI pin. The eighth previously entered bit is shifted out of the SDO pin.

X

High High Load SR data into RDAC latch.

↑ X High High High No operation. X X Low High

Sets all RDAC latches to half scale, wiper centered, and SDO

latch cleared. X High X High High Low

High Latches all RDAC latches to 0x80.

↑

Open circuits all Resistor A

terminals, connects W to B, and

turns off SDO output transistor.

1

↑ = positive edge, X = don’t care, SR = shift register.

The data setup and data hold times in Tab l e 1 determine the data valid time requirements. The AD5260 uses an 8-bit serial input data register word that is transferred to the internal RDAC register when the

CS

line returns to logic high. For the AD5262, the last nine bits of the data word entered into the serial register are held when ignored. At the same time

CS

returns high. Any extra bits are

CS

goes high, it gates the address decoder, enabling one of two positive edge-triggered AD5262 RDAC latches (see ). Figure 48

Rev. A | Page 15 of 24

AD5260/AD5262

V

S

AD5260/AD5262

CS

CLK

SDI

ADDR

DECODE

SERIAL

REGISTER

RDAC1 RDAC2

02695-049

Figure 48. Equivalent Input Control Logic

The target RDAC latch is loaded with the last eight bits of the serial data word completing one RDAC update. For the AD5262, two separate 9-bit data words must be clocked in to change both VR settings.

During shutdown (

SHDN

), the SDO output pin is forced to the off (logic high) state to disable power dissipation in the pull-up resistor. See for the equivalent SDO output circuit

Figure 49

schematic.

SHDN

CS

SDI

CLK

PR

SERIAL

REGISTER

DQ

CK RS

SDO

02695-050

Figure 49. Detail SDO Output Schematic of the AD5260

All digital inputs are protected with a series input resistor and parallel Zener ESD structure as shown in Figure 50. This applies to the

CS

, SDI, SDO, PR,

Figure 50. ESD Protection of Digital Pins

Figure 51. ESD Protection of Resistor Terminals

340Ω

A, B, W

SHDN

, and CLK digital input pins.

LOGIC

02695-051

V

SS

02695-052

DAISY-CHAIN OPERATION

The serial data output (SDO) pin contains an open-drain Nchannel FET. This output requires a pull-up resistor to transfer data to the SDI pin of the next package. This allows for daisychaining several RDACs from a single processor serial data line. The pull-up resistor termination voltage can be larger than the V

supply voltage. It is recommended to increase the clock

DD

period when using a pull-up resistor to the SDI pin of the following device in series because capacitive loading at the daisy-chain node connecting SDO and SDI between devices may induce time delay to subsequent devices. Users should be aware of this potential problem to achieve data transfer successfully (see Figure 52). If two AD5260s are daisy-chained, this requires a total of 16 bits of data. The first eight bits, complying with the format shown in Tabl e 2 , go to U2, and the second eight bits with the same format go to U1. The kept low until all 16 bits are clocked into their respective serial

CS

pin should be

CS

registers, and the

pin is then pulled high to complete the

operation.

DD

MICRO-

CONTROLLER

SCLK SS

AD5260 AD5260

U1

CLK

CS

R

P

2.2kΩ

SDOSDIMOSI

CS

U2

SDOSDI

CLK

02695-055

Figure 52. Daisy-Chain Configuration

RDAC STRUCTURE

The RDAC contains a string of equal resistor segments with an array of analog switches that act as the wiper connection. The number of positions is the resolution of the device. The AD5260/ AD5262 have 256 connection points, allowing it to provide better than 0.4% settability resolution. Figure 53 shows an equivalent structure of the connections between the three terminals that make up one channel of the RDAC. SW on, while one of the switches SW(0) to SW(2

and SWB are always

A

N

– 1) is on one at a time, depending on the resistance position decoded from the data bits. Because the switch is not ideal, there is a 60 Ω wiper resistance, R

. Wiper resistance is a function of supply voltage

W

and temperature. The lower the supply voltage is, the higher the wiper resistance becomes. Similarly, the higher the temperature is, the higher the wiper resistance becomes. Users should be aware of the contribution of the wiper resistance when accurate prediction of the output resistance is needed.

Ax

HDN

D7 D6 D5 D4 D3

D2 D1 D0

RDAC

LATCH

AND

DECODE

DIGIT AL CIRCUITRY OMITTED FOR CLARITY

Figure 53. Simplified RDAC Architecture

R

S

R

S

R

S

Wx

R

S

= RAB/2

R

S

Bx

N

02695-056

PROGRAMMING THE VARIABLE RESISTOR

Rheostat Operation

The nominal resistances of the RDAC between Terminal A and Terminal B are available with values of 20 kΩ, 50 kΩ, and 200 kΩ. The final three digits of the part number determine the nominal resistance value, for example, 20 kΩ = 20, 50 kΩ = 50, 200 kΩ =

200. The nominal resistance (R

) of the VR has 256 contact points

AB

Rev. A | Page 16 of 24

AD5260/AD5262

R

accessed by the wiper terminal, plus the B terminal contact. The 8-bit data in the RDAC latch is decoded to select one of the 256 possible settings. Assuming a 20 kΩ part is used, the wiper’s first connection starts at the B terminal for data 0x00. Because there is a 60 Ω wiper contact resistance, such a connection yields a minimum of 60 Ω resistance between Terminal W and Terminal B. The second connection is the first tap point corresponding to 138 Ω (R

= RAB/256 RW = 78 Ω + 60 Ω) for Data 0x01. The third

WB

connection is the next tap point representing 216 Ω (78 × 2 + 60) for Data 0x02, and so on. Each LSB data value increase moves the wiper up the resistor ladder until the last tap point is reached at 19,982 Ω (R

− 1 LSB + RW). The wiper does not directly connect

AB

to the B terminal. See Figure 53 for a simplified diagram of the equivalent RDAC circuit.

The general equation determining the digitally programmed output resistance between W and B is

WB

DR +×=

)(

D

256

AB

(1)

RR

W

where D is the decimal equivalent of the binary code that is loaded in the 8-bit RDAC register and R

is the nominal end-

AB

to-end resistance.

For example, when R open circuit, the following output resistance values of R

= 20 kΩ, VB = 0 V, and the A terminal is

AB

are

WB

set for the RDAC latch codes shown in Tabl e 9 . The result is the same if Terminal A is tied to W.

Table 9. RWB vs. Code

RDAC (Dec) RWB (Ω) Output State

256 19,982 Full scale (RAB – 1 LSB + RW) 128 10,060 Midscale 1 138 1 LSB 0 60 Zero-scale (wiper contact resistance)

Note that in the zero-scale condition, a finite wiper resistance of 60 Ω is present. Care should be taken to limit the current flow between W and B in this state to no more than 20 mA to avoid degradation or possible destruction of the internal switches.

Like the mechanical potentiometer the RDAC replaces, the AD5260/AD5262 are completely symmetrical. The resistance between Wiper W and Terminal A also produces a digitally controlled complementary resistance, R

. Figure 54 shows the

WA

symmetrical programmability of the various terminal connections. When R tied to the wiper. Setting the resistance value for R

is used, the B terminal can be left floating or

WA

starts at a

WA

maximum value of resistance and decreases as the data loaded in the latch is increased in value. The general equation for this operation is

D

−

256

DR +×

=

)(

256

For example, when R

ABWA

= 20 kΩ, VA = 0 V, and the B terminal is

AB

open circuit, the following output resistance values of R

(2)

RR

W

are

WA

set for the RDAC latch codes shown in Tabl e 1 0 . The result is the same if Terminal B is tied to Terminal W.

Table 10. RWA vs. Code

RDAC (Dec) RWA (Ω) Output State

256 60 Full scale 128 10,060 Half scale 1 19,982 1 LSB 0 20,060 Zero scale

(D) – kΩ

(D), R

20

16

12

WB

8

WA

4

0

R

WA

RAB = 20kΩ

0 64 128 192 256

Figure 54. AD5260/AD5262 Equivalent RDAC Circuit

CODE (Deci mal )

R

WB

02695-057

The typical distribution of the nominal resistance RAB from channel to channel matches within ±1%. Device-to-device matching is process lot-dependent with the worst case of ±30% variation. However, because the resistance element is processed in thin film technology, the change in R

AB

with

temperature has a low 35 ppm/°C temperature coefficient.

PROGRAMMING THE POTENTIOMETER DIVIDER

Voltage Output Operation

The digital potentiometer easily generates output voltages at wiper-to-B and wiper-to-A to be proportional to the input voltage at A-to-B. Ignore the effect of the wiper resistance. For example, connecting the A terminal to 5 V and the B terminal to ground produces an output voltage at W-to-B starting at 0 V up to 1 LSB less than 5 V. Each LSB of voltage is equal to the voltage applied across Terminal A and Terminal B divided by the 256 positions of the potentiometer divider. Because the AD5260/AD5262 operate from dual supplies, the general equation defining the output voltage at V ground for any given input voltage applied to Terminal A and Terminal B is

W

256

AB

D

DV +×=

)(

(3)

VV

B

Operation of the digital potentiometer in the divider mode results in more accurate operation over temperature. Unlike the rheostat mode, the output voltage is dependent on the ratio of the internal resistors, R

and RWB, and not the absolute values;

WA

therefore, the drift reduces to 5 ppm/°C.

with respect to

W

Rev. A | Page 17 of 24

AD5260/AD5262

V

LAYOUT AND POWER SUPPLY BYPASSING

It is good practice to employ a compact, minimum lead length layout design. The leads to the input should be as direct as possible with a minimum conductor length. Ground paths should have low resistance and low inductance.

Similarly, it is also good practice to bypass the power supplies with quality capacitors for optimum stability. Supply leads to the device should be bypassed with 0.01 μF to 0.1 μF disc or chip ceramic capacitors. Low ESR 1 μF to 10 μF tantalum or electrolytic capacitors should also be applied at the supplies to minimize any transient disturbance (see Figure 55). Note that the digital ground should also be joined remotely to the analog ground to minimize the ground bounce.

V

DD

V

SS

+ 10µF + 10µF

C1

0.1µF

C2

0.1µF

C3

C4

Figure 55. Power Supply Bypassing

V

DD

V

GND

SS

02695-053

TERMINAL VOLTAGE OPERATING RANGE

The AD5260/AD5262 positive VDD and negative VSS power supply defines the boundary conditions for proper 3-terminal digital potentiometer operation. Supply signals present on the A, B, and W terminals that exceed V the internal forward-biased diodes (see Figure 56).

Figure 56. Maximum Terminal Voltages Set by V

The ground pin of the AD5260/AD5262 device is primarily used as a digital ground reference, which needs to be tied to the common ground of the PCB. The digital input control signals to the AD5260/AD5262 must be referenced to the device ground pin (GND), and must satisfy the logic level defined in Ta b le 1 . An internal level shift circuit ensures that the common-mode

or VSS are clamped by

DD

A W B

V

SS

02695-054

and VSS

DD

voltage range of the three terminals extends from V regardless of the digital input level.

POWER-UP SEQUENCE

Because there are diodes to limit the voltage compliance at Terminal A, Terminal B, and Terminal W (see Figure 56), it is important to power V

first before applying any voltage to

DD/VSS

the A, B, and W terminals. Otherwise, the diode becomes forward biased such that V

are powered unintentionally and may

DD/VSS

affect the rest of the user’s circuit. The ideal power-up sequence is in the following order: GND, V and V

A/VB/VW

. The order of powering VA/VB/VW and the digital

, VSS, VL, the digital inputs,

DD

inputs is not important as long as they are powered after V

RDAC CIRCUIT SIMULATION MODEL

The internal parasitic capacitances and the external capacitive loads dominate the ac characteristics of the RDACs. Configured as a potentiometer divider, the −3 dB bandwidth of the AD5260 (20 kΩ resistor) measures 310 kHz at half scale. Figure 28 provides the large signal Bode plot characteristics of the three available resistor versions 20 kΩ, 50 kΩ, and 200 kΩ. A parasitic simulation model is shown in Figure 57. The following section provides a macro model net list for the 20 kΩ RDAC.

RDAC

AB

25pF

Figure 57. RDAC Circuit Simulation Model for RDAC 20 kΩ

20kΩ

C

W

55pF

W

C

B

25pF

02695-071

C

A

MACRO MODEL NET LIST FOR RDAC

PARAM D=256, RDAC=20E3 * SUBCKT DPOT (A,W,B) * CA A 0 25E-12 RWA A W {(1-D/256)*RDAC+60} CW W 0 55E-12 RWB W B {D/256*RDAC+60} CB B 0 25E-12 * .ENDS DPOT

to VDD

SS

DD/VSS

.

Rev. A | Page 18 of 24

AD5260/AD5262

V

APPLICATIONS INFORMATION

BIPOLAR DC OR AC OPERATION FROM DUAL SUPPLIES

The AD5260/AD5262 can be operated from dual supplies enabling control of ground referenced ac signals or bipolar operation. The ac signal, as high as V

, can be applied

DD/VSS

directly across Terminal A and Terminal B with output taken from Terminal W. See Figure 58 for a typical circuit connection.

+5.0V

V

DD

GND

SS

SCLK

MOSI

MICROCONTROLLER

Figure 58. Bipolar Operation from Dual Supplies

CS

CLK

SDI

GND

V

DD

±2.5V p-p

D = 0x80

V

SS

±5V p-p

–5.0V

GAIN CONTROL COMPENSATION

Digital potentiometers are commonly used in gain control as in the noninverting gain amplifier shown in Figure 59.

C2

4.7pF

R2

200kΩ

A

R1

47kΩ

C1

25pF

Figure 59. Typical Noninvertng Gain Amplifier

Note that when the RDAC B terminal parasitic capacitance is connected to the op amp noninverting node, it introduces a zero for the 1/β

term with +20 dB/dec, whereas a typical op amp

O

gain bandwidth product (GBP) has −20 dB/dec characteristics. A large R2 and finite C1 can cause this zero’s frequency to fall well below the crossover frequency. Therefore, the rate of closure becomes 40 dB/dec and the system has 0 phase margin at the crossover frequency. The output may ring or oscillate if the input is a rectangular pulse or step function. Similarly, it is also likely to ring when switching between two gain values because this is equivalent to a step change at the input.

Depending on the op amp GBP, reducing the feedback resistor may extend the zero’s frequency far enough to overcome the problem. A better approach, however, is to include a compensation capacitor, C2, to cancel the effect caused by C1. Optimum compensation occurs when R1 × C1 = R2 × C2. This is not an option because of the variation of R2. As a result, the R1 × C1 = R2 × C2 relationship can be used, and scale C2 as if R2 is at its maximum value. Doing so may overcompensate and compromise the performance slightly when R2 is set at low values. However,

B

W

U1

V

i

V

O

02695-059

02695-058

it avoids the ringing or oscillation at the worst case. For critical applications, C2 should be found empirically to suit the need. In general, C2 in the range of a few picofarads (pF) to no more than a few tenths of pF is usually adequate for the compensation.

Similarly, there are W and A terminal capacitances connected to the output (not shown). Fortunately, their effect at this node is less significant, and the compensation can be avoided in most cases.

PROGRAMMABLE VOLTAGE REFERENCE

For voltage divider mode operation, shown in Figure 60, it is common to buffer the output of the digital potentiometer unless the load is much larger than R

. Not only does the buffer serve

WB

the purpose of impedance conversion, but it also allows a heavier load to be driven.

5V

1

U1

V

IN

GND

2

V

OUT

AD1582

AD5260

3

Figure 60. Programmable Voltage Reference

5V

A

W

B

AD8601

A1

V

O

02695-060

8-BIT BIPOLAR DAC

Figure 61 shows a low cost 8-bit bipolar DAC. It offers the same number of adjustable steps but not the precision of conventional DACs. The linearity and temperature coefficients, especially at low values codes, are skewed by the effects of the digital potentiometer wiper resistance. The output of this circuit is

D

2

V ×

O

V

i

U1

V

IN

V

OUT

TRIM

GND

ADR425

⎛

⎜

⎝

−= 1

256

AD5260

+5V

⎞

V

(4)

⎟

REF

⎠

U2

W

BA

R R

+5V

W1

REF

OP2177

A1

–5V

Figure 61. 8-Bit Bipolar DAC

–5V

OP2177

A2

REF

+5

–5V

V

O

02695-061

Rev. A | Page 19 of 24

AD5260/AD5262

V

×

BIPOLAR PROGRAMMABLE GAIN AMPLIFIER

For applications that require bipolar gain, Figure 62 shows one implementation. Digital Potentiometer U1 sets the adjustment range. The wiper voltage at W2 can therefore be programmed between V the noninverting mode allows linear gain and attenuation. The transfer function is

where

Similar to the previous example, in the simpler and more common case, where K = 1, with a single digital potentiometer, AD5260, U1 is replaced by a matched pair of resistors to apply

and −Vi at the ends of the digital potentiometer. The relation-

V

i

ship becomes

If R2 is large, a few picofarad compensation capacitors may be needed to avoid any gain peaking.

Tabl e 1 1 shows the result of adjusting D, with A2 configured as a unity gain, a gain of 2, and a gain of 10. The result is a bipolar amplifier with linearly programmable gain and 256-step resolution.

Table 11. Result of Bipolar Gain Amplifier

D R1 = ∞, R2 = 0 R1 = R2 R2 = 9 × R1

0 −1 −2 −10 64 −0.5 −1 −5 128 0 0 0 192 +0.5 +1 +5 255 +0.968 +1.937 +9.680

and −KVi at a given U2 setting. Configuring A2 in

i

V

O

V

i

R2

⎛

1

+= KK

⎜

R1

⎝

K is the ratio of R

U2

AD5262

A2 B2

V

i

V ×

A1 B1

U1

AD5262

Figure 62. Bipolar Programmable Gain Amplifier

R2

⎛

+= 1

1 (6)

⎜

O

R1

⎝

⎞ ⎟ ⎠

W2

W1

OP2177

A1

⎛

⎞

⎜

⎟

⎝

⎠

D

⎛ ⎜

256

⎝

WB1/RWA 1

V

DD

22

D

256

V

2

()

1

set by U1.

–KV

SS

⎞

V

−

⎟ ⎠

i

⎞

(5)

−+××

⎟ ⎠

DD

OP2177

A2

C1

V

SS

V

O

R2

R1

02695-062

PROGRAMMABLE VOLTAGE SOURCE WITH BOOSTED OUTPUT

For applications that require high current adjustment such as a laser diode driver or tunable laser, a boosted voltage source can be considered (see Figure 63).

V

i

5

A

W

U1

B

A1

Figure 63. Programmable Boosted Voltage Source

10kΩ

R1

P1

C

N1

SIGNAL

LO

U1 = AD5260 A1 = AD8601, AD8605, AD854 1 P1 = FDP360P , NDS 943 0 N1 = FDV301N, 2N7002

V

O

R

BIAS

C

I

L

In this circuit, the inverting input of the op amp forces VO to be equal to the wiper voltage set by the digital potentiometer. The load current is then delivered by the supply via the P-channel FET, P1. The N-channel FET, N

, simplifies the op amp driving

1

requirement. A1 must be the rail-to-rail input type. Resistor R1 is needed to prevent P1 from turning off once it is on. The choice of R1 is a balance between the power loss of this resistor and the output turn-off time. N1 can be any general-purpose signal FET. However, P1 is driven in the saturation state, and therefore, its power handling must be adequate to dissipate (V

power. This circuit can source a maximum of 100 mA at 5 V

× I

L

− VO)

i

supply. Higher current can be achieved with P1 in a larger package. Note that a single N-channel FET can replace P1, N1, and R1 altogether. However, the output swing is limited unless separate power supplies are used. For a precision application, a voltage reference such as the ADR423, ADR292, or AD1584 can be applied at the input of the digital potentiometer.

PROGRAMMABLE 4 mA-TO-20 mA CURRENT SOURCE

A programmable 4 mA-to-20 mA current source can be implemented with the circuit shown in Figure 64. REF191 is a unique low supply headroom and high current handling precision reference that can deliver 20 mA at 2.048 V. The load current is simply the voltage across Terminal B to Terminal W of the digital potentiometer, divided by R

DV

REF

I

=

L

(7)

R

S

.

S

02695-063

Rev. A | Page 20 of 24

AD5260/AD5262

C

−

3

4

+5V

U12

V

S

REF191

SLEEP

OUTPUT

GND

–2.048 TO V

0V TO ( 2.048V + V

6

C1

1µF

L

AD5260

)

L

B A

+5V

U2 OP1177

–5V

W

–

R

S

102Ω

+

R

L

100Ω

V

L

I

L

02695-064

Figure 64. Programmable 4-to-20 mA Current Source

The circuit is simple, but be aware that dual-supply op amps are ideal because the ground potential of REF191 can swing from

−2.048 V at zero scale to V

at full scale of the potentiometer

L

setting. Although the circuit works under single supply, the programmable resolution of the system is reduced.

PROGRAMMABLE BIDIRECTIONAL CURRENT SOURCE

For applications that require bidirectional current control or higher voltage compliance, a Howland current pump can be a solution (see Figure 65). If the resistors are matched, the load current is

()

=

+5V

+

W

I ×

A

AD5260

B

–5V

Figure 65. Programmable Bidirectional Current Source

22

BR

2

+15V

OP2177

A1

–15V

R1BRAR

(8)

V

WL

R1'

150kΩ

C2

10pF

R1

150kΩ

C1

10pF

AD8016

14.95kΩ

R2'

15kΩ

+15V

–15V

R2A

A2

R

L

50Ω

V

L

R

L

500Ω

I

L

PROGRAMMABLE LOW-PASS FILTER

Digital Potentiometer AD5262 can be used to construct a second-order, Sallen-Key low-pass filter (see Figure 66). The design equations are

V

ω

O

=

i

=

O

S

R1R2C1C2

2

ω

O

ω

2

O

S

Q

1

(9)

2

ω

++

O

(10)

11

Q

+=

(11)

R2C2R1C1

Users can first select any convenient value for the capacitors. To achieve maximally flat bandwidth where Q = 0.707, let C1 be twice the size of C2 and let R1 = R2. As a result, users can adjust R1 and R2 to the same settings to achieve the desirable bandwidth.

C1

+2.5V

R2R1

V

i

B

A

W

R

ADJUSTED TO

SAME SETTINGS

B

A

W

R

C2

AD8601

–2.5V

V

O

02695-066

Figure 66. Sallen Key Low-Pass Filter

PROGRAMMABLE OSCILLATOR

In a classic Wien-bridge oscillator (see Figure 67), the Wien network (R, R’, C, C’) provides positive feedback, whereas R1 and R2 provide negative feedback. At the resonant frequency, f the overall phase shift is zero, and the positive feedback causes the circuit to oscillate. With R = R’, C = C’, and R2 = R2A//(R2B +

), the oscillation frequency is

R

DIODE

1

or

=

ω

O

R

where R is equal to R

D

256

R

=

256

R

1

=

f

O

such that

WA

(13)

AB

(12)

R

π

2

At resonance, setting

R2

(14)

2=

R1

balances the bridge. In practice, R2/R1 should be set slightly larger than 2 to ensure the oscillation can start. However, the alternate turn-on of the diodes, D1 and D2, ensures R2/R1 to be smaller than 2 momentarily and therefore stabilizes the oscillation.

02695-065

When the frequency is set, the oscillation amplitude can be tuned by R2B because

2

O

3

, ID, and VD are interdependent variables. With proper

V

O

selection of R2B, an equilibrium is reached such that V

(15)

VBRIV += 2

DD

O

converges. R2B can be in series with a discrete resistor to increase the amplitude, but the total resistance cannot be too large to saturate the output.

In both circuits in Figure 66 and Figure 67, the frequency tuning requires that both RDACs be adjusted to the same settings. Because the two channels are adjusted one at a time, an intermedi-

,

o

Rev. A | Page 21 of 24

AD5260/AD5262

Y

V

le

d

In voltage divider mode, a much lower resistance can be achieved by paralleling a discrete resistor as shown in Figure 69. The equivalent resistance becomes

R += )//(

R +

D

_

256

D

−= )//(

1

256

⎞ ⎟ ⎠

R2

⎛ ⎜

eqWA

_

⎝

Figure 69. Lowering the Nominal Resistance

(16)

RR2R1

WeqWB

RR2R1

(17)

W

A

W

R1

B

R2 << R1

02695-069

Figure 68 and Figure 69 show that the digital potentiometers change steps linearly. However, log taper adjustment is usually preferred in applications like audio control. Figure 70 shows another method of resistance scaling. In this circuit, the smaller R2 is with respect to R

, the more the pseudo-log taper

AB

characteristic behaves.

i

A

W

R1

B

R2

Figure 70. Resistor Scaling with Log Adjustment Characteristics

V

O

02695-070

ate state occurs that may not be acceptable for certain applications. As a result, different devices can also be used in daisy-chaine mode so that par

ts can be programmed to the same setting

simultaneously.

FREQUENC

ADJUSTMENT

C

2.2nF

10kΩ

B

R

W

A

VP

C'

2.2nF

+5V

OP1177

R'

10kΩ

AB

W

U1

V

O

AD5262

R1 = R1' = R2B = AD5 262 D1 = D2 = 1N4148

Figure 67. Programmable Os

–5V

VN

1kΩ

R1

R2B

10kΩ

W

R2A

2.1kΩ

AB

AMPLITUDE ADJUSTMENT

D1

D2

cillator with Amplitude Control

067

02695-

RESISTANCE SCALING

The AD5260/AD5262 offer 20 kΩ, 50 kΩ, and 200 kΩ nominal resistance. For users who need lower resistance and still maintain the numbers of step adjustment, they can place multip devices in parallel. For example, Figure 68 shows a simple scheme of paralleling both channels of the AD5262. To adjust half of the resistance linearly per step, users need t both channels coherently with the same settings.

DD

W1

A2

W2

B2

A1

B1

o program

LD

068

02695-

68. Reduce Resistance by Half with Linear Adjustment Characteristics Figure

Rev. A | Page 22 of 24

AD5260/AD5262

OUTLINE DIMENSIONS

COPLANARITY

PIN 1

1.05

1.00

0.80

5.10

5.00

4.90

4.50

4.40

4.30

0.15

0.05

0.10

14

1

0.65 BSC

0.30

0.19

COMPLIANT TO JEDEC STANDARDS MO-153-AB-1

8

6.40 BSC

7

1.20

0.20

MAX

0.09

SEATING PLANE

8° 0°

Figure 71. 14-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-14)

Dimensions shown in millimeters

5.10

5.00

4.90

0.15

0.05

4.50

4.40

4.30

PIN 1

16

0.65

BSC

COPLANARITY

COMPLIANT TO JEDEC ST A NDAR DS MO-153-AB

0.10

0.30

0.19

9

BSC

81

1.20 MAX

SEATING PLANE

6.40

0.20

0.09

Figure 72. 16-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-16)

Dimensions shown in millimeters

0.75

0.60

0.45

061908-A

8° 0°

0.75

0.60

0.45

Rev. A | Page 23 of 24

AD5260/AD5262

ORDERING GUIDE

Model1 RAB (kΩ) Temperature Package Description Package Option No. of Parts per Container

AD5260BRUZ20 20 −40°C to +85°C 14-Lead TSSOP RU-14 96 AD5260BRUZ20-RL7 20 −40°C to +85°C 14-Lead TSSOP RU-14 1000 AD5260BRUZ50 50 −40°C to +85°C 14-Lead TSSOP RU-14 96 AD5260BRUZ50-REEL7 50 −40°C to +85°C 14-Lead TSSOP RU-14 1000 AD5260BRUZ200 200 −40°C to +85°C 14-Lead TSSOP RU-14 96 AD5260BRUZ200-RL7 200 −40°C to +85°C 14-Lead TSSOP RU-14 1000 AD5262BRU20 20 −40°C to +85°C 16-Lead TSSOP RU-16 96 AD5262BRU20-REEL7 20 −40°C to +85°C 16-Lead TSSOP RU-16 1000 AD5262BRU50 50 −40°C to +85°C 16-Lead TSSOP RU-16 96 AD5262BRU50-REEL7 50 −40°C to +85°C 16-Lead TSSOP RU-16 1000 AD5262BRU200 200 −40°C to +85°C 16-Lead TSSOP RU-16 96 AD5262BRU200-REEL7 200 −40°C to +85°C 16-Lead TSSOP RU-16 1000 AD5262BRUZ20 20 −40°C to +85°C 16-Lead TSSOP RU-16 96 AD5262BRUZ20-RL7 20 −40°C to +85°C 16-Lead TSSOP RU-16 1000 AD5262BRUZ50 50 −40°C to +85°C 16-Lead TSSOP RU-16 96 AD5262BRUZ50-RL7 50 −40°C to +85°C 16-Lead TSSOP RU-16 1000 AD5262BRUZ200 200 −40°C to +85°C 16-Lead TSSOP RU-16 96 AD5262BRUZ200-RL7 200 −40°C to +85°C 16-Lead TSSOP RU-16 1000 EVAL-AD5262EBZ Evaluation Board

1

Z = RoHS Compliant Part.

Rev. A | Page 24 of 24

Datasheet AD5260 Datasheet (ANALOG DEVICES)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAMS

TABLE OF CONTENTS

REVISION HISTORY

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—20 kΩ, 50 kΩ, 200 kΩ VERSIONS

TIMING DIAGRAMS

ABSOLUTE MAXIMUM RATINGS

ESD CAUTION

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

TYPICAL PERFORMANCE CHARACTERISTICS

TEST CIRCUITS

THEORY OF OPERATION

DIGITAL INTERFACING

DAISY-CHAIN OPERATION

RDAC STRUCTURE

PROGRAMMING THE VARIABLE RESISTOR

Rheostat Operation

PROGRAMMING THE POTENTIOMETER DIVIDER

Voltage Output Operation

LAYOUT AND POWER SUPPLY BYPASSING

TERMINAL VOLTAGE OPERATING RANGE

POWER-UP SEQUENCE

RDAC CIRCUIT SIMULATION MODEL

MACRO MODEL NET LIST FOR RDAC

APPLICATIONS INFORMATION

BIPOLAR DC OR AC OPERATION FROM DUAL SUPPLIES

GAIN CONTROL COMPENSATION

PROGRAMMABLE VOLTAGE REFERENCE

8-BIT BIPOLAR DAC

BIPOLAR PROGRAMMABLE GAIN AMPLIFIER

PROGRAMMABLE VOLTAGE SOURCE WITH BOOSTED OUTPUT

PROGRAMMABLE 4 mA-TO-20 mA CURRENT SOURCE

PROGRAMMABLE BIDIRECTIONAL CURRENT SOURCE

PROGRAMMABLE LOW-PASS FILTER

PROGRAMMABLE OSCILLATOR

RESISTANCE SCALING

OUTLINE DIMENSIONS

ORDERING GUIDE