Datasheet AD5259 Datasheet (Analog Devices)

V

V

V

A

Nonvolatile, I2C-Compatible

FEATURES

Nonvolatile memory maintains wiper settings
256-position
Compact MSOP-10 (3 mm × 4.9 mm) package

2

C®-compatible interface

I

pin provides increased interface flexibility

V

LOGIC

End-to-end resistance 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ
Resistance tolerance stored in EEPROM (0.1% accuracy)
Power-on EEPROM refresh time < 1ms
Software write protect command
Three-state Address Decode Pins AD0 and AD1 allow

9 packages per bus
100-year typical data retention at 55°C
Wide operating temperature −40°C

3 V to 5 V single supply

APPLICATIONS

LCD panel V
LCD panel brightness and contrast control
Mechanical potentiometer replacement in new designs
Programmable power supplies
RF amplifier biasing
Automotive electronics adjustment
Gain control and offset adjustment
Fiber to the home systems
Electronics level settings

adjustment

COM

to +85°C

256-Position, Digital Potentiometer

AD5259

FUNCTIONAL BLOCK DIAGRAMS

RDAC

A
W
B

05026-001

A

W

B

05026-003

SCL

SDA

AD0
AD1

GND

V

LOGIC

GND

SCL
SDA

AD0
AD1

DD

RDAC

EEPROM

DATA

8

I2C

SERIAL

INTERFACE

POWER-

ON RESET

8

CONTROL

COMMAND

DECODE LOGIC

ADDRESS

DECODE LOGIC

CONTROL LOGIC

Figure 1. Block Diagram

LOGIC

EEPROM

RDAC

I2C

SERIAL

INTERFACE

COMMAND

DECODE LOGIC

ADDRESS

DECODE LOGIC

CONTROL

LOGIC

REGISTER

AND

LEVEL

SHIFTER

Figure 2. Block Diagram Showing Level Shifters

RDAC

REGISTER

AD5259

DD

GENERAL DESCRIPTION

The AD5259 provides a compact, nonvolatile 3 mm × 4.9 mm
packaged solution for 256-position adjustment applications.
These devices perform the same electronic adjustment function

1

as mechanical potentiometers

or variable resistors, but with

enhanced resolution and solid-state reliability.

2

The wiper settings are controllable through an I

C-compatible
digital interface that is also used to read back the wiper register
and EEPROM content. Resistor tolerance is also stored within
EEPROM providing an end-to-end tolerance accuracy of 0.1%.
There is also a software write protection function that ensures
data cannot be written to the EEPROM register.

A separate V

pin delivers increased interface flexibility. For

LOGIC

users who need multiple parts on one bus, Address Bit AD0 and
Address Bit AD1 allow up to nine devices on the same bus.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

CONNECTION DIAGRAM

AD0
AD1

SD

SCL

W

1
2
3
4
5

AD5259

TOP VIEW

(Not to Scale)

Figure 3. Pinout

10

A

9

B

8

V

DD

GND

7
6

V

LOGIC

05026-002

1

The terms digital potentiometer, VR (variable resistor), and RDAC are used

interchangeably.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
Fax: [phone] © 2005 Analog Devices, Inc. All rights reserved.

www.analog.com

AD5259

TABLE OF CONTENTS

Specifications..................................................................................... 3

Writ e M o des ................................................................................ 17

Electrical Characteristics............................................................. 3

Timing Characteristics ................................................................ 5

Absolute Maximum Ratings............................................................ 6

ESD Caution.................................................................................. 6

Pin Configuration and Function Descriptions............................. 7

Typical Performance Characteristics............................................. 8

Test C ir c uit s ..................................................................................... 13

Theory of Operation ...................................................................... 14

Programming the Variable Resistor......................................... 14

Programming the Potentiometer Divider............................... 14

2

I

C Interface..................................................................................... 15

2

I

C Byte Formats............................................................................. 16

Generic Interface........................................................................ 16

REVISION HISTORY

Read Modes................................................................................. 17

Store/Restore Modes .................................................................. 17

Tole ran c e Re adb ack M o de s ...................................................... 18

ESD Protection of Digital Pins and Resistor Terminals........ 19

Power-Up Sequence ................................................................... 19

Layout and Power Supply Bypassing ....................................... 19

Multiple Devices on One Bus ................................................... 19

Evaluation Board ........................................................................ 19

Display Applications ...................................................................... 20

Circuitry ...................................................................................... 20

Outline Dimensions ....................................................................... 21

Ordering Guide .......................................................................... 21

2/05 — Revision 0: Initial Version

Rev. 0 | Page 2 of 24

AD5259

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS

VDD = V

Table 1.

Parameter Symbol Conditions Min Typ

DC CHARACTERISTICS: RHEOSTAT MODE

Resistor Differential Nonlinearity R-DNL RWB, V

Resistor Integral Nonlinearity R-INL RWB, V

Nominal Resistor Tolerance ∆R
Resistance Temperature Coefficient (∆RAB x 106)/(RAB x ∆T) Code = 0x00/0x80 500/15 ppm/°C
Total Wiper Resistance R

DC CHARACTERISTICS:
POTENTIOMETER DIVIDER MODE

Differential Nonlinearity DNL LSB

Integral Nonlinearity INL LSB

Full-Scale Error V

Zero-Scale Error V

Voltage Divider Temperature

Coefficient

RESISTOR TERMINALS

Voltage Range V
Capacitance A, B C

Capacitance W C

Common-Mode Leakage I

DIGITAL INPUTS AND OUTPUTS

Input Logic High V
Input Logic Low V
Leakage Current I

Input Capacitance C

= 5 V ± 10%, or 3 V ± 10%; VA = VDD; VB = 0 V; −40°C < TA < +85°C; unless otherwise noted.

LOGIC

1

Max Unit

= no connect

A

LSB
5 kΩ –1 ±0.2 +1
10 kΩ −1 ±0.1 +1
50 kΩ/100 kΩ −0.5 ±0.1 +0.5

= no connect

A

LSB
5 kΩ –4 ±0.3 +4
10 kΩ −2 ±0.2 +2
50 kΩ/100 kΩ −1 ±0.4 +1

AB

WB

TA = 25°C, VDD = 5.5 V –30 +30 %

Code = 0x00 75 350 Ω

5 kΩ –1 ±0.2 +1
10 kΩ −0.5 ±0.1 +0.5
50 kΩ/100 kΩ −0.5 ±0.2 +0.5

5 kΩ –1 ±0.2 +1
10 kΩ −0.5 ±0.1 +0.5
50 kΩ/100 kΩ −0.5 ±0.1 +0.5

WFSE

Code = 0xFF LSB
5 kΩ −7 −3 0
10 kΩ −4 −1.5 0
50 kΩ/100 kΩ −1 −0.4 0

WZSE

Code = 0x00 LSB
5 kΩ 0 4 2.5
10 kΩ 0 3 1
50 kΩ/100 kΩ 0 0.5 0.2

x 106)/(VW x T) Code = 0x00/0x80 60/5 ppm/°C

(V

W

A, B, W

A, B

GND V

f = 1 MHz, measured to GND,

45 pF

DD

Code = 0x80

W

f = 1 MHz, measured to GND,

60 pF

Code = 0x80

CM

IH

IL

IL

VA = VB = VDD/2 10 nA

0.7 × VL V

+ 0.5 V

L

−0.5 0.3 × VLV

µA

SDA, AD0, AD1 VIN = 0 V or 5 V 0.01 ±1
SCL – Logic High VIN = 0 V −2.5 −1.3 +1
SCL – Logic Low VIN = 5 V 0.01 ±1

IL

5 pF

V

Rev. 0 | Page 3 of 24

AD5259

Parameter Symbol Conditions Min Typ

1

Max Unit

POWER SUPPLIES

Power Supply Range V
Positive Supply Current I
Logic Supply V
Logic Supply Current I
Programming Mode Current (EEPROM) I
Power Dissipation P

DD

DD

LOGIC

LOGIC

LOGIC(PROG)

DISS

2.7 5.5 V

0.1 2 µA

2.7 5.5 V
VIH = 5 V or VIL = 0 V 3 6 µA
VIH = 5 V or VIL = 0 V 35 mA
VIH = 5 V or VIL = 0 V, VDD = 5 V 15 40 µW

Power Supply Rejection Ratio PSRR VDD = +5 V ± 10%, Code = 0x80 ±0.005 ±0.06 %/%

DYNAMIC CHARACTERISTICS

Bandwidth −3 dB BW Code = 0x80
R
R
R
R
Total Harmonic Distortion THD

W

= 5 kΩ 2000 kHz

AB

= 10 kΩ 800 kHz

AB

= 50 kΩ 160 kHz

AB

= 100 kΩ 80 kHz

AB

RAB = 10 kΩ, VA = 1 V rms, VB = 0,

0.1 %

f = 1 kHz

VW Settling Time t

S

RAB = 10 kΩ, VAB = 5 V,

500 ns

±1 LSB error band

Resistor Noise Voltage Density e

1

Typical values represent average readings at 25°C and V = 5 V.

N_WB

DD

RWB = 5 kΩ, f = 1 kHz 9 nV/√Hz

Rev. 0 | Page 4 of 24

AD5259

TIMING CHARACTERISTICS

VDD = V

Table 2.

Parameter Symbol Conditions Min Typ Max Unit

I2C INTERFACE TIMING CHARACTERISTICS

SCL Clock Frequency f
t

BUF

t

HD;STA

t

LOW

t

HIGH

t

SU;STA

Condition

t

HD;DAT

t

SU;DAT

tF Fall Time of Both SDA and SCL Signals t
tR Rise Time of Both SDA and SCL Signals t
t

SU;STO

EEPROM Data Storing Time t
EEPROM Data Restoring Time at Power On

EEPROM Data Restoring Time upon Restore

Command

EEPROM Data Rewritable Time

FLASH/EE MEMORY RELIABILITY

Endurance
Data Retention

1

During power-up, the output is momentarily preset to midscale before restoring EEPROM content.

2

Delay time after power-on PRESET prior to writing new EEPROM data.

3

Endurance is qualified to 100,000 cycles per JEDEC Std. 22 method A117, and is measured at –40°C, +25°C, and +85°C; typical endurance at +25°C is 700,000 cycles.

4

Retention lifetime equivalent at junction temperature (TJ) = 55°C per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6eV derates

with junction temperature.

= 5 V ± 10%, or 3 V ± 10%; VA = VDD; VB = 0 V; −40°C < TA < +85°C; unless otherwise noted.

LOGIC

0 400 kHz

1.3 µs
After this period, the first clock pulse is

Bus Free Time between STOP and START t

Hold Time (Repeated START) t

SCL

1

2

generated.

Low Period of SCL Clock t

High Period of SCL Clock t

Setup Time for Repeated START

Data Hold Time t

Data Setup Time t

Setup Time for STOP Condition t

1

1

2

3

4

3

4

t

5

6

7

8

9

10

EEMEM_STORE

t

EEMEM_RESTORE1

t

EEMEM_RESTORE2VDD

t

EEMEM_REWRITE

100 700 kCycles
100 Years

1.3 µs

0.6 µs

0.6 µs

0 0.9 µs
100 ns
300 ns
300 ns

0.6 µs
26 ms
VDD rise time dependent. Measure without

decoupling capacitors at V

DD

= 5 V. 300 µs

540 µs

0.6 µs

300 µs

and GND.

t

SCL

SDA

t

8

t

t

3

2

t

9

t

8

t

1

PS P

Figure 4. I

t

9

t

t

4

2

C Interface Timing Diagram

5

6

t

7

t

10

05026-004

Rev. 0 | Page 5 of 24

AD5259

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameter Value

VDD to GND
VA, VB, VW to GND
I

MAX

Pulsed

1

−0.3 V to +7 V
GND − 0.3 V, V

±20 mA

+ 0.3 V

DD

Continuous ±5 mA
Digital Inputs and Output Voltage to GND 0 V to 7 V
Operating Temperature Range

Maximum Junction Temperature (T
Storage Temperature

−40°C to +85°C

) 150°C

JMAX

−65°C to +150°C
Lead Temperature (Soldering, 10 sec) 300°C
Thermal Resistance2

: MSOP–10

θ

JA

1

Maximum terminal current is bounded by the maximum current handling of

the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.

2

Package power dissipation = (T

– TA)/θJA.

JMAX

200°C/W

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. 0 | Page 6 of 24

AD5259

A

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

10

A
B

9

V

8

DD

GND

7

V

6

LOGIC

05026-008

AD0
AD1
SD
SCL

1

W

2
3
4
5

AD5259

TOP VIEW

(Not to Scale)

Figure 5. Pin Configuration

Table 4. AD5259 Pin Function Descriptions

Pin Mnemonic Description

1 W W Terminal, GND ≤ VW ≤ VDD.
2 ADO

Programmable Three-State Address Bit 0 for Multiple Package Decoding. State is registered on
power-up.

3 AD1

Programmable Three-State Address Bit 1 for Multiple Package Decoding. State is registered on

power-up.
4 SDA Serial Data Input/Output.
5 SCL Serial Clock Input. Positive edge triggered.
6 V

LOGIC

Logic Power Supply.
7 GND Digital Ground.
8 V

DD

Positive Power Supply.
9 B B Terminal, GND ≤ VB ≤ VDD.
10 A A Terminal, GND ≤ VA ≤ VDD.

Rev. 0 | Page 7 of 24

AD5259

TYPICAL PERFORMANCE CHARACTERISTICS

VDD = V

RHEOSTAT MODE INL (LSB)

= 5.5 V, RAB = 10 kΩ, TA = +25°C; unless otherwise noted.

LOGIC

1.5

1.3

1.1

0.9

0.7

0.5

0.3

0.1

–0.1

–0.3

–0.5

0 256224192160128966432

2.7V

5.5V

CODE (Decimal)

Figure 6. R-INL vs. Code vs. Supply Voltage

05026-015

POTENTIOMETER MODE DNL (LSB)

0.25

0.20

0.15

0.10

0.05

–0.05

–0.10

–0.15

–0.20

–0.25

0

0 256224192160128966432

CODE (Decimal)

Figure 9. DNL vs. Code vs. Temperature

+25°C

+85°C

–40°C

05026-012

RHEOSTAT MODE DNL (LSB)

POTENTIOMETER MODE INL (LSB)

0.5

0.4

0.3

0.5

0.1

–0.1

–0.2

–0.3

–0.4

–0.5

0

0 256224192160128966432

2.7V

5.5V

CODE (Decimal)

Figure 7. R-DNL vs. Code vs. Supply Voltages

0.25

0.20

0.15

0.10

0.05

–0.05

–0.10

–0.15

–0.20

–0.25

0

0 256224192160128966432

T

A

CODE (Decimal)

Figure 8. INL vs. Code vs. Temperature

= +85°C

T

= +25°C

A

TA = –40°C

05026-017

05026-010

POTENTIOMETER MODE INL (LSB)

POTENTIOMETER MODE DNL (LSB)

0.25

0.20

0.15

0.10

0.05

–0.05

–0.10

–0.15

–0.20

–0.25

0

0 256224192160128966432

2.7V

CODE (Decimal)

Figure 10. INL vs. Supply Voltages

0.25

0.20

0.15

0.10

0.05

–0.05

–0.10

–0.15

–0.20

–0.25

2.7V

0

0 256224192160128966432

5.5V

CODE (Decimal)

Figure 11. DNL vs. Code vs. Supply Voltages

5.5V

05026-011

05026-013

Rev. 0 | Page 8 of 24

AD5259

0.5

0.4

0.3

0.2

0.1

0

–0.1

–0.2

RHEOSTAT MODE INL (LSB)

–0.3

–0.4

–0.5

0 256224192160128966432

–40°C

CODE (Decimal)

+85°C

+25°C

05026-014

Figure 12. R-INL vs. Code vs. Temperature

2.0

1.8

1.6
ZSE @ VDD = 2.7V

1.4

1.2

1.0

ZSE (LSB)

0.8

0.6

0.4

0.2

0

–40 –20 806040200

Figure 15. Zero-Scale Error vs. Temperature

ZSE @ V

TEMPERATURE (°C)

DD

= 5.5V

05026-023

0.5

0.1

0.3

0.2

0.1

0

–0.1

–0.2

RHEOSTAT MODE DNL (LSB)

–0.3

–0.4

–0.5

0 256224192160128966432

Figure 13. R-DNL vs. Code vs. Temperature

0

–0.5

–1.0

FSE @ V

–1.5

FSE (LSB)

–2.0

–2.5

–3.0

–40 –20 806040200

Figure 14. Full-Scale Error vs. Temperature

CODE (Decimal)

= 5.5V

DD

TEMPERATURE (°C)

TA = –40°C

TA = +85°C

TA = +25°C

FSE @ VDD = 2.7V

05026-016

05026-024

1

VDD = 5.5V

, SUPPLY CURRENT (µA)

DD

I

0.1

–40 –20 806040200

TEMPERATURE (°C)

Figure 16. Supply Current vs. Temperature

6

5

4

3

2

1

, LOGIC SUPPLY CURRENT (µA)

0

LOGIC

I

–1

–40 –20 806040200

VDD = 2.7V

TEMPERATURE (°C)

VDD = 5.5V

Figure 17. Logic Supply Current vs. Temperature vs. V

05026-020

05026-021

DD

Rev. 0 | Page 9 of 24

AD5259

400

100kΩ

300

200

100

0

50kΩ

10kΩ

5kΩ

0 256224192160128966432

C)

°

–100

–200

–300

–400

RHEOSTAT MODE TEMPCO (ppm/

–500

–600

Figure 18. Rheostat Mode Tempco (ΔR

CODE (Decimal)

x 106)/(RAB x ΔT) vs. Code

AB

05026-019

120

100

)

Ω

80

60

40

TOTAL RESISTANCE (k

20

0

–40 –20 806040200

Figure 21. Total Resistance vs. Temperature

100kΩ Rt @ VDD = 5.5V

50kΩ Rt @ V

5kΩ Rt @ V

TEMPERATURE (°C)

DD

10kΩ Rt @ V

= 5.5V

DD

= 5.5V

DD

= 5.5V

05026-025

70
60

C)

°

50
40
30
20
10

0
–10
–20
–30

POTENTIOMETER MODE TEMPCO (ppm/

–40

0 256224192160128966432

10kΩ

50kΩ

100kΩ

5kΩ

CODE (Decimal)

Figure 19. Potentiometer Mode Tempco (ΔVW x 106)/(VW x ΔT) vs. Code

350

300

250

@ VDD = 2.7V

R

200

@ 0x00

150

WB

R

100

RWB @ VDD = 5.5V

50

0

–40 –20 806040200

Figure 20. R

TEMPERATURE (°C)

WB

WB

vs. Temperature

05026-018

05026-022

0

–6

–12

–18

–24

–30

GAIN (dB)

–36

–42

–48

–54

–60

1k 10M1M100k10k

80

H

40

H

20

H

10

H

08

H

04

H

02

H

01

H

FREQUENCY (Hz)

Figure 22. Gain vs Frequency vs. Code, R

0

–6

–12

–18

–24

–30

GAIN (dB)

–36

–42

–48

–54

–60

1k 10M1M100k10k

80

H

40

H

20

H

10

H

08

H

04

H

02

H

01

H

FREQUENCY (Hz)

Figure 23. Gain vs. Frequency vs. Code, R

= 5 kΩ

AB

= 10 kΩ

AB

05026-026

05026-027

Rev. 0 | Page 10 of 24

AD5259

0

–6

–12

–18

–24

–30

GAIN (dB)

–36

–42

–48

–54

–60

1k 1M100k10k

80

H

40

H

20

H

10

H

08

H

04

H

02

H

01

H

FREQUENCY (Hz)

Figure 24. Gain vs. Frequency vs. Code, R

= 50 kΩ

AB

05026-028

10k

1k

A)

µ

(

LOGIC

I

100

10

012345

Figure 27. I

V

DD

DD

VDD = V

= V

= 3V

LOGIC

VIH (V)

vs. Input Voltage

LOGIC

= 5V

05026-055

0

–6

–12

–18

–24

–30

GAIN (dB)

–36

–42

–48

–54

–60

1k 1M100k10k

80

H

40

H

20

H

10

H

08

H

04

H

02

H

01

H

FREQUENCY (Hz)

Figure 25. Gain vs. Frequency vs. Code, R

0

–6

–12

–18

–24

–30

GAIN (dB)

–36

–42

–48

–54

–60

1k 10M1M100k10k

100k

Ω

80kHz

FREQUENCY (Hz)

Figure 26. −3 dB Bandwidth @ Code = 0×80

50k

Ω

160kHz

Ω

10k
800kHz

= 100 kΩ

AB

5k

Ω

2MHz

05026-029

05026-050

80

CODE = MIDSCALE, VA = V

60

40

PSRR @ V

PSRR (dB)

20

0

100 1k 1M100k10k

PSRR @ V

= 3V DC± 10% p-p AC

LOGIC

Figure 28. PSRR v s. Frequency

V

200mV/DIV

1

2

5V/DIV

W

SCL

Figure 29. Digital Feedthrough

, VB = 0V

LOGIC

= 5V DC± 10% p-p AC

LOGIC

FREQUENCY (Hz)

400ns/DIV

05026-054

05026-051

Rev. 0 | Page 11 of 24

AD5259

2V/DIV

V

1

50mV/DIV

W

1µs/DIV

Figure 30. Midscale Glitch, Code 0×7F to 0×80

1

5V/DIV

2

05026-052

V

W

SCL

200ns/DIV

Figure 31. Large Signal Settling Time

05026-053

Rev. 0 | Page 12 of 24

AD5259

V

TEST CIRCUITS

Figure 32 through Figure 37 illustrate the test circuits that
define the test conditions used in the product specification
tables.

V+ = V

DUT

A

V+

W

B

DD

1LSB = V+/2

V

MS

N

05026-030

Figure 32. Test Circuit for Potentiometer Divider Nonlinearity Error (INL, DNL)

V+

Figure 35. Test Circuit for Power Supply Sensitivity (PSS, PSSR)

A

DUT

A

∆V

DD

W

B

V+ = V

±

10%

DD

PSRR (dB) = 20 LOG
PSS (%/%) =

V

MS

∆VMS%
∆VDD%

∆V

MS

( )

∆V

DD

05026-033

NO CONNECT

DUT

A

W

B

V

MS

Figure 33. Test Circuit for Resistor Position Nonlinearity Error

(Rheostat Operation; R-INL, R-DNL)

DUT

A

V

MS2

W

B

V

W

IW = VDD/R

V

MS1

RW = [V

Figure 34. Test Circuit for Wiper Resistance

I

W

NOMINAL

MS1

05026-031

– V

MS2

OFFSET

GND

DUT

A

V

IN

+2.5V

W

B

+5V

AD8610

–5V

V

OUT

05026-034

Figure 36. Test Circuit for Gain vs. Frequency

0.1V

R

=

SW

I

DUT

W

]/I

W

05026-032

I

SW

B

GND TO V

SW

CODE = 0x00

DD

0.1V

05026-035

Figure 37. Test Circuit for Common-Mode Leakage Current

Rev. 0 | Page 13 of 24

AD5259

−

−

THEORY OF OPERATION

The AD5259 is a 256-position digitally controlled variable
resistor (VR) device.

PROGRAMMING THE VARIABLE RESISTOR

Rheostat Operation

The nominal resistance (RAB) of the RDAC between Terminal A
and Terminal B is available in 5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ.
The nominal resistance of the VR has 256 contact points
accessed by the wiper terminal. The 8-bit data in the RDAC
latch is decoded to select one of 256 possible settings.

A

W

A

W

A

W

Similar to the mechanical potentiometer, the resistance of the
RDAC between Wiper W and Terminal A produces a digitally
controlled complementary resistance, R
setting for R

starts at a maximum value of resistance and

WA

. The resistance value

WA

decreases as the data loaded in the latch increases in value. The
general equation for this operation is

D

256

DR ×+×

= 2

)(

256

ABWA

(2)

RR

W

Typical device-to-device matching is process lot dependent and
may vary by up to ±30%. For this reason, resistance tolerance is
stored in the EEPROM such that the user will know the actual

within 0.1%.

R

AB

B

Figure 38. Rheostat Mode Configuration

B

B

05026-036

The general equation determining the digitally programmed
output resistance between Wiper W and Terminal B is

WB

256

D

DR ×+×= 2

)(

AB

(1)

RR

W

where:
D is the decimal equivalent of the binary code loaded in the
8-bit RDAC register.

is the end-to-end resistance.

R

AB

R

is the wiper resistance contributed by the ON resistance of

W

each internal switch.

A

R

S

D7
D6
D5
D4
D3
D2
D1
D0

R

S

R

S

W

PROGRAMMING THE POTENTIOMETER DIVIDER

Voltage Output Operation

The digital potentiometer easily generates a voltage divider at
Wiper W-to-Terminal B and Wiper W-to-Terminal A propor­tional to the input voltage at Terminal A to Terminal B. Unlike
the polarity of V
ac r o ss Te rm i nal A to Te rm i na l B, Wip er W to Te r mi n al A , a n d
Wiper W to Terminal B can be at either polarity.

If ignoring the effect of the wiper resistance for approximation,
connecting the A terminal to 5 V and the B terminal to ground
produces an output voltage at Wiper W-to-Terminal B starting
at 0 V up to 1 LSB less than 5 V. The general equation defining
the output voltage at V
input voltage applied to Terminal A and Terminal B is

DV

W

to GND, which must be positive, voltage

DD

V

I

A

W

V

O

B

05026-038

Figure 40. Potentiometer Mode Configuration

with respect to ground for any valid

W

D

V

)(

256

+=

A

256

256

D

(3)

V

B

A more accurate calculation, which includes the effect of wiper

RDAC

LATCH

AND

DECODER

Figure 39. AD5259 Equivalent RDAC Circuit

Note that in the zero-scale condition, there is a relatively low
value finite wiper resistance. Care should be taken to limit the
current flow between Wiper W and Terminal B in this state to a
maximum pulse current of no more than 20 mA. Otherwise,
degradation or destruction of the internal switch contact can

R

S

B

05026-037

resistance, V

, is

W

DR

DR

)(

WB

DV

)(

W

V

+=

A

R

AB

WA

)(

(4)

V

B

R

AB

Operation of the digital potentiometer in the divider mode
results in a more accurate operation over temperature. Unlike
the rheostat mode, the output voltage is dependent mainly on
the ratio of the Internal Resistors R

and RWB and not the

WA

absolute values.

occur.

Rev. 0 | Page 14 of 24

AD5259

I2C INTERFACE

1. The master initiates data transfer by establishing a START

condition, which is when a high-to-low transition on the
SDA line occurs while SCL is high (see Figure 4). The next
byte is the slave address byte, which consists of the slave
address (first 7 bits) followed by an R/

When the R/
device. When the R/
slave device.

bit is high, the master reads from the slave

W

bit is low, the master writes to the

W

bit (see Table 6).

W

(store), or from EEPROM to RDAC (restore). The final five
bits are all zeros (see Table 13 to Table 14).

4. Reading: Assuming the register of interest was not just

written to, it is necessary to write a dummy address and
instruction byte. The instruction byte will vary depending
on whether the data that is wanted is the RDAC register,
EEPROM register, or tolerance register (see Table 11 to
Table 16).

The slave address of the part is determined by two three­state configurable Address Pins AD0 and AD1. The state of
these two pins is registered upon power-up and decoded
into a corresponding I
slave address corresponding to the transmitted address bits
responds by pulling the SDA line low during the ninth
clock pulse (this is termed the slave acknowledge bit).

At this stage, all other devices on the bus remain idle while
the selected device waits for data to be written to, or read
from, its serial register.

2. Wr it i n g: In the write mode, the last bit (R/

address byte is logic low. The second byte is the instruction
byte. The first three bits of the instruction byte are the
command bits (see Table 6). The user must choose whether
to write to the RDAC register, EEPROM register, or
activate the software write protect (see Table 7 to Table 10).
The final five bits are all zeros (see Table 13 to Table 14).
The slave again responds by pulling the SDA line low during
the ninth clock pulse.

The final byte is the data byte MSB first. In the case of the
write protect mode, data is not stored; rather, a logic high
in the LSB enables write protect. Likewise, a logic low will
disable write protect. The slave again responds by pulling
the SDA line low during the ninth clock pulse.

3. Storing/Restoring: In this mode, only the address and

instruction bytes are necessary. The last bit (R/
address byte is logic low. The first three bits of the

instruction byte are the command bits (see Table 6). The
two choices are transfer data from RDAC to EEPROM

2

C 7-bit address (see Table 5). The

) of the slave

W

) of the

W

After the dummy address and instruction bytes are sent, a
repeat start is necessary. After the repeat start, another
address byte is needed, except this time the R/

high. Following this address byte is the readback byte
containing the information requested in the instruction
byte. Read bits appear on the negative edges of the clock.

The tolerance register can be read back individually (see
Table 15) or consecutively (see Table 16). Refer to the Read
Modes section for detailed information on the
interpretation of the tolerance bytes.

5. After all data bits have been read or written, a STOP

condition is established by the master. A STOP condition is
defined as a low-to-high transition on the SDA line while
SCL is high. In write mode, the master pulls the SDA line
high during the tenth clock pulse to establish a STOP
condition (see Figure 46). In read mode, the master issues a
no acknowledge for the ninth clock pulse (that is, the SDA
line remains high). The master then brings the SDA line
low before the tenth clock pulse, and then raises SDA high
to establish a STOP condition (see Figure 47).

A repeated write function gives the user flexibility to
update the RDAC output a number of times after
addressing and instructing the part only once. For
example, after the RDAC has acknowledged its slave
address and instruction bytes in the write mode, the RDAC
output is updated on each successive byte until a STOP
condition is received. If different instructions are needed,
the write/read mode has to start again with a new slave
address, instruction, and data byte. Similarly, a repeated
read function of the RDAC is also allowed.

bit is logic

W

Rev. 0 | Page 15 of 24

AD5259

I2C BYTE FORMATS

The following generic, write, read, and store/restore control
registers for the AD5259 all refer to the device addresses listed
in Table 5, and the mode/condition reference key (S, P, SA, MA,

W

NA,

, R, and X) listed below.

S = Start Condition

P = Stop Condition

SA = Slave Acknowledge

MA = Master Acknowledge

NA = No Acknowledge

W

= Write

Table 5. Device Address Lookup

AD1 and AD0 are three-state address pins.

Device Address

0011000 0 0
0011001 NC 0
0011010 1 0
0101001 0 NC
0101010 NC NC
0101011 1 NC
1001100 0 1
1001101 NC 1
1001110 1 1

AD1

AD0

R = Read

X = Don’t Care

GENERIC INTERFACE

Table 6. Generic Interface Format

7-Bit Device Address

R/

W

S

Slave Address Byte Instruction Byte Data Byte

(See Table 5)

Table 7. RDAC-to-EEPROM Interface Command Descriptions

C2 C1 C0 Command Description

0 0 0 Operation between I2C and RDAC
0 0 1 Operation between I2C and EEPROM
0 1 0

1 0 0 NOP
1 0 1 Restore EEPROM to RDAC
1 1 0 Store RDAC to EEPROM

SA C2 C1 C0 A4 A3 A2 A1 A0 SA D7 D6 D5 D4 D3 D2 D1 D0 SA P

2

Operation between I
Register. See Table 10.

C and Write Protection

Rev. 0 | Page 16 of 24

AD5259

WRITE MODES

Table 8. Writing to RDAC Register

7-Bit Device Address

S

Slave Address Byte Instruction Byte Data Byte

Table 9. Writing to EEPROM Register

S

Slave Address Byte Instruction Byte Data Byte

Table 10. Activating/Deactivating Software Write Protect

S

Slave Address Byte Instruction Byte Data Byte

In order to activate the write protection mode, the WP bit in Table 10 must be logic high. In order to deactivate the write protection, the
command must be sent again except with the WP in logic zero state.

READ MODES

Read modes are referred to as traditional because the first two
bytes for all three cases are “dummy” bytes which function to
place the pointer towards the correct register. This is the reason
for the repeat start. In theory, this step can be avoided if the
user is interested in reading a register that was previously

Table 11. Traditional Readback of RDAC Register Value

7-Bit Device Address

S

(See Table 5)

Slave Address Byte Instruction Byte Slave Address Byte Read Back Data

(See Table 5) 0 SA 0 0 0 0 0 0 0 0 SA D7 D6 D5 D4 D3 D2 D1 D0 SA P

7-Bit Device Address

(See Table 5) 0 SA 0 0 1 0 0 0 0 0 SA D7 D6 D5 D4 D3 D2 D1 D0 SA P

7-Bit Device Address

(See Table 5) 0 SA 0 1 0 0 0 0 0 0 SA 0 0 0 0 0 0 0 WP SA P

written to. For example, if the EEPROM was just written to,
then the user can skip the two dummy bytes and proceed
directly to the slave address byte followed by the EEPROM
readback data.

7-Bit Device Address

0 SA 0 0 0 0 0 0 0 0 SA S

(See Table 5)

1 SA D7 D6 D5 D4 D3 D2 D1 D0 NA P

↑

Repeat start

Table 12. Traditional Readback of Stored EEPROM Value

7-Bit Device Address

S

(See Table 5)

Slave Address Byte Instruction Byte Slave Address Byte Read Back Data

0 SA 0 0 1 0 0 0 0 0 SA S

7-Bit Device Address

(See Table 5)

1 SA D7 D6 D5 D4 D3 D2 D1 D0 NA P

↑

Repeat start

STORE/RESTORE MODES

Table 13. Storing RDAC Value to EEPROM

7-Bit Device Address

S

(See Table 5) 0 SA 1 1 0 0 0 0 0 0 SA P

Slave Address Byte Instruction Byte

Table 14. Restoring EEPROM to RDAC

7-Bit Device Address

S

(See Table 5)

Slave Address Byte Instruction Byte

0 SA 1 0 1 0 0 0 0 0 SA P

Rev. 0 | Page 17 of 24

AD5259

A

TOLERANCE READBACK MODES

Table 15. Traditional Readback of Tolerance (Individually)

7-Bit Device Address

(See Table 5)

S

0 SA 0 0 1 1 1 1 1 0 SA S

Slave Address Byte Instruction Byte Slave Address Byte Sign + Integer Byte

↑

Repeat start

7-Bit Device Address

(See Table 5)

S

0 SA 0 0 1 1 1 1 1 1 SA S

Slave Address Byte Instruction Byte Slave Address Byte Decimal Byte

Repeat start

Table 16.Traditional Readback of Tolerance (Consecutively)

7-Bit Device Address

S

(See Table 5) 0 SA 0 0 1 1 1 1 1 0 SA S

Slave Address Byte Instruction Byte Slave Address Byte Sign + Integer Byte Decimal Byte

↑

Repeat start

7-Bit Device Address

(See Table 5)

1SAD7D6D5D4D3D2D1D0NA P

7-Bit Device Address

(See Table 5)

1SAD7D6D5D4D3D2D1D0NA P

↑

7-Bit Device Address

(See Table 5) 1 SA D7 D6 D5 D4 D3 D2 D1 D0 MA D7 D6 D5 D4 D3 D2 D1 D0 NA P

Calculating RAB Tolerance Stored in Read-Only Memory

D7 D6 D5 D4 D3 D2 D1 D0

6252423222120

SIGN

2

SIGN

7 BITS FOR INTEGER NUMBER

Figure 41. Format of Stored Tolerance in Sign Magnitude Format with Bit Position Descriptions.

(Unit is Percent. Only Data Bytes are Shown.)

The AD5259 features a patented RAB tolerance storage in the
nonvolatile memory. The tolerance is stored in the memory
during factory production and can be read by users at any time.
The knowledge of stored tolerance allows users to accurately
calculate R

. This feature is valuable for precision, rheostat

AB

mode, and open-loop applications where knowledge of absolute
resistance is critical.

The stored tolerance resides in the read-only memory and is
expressed as a percentage. The tolerance is stored in two memory
location bytes in sign magnitude binary form (see Figure 41).
The two EEPROM address bytes are 11110 (sign + integer) and
11111 (decimal number). The two bytes can be individually
accessed with two separate commands (see Table 15). Alternatively,
readback of the first byte followed by the second byte can be
done in one command (see Table 16). In the latter case, the
memory pointer will automatically increment from the first to

AA

D7 D6 D5 D4 D3 D2 D1 D0

2–12–22–32–42–52–62

8 BITS FOR DECIMAL NUMBER

–7

–8

2

05026-005

the second EEPROM location (increments from 11110 to

11111) if read consecutively.

In the first memory location, the MSB is designated for the sign
(0 = + and 1= –) and the seven LSBs are designated for the integer
portion of the tolerance. In the second memory location, all eight
data bits are designated for the decimal portion of tolerance. Note
that the decimal portion has a limited accuracy of only 0.1%. For
example, if the rated R

= 10 kΩ and the data readback from

AB

Address 11110 shows 0001 1100, and Address 11111 shows
0000 1111, then the tolerance can be calculated as

MSB: 0 = +
Next 7 MSB: 001 1100 = 28

–8

8 LSB: 0000 1111 = 15 × 2

= 0.06
Tolerance = +28.06%
Rounded Tolerance = +28.1% and therefore,
R

AB_ACTUAL

= 12.810 kΩ

Rev. 0 | Page 18 of 24

AD5259

V

ESD PROTECTION OF DIGITAL PINS AND RESISTOR TERMINALS

The AD5259 VDD, V
boundary conditions for proper 3-terminal and digital input
operation. Supply signals present on Terminal A, Terminal B,
and Terminal W that exceed V
internal forward biased ESD protection diodes (see Figure 42).
Digital Input SCL and Digital Input SDA are clamped by ESD
protection diodes with respect to V
Figure 43.

Figure 42. Maximum Terminal Voltages Set by V

Figure 43. Maximum Terminal Voltages Set by V

, and GND power supplies define the

LOGIC

or GND are clamped by the

DD

and GND as shown in

LOGIC

V

DD

A

W

B

GND

05026-039

and GND

DD

V

LOGIC

SCL

SDA

GND

05026-040

and GND

LOGIC

POWER-UP SEQUENCE

Because the ESD protection diodes limit the voltage compliance
at Te r mi n al A , Te r min al B , and Te rm i na l W ( s ee Fi gu r e 42 ), i t is
important to power GND/V

DD/VLOGIC

voltage to Terminal A, Terminal B, and Terminal W; otherwise,
the diode is forward biased such that V
powered unintentionally and may affect the user’s circuit. The
ideal power-up sequence is in the following order: GND, V

, digital inputs, and then VA, VB, VW. The relative order of

V

LOGIC

powering V

, VB, VW, and the digital inputs is not important as

A

long as they are powered after GND/V

before applying any

and V

DD

DD/VLOGIC

LOGIC

.

are

DD

,

Similarly, it is also good practice to bypass the power supplies
with quality capacitors for optimum stability. Supply leads to
the device should be bypassed with disc or chip ceramic
capacitors of 0.01 µF to 0.1 µF. Low ESR 1 µF to 10 µF tantalum
or electrolytic capacitors should also be applied at the supplies
to minimize any transient disturbance and low frequency ripple
(see Figure 44). The digital ground should also be joined
remotely to the analog ground at one point to minimize the
ground bounce.

DD

+

C2

10µFC10.1µF

Figure 44. Power Supply Bypassing

V

DD

AD5259

GND

05026-041

MULTIPLE DEVICES ON ONE BUS

The AD5259 has two three-state configurable Address Pins
AD0 and AD1. The state of these two pins is registered upon

2

power-up and decoded into a corresponding I

C 7-bit address
(see Table 5). This allows up to nine devices on the bus to be
written to, or read from, independently. In the case that the
address pin is assigned to be floated, the static voltage will be

/2.

V

LOGIC

EVALUATION BOARD

An evaluation board, along with all necessary software, is
available to program the AD5259 from any PC running
Windows® 98/2000/XP. The graphical user interface, as shown
in Figure 45, is straightforward and easy to use. More detailed
information is available in the user manual that comes with the
board.

LAYOUT AND POWER SUPPLY BYPASSING

It is good practice to employ compact, minimum lead length
layout design. The leads to the inputs should be as direct as
possible with minimum conductor length. Ground paths should

Figure 45. AD5259 Evaluation Board Software

have low resistance and low inductance.

Rev. 0 | Page 19 of 24

05026-042

AD5259

DISPLAY APPLICATIONS

CIRCUITRY

A special feature of the AD5259 is its unique separation of the

and VDD supply pins. The reason for doing this is to

V

LOGIC

provide greater flexibility in applications that do not always
provide needed supply voltages.

In particular, LCD panels often require a V
range of 3 V to 5 V. The circuit in Figure 46 is the rare exception
in which a 5 V supply is available to power the digital
potentiometer.

14.4VVCC (~3.3V) 5V

R1

C1

1µF

MCU

R6

10kΩ

R5

10kΩ

Figure 46. V

AD5259

V
V

SCL
SDA
GND

70kΩ

DD
LOGIC

R2

A

10kΩ

W

B

R3
25kΩ

Adjustment Application

COM

COM

–

U1

AD8565

+

voltage in the

3.5V < V

COM

< 4.5V

05026-006

will not affect that node’s bias because it is only on the

V

DD

order of microamps. V
supply because V

LOGIC

is tied to the MCU’s 3.3 V digital

LOGIC

will draw the 35 mA which is needed
when writing to the EEPROM. It would be impractical to try
and source 35 mA through the 70 kΩ resistor, therefore, V
is not connected to the same node as V

For this reason, V

and VDD are provided as two separate

LOGIC

DD

.

LOGIC

supply pins that can either be tied together or treated inde­pendently; V
and V

biasing up the A, B, and W terminals for added

DD

supplying the logic/EEPROM with power,

LOGIC

flexibility.

AD5259

V

DD

V

LOGIC

SCL
SDA
GND

14.4VVCC (~3.3V)
R1

70kΩ

–

U1

R2

A

10kΩ

W

B

R3
25kΩ

AD8565

+

3.5V < V

COM

DD

SUPPLIES POWER
TO BOTH THE
MICRO AND THE
LOGIC SUPPLY OF

10kΩ

MCU

THE DIGITAL POT

R5

R6

10kΩ

C1

1µF

Figure 47. Circuitry When a Separate Supply is Not Available for V

< 4.5V

05026-007

In the more common case shown in Figure 47, only analog 14.4 V
and digital logic 3.3 V supplies are available. By placing discrete
resistors above and below the digital pot, V

can now be tapped

DD

off the resistor string itself. Based on the chosen resistor values,
the voltage at V

in this case equals 4.8 V, allowing the wiper to

DD

be safely operated all the way up to 4.8 V. The current draw of

For a more detailed look at this application, refer to the article,
“Simple VCOM Adjustment uses any Logic Supply Voltage” in
the September 30, 2004 issue of EDN magazine.

Rev. 0 | Page 20 of 24

AD5259

OUTLINE DIMENSIONS

3.00 BSC

6

10

3.00 BSC

1

PIN 1

0.50 BSC

0.95

0.85

0.75

0.15

0.00

0.27

0.17

COPLANARITY

0.10
COMPLIANT TO JEDEC STANDARDS MO-187BA

Figure 48. 10-Lead Mini Small Outline Package [MSOP]

4.90 BSC

5

1.10 MAX

SEATING
PLANE

0.23

0.08

8°
0°

(RM-10)

Dimensions shown in millimeters

0.80

0.60

0.40

ORDERING GUIDE

Model

AD5259BRMZ5

1

(Ω)

R

AB

Temperature

5 k –40°C to +85°C MSOP-10 RM-10 D4P
AD5259BRMZ5-R71 5 k –40°C to +85°C MSOP-10 RM-10 D4P
AD5259BRMZ101 10 k –40°C to +85°C MSOP-10 RM-10
AD5259BRMZ10-R71 10 k –40°C to +85°C MSOP-10 RM-10
AD5259BRMZ501 50 k –40°C to +85°C MSOP-10 RM-10
AD5259BRMZ50-R71 50 k –40°C to +85°C MSOP-10 RM-10
AD5259BRMZ1001 100 k –40°C to +85°C MSOP-10 RM-10
AD5259BRMZ100-R71 100 k –40°C to +85°C MSOP-10 RM-10
AD5259EVAL

1

Z = Pb-free part.

2

The evaluation board is shipped with the 10 kΩ RAB resistor option; however, the board is compatible with all available resistor value options.

2

Evaluation Board

Package Description Package Option

Branding

D4Q

D4Q

D4R
D4R
D4S
D4S

Rev. 0 | Page 21 of 24

AD5259

NOTES

Rev. 0 | Page 22 of 24

AD5259

NOTES

Rev. 0 | Page 23 of 24

AD5259

NOTES

Purchase of licensed I C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I C Patent
Rights to use these components in an I

2 2

2 2

C system, provided that the system conforms to the I C Standard Specification as defined by Philips

.

© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective companies.

D05026–0–2/05(0)

Rev. 0 | Page 24 of 24