Datasheet AD5247 Datasheet (Analog Devices)

Page 1

128-Position I2C Compatible

FEATURES

128-position End-to-end resistance 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ Ultracompact SC70-6 (2 mm × 2.1 mm) package

C® compatible interface

I Full read/write of wiper register Power-on preset to midscale Single supply 2.7 V to 5.5 V Low temperature coefficient 45 ppm/°C Low power, I Wide operating temperature –40°C to +125°C Evaluation board available

APPLICATIONS

Mechanical potentiometer replacement in new designs Transducer adjustment of pressure, temperature, position,

chemical, and optical sensors RF amplifier biasing LCD brightness and contrast adjustment Automotive electronics adjustment Gain control and offset adjustment

GENERAL OVERVIEW

The AD5247 provides a compact 2 mm × 2.1 mm packaged solution for 128-position adjustment applications. This device performs the same electronic adjustment function as a mechanical potentiometer or a variable resistor. Available in four different end-to-end resistance values (5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ), these low temperature coefficient devices are ideal for high accuracy and stability variable resistance adjustments.

The wiper settings are controllable through the I digital interface, which can also be used to read back the present wiper register control word. The resistance between the wiper and either end point of the fixed resistor varies linearly with respect to the digital code transferred into the RDAC

= 3 µA typical

C compatible

latch.

Digital Potentiometer

AD5247

FUNCTIONAL BLOCK DIAGRAM

SDA

SCL

Note: The terms digital potentiometer, VR, and RDAC are used

interchangeably in this document.

I2C INTERFACE

WIPER

GND

Figure 1.

03876-0-001

Operating from a 2.7 V to 5.5 V power supply and consuming 3 µA allows for usage in portable battery-operated applications.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.

Page 2

AD5247

TABLE OF CONTENTS

Electrical Characteristics—5 kΩ Version ...................................... 3

Electrical Characteristics—10 kΩ, 50 kΩ, 100 kΩ Versions ....... 4

Timing Characteristics

5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ Versions........................................ 5

Absolute Maximum Ratings............................................................ 6

Typical Performance Characteristics ............................................. 7

Test Circuits..................................................................................... 11

I2C Interface..................................................................................... 12

Operation......................................................................................... 13

Programming the Variable Resistor......................................... 13

Programming the Potentiometer Divider............................... 14

I2C Compatible 2-Wire Serial Bus............................................ 14

REVISION HISTORY

Revision 0: Initial Version

Level Shifting for Bidirectional Interface................................ 15

ESD Protection ........................................................................... 15

Terminal Voltage Operating Range.......................................... 15

Maximum Operating Current.................................................. 15

Power-Up Sequence ................................................................... 15

Layout and Power Supply Bypassing ....................................... 16

Constant Bias to Retain Resistance Setting............................. 16

Evaluation Board........................................................................ 16

Pin Configuration and Function Descriptions........................... 17

Outline Dimensions....................................................................... 18

Ordering Guide .......................................................................... 18

Rev. 0 | Page 2 of 20

Page 3

AD5247

ELECTRICAL CHARACTERISTICS—5 kΩ VERSION

Table 1. VDD = 5 V ±10% or 3 V ± 10%; VA = +VDD; –40°C < TA < +125°C; unless otherwise noted

Parameter Symbol Conditions Min Typ1 Max Unit

DC CHARACTERISTICS—RHEOSTAT MODE

Resistor Differential Nonlinearity2 R-DNL RWB, VA = No Connect –1.5 ±0.1 +1.5 LSB

Resistor Integral Nonlinearity2 R-INL RWB, VA = No Connect –4 ±0.75 +4 LSB

Nominal Resistor Tolerance3 ∆RAB –30 +30 %

Resistance Temperature Coefficient ∆RAB/∆T VA = VDD, Wiper = No Connect 45 ppm/°C

RWB R DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE

Differential Nonlinearity4 DNL –1 ±0.1 +1 LSB

Integral Nonlinearity4 INL –1 ±0.2 +1 LSB

Voltage Divider Temperature Coefficient ∆VW/∆T Code = 0x40 15 ppm/°C

Full-Scale Error V

Zero-Scale Error V RESISTOR TERMINALS

Voltage Range5 V

Capacitance6 A CA

Capacitance6 W CW

Common-Mode Leakage ICM V DIGITAL INPUTS AND OUTPUTS

Input Logic High VIH V

Input Logic Low VIL V

Input Logic High VIH V

Input Logic Low VIL V

Input Current IIL V

Input Capacitance6 C POWER SUPPLIES

Power Supply Range V

Supply Current IDD V

Power Dissipation7 P

Power Supply Sensitivity PSSR

DYNAMIC CHARACTERISTICS

6, 8

Bandwidth –3 dB BW_5K RAB = 5 kΩ, Code = 0x40 1.2 MHz

Total Harmonic Distortion THDW

VW Settling Time tS V

Resistor Noise Voltage Density e

Typical specifications represent average readings at 25°C and VDD = 5 V.

Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper

positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.

VA = VDD, Wiper (VW) = no connect.

INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.

DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.

Resistor terminals A and W have no limitations on polarity with respect to each other.

Guaranteed by design and not subject to production test.

is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.

DISS

All dynamic characteristics use VDD = 5 V.

Code = 0x00 75 300 Ω

Code = 0x7F –3 –2 0 LSB

WFSE

Code = 0x00 0 +1 +2 LSB

WZSE

GND VDD V

B, W

f = 1 MHz, Measured to GND, Code = 0x40

= VDD/2 1 nA

= 5 V 2.4 V

= 5 V 0.8 V

= 3 V 2.1 V

= 3 V 0.6 V

= 0 V or 5 V ±1 µA

5 pF

2.7 5.5 V

DD RANGE

= 5 V or VIL = 0 V 3 8 µA

DISS

= 5 V or VIL = 0 V, VDD = 5 V 40 µW

= +5 V ± 10%,

Code = Midscale

= 1 V rms, VB = 0 V,

f = 1 kHz

= 5 V, ±1 LSB Error Band 1 µs

N_WB

RWB = 2.5 kΩ, RS = 0 Ω 6 nV/√Hz

45 pF

60 pF

±0.003 ±0.05 %/%

0.05 %

Rev. 0 | Page 3 of 20

Page 4

AD5247

ELECTRICAL CHARACTERISTICS—10 kΩ, 50 kΩ, 100 kΩ VERSIONS

Table 2. VDD = 5 V ± 10% or 3 V ± 10%; VA = VDD; –40°C < TA < +125°C; unless otherwise noted

Parameter Symbol Conditions Min Typ1 Max Unit

DC CHARACTERISTICS—RHEOSTAT MODE

Resistor Differential Nonlinearity2 R-DNL RWB, VA = No Connect –1 ±0.1 +1 LSB Resistor Integral Nonlinearity2 R-INL RWB, VA = No Connect –2 ±0.25 +2 LSB Nominal Resistor Tolerance3 ∆RAB –20 +20 % Resistance Temperature Coefficient ∆RAB/∆T VA = VDD, Wiper = No Connect 45 ppm/°C RWB R

DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE

Differential Nonlinearity4 DNL –1 ±0.1 +1 LSB Integral Nonlinearity4 INL –1 ±0.2 +1 LSB Voltage Divider Temperature Coefficient ∆VW/∆T Code = 0x40 15 ppm/°C Full-Scale Error (50 kΩ, 100 kΩ) V Zero-Scale Error (50 kΩ, 100 kΩ) V Full-Scale Error (10 kΩ) V Zero-Scale Error (10 kΩ) V

RESISTOR TERMINALS

Voltage Range5 V Capacitance6 A CA

Capacitance6 W CW

Common-Mode Leakage ICM V

DIGITAL INPUTS AND OUTPUTS

Input Logic High VIH V Input Logic Low VIL V Input Logic High VIH V Input Logic Low VIL V Input Current IIL V Input Capacitance6 C

POWER SUPPLIES

Power Supply Range V Supply Current IDD V Power Dissipation7 P Power Supply Sensitivity PSSR VDD = +5 V ± 10%, Code = Midscale ±0.01 ±0.02 %/%

DYNAMIC CHARACTERISTICS

6, 8

Bandwidth –3 dB BW

Total Harmonic Distortion THDW VA =1 V rms, f = 1 kHz, RAB = 10 kΩ 0.05 % VW Settling Time (10 kΩ/50 kΩ/100 kΩ) tS V Resistor Noise Voltage Density e

Typical specifications represent average readings at 25°C and VDD = 5 V.

Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper

positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.

VA = VDD, Wiper (VW) = no connect.

INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.

DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.

Resistor terminals A and W have no limitations on polarity with respect to each other.

Guaranteed by design and not subject to production test.

is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.

DISS

All dynamic characteristics use VDD = 5 V.

Code = 0x00 75 300 Ω

Code = 0x7F –1 –1 0 LSB

WFSE

Code = 0x00 0 +0.4 +1 LSB

WZSE

Code = 0x7F –2 –0.5 0 LSB

WFSE

Code = 0x00 0 +0.5 +1 LSB

WZSE

GND VDD V

A, W

f = 1 MHz, Measured to GND, Code = 0x40

= VDD/2 1 nA

= 5V 2.4 V

= 5 V 0.8 V

= 3 V 2.1 V

= 3 V 0.6 V

= 0 V or 5 V ±1 µA

5 pF

2.7 5.5 V

DD RANGE

= 5 V or VIL = 0 V 3 8 µA

VIH = 5 V or VIL = 0 V, VDD = 5 V 40 µW

DISS

= 10 kΩ/50 kΩ/100 kΩ,

Code = 0x40

= 5 V ±1 LSB Error Band 2 µs

RWB = 5 kΩ, RS = 0 9 nV/√Hz

N_WB

45 pF

60 pF

600/100/40 kHz

Rev. 0 | Page 4 of 20

Page 5

AD5247

TIMING CHARACTERISTICS—5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ VERSIONS

Table 3. VDD = 5 V ± 10% or 3 V ± 10%; VA = VDD; –40°C < TA < +125°C; unless otherwise noted

Parameter Symbol Conditions Min Typ1 Max Unit

I2C INTERFACE TIMING CHARACTERISTICS

(Specifications Apply to All Parts)

SCL Clock Frequency f

Bus Free Time between STOP and START t1 1.3 µs

BUF

Hold Time (Repeated START) t2

HD;STA

Low Period of SCL Clock t3 1.3 µs

LOW

High Period of SCL Clock t4 0.6 50 µs

HIGH

Setup Time for Repeated START Condition t5 0.6 µs

SU;STA

Data Hold Time t6 0.9 µs

HD;DAT

Data Setup Time t7 100 ns

SU;DAT

tF Fall Time of Both SDA and SCL Signals t8 300 ns

tR Rise Time of Both SDA and SCL Signals t9 300 ns

Setup Time for STOP Condition t10 0.6 µs

SU;STO

Typical specifications represent average readings at 25°C and VDD = 5 V.

Guaranteed by design and not subject to production test.

See timing diagrams ( , Figu , ) for locations of measured values. Figure 31 re 32 Figure 33

2, 3

400 kHz

SCL

After this period, the first clock pulse is generated. 0.6 µs

Rev. 0 | Page 5 of 20

Page 6

AD5247

ABSOLUTE MAXIMUM RATINGS

Table 4. TA = 25°C, unless otherwise noted1

Parameter Value

VDD to GND –0.3 V to +7 V VA, VW to GND VDD Terminal Current, Ax–Bx, Ax–Wx, Bx–Wx

Pulsed2 ±20 mA

Continuous ±5 mA Digital Inputs and Output Voltage to GND 0 V to VDD + 0.3 V Operating Temperature Range –40°C to +125°C Maximum Junction Temperature (T

) 150°C

JMAX

Storage Temperature –65°C to +150°C Lead Temperature (Soldering, 10 sec) 300°C Thermal Resistance3 θJA: SC70-6 340°C/W

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

Stresses above those listed under Absolute Maximum Ratings may cause

permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Maximum terminal current is bounded by the maximum current handling of

the switches, maximum power dissipation of the package, and maximum applied voltage across any two of the A, B, and W terminals at a given resistance.

Package power dissipation = (T

– TA)/θJA.

JMAX

Rev. 0 | Page 6 of 20

Page 7

AD5247

TYPICAL PERFORMANCE CHARACTERISTICS

RHEOSTAT MODE INL (LSB)

POTENTIOMETER MODE INL (LSB)

RHEOSTAT MODE DNL (LSB)

1.0

0.8

–0.2

–0.4

–0.6

–0.8

–1.0

0.6

0.4

0.2

16 32 48

VDD = 2.7V

VDD = 5.5V

CODE (Decimal)

Figure 2. R-INL vs. Code vs. Supply Voltages

0.5

0.4

0.3

0.2

0.1

–0.1

–0.2

–0.3

–0.4

–0.5

16 32 48

VDD = 2.7V

= 5.5V

CODE (Decimal)

Figure 3. R-DNL vs. Code vs. Supply Voltages

0.25

0.20

0.15

0.10

0.05

–0.05

–0.10

–0.15

–0.20

–0.25

TA = –40°C

TA = +25°C

TA = +85°C

TA = +125°C

16 32 48

CODE (Decimal)

Figure 4. INL vs. Code vs. Temperature

TA= 25

°C

= 10kΩ

64 80 96 112 128

TA = 25

°C

= 10kΩ

64 80 96 112 128

VDD= 2.7V

RAB = 10kΩ

TA = +25°C, +85°C, +125°C

TA = –40°C

64 80 96 112 128

03876-0-034

03876-0-035

03876-0-036

–0.05

–0.10

–0.15

POTENTIOMETER MODE DNL (LSB)

–0.20

–0.25

0.25

0.20

0.15

0.10

0.05

–40°C +25°C +85°C +125°C

16 32 48

TA = –40

°C, +25°C, +85°C, +125°C

64 80 96 112

CODE (Decimal)

VDD = 2.7V

= 10kΩ

03876-0-037

128

Figure 5. DNL vs. Code vs. Temperature

POTENTIOMETER MODE INL (LSB)

0.25

0.20

0.15

0.10

0.05

–0.05

–0.10

–0.15

–0.20

–0.25

VDD = 2.7V

16 32 48

= 5.5V

64 80 96 112 128

CODE (Decimal)

TA= 25°C

= 10kΩ

03876-0-038

Figure 6. INL vs. Code vs. Supply Voltages

POTENTIOMETER MODE DNL (LSB)

0.25

0.20

0.15

0.10

0.05

–0.05

–0.10

–0.15

–0.20

–0.25

VDD = 2.7V

VDD = 5.5V

VDD = 2.7V

16 32 48

VDD = 5.5V

64 80 96 112 128

CODE (Decimal)

TA= 25°C

= 10kΩ

03876-0-039

Figure 7. DNL vs. Code vs. Supply Voltages

Rev. 0 | Page 7 of 20

Page 8

AD5247

1.0

0.8

TA = +85°C

0.6

0.4

0.2

–0.2

–0.4

RHEOSTAT MODE INL (LSB)

–0.6

–0.8

–1.0

0.5

–40°C

0.4 +25°C

+85°C

0.3 +125°C

0.2

0.1

–0.1

–0.2

RHEOSTAT MODE DNL (LSB)

–0.3

–0.4

–0.5

–1.0

–1.5

–2.0

RHEOSTAT MODE INL (LSB)

FSE, FULL-SCALE ERROR (LSB)

–2.5

–3.0

–25 –10 5

–40

TA = –40°C

TA = +25°C

16 32 48

CODE (Decimal)

TA = +125°C

TA = –40

TA = +25°C

TA = +85°C

TA = +125°C

64 80 96 112 128

Figure 8. R-INL vs. Code vs. Temperature

VDD = 2.7V RAB = 10k

TA = –40°C, +25°C, +85°C, +125°C

16 32 48

64 80 96 112

CODE (Decimal)

Figure 9. R-DNL vs. Code vs. Temperature

VDD = 5.5V, VA = 5.5V

VDD = 2.7V, VA = 2.7V

20 35 50 65 80

TEMPERATURE (

°C)

Figure 10. Full-Scale Error vs. Temperature

°C

Ω

128

95 110 125

03876-0-040

03876-0-041

03876-0-042

1.50

1.25

1.00

0.75

0.50

0.25

ZSE, ZERO-SCALE ERROR (LSB)

–40

–25 –10 5

VDD = 5.5V, VA = 5.5V

20 35 50 65 80 95 110 125

TEMPERATURE (°C)

Figure 11. Zero-Scale Error vs. Temperature

100

SUPPLY CURRENT (µA)

0.1

DD,

0.01 –40

–25 –10

5 20 35 50 65 80 95 110 125

TEMPERATURE (°C)

Figure 12. Supply Current vs. Temperature

500

400

300

°C)

200

100

–100

–200

–300

RHEOSTAT MODE TEMPCO (ppm/

–400

–500

TA = –40°C to +85°C

TA = –40°C to +125°C

16 32 48 64 80 96 112 128

Figure 13. Rheostat Mode Tempco ∆R

VDD = 2.7V, VA = 2.7V

DIGITAL INPUTS = 0V CODE = 0x40

CODE (Decimal)

VDD = 5.5V

VDD = 2.7V

/∆T vs. Code

VDD = 2.7V

RAB = 10kΩ

03876-0-043

03876-0-044

03876-0-045

Rev. 0 | Page 8 of 20

Page 9

AD5247

°C)

= –40°C TO +85°C

POTENTIOMETER (ppm/

–10

–5

TA = –40°C TO +125°C

16 32 48

64 80 96 112 128

CODE (Decimal)

Figure 14. Potentiometer Mode Tempco ∆V

–6

–12

–18

–24

–30

GAIN (dB)

–36

–42

–48

–54

–60

0x40

0x20

0x10

0x08

0x04

0x02

0x01

10k

100k 1M 10M

FREQUENCY (Hz)

Figure 15. Gain vs. Frequency vs. Code, R

–6

–12

–18

–24

–30

GAIN (dB)

–36

–42

–48

–54

–60

0x40

0x20

0x10

0x08

0x04

0x02

0x01

10k

100k 1M 10M

FREQUENCY (Hz)

Figure 16. Gain vs. Frequency vs. Code, R

VDD= 2.7V R

/∆T vs. Code

= 5 kΩ

= 10 kΩ

= 10kΩ

03876-0-046

03876-0-047

03876-0-048

–6

–12

–18

–24

–30

GAIN (dB)

–36

–42

–48

–54

–60

0x40

0x20

0x10

0x08

0x04

0x02

0x01

10k

FREQUENCY (Hz)

Figure 17. Gain vs. Frequency vs. Code, R

–6

–12

–18

–24

–30

GAIN (dB)

–36

–42

–48

–54

–60

0x40

0x20

0x10

0x08

0x04

0x02

0x01

10k

FREQUENCY (Hz)

Figure 18. Gain vs. Frequency vs. Code, R

–6

–12

–18

–24

–30

GAIN (dB)

–36

–42

–48

–54

–60

10k

FREQUENCY (Hz)

Figure 19. –3 dB Bandwidth @ Code = 0x80

100k 1M 10M

= 50 kΩ

100k 1M 10M

= 100 kΩ

5kΩ

10kΩ

100kΩ

100k 1M 10M

50kΩ

03876-0-049

03876-0-050

03876-0-051

Rev. 0 | Page 9 of 20

Page 10

AD5247

0.30

0.25

0.20

0.15

(

0.10

0.05

A - VDD = 5.5V CODE = 0x55

= 5.5V

B - V

CODE = 0x7F

C - V

= 2.7V

CODE = 0x55

= 2.7V

D - V

CODE = 0x7F

10k 100k 1M

FREQUENCY (Hz)

Figure 20. I

vs. Frequency

TA= 25°C

03876-0-052

VDD = 5.5V V V CODE 0x40 to 0x3F

= 5.0V

= 0V

Figure 23. Midscale Glitch, Code 0x40 to 0x3F

150

125

100

VDD= 2.7V

TA= 25°C

= 50k

Ω

VDD = 5.5V V

= 5.0V

= 0V

CODE 0x00 to 0x7F

200ns/DIV

TA = 25°C

= 10kΩ

TA = 25°C

= 10k

03876-0-054

Ω

WIPER RESISTANCE (Ω)

16 80 128

32 48 64 96 112

Figure 21. Wiper Resistance vs. Code vs. V

VDD = 5.5V

= 5.0V

= 0V

VDD= 5.5V

CODE (Decimal)

1µs/DIV

TA = 25°C

= 10kΩ

= 100kHz

CLK

03876-0-056

4µs/DIV

Figure 24. Large Signal Settling Time

03876-0-055

03876-0-053

Figure 22. Digital Feedthrough

Rev. 0 | Page 10 of 20

Page 11

AD5247

TEST CIRCUITS

DUT

GND

V+ = V

PSRR (dB) = 20 LOG

PSS (%/ %) =

+15V

OP27

–15V

10%

∆V

03876-0-030

OUT

∆V

( )

∆V

03876-0-028

03876-0-025

Figure 25 to Figure 30 define the test conditions used in the product Specification tables.

IW= VDD/R

MS1

V+ = V

1LSB = V+/2

NOMINAL

RW= [V

MS1

03876-0-022

03876-0-023

– V

MS2

]/I

03876-0-024

DUT

V+

Figure 25. Test Circuit for Potentiometer Divider

Nonlinearity Error (INL, DNL)

NO CONNECT

DUT

Figure 26. Test Circuit for Resistor Position Nonlinearity Error

(Rheostat Operation; R-INL, R-DNL)

DUT

MS2

Figure 27. Test Circuit for Wiper Resistance

DUT

V+

Figure 28. Test Circuit for Power Supply Sensitivity (PSS, PSSR)

Figure 29. Test Circuit for Gain vs. Frequency

DUT

Figure 30. Test Circuit for Common-Mode Leakage Current

Rev. 0 | Page 11 of 20

Page 12

AD5247

I2C INTERFACE

Table 5. Write Mode

S 0 1 0 1 1 1 0 Slave Address Byte Data Byte

Table 6. Read Mode

S 0 1 0 1 1 1 0 R A 0 D6 D5 D4 D3 D2 D1 D0 A P Slave Address Byte Data Byte

A X D6 D5 D4 D3 D2 D1 D0 A P

S = Start Condition.

P = Stop Condition.

A = Acknowledge.

X = Don’t Care.

SCL

SDA

PS PS

START B

MASTER

START BY

MASTER

Figure 31. I

SCL

0 1 0 1 1 1 0 R/W

SDA

FRAME 1 FRAME 2

SLAVE ADDRESS BYTE

Figure 32. Writing to the RDAC Register

1 919

SCL

0 1 0 1 1 1 0 R/W

SDA

FRAME 1

SLAVE ADDRESS BYTE

Figure 33. Reading from the RDAC Register

= Write.

R = Read.

D6, D5, D4, D3, D2, D1, D0 = Data Bits.

C Interface, Detailed Timing Diagram

119

XD6 D4D3D2D1D0

ACK BY AD5247

D6 D5 D4 D3 D2 D1 D0

ACK BY AD5247

DATA BYTE

FRAME 2

RDAC REGISTER

03876-0-003

ACK BY AD5247

STOP BY MASTER

NO ACK BY MASTER

STOP BY MASTER

03876-0-004

03876-0-005

Rev. 0 | Page 12 of 20

Page 13

AD5247

OPERATION

The AD5247 is a 128-position, digitally controlled variable resistor (VR) device. An internal power-on preset places the wiper at midscale during power-on, which simplifies the default condition recovery at power-up.

PROGRAMMING THE VARIABLE RESISTOR

Rheostat Operation

The nominal resistance of the RDAC between terminals A and B is available in 5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ. The final two or three digits of the part number determine the nominal resistance value, e.g., 10 kΩ = 10, 50 kΩ = 50. The nominal resistance (R the wiper terminal, plus the B terminal contact. The 7-bit data in the RDAC latch is decoded to select one of the 128 possible settings.

Assuming a 10 kΩ part is used, the wiper’s first connection starts at the B terminal for data 0x00. Since there is a 50 Ω wiper contact resistance, such a connection yields a minimum of 100 Ω (2 × 50 Ω) resistance between terminals W and B. The second connection is the first tap point, which corresponds to 178 Ω (R The third connection is the next tap point, representing 256 Ω (2 × 78 Ω + 2 × 50 Ω) for data 0x02, and so on. Each LSB data value increase moves the wiper up the resistor ladder until the last tap point is reached at 10,100 Ω (R

) of the VR has 128 contact points accessed by

= RAB/128+ RW = 78 Ω + 2 × 50 Ω) for data 0x01.

+ 2 × RW).

The general equation determining the digitally programmed output resistance between W and B is

DR ×+×= 2

)(

128

D is the decimal equivalent of the binary code loaded in

where the 7-bit RDAC register,

is the wiper resistance contributed by the on resistance of

the internal switch. In summar y, if terminal is open-circuited, the output resistance

(1)

WABWB RR

is the end-to-end resistance, and

= 10 kΩ and the A

shown in

will be set for the indicated RDAC latch codes. Table 7

Table 7. Codes and Corresponding RWB Resistance

D (Dec.) RWB (Ω) Output State

127 10,100 Full Scale (RAB + 2 × RW) 64 5,100 Midscale 1 178 1 LSB 0 100 Zero Scale (Wiper Contact Resistance)

Note that in the zero-scale condition, a finite resistance of 100 Ω between terminals W and B is present. Care should be taken to limit the current flow between W and B in this state to a maximum pulse current of no more than 20 mA. Otherwise, degradation or possible destruction of the internal switch contact can occur.

Figure 34

shows a simplified diagram of the equivalent RDAC

circuit where the last resistor string will not be accessed.

D6 D5 D4 D3 D2 D1 D0

DECODER

Figure 34. AD5247 Equivalent RDAC Circuit

RDAC

LATCH

AND

03876-0-006

Similar to the mechanical potentiometer, the resistance of the RDAC between the wiper W and terminal A also produces a digitally controlled complementary resistance

. When these

terminals are used, the B terminal can be opened. Setting the

resistance value for

starts at a maximum value of resistance

and decreases as the data loaded in the latch increases in value. The general equation for this operation is

–128

DR ×+×= 2

)(

= 10 kΩ and the B terminal open circuited, the output

For

resistance

128

shown in will be set for the indicated

Table 8

(2)

WABWA RR

RDAC latch codes.

Table 8. Codes and Corresponding RWA Resistance

D (Dec.) RWA (Ω) Output State

127 178 Full Scale 64 5,100 Midscale 1 9,961 1 LSB 0 10,100 Zero Scale

Typical device-to-device matching is process lot dependent and may vary by up to ±30%. Since the resistance element is processed in thin film technology, the change in R

with

temperature has a very low 45 ppm/°C temperature coefficient.

Rev. 0 | Page 13 of 20

Page 14

AD5247

PROGRAMMING THE POTENTIOMETER DIVIDER

Voltage Output Operation

The digital potentiometer easily generates a voltage divider at wiper-to-B and wiper-to-A proportional to the input voltage at A-to-B. Unlike the polarity of V positive, voltage across A–B, W–A, and W–B can be at either polarity.

If ignoring the effect of the wiper resistance for approximation, connecting the A terminal to 5 V and the B terminal to ground produces an output voltage at the wiper-to-B starting at 0 V up to 1 LSB less than 5 V. Each LSB of voltage is equal to the voltage applied across terminal AB divided by the 128 positions of the potentiometer divider. The general equation defining the

output voltage at

with respect to ground for any valid input

voltage applied to terminals A and B is

128

AW V

)( = (3)

For a more accurate calculation, which includes the effect of wiper resistance, V

DV)()( =

, can b e found as

Operation of the digital potentiometer in the divider mode results in a more accurate operation over temperature. Unlike in rheostat mode, the output voltage in divider mode is dependent mainly on the ratio of internal resistors R the absolute values. Therefore, the temperature drift reduces to 15 ppm/°C.

I2C COMPATIBLE 2-WIRE SERIAL BUS

The first byte of the AD5247 is a slave address byte (see and ). It has a 7-bit slave address and a R/W bit. The

Table 6

seven MSBs of the slave address are 0101110 followed by 0 for a write command or 1 to place the device in read mode.

The 2-wire I

The master initiates data transfer by establishing a START

condition, which is when a high-to-low transition on the SDA line occurs while SCL is high (see ). The following byte is the slave address byte, which consists of the 7-bit slave address followed by an R/

determines whether data will be read from or written to the slave device).

C serial bus protocol operates as follows:

to GND, which must be

(4)

and RWB and not

Table 5

Figure 32

bit (this bit

The slave whose address corresponds to the transmitted address responds by pulling the SDA line low during the ninth clock pulse (this is termed the acknowledge bit). At this stage, all other devices on the bus remain idle while the selected device waits for data to be written to or read from its serial register. If the R/

from the slave device. On the other hand, if the R/ low, the master will write to the slave device.

In write mode, after acknowledgement of the slave address

2. byte, the next byte is the data byte. Data is transmitted over the serial bus in sequences of nine clock pulses (eight data bits followed by an acknowledge bit). The transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL (see T ).

In read mode, after acknowledgment of the slave address

byte, data is received over the serial bus in sequences of nine clock pulses (a slight difference from write mode, where eight data bits are followed by an acknowledge bit). Similarly, the transitions on the SDA line must occur during the low period of SCL and remain stable during the high period of SCL (see ). Figure 33

When all data bits have been read or written, a STOP

condition is established by the master. A STOP condition is defined as a low-to-high transition on the SDA line while SCL is high. In write mode, the master will pull the SDA line high during the tenth clock pulse to establish a STOP condition (see F ). In read mode, the master will

igure 32 issue a No Acknowledge for the ninth clock pulse (i.e., the SDA line remains high). The master will then bring the SDA line low before the tenth clock pulse, which goes high to establish a STOP condition (see F ).

A repeated write function gives the user flexibility to update the RDAC output a number of times after addressing the part only once. For example, after the RDAC has acknowledged its slave address in the write mode, the RDAC output will update on each successive byte. If different instructions are needed, the write/read mode has to start again with a new slave address and data byte. Similarly, a repeated read function of the RDAC is also allowed.

bit is high, the master will read

bit is

able 5

igure 33

Rev. 0 | Page 14 of 20

Page 15

AD5247

LEVEL SHIFTING FOR BIDIRECTIONAL INTERFACE

While most legacy systems may be operated at one voltage, a new component may be optimized at another. When two systems operate the same signal at two different voltages, proper level shifting is needed. For instance, one can use a 3.3 V

PROM to interface with a 5 V digital potentiometer. A level shifting scheme is needed to enable a bidirectional communication so that the setting of the digital potentiometer can be stored to and retrieved from the E of the implementations. M1 and M2 can be any N channel signal FETs, or if VDD falls below 2.5 V, M1 and M2 can be low threshold FETs such as the FDV301N.

= 3.3V V

DD1

SDA1

SCL1

3.3V

E2PROM

Figure 35. Level Shifting for Operation at Different Potentials

PROM. F shows one

igure 35

DD2

SDA2

AD5247

SCL2

03876-0-007

GND

03876-0-010

Figure 38. Maximum Terminal Voltages Set by V

and GND

MAXIMUM OPERATING CURRENT

At low code values, the user should be aware that due to low resistance values, the current through the RDAC may exceed the 5 mA limit. In F , a 5 V supply is placed on the wiper, and the current through terminals W and B is plotted with respect to code. A line is also drawn denoting the 5 mA current limit. Note that at low code values (particularly for the 5 kΩ and 10 kΩ options), the current level increases significantly. Care should be taken to limit the current flow between W and B in this state to a maximum continuous current of 5 mA and a maximum pulse current of no more than 20 mA. Otherwise, degradation or possible destruction of the internal switch contacts can occur.

100.00

igure 39

ESD PROTECTION

All digital inputs are protected with a series input resistor and parallel Zener ESD structures shown in and .

Figure 36

Figure 37

This applies to the digital input pins SDA and SCL.

340Ω

Figure 36. ESD Protection of Digital Pins

A,W

Figure 37. ESD Protection of Resistor Terminals

GND

LOGIC

03876-0-008

03876-0-009

TERMINAL VOLTAGE OPERATING RANGE

The AD5247 VDD and GND power supply defines the boundary conditions for proper 3-terminal digital potentiometer operation. Supply signals present on terminals A and W that exceed V biased diodes (see ). Figure 38

or GND will be clamped by the internal forward

10.00

1.00

IWB CURRENT (mA)

0.10

0.01 0

16 32 48

5mA CURRENT LIMIT

RAB= 10k

RAB= 100k

64 80 96 112 128

CODE (Decimal)

Ω

RAB= 50k

= 5k

Ω

03876-0-057

Figure 39. Maximum Operating Current

POWER-UP SEQUENCE

Since the ESD protection diodes limit the voltage compliance at terminals A and W (see F ), it is important to power V

/GND before applying any voltage to terminals A and W;

otherwise, the diode will be forward biased such that V powered unintentionally and may affect the rest of the user’s circuit. The ideal power-up sequence is in the following order: GND, V powering V

, digital inputs, and then VA/VW. The relative order of

and VW and the digital inputs is not important as

long as they are powered after V

igure 38

/GND.

will be

Rev. 0 | Page 15 of 20

Page 16

AD5247

LAYOUT AND POWER SUPPLY BYPASSING

It is a good practice to employ a compact, minimum lead-length layout design. The leads to the inputs should be as direct as possible with a minimum conductor length. Ground paths should have low resistance and low inductance.

Similarly, it is a good practice to bypass the power supplies with quality capacitors for optimum stability. Supply leads to the device should be bypassed with 0.01 µF to 0.1 µF disc or chip ceramic capacitors. Low ESR 1 µF to 10 µF tantalum or electrolytic capacitors should also be applied at the supplies to minimize any transient disturbance and low frequency ripple (see ). Note that the digital ground should also be

Figure 40 joined remotely to the analog ground at one point to minimize the ground bounce.

Figure 40. Power Supply Bypassing

10µF

0.1µF

AD5247

GND

03876-0-011

CONSTANT BIAS TO RETAIN RESISTANCE SETTING

For users who desire nonvolatility but cannot justify the additional cost for the EEMEM, the AD5247 may be considered as a low cost alternative by maintaining a constant bias to retain the wiper setting. The AD5247 was designed specifically with low power in mind, which allows low power consumption even in battery-operated systems. The graph in demonstrates the power consumption from a 3.4 V 450 mAhr Li-ion cell phone battery, which is connected to the AD5247. The measurement over time shows that the device draws approximately 1.3 µA and consumes negligible power. Over a course of 30 days, the battery was depleted by less than 2%, the majority of which is due to the intrinsic leakage current of the battery itself.

Figure 41

110%

108%

106%

104%

102%

100%

98%

96%

BATTERY LIFE DEPLETED

94%

92%

90%

51015

DAYS

Figure 41. Battery Operating Life Depletion

TA= 25

°C

20 25 30

03876-0-059

This demonstrates that constantly biasing the pot is not an impractical approach. Most portable devices do not require the removal of batteries for the purpose of charging. Although the resistance setting of the AD5247 will be lost when the battery needs replacement, such events occur rather infrequently such that this inconvenience is justified by the lower cost and smaller size offered by the AD5247. If and when total power is lost, the user should be provided with a means to adjust the setting accordingly.

EVALUATION BOARD

An evaluation board, along with all necessary software, is available to program the AD5247 from any PC running Windows® 98, Windows 2000®, or Windows XP®. The graphical user interface, as shown in , is straightforward and easy to use. More detailed information is available in the user manual, which comes with the board.

Figure 42

03876-0-061

Figure 42. AD5247 Evaluation Board Software

Rev. 0 | Page 16 of 20

Page 17

AD5247

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

GND

SCL

AD5247

TOP VIEW

(Not to Scale)

SDA

03876-0-002

Figure 43. Pin Configuration (6-Lead SC70)

Table 9. AD5247 Pin Function Descriptions

Pin No. Mnemonic Description

1 VDD Positive Power Supply. 2 GND Digital Ground and B Termination Voltage. 3 SCL Serial Clock Input. Positive edge triggered. 4 SDA Serial Data Input/Output. 5 W W Terminal. 6 A A Terminal.

Rev. 0 | Page 17 of 20

Page 18

AD5247

OUTLINE DIMENSIONS

2.00 BSC

5 4

1.25 BSC

1.00

0.90

0.70

0.10 MAX

PIN 1

1.30 BSC

0.30

0.15

0.10 COPLANARITY

COMPLIANT TO JEDEC STANDARDS MO-203AB

0.65 BSC

2.10 BSC

1.10 MAX

SEATING PLANE

0.22

0.08

Figure 44. 6-Lead Thin Shrink Small Outline Transistor [SC70]

(KS-6)

Dimensions shown in millimeters

0.46 8° 4° 0°

0.36

0.26

ORDERING GUIDE

Model RAB (kΩ) Temperature Range Package Description Package Option Branding

AD5247BKS5-R2 5 –40°C to +125°C 6-lead SC70 KS-6 D1E AD5247BKS5-RL7 5 –40°C to +125°C 6-lead SC70 KS-6 D1E AD5247BKS10-R2 10 –40°C to +125°C 6-lead SC70 KS-6 D19 AD5247BKS10-RL7 10 –40°C to +125°C 6-lead SC70 KS-6 D19 AD5247BKS50-R2 50 –40°C to +125°C 6-lead SC70 KS-6 D18 AD5247BKS50-RL7 50 –40°C to +125°C 6-lead SC70 KS-6 D18 AD5247BKS100-R2 100 –40°C to +125°C 6-lead SC70 KS-6 D17 AD5247BKS100-RL7 100 –40°C to +125°C 6-lead SC70 KS-6 D17 AD5247EVAL See Note 1 Evaluation Board

The evaluation board is shipped with the 10 kΩ RAB resistor option; however, the board is compatible with all available resistor value options.

Rev. 0 | Page 18 of 20

Page 19

AD5247

NOTES

Rev. 0 | Page 19 of 20

Page 20

AD5247

NOTES

Purchase of licensed I purchaser under the Philips I

C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the

C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C

Standard Specification as defined by Philips.

C03876–0–9/03(0)

Rev. 0 | Page 20 of 20

Datasheet AD5247 Datasheet (Analog Devices)

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES

APPLICATIONS

GENERAL OVERVIEW

FUNCTIONAL BLOCK DIAGRAM

ABSOLUTE MAXIMUM RATINGS

TYPICAL PERFORMANCE CHARACTERISTICS

TEST CIRCUITS

I2C INTERFACE

OPERATION

PROGRAMMING THE VARIABLE RESISTOR

Rheostat Operation

PROGRAMMING THE POTENTIOMETER DIVIDER

Voltage Output Operation

I2C COMPATIBLE 2-WIRE SERIAL BUS

LEVEL SHIFTING FOR BIDIRECTIONAL INTERFACE

MAXIMUM OPERATING CURRENT

ESD PROTECTION

TERMINAL VOLTAGE OPERATING RANGE

POWER-UP SEQUENCE

LAYOUT AND POWER SUPPLY BYPASSING

CONSTANT BIAS TO RETAIN RESISTANCE SETTING

EVALUATION BOARD

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

OUTLINE DIMENSIONS

ORDERING GUIDE