Datasheet AD5231 Datasheet (Analog Devices)

Nonvolatile Memory,

FEATURES

1024-position resolution
Nonvolatile memory maintains wiper setting
Power-on refresh with EEMEM setting
EEMEM restore time: 140 µs typ
Full monotonic operation
10 kΩ, 50 kΩ, and 100 kΩ terminal resistance
Permanent memory write protection
Wiper setting readback
Predefined linear increment/decrement instructions
Predefined ±6 dB/step log taper increment/decrement

instructions
SPI®-compatible serial interface
3 V to 5 V single-supply or ±2.5 V dual-supply operation
28 bytes extra nonvolatile memory for user-defined data
100-year typical data retention, T

APPLICATIONS

Mechanical potentiometer replacement
Instrumentation: gain, offset adjustment
Programmable voltage to current conversion
Programmable filters, delays, time constants
Programmable power supply
Low resolution DAC replacement
Sensor calibration

GENERAL DESCRIPTION

The AD5231 is a nonvolatile memory,1 digitally controlled
potentiometer
the same electronic adjustment function as a mechanical poten­tiometer with enhanced resolution, solid state reliability, and
remote controllability. The AD5231 has versatile programming
that uses a standard 3-wire serial interface for 16 modes of
operation and adjustment, including scratchpad programming,
memory storing and restoring, increment/decrement,
±6 dB/step log taper adjustment, wiper setting readback, and
extra EEMEM for user-defined information, such as memory
data for other components, look-up table, or system identifica­tion information.

In scratchpad programming mode, a specific setting can be
programmed directly to the RDAC2 register that sets the resis­tance between Terminals W–A and W–B. This setting can be
stored into the EEMEM and is transferred automatically to the
RDAC register during system power-on.

2

with 1024-step resolution. The device performs

= 55°C

A

1024-Position Digital Potentiometer

AD5231

FUNCTIONAL BLOCK DIAGRAM

AD5231

RDAC

2

DIGITAL
OUTPUT
BUFFER

R

WB

CS

CLK

SDI

GND

SDO

WP

RDY

PR

SDI

SERIAL

INTERFACE

SDO

EEMEM

CONTROL

ADDR

DECODE

28 BYTES

USER EEMEM

RDAC

REGISTER

EEMEM(0)

DIGITAL

REGISTER

EEMEM(1)

Figure 1.

100

)
R

(D) – Percent of Nominal (%

(D), R
R

AB

WB

WA

75

50

25

0

R

WA

0 1023256

Figure 2. R

512 768

CODE (Decimal)

(D) and RWB (D) vs. Decimal Code

WA

The EEMEM content can be restored dynamically or through

PR

external

strobing, and a WP function protects EEMEM con­tents. To simplify the programming, the linear-step increment
or decrement commands can be used to move the RDAC wiper
up or down, one step at a time. The ±6 dB step commands can
be used to double or half the RDAC wiper setting.

The AD5231 is available in a 16-lead TSSOP. The part is guaran­teed to operate over the extended industrial temperature range
of −40°C to +85°C.

1

The terms nonvolatile memory and EEMEM are used interchangeably.

2

The terms digital potentiometer and RDAC are used interchangeably.

V

A
W
B

O1
O2

V

DD

SS

02739-0-001

03684-0-002

Rev. B

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone]
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

www.analog.com

AD5231

TABLE OF CONTENTS

Specifications..................................................................................... 3

RDAC Structure.......................................................................... 19

Electrical Characteristics—10 kΩ, 50 kΩ, 100 kΩ Versions ...3

Timing Characteristics—10 kΩ, 50 kΩ, 100 kΩ Versions....... 5

Absolute Maximum Ratings............................................................ 7

ESD Caution.................................................................................. 7

Pin Configuration and Function Descriptions............................. 8

Typical Performance Characteristics ............................................. 9

Test Circuits..................................................................................... 13

Theory of Operation ...................................................................... 14

Scratchpad and EEMEM Programming.................................. 14

Basic Operation .......................................................................... 14

EEMEM Protection.................................................................... 15

Digital Input/Output Configuration........................................ 15

Serial Data Interface................................................................... 15

Daisy-Chain Operation .............................................................15

Terminal Voltage Operation Range.......................................... 16

Programming the Variable Resistor......................................... 19

Programming the Potentiometer Divider............................... 20

Programming Examples............................................................ 21

Flash/EEMEM Reliability.......................................................... 21

Applications..................................................................................... 23

Bipolar Operation from Dual Supplies.................................... 23

High Voltage Operation............................................................. 23

Bipolar Programmable Gain Amplifier................................... 23

10-Bit Bipolar DAC.................................................................... 23

10-Bit Unipolar DAC................................................................. 24

Programmable Voltage Source with Boosted Output............ 24

Programmable Current Source ................................................ 24

Programmable Bidirectional Current Source......................... 25

Resistance Scaling ...................................................................... 25

RDAC Circuit Simulation Model............................................. 26

Power-Up Sequence ................................................................... 16

Latched Digital Outputs ............................................................ 16

Advanced Control Modes ......................................................... 18

REVISION HISTORY

9/04—Data Sheet Changed from Rev. A to Rev. B

Updated Format.................................................................. Universal

Changes to Table 20.........................................................................23

Changes to Resistance Scaling Section .........................................25

Changes to Ordering Guide...........................................................27

Outline Dimensions....................................................................... 27

Ordering Guide .......................................................................... 27

5/04—Data Sheet Changed from Rev. 0 to Rev. A

Updated formatting............................................................ Universal

Edits to Features, General Description, and Block Diagram....... 1

Changes to Specifications................................................................. 3

Replaced Timing Diagrams..............................................................6

Changes to Pin Function Descriptions...........................................8

Changes to Typical Performance Characteristics..........................9

Changes to Test Circuits .................................................................13

Edits to Theory of Operation.........................................................14

Edits to Applications.......................................................................23

Updated Outline Dimensions........................................................27

12/01—Revision 0: Initial Version

Rev. B | Page 2 of 28

AD5231

SPECIFICATIONS

ELECTRICAL CHARACTERISTICS—10 kΩ, 50 kΩ, 100 kΩ VERSIONS

VDD = 3 V ± 10% or 5 V ± 10%, VSS = 0 V, VA = VDD, VB = 0 V, −40°C < TA < +85°C, unless otherwise noted.

Table 1.

Parameter Symbol Conditions Min Typ1 Max Unit

DC CHARACTERISTICS
RHEOSTAT MODE

Resistor Differential Nonlinearity2 R-DNL RWB, VA = NC, Monotonic −1 ±1/2 +1.8 LSB
Resistor Integral Nonlinearity2 R-INL RWB,VA = NC −0.2 +0.2 LSB
Nominal Resistor Tolerance ∆RAB/RAB D = 0x3FF −40 +20 %
Resistance Temperature Coefficient (∆RWB/RWB)/∆T × 106 600 ppm/°C
Wiper Resistance RW

= 100 µA, VDD = 5.5 V,

I

W

Code = half scale

= 100 µA, VDD = 3 V,

I

W

Code = half scale
DC CHARACTERISTICS
POTENTIOMETER DIVIDER MODE

Resolution N 10 Bits
Differential Nonlinearity3 DNL Monotonic, TA = 25°C −1 ±1/2 +1 LSB
Monotonic, TA = −40°C or +85°C −1 +1.25 LSB
Integral Nonlinearity3 INL −0.4 +0.4 LSB
Voltage Divider Temperature

(∆V

)/∆T × 106 Code = half scale 15 ppm/°C

W/VW

Coefficient
Full-Scale Error V
Zero-Scale Error V

Code = full scale −3 0 % FS

WFSE

Code = zero scale 0 1.5 % FS

WZSE

RESISTOR TERMINALS

Terminal Voltage Range4 V
Capacitance A, B5 C

V

A, B, W

f = 1 MHz, measured to GND,

A, B

code = half-scale

Capacitance W5 C

f = 1 MHz, measured to GND,

W

Code = half-scale

Common-Mode Leakage Current

5, 6

ICM V

= VDD/2 0.01 1 µA

W

DIGITAL INPUTS AND OUTPUTS

Input Logic High VIH With respect to GND, VDD = 5 V 2.4 V
Input Logic Low VIL With respect to GND, VDD = 5 V 0.8 V
Input Logic High VIH With respect to GND, VDD = 3 V 2.1 V
Input Logic Low VIL With respect to GND, VDD = 3 V 0.6 V
Input Logic High VIH

Input Logic Low VIL

Output Logic High (SDO, RDY) VOH

With respect to GND, V
V

= −2.5 V

SS

With respect to GND, V

= −2.5 V

V

SS

= 2.2 kΩ to 5 V

R

PULL-UP

= +2.5 V,

DD

= +2.5 V,

DD

(see Figure 26)

Output Logic Low VOL

= 1.6 mA, V

I

OL

LOGIC

= 5 V

(see Figure 26)
Input Current IIL V
Input Capacitance5 C
Output Current5 I

4 pF

IL

, IO2 V

O1

V

= 0 V or VDD ±2.5 µA

IN

= 5 V, VSS = 0 V, TA = 25°C 50 mA

DD

= 2.5 V, VSS = 0 V, TA = 25°C 7 mA

DD

POWER SUPPLIES

Single-Supply Power Range VDD V

= 0 V 2.7 5.5 V

SS

Dual-Supply Power Range VDD/VSS ±2.25 ±2.75 V
Positive Supply Current IDD V

= VDD or VIL = GND 2.7 10 µA

IH

15 100 Ω

50 Ω

VDD V

SS

50 pF

50 pF

2.0 V

0.5 V

4.9 V

0.4 V

Rev. B | Page 3 of 28

AD5231

Parameter Symbol Conditions Min Typ1 Max Unit

Negative Supply Current ISS

EEMEM Store Mode Current IDD (store)

I
EEMEM Restore Mode Current7 I

I
Power Dissipation8 P
Power Supply Sensitivity5 P

DYNAMIC CHARACTERISTICS

5, 9

(store) VDD = +2.5 V, VSS = −2.5 V −40 mA

SS

(restore)

DD

(restore) VDD = +2.5 V, VSS = −2.5 V −0.3 −3 −9 mA

SS

V

DISS

∆VDD = 5 V ± 10% 0.002 0.01 %/%

SS

Bandwidth BW

= VDD or VIL = GND,

V

IH

= +2.5 V, VSS = −2.5 V

V

DD

= VDD or VIL = GND,

V

IH

V

= GND, ISS ≈ 0

SS

= VDD or VIL = GND,

V

IH

= GND, ISS ≈ 0

V

SS

= VDD or VIL = GND 0.018 0.05 mW

IH

−3 dB, R

= 10 kΩ/50 kΩ/

AB

100 kΩ

Total Harmonic Distortion THDW

VW Settling Time tS

= 1 V rms, VB = 0 V, f = 1 kHz,

V

A

= 10 kΩ

R

AB

= 1 V rms, VB = 0 V, f = 1 kHz,

V

A

R

= 50 kΩ, 100 kΩ

AB

= VDD, VB = 0 V,

V

A

= 0.50% error band,

V

W

Code 0x000 to 0x200
for R

= 10 kΩ/50 kΩ/100 kΩ

AB

Resistor Noise Voltage e

R

N_WB

= 5 kΩ, f = 1 kHz 9

WB

1

Typicals represent average readings at 25°C and VDD = 5 V.

2

Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper posi-

tions. R-DNL measures the relative step change from ideal between successive tap positions. I
version, I

3

INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = VSS. DNL specification limits of

−1 LSB minimum are guaranteed monotonic operating condition (see Figure 27).

4

Resistor Terminals A, B, and W have no limitations on polarity with respect to each other. Dual-supply operation enables ground-referenced bipolar signal adjustment.

5

Guaranteed by design and not subject to production test.

6

Common-mode leakage current is a measure of the dc leakage from any Terminal B–W to a common-mode bias level of VDD/2.

7

EEMEM restore mode current is not continuous. Current consumed while EEMEM locations are read and transferred to the RDAC register (see Figure 23). To minimize

power dissipation, a NOP Instruction 0 (0x0) should be issued immediately after Instruction 1 (0x1).

8

P

9

All dynamic characteristics use VDD = +2.5 V and VSS = −2.5 V.

~ 50 µA for the RAB = 50 kΩ and IW ~ 25 µA for the RAB = 100 kΩ version (see Figure 26).

W

is calculated from (IDD × VDD) + (ISS × VSS).

DISS

~ 50 µA @ VDD = 2.7 V and IW ~ 400 µA @ VDD = 5 V for the RAB = 10 kΩ

W

0.5 10 µA

40 mA

0.3 3 9 mA

370/85/44 kHz

0.022 %

0.045 %

1.2/3.7/7 µs

Hz

nV/√

Rev. B | Page 4 of 28

AD5231

TIMING CHARACTERISTICS—10 kΩ, 50 kΩ, 100 kΩ VERSIONS

VDD = 3 V to 5.5 V, VSS = 0 V, and −40°C < TA < +85°C, unless otherwise noted.

Table 2.

Parameter Symbol Conditions Min Typ1 Max Unit

INTERFACE TIMING CHARACTERISTICS

Clock Cycle Time (t

) t1 20 ns

CYC

CS Setup Time
CLK Shutdown Time to CS Rise
Input Clock Pulse Width t4, t5 Clock level high or low 10 ns
Data Setup Time t6 From positive CLK transition 5 ns
Data Hold Time t7 From positive CLK transition 5 ns
CS to SDO-SPI Line Acquire
CS to SDO-SPI Line Release
CLK to SDO Propagation Delay4 t
CLK to SDO Data Hold Time t11 R
CS High Pulse Width5
CS High to CS High5
RDY Rise to CS Fall
CS Rise to RDY Fall Time
Store/Read EEMEM Time6 t
Power-On EEMEM Restore Time t
Dynamic EEMEM Restore Time t
CS Rise to Clock Rise/Fall Setup
Preset Pulse Width (Asynchronous) t

Preset Response Time to Wiper Setting t

FLASH/EE MEMORY RELIABILITY

Endurance7 100 kCycles
Data Retention8 100 Years

1

Typicals represent average readings at 25°C and VDD = 5 V.

2

Guaranteed by design and not subject to production test.

3

See timing diagrams (Figure 3 and Figure 4) for location of measured values. All input control voltages are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed

from a voltage level of 1.5 V. Switching characteristics are measured using both V

4

Propagation delay depends on the value of VDD, R

5

Valid for commands that do not activate the RDY pin.

6

RDY pin low only for Instructions 2, 3, 8, 9, 10, and the PR hardware pulse: CMD_2, 3 ~ 20 µs; CMD_8 ~ 1 µs; CMD_9, 10 ~ 0.12 µs. Device operation at TA = −40°C and

V

< 3 V extends the EEMEM store time to 35 ms.

DD

7

Endurance is qualified to 100,000 cycles per JEDEC Standard 22, Method A117 and measured at −40°C, +25°C, and +85°C; typical endurance at +25°C is 700,000 cycles.

8

Retention lifetime equivalent at junction temperature (TJ) = 55°C per JEDEC Standard 22, Method A117. Retention lifetime based on an activation energy of 0.6 eV
derates with junction temperature, as shown in Figure 45 in the Flash/EEMEM Reliability section.

2, 3

t

10 ns

2

t

1 t

3

t

40 ns

8

t

50 ns

9

R

10

t

10 ns

12

t

4 t

13

t

0 ns

14

t

0.1 0.15 ms

15

Applies to instructions 0x2, 0x3, and 0x9 25 ms

16

RAB = 10 kΩ 140 µs

EEMEM1

RAB = 10 kΩ 140 µs

EEMEM2

t

10 ns

17

Not shown in timing diagram 50 ns

PRW

PRESP

, and CL.

PULL-UP

= 2.2 kΩ, CL < 20 pF 50 ns

P

= 2.2 kΩ, CL < 20 pF 0 ns

P

PR pulsed low to refresh wiper positions

= 3 V and VDD = 35 V.

DD

70 µs

CYC

CYC

Rev. B | Page 5 of 28

AD5231

CPHA = 1

CS

CLK

CPOL = 1

SDI

SDO

RDY

t

t

t

2

HIGH
OR LOW

t

8

B24* B23–MSB B0–LSB

t

14

*NOT DEFINED, BUT NORMALLY LSB OF CHARACTER PREVIOUSLY TRANSMITTED.

THE CPOL = 1 MICROCONTROLLER COMMAND ALIGNS THE INCOMING DATA TO THE POSITIVE EDGE OF THE CLOCK.

1

t

B23 B0

5

t

4

t

7

t

6

B23–MSB

t

10

t

B0–LSB

11

3

t

12

t

13

t

17

HIGH
OR LOW

t

9

t

15

t

16

02739-0-003

Figure 3. CPHA = 1 Timing Diagram

CPHA = 0

CLK

CPOL = 0

CS

t

1

t

2

t

B23 B0

5

t

4

t

3

t

12

t

13

t

17

t

6

B0–LSB

t

10

t

11

t

9

HIGH
OR LOW

*

t

7

t

15

t

16

02739-0-004

SDI

SDO

RDY

HIGH
OR LOW

t

14

*NOT DEFINED, BUT NORMALLY MSB OF CHARACTER PREVIOUSLY RECEIVED.

THE CPOL = 0 MICROCONTROLLER COMMAND ALIGNS THE INCOMING DATA TO THE POSITIVE EDGE OF THE CLOCK.

B23–MSB IN

t

8

B23–MSB OUT B0–LSB

Figure 4. CPHA = 0 Timing Diagram

Rev. B | Page 6 of 28

AD5231

ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted.

Table 3.

Parameters Ratings

VDD to GND –0.3 V, +7 V
VSS to GND +0.3 V, −7 V
VDD to VSS 7 V
VA, VB, VW to GND VSS − 0.3 V, VDD + 0.3 V
A–B, A–W, B–W

Intermittent1 ±20 mA
Continuous ±2 mA

Digital Input and Output Voltage to GND −0.3 V, VDD + 0.3 V
Operating Temperature Range2 −40°C to +85°C
Maximum Junction Temperature (TJ max) 150°C
Storage Temperature −65°C to +150°C
Lead Temperature, Soldering

Vapor Phase (60 s) 215°C
Infrared (15 s) 220°C

Thermal Resistance Junction-to-Ambient

θ

,TSSOP-16

JA

Thermal Resistance Junction-to-Case θJC,

TSSOP-16

Package Power Dissipation (TJ max − TA)/θJA

150°C/W

28°C/W

1

Maximum terminal current is bounded by the maximum current handling of

the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.

2

Includes programming of nonvolatile memory.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. B | Page 7 of 28

AD5231

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

16

O2

15

RDY

14

CS

13

PR

12

WP

11

V

DD

10

A

9

W

02739-0-005

CLK

SDI
SDO
GND

V

O1

SS

T

B

1

2

3

AD5231

4

TOP VIEW

5

(Not to Scale)

6

7

8

Figure 5. Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1 O1

Nonvolatile Digital Output 1. ADDR = 0x1, data bit position D0. For example, to store O1 high, the data bit

format is 0x310001.
2 CLK Serial Input Register Clock Pin. Shifts in one bit at a time on positive clock edges.
3 SDI Serial Data Input Pin. Shifts in one bit at a time on positive clock CLK edges. MSB loaded first.
4 SDO Serial Data Output Pin. Serves readback and daisy-chain functions.

Commands 9 and 10 activate the SDO output for the readback function, delayed by 24 or 25 clock pulses,

depending on the clock polarity before and after the data-word (see Figure 3, Figure 4, and Table 7).

In other commands, the SDO shifts out the previously loaded SDI bit pattern, delayed by 24 or 25 clock pulses

depending on the clock polarity (see Figure 3 and Figure 4). This previously shifted-out SDI can be used for

daisy-chaining multiple devices.

Whenever SDO is used, a pull-up resistor in the range of 1 kΩ to 10 kΩ is needed.
5 GND Ground Pin, Logic Ground Reference.
6 VSS

Negative Supply. Connect to 0 V for single-supply applications. If V

is used in dual-supply applications, it

SS

must be able to sink 40 mA for 25 ms when storing data to EEMEM.
7 T Reserved for factory testing. Connect to VDD or VSS.
8 B Terminal B of RDAC.
9 W Wiper Terminal of RDAC. ADDR (RDAC) = 0x0.
10 A Terminal A of RDAC.
11 VDD Positive Power Supply Pin.
12

WP Optional Write Protect Pin. When active low, WP prevents any changes to the present contents, except PR and

Instructions 1 and 8 and refreshes the RDAC register from EEMEM. Execute a NOP instruction before returning

WP high. Tie WP to VDD, if not used.

to
13

14
15 RDY
16 O2

PR Optional Hardware Override Preset Pin. Refreshes the scratchpad register with current contents of the EEMEM

register. Factory default loads midscale 512

at the logic high transition. Tie

PR to VDD, if not used.

until EEMEM is loaded with a new value by the user. PR is activated

10

CS Serial Register Chip Select Active Low. Serial register operation takes place when CS returns to logic high.

Ready. Active-high open-drain output. Identifies completion of Instructions 2, 3, 8, 9, 10, and

Nonvolatile Digital Output 2. ADDR = 0x1, data bit position D1. For example, to store O2 high, the data bit

format is 0x310002.

PR.

Rev. B | Page 8 of 28

AD5231

TYPICAL PERFORMANCE CHARACTERISTICS

1.5

TA = +85°C

1.0

2.0
VDD = 5V, VSS = 0V

1.5

1.0

TA = –40°C

0.5

0

INL ERROR (LSB)

–0.5

–1.0

128 384 640 896

0

Figure 6. INL vs. Code, T

2.0
VDD = 5V, VSS = 0V

1.5

1.0

0.5

0

–0.5

DNL ERROR (LSB)

–1.0

–1.5

–2.0

0 256 512 768 1024128 384 640 896

Figure 7. DNL vs. Code, T

1.0
VDD = 5V, VSS = 0V

0.5

0

R-INL (LSB)

–0.5

–1.0

0 256 512 768 1024128 384 640 896

Figure 8. R-INL vs. Code, T

TA =–

40°C

256 512 768

CODE (Decimal)

= −40°C, +25°C, +85°C Overlay, RAB = 10 kΩ

A

TA = –40°C

TA = +85°C

TA = +25°C

CODE (Decimal)

= −40°C, +25°C, +85°C Overlay, RAB = 10 kΩ

A

TA = +85°C

TA = +25°C

TA = –40°C

CODE (Decimal)

= −40°C, +25°C, +85°C Overlay, RAB = 10 kΩ

A

TA = +25°C

1024

02739-0-006

02739-0-007

02739-0-008

0.5

0

R-DNL (LSB)

–0.5

–1.0

–1.5

–2.0

0 128 256 384 512 640 768 896 1024

Figure 9. R-DNL vs. Code, T

3000

2500

2000

1500

1000

500

RHEOSTAT MODE TEMPCO (ppm/°C)

0

0 256 512 768 1024128 384 640 896

100

C)

°

80

60

40

20

0

POTENTIOMETER MODE TEMPCO (ppm/

–20

0 256 512 768 1024128 384 640 896

TA = +85°C

VDD = 5.5V, VSS = 0V
T

=–40°CTO+85°C

A

Figure 10. (∆R

Figure 11. (∆V

TA = +25°C

CODE (Decimal)

= −40°C, +25°C, +85°C Overlay, RAB = 10 kΩ

A

CODE (Decimal)

)/∆T × 106

WB/RWB

VDD = 5.5V, VSS = 0V
T

= –40°CTO+85°C

A

V

= 0V

B

V

= 2.00V

A

CODE (Decimal)

)/∆T × 106

W/VW

02739-0-009

02739-0-010

02739-0-011

Rev. B | Page 9 of 28

AD5231

60

VDD = 2.7V, VSS = 0V
T

50

40

)

Ω

(

30

W

R

20

10

0

0 256 512 768 1024128 384 640 896

4

3

A)

2

µ

1

CURRENT (

= 25°C

A

CODE (Decimal)

Figure 12. Wiper On Resistance vs. Code

IDD @ VDD/VSS = 5V/0V

ISS @ VDD/VSS = 5V/0V

02739-0-012

2

0

–2

–4

f

= 44kHz, RAB = 100kΩ

–3dB

–6

GAIN (dB)

–8

–10

–12

–14

–16

f

V

= 1mV rms

A

V

DD/VSS

D = MIDSCALE

1k 10k

= 85kHz, RAB = 50kΩ

–3dB

= ±2.5V

FREQUENCY (Hz)

f

= 370kHz, RAB = 10k

–3dB

100k 1M

Figure 15. −3 dB Bandwidth vs. Resistance (Figure 32)

0.12
VDD/V

= ±2.5V

SS

V

= 1V rms

A

0.10

0.08

0.06

RAB = 10k

THD + NOISE (%)

0.04

Ω

Ω

02739-0-015

0

–1

–40 0 40 80–20 20 60 100

Figure 13. I

0.25
VDD = 5V

V

= 0V

SS

0.20

0.15

(mA)

DD

I

FULL-SCALE

0.10

0.05

0

0482 6 10 12

Figure 14. I

IDD @ VDD/VSS = 2.7V/0V

I

@ VDD/VSS = 2.7V/0V

SS

TEMPERATURE (°C)

vs. Temperature, RAB = 10 kΩ

DD

ZERO-SCALE

MIDSCALE

CLOCK FREQUENCY (MHz)

vs. Clock Frequency, RAB = 10 kΩ

DD

02739-0-013

02739-0-014

0.02

0

0.01

50kΩ

100k

Ω

0.1 1 10
FREQUENCY (kHz)

Figure 16. Total Harmonic Distortion vs. Frequency

0

CODE = 0x200

–5

–10

0x100

–15

0x80

–20

0x40

–25

–30

–35

–40

–45

–50

0x20
0x10
0x08

0x04

0x02

0x01

1k

100k10k

FREQUENCY (Hz)

GAIN (dB)

Figure 17. Gain vs. Frequency vs. Code, R

1M

= 10 kΩ (Figure 32)

AB

100

10M

02739-0-016

02739-0-017

Rev. B | Page 10 of 28

AD5231

0

CODE = 0x200

–10

0x100

0x80

–20

0x40
0x20

–30

0x10

GAIN (dB)

0x08

–40

0x04
0x02

–50

0x01

–60

1k

FREQUENCY (Hz)

Figure 18. Gain vs. Frequency vs. Code, R

100k10k

= 50 kΩ (Figure 32)

AB

1M

02739-0-018

Figure 21. Power-On Reset, V

100

0%

90

10

VDD = 5V
V

= 2.25V

A

= 0V

V

B

100 µs/DIV

V

A

V

W

EXPECTED

VALUE



MIDSCALE

= 2.25 V, VB = 0 V, Code = 1010101010B

A

0.5V/DIV

02739-0-021

0

CODE = 0x200

–10

–20

–30

GAIN (dB)

–40

–50

–60

Figure 19. Gain vs. Frequency vs. Code, R

80

70

60

50

40

PSRR (–dB)

30

20

10

0x100

0x80
0x40

0x20

0x10
0x08

0x04

0x02

0x01

1k

FREQUENCY (Hz)

RAB = 100k

RAB = 50k

= +5.0V±100mV AC

V

DD

V

= 0V, VA = 5V, VB = 0V

SS

MEASURED ATV

0

100 10k 1M1k 100k 10M

W

Ω

Ω

RAB = 10k

WITH CODE = 0x200

FREQUENCY (Hz)

100k10k

= 100 kΩ (Figure 32)

AB

Ω

Figure 20. PSRR v s. Frequency

1M

02739-0-019

02739-0-020

2.55
VDD/VSS = 5V/0V
CODE = 0x200 TO0x1FF

2.53

2.51

(V)

OUT

V

2.49

2.47

2.45

0102051525

TIME (µs)

RAB= 10k
RAB = 50k
RAB = 100k

Ω
Ω

Ω

Figure 22. Midscale Glitch Energy, Code 0x200 to 0x1FF

5V/DIV

CS

CLK

SDI

I

DD

20mA/DIV

Figure 23. I

4ms/DIV

vs. Time when Storing Data to EEMEM

DD

5V/DIV

5V/DIV

02739-0-022

02739-0-023

Rev. B | Page 11 of 28

AD5231

CS

CLK

SDI

*

I

DD

2mA/DIV

4ms/DIV

*SUPPLY CURRENT RETURNS TO MINIMUM POWER CONSUMPTION

IF INSTRUCTION 0 (NOP) IS EXECUTED IMMEDIATELY AFTER
INSTRUCTION 1 (READ EEMEM)

Figure 24. I

vs. Time when Restoring Data from EEMEM

DD

5V/DIV

5V/DIV

5V/DIV

02739-0-024

100

(mA)

WB_MAX

THEORETICAL—I

0.01

0.1

10

= 10kΩ

R

AB

1

= 50kΩ

R

AB

= 100kΩ

R

AB

CODE (Decimal)

Figure 25. I

WB_MAX

vs. Code

VA = VB = OPEN

= 25°C

T

A

896768640512384128 2560

1024

02739-0-025

Rev. B | Page 12 of 28

AD5231

V

T

TEST CIRCUITS

Figure 26 to Figure 35 define the test conditions used in the specifications.

NC

DUT
A

W

B

NC = NO CONNECT

I

W

V

MS

02739-0-026

Figure 26. Resistor Position Nonlinearity Error

(Rheostat Operation; R-INL, R-DNL)

DUT
A

V+

B

V+ =V

DD

1LSB =V+/2

W

N

V

MS

02739-0-027

OFFSET

OFFSET

GND

GND

V

IN

W

ABDUT

OFFSET BIAS

Figure 31. Noninverting Gain

A

V

IN

DUT

B

2.5V

5V

OP279

+15V

W

OP42

–15V

V

OUT

02739-0-031

V

OUT

02739-0-032

Figure 27. Potentiometer Divider Nonlinearity Error (INL, DNL)

I

W

W

=

R

[

V

–V

]

V

MS1

W

MS1

MS2

/I

W

MS2

DUT
A

B

V

W

Figure 28. Wiper Resistance

V

A

V

A

DD

V+

W

B

V

MS

V+ = VDD±1 0%
PSRR (dB) = 20 LOG

∆V

PSS (%/%) =

MS

∆V

DD

V

∆

MS

(

∆V

DD

%

%

Figure 29. Power Supply Sensitivity (PSS, PSRR)

ABDUT

OFFSET

GND

V

IN

W

OFFSET BIAS

OP279

5V

V

OUT

02739-0-030

Figure 30. Inverting Gain

02739-0-028

)

02739-0-029

Figure 32. Gain vs. Frequency

0.1V

RSW=

DUT

B

A = NC

W

I

SW

I

SW

CODE = 0X00

V

BIAS

+

–

Figure 33. Incremental On Resistance

NC

GND

NC

A

B

NC = NO CONNECT

I

CM

W

V

CM

V

DD

DUT

V

SS

Figure 34. Common-Mode Leakage Current

200µAI

O OUTPUT

PIN

C

L

50pF

200µAI

Figure 35. Load Circuit for Measuring V

OL

OH

and VOL (The diode bridge test

OH

circuit is equivalent to the application circuit with R

0.1V

VOH (MIN)
OR
V

(MAX)

OL

02739-0-033

02739-0-034

PULL-UP

02739-0-057

of 2.2 kΩ)

Rev. B | Page 13 of 28

AD5231

THEORY OF OPERATION

The AD5231 digital potentiometer is designed to operate as a
true variable resistor replacement device for analog signals that
remain within the terminal voltage range of V
The basic voltage range is limited to V

DD

< V

SS

− VSS < 5.5 V. The
digital potentiometer wiper position is determined by the
RDAC register contents.

The RDAC register acts as a scratchpad register, allowing as
many value changes as necessary to place the potentiometer
wiper in the correct position. The scratchpad register can be
programmed with any position value using the standard SPI
serial interface mode by loading the complete representative
data-word. Once a desirable position is found, this value can be
stored in an EEMEM register. Thereafter, the wiper position is
always restored to that position for subsequent power-up.

The storing of EEMEM data takes approximately 25 ms; during
this time, the shift register is locked, preventing any changes
from taking place. The RDY pin pulses low to indicate the
completion of this EEMEM storage.

The following instructions facilitate the user’s programming
needs (see Table 7 for details):

0. Do nothing.

1. Restore EEMEM content to RDAC.

2. Store RDAC setting to EEMEM.

3. Store RDAC setting or user data to EEMEM.

4. Decrement 6 dB.

5. Decrement 6 dB.

6. Decrement one step.

TERM

< VDD.

SCRATCHPAD AND EEMEM PROGRAMMING

The scratchpad RDAC register directly controls the position of
the digital potentiometer wiper. For example, when the scratch­pad register is loaded with all zeros, the wiper is connected to
Terminal B of the variable resistor. The scratchpad register is a
standard logic register with no restriction on the number of
changes allowed, but the EEMEM registers have a program
erase/write cycle limitation (see the Flash/EEMEM Reliability
section).

BASIC OPERATION

The basic mode of setting the variable resistor wiper position
(programming the scratchpad register) is accomplished by load­ing the serial data input register with Instruction 11 (0xB),
Address 0, and the desired wiper position data. When the
proper wiper position is determined, the user can load the serial
data input register with Instruction 2 (0x2), which stores the
wiper position data in the EEMEM register. After 25 ms, the
wiper position is permanently stored in the nonvolatile mem­ory. Table 5 provides a programming example listing the
sequence of serial data input (SDI) words with the serial data
output appearing at the SDO pin in hexadecimal format.

Table 5. Set and Store RDAC Data to EEMEM Register

SDI SDO Action

0xB00100 0xXXXXXX

0x20XXXX 0xB00100

At system power-on, the scratchpad register is automatically
refreshed with the value previously stored in the EEMEM
register. The factory-preset EEMEM value is midscale, but
it can be changed by the user thereafter.

Writes data 0x100 to the RDAC
register, Wiper W moves to 1/4
full-scale position.

Stores RDAC register content into
the EEMEM register.

7. Decrement one step.

8. Reset EEMEM content to RDAC.

9. Read EEMEM content from SDO.

10. Read RDAC wiper setting from SDO.

11. Write d ata t o RDAC .

12. Increment 6 dB.

13. Increment 6 dB.

14. Increment one step.

15. Increment one step.

During operation, the scratchpad (RDAC) register can be
refreshed with the EEMEM register data with Instruction 1
(0x1) or Instruction 8 (0x8). The RDAC register can also be
refreshed with the EEMEM register data under hardware
control by pulsing the
at midscale when brought to logic zero, and then, on the posi­tive transition to logic high, it reloads the RDAC wiper register
with the contents of EEMEM.

Many additional advanced programming commands are avail­able to simplify the variable resistor adjustment process (see
Table 7). For example, the wiper position can be changed one
step at a time using the increment/decrement instruction or by
6 dB with the shift left/right instruction. Once an increment,
decrement, or shift instruction has been loaded into the shift
register, subsequent

Rev. B | Page 14 of 28

PR

pin. The PR pulse first sets the wiper

CS

strobes can repeat this command.

AD5231

K

A serial data output SDO pin is available for daisy-chaining and
for readout of the internal register contents.

EEMEM PROTECTION

The write protect (WP) pin disables any changes to the scratch­pad register contents, except for the EEMEM setting, which
can still be restored using Instruction 1, Instruction 8, and the
PR

pulse. Therefore, WP can be used to provide a hardware

WP

EEMEM protection feature. To disable
to execute a NOP instruction before returning

, it is recommended

WP

to logic

high.

DIGITAL INPUT/OUTPUT CONFIGURATION

All digital inputs are ESD protected, high input impedance that
can be driven directly from most digital sources. Active at logic

PR

low,

and WP must be tied to VDD if they are not used. No
internal pull-up resistors are present on any digital input pins.
The SDO and RDY pins are open-drain digital outputs that
need pull-up resistors only if these functions are used. A resistor
value in the range of 1 kΩ to 10 kΩ is a proper choice that
balances the dissipation and switching speed.

The equivalent serial data input and output logic is shown in
Figure 36. The open-drain output SDO is disabled whenever

CS

chip-select
inputs is shown in Figure 37 and Figure 38.

CL

CS

SDI

is in logic high. ESD protection of the digital

PR WP

VALID

COMMAND

COUNTER

Figure 36. Equivalent Digital Input-Output Logic

COMMAND

PROCESSOR

AND ADDRESS

DECODE

SERIAL

REGISTER

AD5231

5V

R

PULL-UP

SDO

GND

V

DD

02739-0-035

V

DD

INPUT

Ω

WP

Figure 38. Equivalent

300

GND

WP

Input Protection

02739-0-037

SERIAL DATA INTERFACE

The AD5231 contains a 4-wire SPI-compatible digital interface

CS

(SDI, SDO,
loaded MSB first. The format of the SPI-compatible word is
shown in Table 6. The chip-select
the complete data-word is loaded into the SDI pin. When
returns high, the serial data-word is decoded according to the
instructions in Table 7. The command bits (Cx) control the
operation of the digital potentiometer. The address bits (Ax)
determine which register is activated. The data bits (Dx) are the
values that are loaded into the decoded register.

The AD5231 has an internal counter that counts a multiple of
24 bits (a frame) for proper operation. For example, AD5231
works with a 48-bit word, but it cannot work properly with a
23-bit or 25-bit word. In addition, AD5231 has a subtle feature
that, if
previous command (except during power-up). As a result, care
must be taken to ensure that no excessive noise exists in the
CLK or
(ENOB) pattern. Also, to prevent data from mislocking (due
to noise, for example), the counter resets if the count is not a
multiple of four when

The SPI interface can be used in two slave modes: CPHA = 1,
CPOL = 1 and CPHA = 0, CPOL = 0. CPHA and CPOL refer to
the control bits that dictate SPI timing in the following Micro­Converters and microprocessors: ADuC812/ADuC824,
M68HC11, and MC68HC16R1/916R1.

, and CLK). It uses a 24-bit serial data-word

CS

pin must be held low until

CS

is pulsed without CLK and SDI, the part repeats the

CS

line that might alter the effective number of bits

CS

goes high.

CS

DAISY-CHAIN OPERATION

INPUT

300

LOGIC

PINS

Figure 37. Equivalent ESD Digital Input Protection

Ω

GND

02739-0-036

Rev. B | Page 15 of 28

The serial data output pin (SDO) serves two purposes. It can be
used to read the contents of the wiper setting and EEMEM
values using Instructions 10 and 9, respectively. The remaining
instructions (0 to 8, 11 to 15) are valid for daisy-chaining
multiple devices in simultaneous operations. Daisy-chaining
minimizes the number of port pins required from the
controlling IC (Figure 39). The SDO pin contains an
open-drain N-Ch FET that requires a pull-up resistor if this
function is used. As shown in Figure 39, users need to tie the
SDO pin of one package to the SDI pin of the next package.

AD5231

Users might need to increase the clock period, because the
pull-up resistor and the capacitive loading at the SDO to SDI
interface might require additional time delay between sub­sequent packages. When two AD5231s are daisy-chained, 48 bits
of data are required. The first 24 bits go to U2 and the second
24 bits go to U1. The
clocked into their respective serial registers. The
pulled high to complete the operation.

µ

C

SDI SDO

CS

should be kept low until all 48 bits are

CS

+V

AD5231 AD5231

U1 U2

CS

CLK

R

P

2k

Ω

SDI SDO

CS

is then

CLK

POWER-UP SEQUENCE

Because there are diodes to limit the voltage compliance at
Terminals A, B, and W (Figure 40), it is important to power

first before applying any voltage to Terminals A, B, and

V

DD/VSS

W. Otherwise, the diode is forward-biased such that V
powered unintentionally and might affect the rest of the user’s
circuit. The ideal power-up sequence is GND, V
inputs, and V

A/VB/VW

. The order of powering VA, VB, VW, and

, VSS, digital

DD

digital inputs is not important as long as they are powered after

.

V

DD/VSS

Regardless of the power-up sequence and the ramp rates of the
power supplies, once V

are powered, the power-on preset

DD/VSS

remains effective, which restores the EEMEM value to the
RDAC register.

DD/VSS

are

02739-0-038

Figure 39. Daisy-Chain Configuration Using SDO

TERMINAL VOLTAGE OPERATION RANGE

The AD5231’s positive VDD and negative VSS power supplies
define the boundary conditions for proper 3-terminal digital
potentiometer operation. Supply signals present on Terminals A,
B, and W that exceed V
forward-biased diodes (see Figure 40).

The ground pin of the AD5231 device is primarily used as a
digital ground reference, which needs to be tied to the PCB’s
common ground. The digital input control signals to the
AD5231 must be referenced to the device ground pin (GND)
and satisfy the logic level defined in the Specifications section.
An internal level-shift circuit ensures that the common-mode
voltage range of the three terminals extends from V
regardless of the digital input level.

or VSS are clamped by the internal

DD

to VDD,

SS

V

DD

A

W

LATCHED DIGITAL OUTPUTS

A pair of digital outputs, O1 and O2, is available on the AD5231.
These outputs provide a nonvolatile Logic 0 or Logic 1 setting.
O1 and O2 are standard CMOS logic outputs, shown in
Figure 41. These outputs are ideal to replace the functions often
provided by DIP switches. In addition, they can be used to drive
other standard CMOS logic-controlled parts that need an occa­sional setting change. Pins O1 and O2 default to Logic 1, and
they can drive up to 50 mA of load at 5 V/25°C.

V

DD

OUTPUTS

O1 AND O2
PINS

GND

Figure 41. Logic Outputs O1 and O2

02739-0-040

B

V

02739-0-039

SS

Figure 40. Maximum Terminal Voltages Set by V

and V

DD

SS

Rev. B | Page 16 of 28

AD5231

In Table 6, command bits are C0 to C3, address bits are A3 to A0, Data Bits D0 to D9 are applicable to RDAC, and D0 to D15 are
applicable to EEMEM.

Table 6. AD5231 24-Bit Serial Data-Word

MSB Command Byte 0 Data Byte 1 Data Byte 0 LSB

RDAC C3 C2 C1 C0 0 0 0 0 X X X X X X D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
EEMEM C3 C2 C1 C0 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Command instruction codes are defined in Table 7.

Table 7. Command/Operation Truth Table

Command Byte 0 Data Byte 1 Data Byte 0

Instruction
Number

B23 B16 B15 B8 B7 B0

C3 C2 C1 C0 A3 A2 A1 A0 X … D9 D8 D7 … D0

0 0 0 0 0 X X X X X … X X X … X NOP: Do nothing. See Table 15.
1 0 0 0 1 0 0 0 0 X … X X X … X Restore EEMEM(0) contents to RDAC register.

2 0 0 1 0 0 0 0 0 X … X X X … X Store Wiper Setting: Store RDAC setting to

34 0 0 1 1 A3 A2 A1 A0 D15 … D8 D7 … D0 Store contents of Data Bytes 0 and 1 (total 16

45 0 1 0 0 0 0 0 0 X … X X X … X Decrement RDAC by 6 dB.
55
65
75

0 1 0 1 X X X X X … X X X … X Same as Instruction 4.
0 1 1 0 0 0 0 0 X … X X X … X Decrement RDAC by 1 position.
0 1 1 1 X X X X X … X X X … X Same as Instruction 6.

8 1 0 0 0 X X X X X … X X X … X Reset: Restore RDAC with EEMEM (0) value.
9 1 0 0 1 A3 A2 A1 A0 X … X X X … X Read EEMEM (ADDR 0 to ADDR 15) from SDO

10 1 0 1 0 0 0 0 0 X … X X X … X Read RDAC wiper setting from SDO output in

11 1 0 1 1 0 0 0 0 X … D9 D8 D7 … D0 Write contents of Data Bytes 0 and 1 (total 10

125
135
145
155

1 1 0 0 0 0 0 0 X … X X X … X Increment RDAC by 6 dB. See Table 16.
1 1 0 1 X X X X X … X X X … X Same as Instruction 12.
1 1 1 0 0 0 0 0 X … X X X … X Increment RDAC by 1 position. See Table 14.
1 1 1 1 X X X X X … X X X … X Same as Instruction 14.

1

The SDO output shifts out the last 24 bits of data clocked into the serial register for daisy-chain operation. Exception: for any instruction following Instruction 9 or

Instruction 10, the selected internal register data is present in Data Bytes 0 and 1. The instruction following 9 and 10 must also be a full 24-bit data-word to completely
clock out the contents of the serial register.

2

The RDAC register is a volatile scratchpad register that is refreshed at power-on from the corresponding nonvolatile EEMEM register.

3

Execution of these operations takes place when the CS strobe returns to logic high.

4

Instruction 3 writes two data bytes (16 bits of data) to EEMEM. In the case of 0 addresses, only the last 10 bits are valid for wiper position setting.

5

The increment, decrement, and shift instructions ignore the contents of the shift register Data Bytes 0 and 1.

1, 2, 3

Operation

This command leaves the device in the read
program power state. To return the part to the
idle state, perform NOP instruction 0. See
Table 15.

EEMEM(0). See Table 14.

bits) to EEMEM (ADDR 1to ADDR 15). See
Table 17.

output in the next frame. See Table 18.

the next frame. See Table 19.

bits) to RDAC. See Table 13.

Rev. B | Page 17 of 28

AD5231

ADVANCED CONTROL MODES

The AD5231 digital potentiometer includes a set of user
programming features to address the wide number of applica­tions for these universal adjustment devices.

Key programming features include:

• Scratchpad programming to any desirable values

• Nonvolatile memory storage of the scratchpad RDAC register

value in the EEMEM register

• Increment and decrement instructions for the RDAC wiper

register

• Left and right bit shift of the RDAC wiper register to achieve

±6 dB level changes

• 28 extra bytes of user-addressable nonvolatile memory

Linear Increment and Decrement Instructions

The increment and decrement instructions (14, 15, 6, and 7) are
useful for linear step-adjustment applications. These commands
simplify microcontroller software coding by allowing the
controller to send just an increment or decrement command to
the device.

For an increment command, executing Instruction 14 with the
proper address automatically moves the wiper to the next
resistance segment position. Instruction 15 performs the same
function, except that the address does not need to be specified.

Logarithmic Taper Mode Adjustment

Four programming instructions produce logarithmic taper
increment and decrement of the wiper. These settings are acti­vated by the 6 dB increment and 6 dB decrement instructions
(12, 13, 4, and 5). For example, starting at zero scale, executing
the increment Instruction 12 eleven times moves the wiper in
6 dB per step from 0% to full scale, R
instruction doubles the value of the RDAC register contents
each time the command is executed. When the wiper position is
near the maximum setting, the last 6 dB increment instruction
causes the wiper to go to the full-scale 1023 code position.
Further 6 dB per increment instructions do not change the
wiper position beyond its full scale.

. The 6 dB increment

AB

than or equal to midscale and the data is shifted left, then the
data in the RDAC register is automatically set to full scale. This
makes the left-shift function as ideal a logarithmic adjustment
as possible.

The right-shift 4 and 5 instructions are ideal only if the LSB is 0
(ideal logarithmic = no error). If the LSB is 1, the right-shift
function generates a linear half-LSB error, which translates to a
number-of-bits dependent logarithmic error, as shown in Figure 42.
The plot shows the error of the odd numbers of bits for the
AD5231.

Table 8. Detail Left-Shift and Right-Shift Functions
for 6 dB Step Increment and Decrement

Left-Shift Right-Shift

00 0000 0000 11 1111 1111
00 0000 0001 01 1111 1111
00 0000 0010 00 1111 1111
00 0000 0100 00 0111 1111

Left-Shift
(+6 dB/Step)

00 0000 1000 00 0011 1111
00 0001 0000 00 0001 1111
00 0010 0000 00 0000 1111
00 0100 0000 00 0000 0111

Right-Shift

(–6 dB/Step)

00 1000 0000 00 0000 0011
01 0000 0000 00 0000 0001
10 0000 0000 00 0000 0000
11 1111 1111 00 0000 0000
11 1111 1111 00 0000 0000

Actual conformance to a logarithmic curve between the data
contents in the RDAC register and the wiper position for each
right-shift 4 and 5 command execution contains an error only
for odd numbers of bits. Even numbers of bits are ideal. The
graph in Figure 42 shows plots of Log_Error [20 × log

10

(error/code)] for the AD5231. For example, Code 3 Log_Error =
20 × log

(0.5/3) = −15.56 dB, which is the worst case. The plot

10

of Log_Error is more significant at the lower codes.

0

–20

–40

dB

The 6 dB step increments and 6 dB step decrements are
achieved by shifting the bit internally to the left or right,
respectively. The following information explains the nonideal
±6 dB step adjustment under certain conditions. Table 8
illustrates the operation of the shifting function on the RDAC
register data bits. Each table row represents a successive shift
operation. Note that the left-shift 12 and 13 instructions were
modified such that, if the data in the RDAC register is equal to
zero and the data is shifted left, the RDAC register is then set to
Code 1. Similarly, if the data in the RDAC register is greater

Rev. B | Page 18 of 28

–60

–80

0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1

0

CODE (From 1 to 1023 by 2.0 × 103)

Figure 42. Plot of Log_Error Conformance for Odd Numbers of Bits Only

(Even Numbers of Bits Are Ideal)

02739-0-041

AD5231

Using Additional Internal Nonvolatile EEMEM

The AD5231 contains additional user EEMEM registers for
storing any 16-bit data such as memory data for other compo­nents, look-up tables, or system identification information.
Table 9 provides an address map of the internal storage registers
shown in the functional block diagram as EEMEM1, EEMEM2,
and 28 bytes (14 addresses × 2 bytes each) of user EEMEM.

Table 9. EEMEM Address Map

Address EEMEM for…

0000 RDAC

1, 2

0001 O1 and O23
0010 USER14
0011 USER2
… …
1110 USER13
1111 USER14

1

RDAC data stored in EEMEM location is transferred to the RDAC register at
power-on, or when Instruction 1, Instruction 8, and

2

Execution of Instruction 1 leaves the device in the read mode power con­sumption state. After the last Instruction 1 is executed, the user should per­form a NOP, Instruction 0 to return the device to the low power idling state.

3

O1 and O2 data stored in EEMEM locations is transferred to the correspond-

ing digital register at power-on, or when Instructions 1 and 8 are executed.

4

USERx are internal nonvolatile EEMEM registers available to store 16-bit

information using Instruction 3 and restore the contents using Instruction 9.

are executed.

PR

RDAC STRUCTURE

The patent-pending RDAC contains multiple strings of equal
resistor segments with an array of analog switches that act as
the wiper connection. The number of positions is the resolution
of the device. The AD5231 has 1024 connection points, allowing
it to provide better than 0.1% settability resolution. Figure 43
shows an equivalent structure of the connections among the
three terminals of the RDAC. The SW
while the switches SW(0) to SW(2
depending on the resistance position decoded from the data
bits. Because the switch is not ideal, there is a 15 Ω wiper resis­tance, R

. Wiper resistance is a function of supply voltage and

W

temperature. The lower the supply voltage or the higher the
temperature, the higher the resulting wiper resistance. Users
should be aware of the wiper resistance dynamics if accurate
prediction of the output resistance is needed.

and SWB are always on,

A

N

−1) are on one at a time,

SW

A

A

N

SW(2

1)

–

RDAC

WIPER

REGISTER

AND

DECODER

RS= RAB/2
DIGITAL

CIRCUITRY
OMITTED FOR
CLARITY

N

R

S

SW(2

SW

R

S

R

S

SW

SW

W

N

2)

–

(1)

(0)

B

B

02739-0-042

Figure 43. Equivalent RDAC Structure (Patent Pending)

Table 10. Nominal Individual Segment Resistor (RS)

Device
Resolution

10 kΩ
Version

50 kΩ
Version

100 kΩ
Version

10-Bit 9.8 Ω 48.8 Ω 97.6 Ω

PROGRAMMING THE VARIABLE RESISTOR

Rheostat Operation

The nominal resistance of the RDAC between Terminals A
and B, R
1024 positions (10-bit resolution). The final digit(s) of the part
number determine the nominal resistance value, for example,
10 kΩ = 10; 50 kΩ = 50; 100 kΩ = C.

The 10-bit data-word in the RDAC latch is decoded to select
one of the 1024 possible settings. The following discussion
describes the calculation of resistance R
10 kΩ part. For V
Terminal B for data 0x000. R
resistance, and because it is independent of the nominal resis­tance. The second connection is the first tap point where
R

WB

third connection is the next tap point representing R

19.4 Ω + 15 Ω = 34.4 Ω for data 0x002 and so on. Each LSB data
value increase moves the wiper up the resistor ladder until the
last tap point is reached at R
for a simplified diagram of the equivalent RDAC circuit. When
R

WB

, is available with 10 kΩ, 50 kΩ, and 100 kΩ with

AB

at different codes of a

WB

= 5 V, the wiper’s first connection starts at

DD

(0) is 15 Ω because of the wiper

WB

(1) becomes 9.7 Ω + 15 Ω = 24.7 Ω for data 0x001. The

(2) =

WB

(1023) = 10005 Ω. See Figure 43

WB

is used, Terminal A can be left floating or tied to the wiper.

Rev. B | Page 19 of 28

AD5231

−

100

R

)

AB

75

50

(D) (% of Nominal R

WB

25

(D), R

WA

R

0

WA

0 1023256

Figure 44. R

512 768

CODE (Decimal)

(D) and RWB(D) vs. Decimal Code

WA

The general equation that determines the programmed output
resistance between W and B is

WB

1024

D

DR +×=

)( (1)

RR

W

AB

R

WB

02739-0-043

The general transfer equation for this operation is

D

WB

1024

1024

DR +×

=

)( (2)

RR

W

AB

For example, the output resistance values in Table 12 are set for
the RDAC latch codes with V

= 5 V (applies to RAB = 10 kΩ

DD

digital potentiometers).

Table 12. RWA(D) at Selected Codes for R

= 10 kΩ

AB

D (DEC) RWA(D) (Ω) Output State

1023 24.7 Full scale
512 5015 Midscale
1 10005 1 LSB
0 10,015 Zero scale

The typical distribution of RAB from device to device matches
tightly when they are processed in the same batch. When
devices are processed at a different time, device-to-device
matching becomes process-lot dependent and exhibits a −40%
to +20% variation. The change in R

with temperature has a

AB

600 ppm/°C temperature coefficient.

where:

D is the decimal equivalent of the data contained in the RDAC

register.

R

is the nominal resistance between Terminals A and B.

AB

R

is the wiper resistance.

W

For example, the output resistance values in Table 11 are set for
the given RDAC latch codes with V

= 5 V (applies to RAB =

DD

10 kΩ digital potentiometers).

Table 11. RWB (D) at Selected Codes for RAB = 10 kΩ

D (DEC) RWB(D) (Ω) Output State

1023 10,005 Full scale
512 50015 Midscale
1 24.7 1 LSB
0 15 Zero scale (wiper contact resistor)

Note that, in the zero-scale condition, a finite wiper resistance
of 15 Ω is present. Care should be taken to limit the current
flow between W and B in this state to no more than 20 mA to
avoid degradation or possible destruction of the internal
switches.

Like the mechanical potentiometer that the RDAC replaces, the
AD5231 part is totally symmetrical. The resistance between
Wiper W and Terminal A also produces a digitally controlled
complementary resistance, R

. Figure 44 shows the symmetri-

WA

cal programmability of the various terminal connections. When
RWA is used, Terminal B can be left floating or tied to the wiper.
Setting the resistance value for R

starts at a maximum value

WA

of resistance and decreases as the data loaded in the latch is
increased in value.

PROGRAMMING THE POTENTIOMETER DIVIDER

Voltage Output Operation

The digital potentiometer can be configured to generate an
output voltage at the wiper terminal that is proportional to the
input voltages applied to Terminals A and B. For example,
connecting Terminal A to 5 V and Terminal B to ground
produces an output voltage at the wiper that can be any value
from 0 V to 5 V. Each LSB of voltage is equal to the voltage
applied across Terminal AB divided by the 2
tion of the potentiometer divider.

Because AD5231 can also be supplied by dual supplies, the
general equation defining the output voltage at V
to ground for any given input voltages applied to Terminals A
and B is

W

1024

D

DV +×=

)( (3)

Equation 3 assumes that V

VV

B

AB

is buffered so that the effect of

W

wiper resistance is minimized. Operation of the digital poten­tiometer in divider mode results in more accurate operation
over temperature. Here, the output voltage is dependent on
the ratio of the internal resistors and not the absolute value;
therefore, the drift improves to 15 ppm/°C. There is no voltage
polarity restriction between Terminals A, B, and W as long as
the terminal voltage (V

) stays within VSS < V

TERM

N

position resolu-

with respect

W

< VDD.

TERM

Rev. B | Page 20 of 28

AD5231

PROGRAMMING EXAMPLES

The following programming examples illustrate a typical
sequence of events for various features of the AD5231. See
Table 7 for the instructions and data-word format. The
instruction numbers, addresses, and data appearing at SDI
and SDO pins are in hexadecimal format.

Table 13. Scratchpad Programming

SDI SDO Action

0xB00100 0xXXXXXX

Table 14. Incrementing RDAC Followed by Storing the
Wiper Setting to EEMEM

SDI SDO Action

0xB00100 0xXXXXXX

0xE0XXXX 0xB00100

0xE0XXXX 0xE0XXXX

0x20XXXX 0xXXXXXX

The EEMEM value for the RDAC can be restored by power-on,
by strobing the

PR

Table 15.

Table 15. Restoring the EEMEM Value to the RDAC Register

SDI SDO Action

0x10XXXX 0xXXXXXX

0x00XXXX 0x10XXXX

Table 16. Using Left-Shift by One to Increment 6 dB Step

SDI SDO Action

0xC0XXXX 0xXXXXXX

Table 17. Storing Additional User Data in EEMEM

SDI SDO Action

0x32AAAA 0xXXXXXX

0x335555 0x32AAAA

Writes data 0x100 into RDAC register,
Wiper W moves to 1/4 full-scale
position.

Writes data 0x100 into RDAC register,
Wiper W moves to 1/4 full-scale
position.

Increments RDAC register by one to
0x101.

Increments RDAC register by one to
0x102. Continue until desired wiper
position is reached.

Stores RDAC register data into EE­MEM(0). Optionally tie
protect EEMEM values.

WP to GND to

pin, or by programming, as shown in

Restores the EEMEM(0) value to the
RDAC register.

NOP. Recommended step to minimize
power consumption.

Moves the wiper to double the pre­sent data contained in the RDAC
register.

Stores data 0xAAAA in the extra EE­MEM location USER1. (Allowable to
address in 14 locations with a maxi­mum of 16 bits of data.)

Stores data 0x5555 in the extra EE­MEM location USER2. (Allowable to
address in 14 locations with a maxi­mum of 16 bits of data.)

Table 18. Reading Back Data from Memory Locations

SDI SDO Action

0x92XXXX 0xXXXXXX

0x00XXXX 0x92AAAA

Prepares data read from EEMEM(2)
location.

NOP Instruction 0 sends a 24-bit word
out of SDO, where the last 16 bits
contain the contents in the EEMEM(2)
location. The NOP command ensures
that the device returns to the idle
power dissipation state.

Table 19. Reading Back Wiper Settings

SDI SDO Action

0xB00200 0xXXXXXX Writes RDAC to midscale.
0xC0XXXX 0xB00200

0xA0XXXX 0xC0XXXX

0xXXXXXX 0xA003FF Reads back full-scale value from SDO.

Doubles RDAC from midscale to full
scale (left-shift instruction).

Prepares reading wiper setting from
RDAC register.

FLASH/EEMEM RELIABILITY

The Flash/EE memory array on the AD5231 is fully qualified
for two key Flash/EE memory characteristics, namely Flash/EE
memory cycling endurance and Flash/EE memory data
retention.

Endurance quantifies the ability of the Flash/EE memory to be
cycled through many program, read, and erase cycles. In real
terms, a single endurance cycle is composed of four
independent, sequential events. These events are defined as

•

Initial page erase sequence
Read/verify sequence

•

Byte program sequence

•

•

Second read/verify sequence

During reliability qualification, Flash/EE memory is cycled
from 0x000 to 0x3FF until a first fail is recorded signifying the
endurance limit of the on-chip Flash/EE memory.

As indicated in the Specifications section, the AD5231 Flash/EE
memory endurance qualification has been carried out in
accordance with JEDEC Specification A117 over the industrial
temperature range of −40°C to +85°C. The results allow the
specification of a minimum endurance figure over supply and
temperature of 100,000 cycles, with an endurance figure of
700,000 cycles being typical of operation at 25°C.

Retention quantifies the ability of the Flash/EE memory to
retain its programmed data over time. Again, the AD5231 has
been qualified in accordance with the formal JEDEC Retention
Lifetime Specification (A117) at a specific junction temperature
(T

= 55°C). As part of this qualification procedure, the Flash/EE

J

Rev. B | Page 21 of 28

AD5231

memory is cycled to its specified endurance limit, described
previously, before data retention is characterized. This means
that the Flash/EE memory is guaranteed to retain its data
for its full specified retention lifetime every time the Flash/EE
memory is reprogrammed. It should also be noted that reten­tion lifetime, based on an activation energy of 0.6 eV, derates
with T

, as shown in Figure 45. For example, the data is retained

J

for 100 years at 55°C operation but reduces to 15 years at 85°C
operation. Beyond these limits, the part must be reprogrammed
so that the data can be restored.

300

250

200

150

100

RETENTION (Years)

50

0

40

ADI TYPICAL
PERFORMANCE
AT TJ = 55°C

50 60 70 80 90 100 110

TJ JUNCTION TEMPERATURE (°C)

02739-0-044

Figure 45. Flash/EE Memory Data Retention

Rev. B | Page 22 of 28

AD5231

V

APPLICATIONS

BIPOLAR OPERATION FROM DUAL SUPPLIES

The AD5231 can be operated from dual supplies ±2.5 V, which
enables control of ground referenced ac signals or bipolar
operation. AC signals as high as V

can be applied directly

DD/VSS

across Terminals A to B with output taken from Terminal W.
See Figure 46 for a typical circuit connection.

+2.5V

V

SS

DD

SCLK

µ

C

MOSI

GND

CS
CLK
SDI

GND

AD5231

Figure 46. Bipolar Operation from Dual Supplies

V

DD

A

±

±

1.25V p-p

W

B

V

SS

2.5V p-p

D = MIDSCALE

–2.5V

HIGH VOLTAGE OPERATION

The digital potentiometer can be placed directly in the feedback
or input path of an op amp for gain control, provided that the
voltage across Terminals A-B, W-A, or W-B does not exceed
|5 V|. When high voltage gain is needed, users should set a fixed
gain in an op amp operated at a higher voltage and let the
digital potentiometer control the adjustable input. Figure 47
shows a simple implementation.

R2R

C

C

2.2pF

15V

5V

A

AD5231

W

B

Figure 47. 15 V Voltage Span Control

–

V+

A1

V–

+

0VTO15V

V

O

02739-0-046

BIPOLAR PROGRAMMABLE GAIN AMPLIFIER

There are several ways to achieve bipolar gain. Figure 48 shows
one versatile implementation. Digital potentiometer U1 sets the
adjustment range; the wiper voltage V
grammed between V

and −KVi at a given U2 setting. For linear

i

adjustment, configure A2 as a noninverting amplifier and the
transfer function becomes

V

O

V

I

R2

⎛

+= KK

1 (4)

⎜

R1

⎝

D2

⎞

⎛

⎟

⎜

1024

⎠

⎝

can, therefore, be pro-

W2

⎞

−+××

)1(

⎟
⎠

02739-0-045

where:

K is the ratio of R

that is set by U1.

WB/RWA

D is the decimal equivalent of the input code.

V

DD

i

AD5231

AD5231

U2

W

A

B

B

A

W

V

DD

U1

V+

OP2177

V–

A

V

SS

–kVi

V+

OP2177

V–

A2

V

O

C

R2

V

SS

R1

C

2.2pF

02739-0-047

Figure 48. Bipolar Programmable Gain Amplifier

In the simpler (and much more usual) case where K = 1,
a pair of matched resistors can replace U1. Equation 4 can be
simplified to

2

V

O

V

I

R2

⎛

1

+= 1

⎜

R1

⎝

D

⎞

⎛

⎟

⎜

1024

⎠

⎝

⎞

2

−×

(5)

⎟
⎠

Table 20 shows the result of adjusting D with A2 configured as a
unity gain, a gain of 2, and a gain of 10. The result is a bipolar
amplifier with linearly programmable gain and 1024-step
resolution.

Table 20. Result of Bipolar Gain Amplifier

D R1 = ∞, R2 = 0 R1 = R2 R2 = 9 × R1

0 −1 −2 −10
256 −0.5 −1 −5
512 0 0 0
768 0.5 1 5
1023 0.992 1.984 9.92

10-BIT BIPOLAR DAC

If the circuit in Figure 48 is changed with the input taken from a
voltage reference and A2 configured as a buffer, a 10-bit bipolar
DAC can be realized. Compared to the conventional DAC, this
circuit offers comparable resolution but not the precision
because of the wiper resistance effects. Degradation of the
nonlinearity and temperature coefficient is prominent near
both ends of the adjustment range. On the other hand, this
circuit offers a unique nonvolatile memory feature that in some
cases outweighs any shortfall in precision.

Rev. B | Page 23 of 28

AD5231

×

The output of this circuit is

D

2

⎛

V ×

⎜

O

1024

⎝

+5V

V

V

OUT

IN

+2.5VREF

TRIM

GND

ADR421

10-BIT UNIPOLAR DAC

Figure 50 shows a unipolar 10-bit DAC using AD5231. The
buffer is needed to drive various leads.

5V

1

V

GND

2

PROGRAMMABLE VOLTAGE SOURCE WITH BOOSTED OUTPUT

For applications that require high current adjustment, such as a
laser diode driver or tunable laser, a boosted voltage source can
be considered (see Figure 51).

V

IN

A

B

Figure 51. Programmable Booster Voltage Source

⎞

2

V

−= 1

(6)

⎟

REF

⎠

AD5231

U1

W
B

A

RR

+5V

V+

AD8552

V–

A1

–5V

Figure 49. 10-Bit Bipolar DAC

AD5231

U1

3

V

IN

OUT

AD1582

A

W

B

Figure 50. 10-Bit Unipolar DAC

AD5231

U2

W

AD8601

2N7002

V+

V–

V+

AD8601

V–

A1

–2.5VREF

5V

AD8552

SIGNAL

+5V

V+

V–

A2

–5V

V

C

C

LD

O

02739-0-049

V

R

BIAS

I

OUT

L

V

O

02739-0-058

02739-0-048

For precision applications, a voltage reference such as ADR421,
ADR03, or ADR370 can be applied at Terminal A of the digital
potentiometer.

PROGRAMMABLE CURRENT SOURCE

A programmable current source can be implemented with the
circuit shown in Figure 52.

+5V

2

U1

VIN

3

SLEEP

REF191

GND

4

AD5231

–2.048V TO V

Figure 52. Programmable Current Source

REF191 is a unique low supply, headroom precision reference
that can deliver the 20 mA needed at 2.048 V. The load current
is simply the voltage across Terminals B–W of the digital
potentiometer divided by R

REF

=

I (7)

L

1024×

R

S

The circuit is simple but be aware that there are two issues. First,
dual-supply op amps are ideal because the ground potential of
REF191 can swing from −2.048 V at zero scale to V
of the potentiometer setting. Although the circuit works under
single-supply, the programmable resolution of the system is
reduced. Second, the voltage compliance at V
or equivalently a 125 Ω load. Should higher voltage compliance
be needed, users can consider digital potentiometers AD5260,
AD5280, and AD7376. Figure 53 shows an alternate circuit for
high voltage compliance.

To achieve higher current, such as when driving a high power
LED, the user can replace the UI with an LDO, reduce R
add a resistor in series with the digital potentiometer’s
A terminal. This limits the potentiometer’s current and
increases the current adjustment resolution.

VOUT

L

DV

0TO (2.048 +VL)

6

C1

1

µ

F

V+

OP1177

V–

:

S

+5V

–5V

B

W

A

–

U2

+

R

S

102

Ω

V

L

R

100

L

Ω

L

I

L

at full scale

L

is limited to 2.5 V

02739-0-051

, and

S

In this circuit, the inverting input of the op amp forces the V

OUT

to be equal to the wiper voltage set by the digital potentiometer.
The load current is then delivered by the supply via the
N-Ch FET N
(V

− VO) × IL power. This circuit can source a maximum of

i

. N1 power handling must be adequate to dissipate

1

100 mA with a 5 V supply.

Rev. B | Page 24 of 28

AD5231

A

PROGRAMMABLE BIDIRECTIONAL CURRENT SOURCE

For applications that require bidirectional current control or
higher voltage compliance, a Howland current pump can be a
solution. If the resistors are matched, the load current is

()

R2BR2A

+

I ×

D5231

R1

= (8)

R2B

+2.5V

A

B

–2.5V

+

W

–

A1

Figure 53. Programmable Bidirectional Current Source

+15V

V+

OP2177

V–

–15V

V

WL

15k

+15V

–

V+

OP2177

V–

+

–15V

14.95k

R2

Ω

R2A

C1

10pF

A2

R2B
50

Ω

V

L

R

L

Ω

500

Ω

R1

150k

150k

R1

Ω

Ω

I

L

02739-0-052

RESISTANCE SCALING

AD5231 offers 10 kΩ, 50 kΩ, and 100 kΩ nominal resistance.
For users who need lower resistance but want to maintain the
number of adjustment steps, they can parallel multiple devices.
For example, Figure 54 shows a simple scheme of paralleling
two AD5231s. To adjust half the resistance linearly per step,
users need to program both devices coherently with the same
settings and tie the terminals as shown.

A1

B1

LD

Figure 54. Reduce Resistance by Half with Linear Adjustment Characteristics

In voltage diver mode, by paralleling a discrete resistor as
shown in Figure 55, a proportionately lower voltage appears at
Terminal A-to-B. This translates into a finer degree of precision,
because the step size at Terminal W is smaller. The voltage can
be found as follows:

R2R

)//(

DV ××

W

AB

=

)(

R2RR3

+

AB

W1

A2

W2

B2

02739-0-053

D

1024//

(10)

V

DD

R2B, in theory, can be made as small as necessary to achieve the
current needed within the A2 output current-driving capability.
In this circuit, OP2177 delivers ±5 mA in both directions, and
the voltage compliance approaches 15 V. It can be shown that
the output impedance is

)(

R2AR1R2BR1'

Z

=

0

Z

can be infinite if resistors R1 and R2 match precisely with R1

O

and R2A + R2B,

respectively. On the other hand, ZO can be

+

(9)

)(

R2BR2AR1'R1R2'

+−

negative if the resistors are not matched. As a result C1, in the
range of 1 pF to 10 pF, is needed to prevent oscillation from the
negative impedance.

R3

A

R1R2

W

B

02739-0-059

Figure 55. Lowering the Nominal Resistance

Figure 54 and Figure 55 show that the digital potentiometers
change steps linearly. On the other hand, pseudo log taper
adjustment is usually preferred in applications such as audio
control. Figure 56 shows another type of resistance scaling. In
this configuration, the smaller the R2 with respect to R1, the
more the pseudo log taper characteristic of the circuit behaves.

A

R1

W

B

Figure 56. Resistor Scaling with Pseudo Log Adjustment Characteristics

V

O

R2

02739-0-055

Rev. B | Page 25 of 28

AD5231

RDAC CIRCUIT SIMULATION MODEL

The internal parasitic capacitances and the external load
dominates the ac characteristics of the RDACs. The −3 dB
bandwidth of the AD5231BRU10 (10 kΩ resistor) measures
370 kHz at half scale when configured as a potentiometer
divider. Figure 15 provides the large signal BODE plot charac­teristics. A parasitic simulation mode is shown in Figure 57.

RDAC
10k

A

C

A

50pF

Figure 57. RDAC Circuit Simulation Model for RDAC = 10 kΩ

Ω

C

W

50pF

W

C

B

50pF

B

02739-0-056

The following code provides a macro model net list for the
10 kΩ RDAC:

.PARAM D = 1024, RDAC = 10E3
*
.SUBCKT DPOT (A, W, B)
*
CA A 0 50E-12
RWA A W {(1-D/1024)* RDAC + 15}
CW W 0 50E-12
RWB W B {D/1024 * RDAC + 15}
CB B 0 50E-12
*
.ENDS DPOT

Rev. B | Page 26 of 28

AD5231

OUTLINE DIMENSIONS

5.10

5.00

4.90

0.15

0.05

4.50

4.40

4.30

PIN 1

16

0.65

BSC

COPLANARITY

COMPLIANT TO JEDEC STANDARDS MO-153AB

0.10

0.30

0.19

9

81

1.20
MAX

SEATING
PLANE

6.40
BSC

0.20

0.09
8°

0°

0.75

0.60

0.45

Figure 58. 16-Lead Thin Shrink Small Outline Package [TSSOP]

(RU-16)

Dimensions shown in millimeters

ORDERING GUIDE

Package

Model RAB (kΩ) Temperature Range (°C)

Description

AD5231BRU10 10 −40°C to +85°C TSSOP-16 RU-16 96 5231B10
AD5231BRU10-REEL7 10 −40°C to +85°C TSSOP-16 RU-16 1,000 5231B10
AD5231BRU50 50 −40°C to +85°C TSSOP-16 RU-16 96 5231B10
AD5231BRU50-REEL7 50 −40°C to +85°C TSSOP-16 RU-16 1,000 5231B10
AD5231BRU100 100 −40°C to +85°C TSSOP-16 RU-16 96 5231B100
AD5231BRU100-REEL7 100 −40°C to +85°C TSSOP-16 RU-16 1,000 5231B100
AD5231BRUZ1002 100 −40°C to +85°C TSSOP-16 RU-16 96 5231B100
AD5231BRUZ100-REEL72 100 −40°C to +85°C TSSOP-16 RU-16 1,000 5231B100

1

Line 1 contains the model number. Line 2 contains the ADI logo followed by the end-to-end resistance value. Line 3 contains the date code, YWW or #YWW for Pb-free

parts.

2

Z = Pb-free part.

Package
Option

Ordering
Quantity Branding1

Rev. B | Page 27 of 28

AD5231

NOTES

Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent
Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.

© 2004 Analog Devices, Inc. All rights reserved. Trademarks and regis-
tered trademarks are the property of their respective owners.

C02739–0–9/04(B)

Rev. B | Page 28 of 28