Datasheet AD5227 Datasheet (Analog Devices)

64-Position Up/Down

FEATURES

64-position digital potentiometer
10 kΩ, 50 kΩ, 100 kΩ end-to-end terminal resistance
Simple up/down digital or manual configurable control
Midscale preset
Low potentiometer mode tempco = 10 ppm/°C
Low rheostat mode tempco = 35 ppm/°C
Ultralow power, I
Fast adjustment time, ts = 1 µs
Chip select enable multiple device operation
Low operating voltage, 2.7 V to 5.5 V
Automotive temperature range, −40°C to +105°C
Compact thin SOT-23-8 (2.9 mm × 3 mm) Pb-free package

APPLICATIONS

Mechanical potentiometer and trimmer replacements
LCD backlight, contrast, and brightness controls
Portable electronics level adjustment
Programmable power supply
Digital trimmer replacements
Automatic closed-loop control

GENERAL DESCRIPTION

The AD5227 is Analog Devices’ latest 64-step up/down control
digital potentiometer
adjustment function as a 5 V potentiometer or variable resistor.
Its simple 3-wire up/down interface allows manual switching or
high speed digital control. The AD5227 presets to midscale at
power-up. When

every clock pulse. The direction is determined by the state of
the U/

any host controller, discrete logic, or manually with a rotary
encoder or pushbuttons. The AD5227’s 64-step resolution, small
footprint, and simple interface enable it to replace mechanical
potentiometers and trimmers with typically 6× improved
resolution, solid-state reliability, and design layout flexibility,
resulting in a considerable cost savings in end users’ systems.

pin (see Table 1). The interface is simple to activate by

D

= 0.4 µA typ and 3 µA max

DD

1

. This device performs the same electronic

is enabled, the devices changes step at

CS

Control Digital Potentiometer

AD5227

FUNCTIONAL BLOCK DIAGRAM

V

DD

AD5227

CS

U/D

CLK

GND

6-BIT UP/DOWN

CONTROL

LOGIC

POR

MIDSCALE

Figure 1.

WIPER

REGISTER

The AD5227 is available in a compact thin SOT-23-8 (TSOT-8)
Pb-free package. The part is guaranteed to operate over the
automotive temperature range of −40°C to +105°C.

Users who consider EEMEM potentiometers should refer to
some recommendations in the Applications section.

Table 1. Truth Table

U/

CS

0
0

CLK

↓
↓

D

Operation

0 RWB Decrement
1 RWB Increment

1 X X No Operation

1

RWA increments if RWB decrements and vice versa.

A

W

B

04419-0-001

1

1

The term s digital potentiometer and RDAC are used interchangeably.

Rev. 0

Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: [phone] www.analog.com
Fax: [phone] © 2004 Analog Devices, Inc. All rights reserved.

AD5227

TABLE OF CONTENTS

Electrical Characteristics ................................................................. 3

Layout and Power Supply Biasing............................................ 11

Interface Timing Diagrams ......................................................... 4

Absolute Maximum Ratings............................................................ 5

ESD Caution.................................................................................. 5

Pin Configuration and Function Descriptions............................. 6

Typical Performance Characteristics ............................................. 7

Theory of Operation ...................................................................... 10

Programming the Digital Potentiometers............................... 10

Digital Interface.......................................................................... 11

Terminal Voltage Operation Range.......................................... 11

Power-Up and Power-Down Sequences.................................. 11

REVISION HISTORY

Revision 0: Initial Version

Applications..................................................................................... 12

Manual Control with Toggle and Pushbutton Switches........ 12

Manual Control with Rotary Encoder..................................... 12

Adjustable LED Driver.............................................................. 12

Adjustable Current Source for LED Driver ............................ 12

Automatic LCD Panel Backlight Control................................ 13

6-Bit Controller .......................................................................... 13

Constant Bias with Supply to Retain Resistance Setting...... 14

Outline Dimensions....................................................................... 15

Ordering Guide .......................................................................... 15

Rev. 0 | Page 2 of 16

AD5227

ELECTRICAL CHARACTERISTICS

10 kΩ, 50 kΩ, 100 kΩ versions: VDD = 3 V ± 10% or 5 V ± 10%, VA = VDD, VB = 0 V, −40°C < TA < +105°C, unless otherwise noted.

Table 2.

Parameter Symbol Conditions Min Typ1 Max Unit

DC CHARACTERISTICS RHEOSTAT MODE

Resistor Differential Nonlinearity2 R-DNL RWB, A = no connect −0.5 ±0.15 +0.5 LSB
Resistor Integral Nonlinearity2 R-INL RWB, A = no connect −1 ±0.3 +1 LSB
Nominal Resistor Tolerance3 ∆RAB/RAB −20 +20 %
Resistance Temperature Coefficient (∆RAB/RAB)/∆T × 106 35 ppm/°C

Wiper Resistance RW V
V
DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE

Resolution N 6 Bits

Integral Nonlinearity3 INL −1 ±0.1 +1 LSB

Differential Nonlinearity

3, 4

DNL −0.5 ±0.1 +0.5 LSB
Voltage Divider Temperature Coefficient (∆VW/VW)/∆T × 106 Midscale 5 ppm/°C
Full-Scale Error V
Zero-Scale Error V

≥+31 steps from midscale −1 −0.5 0 LSB

WFSE

≤−32 steps from midscale 0 0.5 +1 LSB

WZSE

RESISTOR TERMINALS

Voltage Range5 V
Capacitance A, B6 C

With respect to GND 0 VDD V

A, B, W

A, B

Capacitance W6 CW

Common-Mode Leakage ICM V

DIGITAL INPUTS (CS, CLK, U/D)

Input Logic High VIH 2.4 5.5 V
Input Logic Low VIL 0 0.8 V
Input Current II V
Input Capacitance6 C

5 pF

I

POWER SUPPLIES

Power Supply Range VDD 2.7 5.5 V
Supply Current IDD

Power Dissipation7 P

DISS

Power Supply Sensitivity PSSR VDD = 5 V ± 10% 0.01 0.05 %/%

DYNAMIC CHARACTERISTICS6, 8, 9

Bandwidth –3 dB BW_10 k RAB = 10 kΩ, midscale 460 kHz

BW_50 k RAB = 50 kΩ, midscale 100 kHz
BW_100 k RAB = 100 kΩ, midscale 50 kHz

Total Harmonic Distortion THD

Adjustment Settling Time tS

Resistor Noise Voltage e

Footnotes on the next page.

R

N_WB

= 2.7 V 100 200 Ω

DD

= 5.5 V 50 Ω

DD

f = 1 MHz, measured to

140 pF

GND
f = 1 MHz, measured to

150 pF

GND

= VB = VW 1 nA

A

= 0 V or 5 V ±1 µA

IN

= 5 V or VIL = 0 V,

V

IH

V

= 5 V

DD

= 5 V or VIL = 0 V,

V

IH

= 5 V

V

DD

= 1 V rms, RAB = 10 kΩ,

V

A

= 0 V dc, f = 1 kHz

V

B

= 5 V ± 1 LSB error

V

A

band, V
V

= 0, measured at

B

W

= 5 kΩ, f = 1 kHz 14 nV/√Hz

WB

0.4 3 µA

17 µW

0.05 %

1 µs

Rev. 0 | Page 3 of 16

AD5227

Parameter Symbol Conditions Min Typ1 Max Unit

INTERFACE TIMING CHARACTERISTICS (applies to all parts

Clock Frequency f

CLK

Input Clock Pulse Width tCH, tCL Clock level high or low 10 ns
CS to CLK Setup Time
CS Rise to CLK Hold Time
U/D to Clock Fall Setup Time

t

CSS

t

CSH

t

UDS

1

Typicals represent average readings at 25°C, VDD = 5 V.

2

Resistor position nonlinearity error, R-INL, is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper

positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.

3

NL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.

4

DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.

5

Resistor Terminals A, B, W have no limitations on polarity with respect to each other.

6

Guaranteed by design and not subject to production test.

7

P

is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.

DISS

8

Bandwidth, noise, and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest

bandwidth. The highest R value results in the minimum overall power consumption.

9

All dynamic characteristics use VDD = V.

10

All input control voltages are specified with tR = tF = 1 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V. Switching characteristics are measured using

VDD = 5 V.

INTERFACE TIMING DIAGRAMS

CS = LOW
U/D = HIGH

6, 10

)

50 MHz

10 ns

10 ns
10 ns

CLK

R

WB

Figure 2. Increment R

CS = LOW
U/D = 0

CLK

R

WB

Figure 3. Decrement R

1

CS

0

t

CLK

U/D

R

WB

CSS

1

0

1

0

t

t

UDS

t

CL

CH

t

S

Figure 4. Detailed Timing Diagram(Only R

04419-0-004

WB

04419-0-005

WB

t

CSH

04419-0-006

Decrement Shown)

WB

Rev. 0 | Page 4 of 16

AD5227

ABSOLUTE MAXIMUM RATINGS

Table 3.

Parameter Rating

VDD to GND −0.3 V, +7 V
VA, VB, VW to GND 0 V, VDD

0 V, V

Digital Input Voltage to GND (CS, CLK, U/D)

DD

Maximum Current

IWB, IWA Pulsed ±20 mA
IWB Continuous (R

≤ 5 kΩ, A open)1 ±1 mA

WB

IWA Continuous (RWA ≤ 5 kΩ, B open)1 ±1 mA
IAB Continuous

= 10 kΩ/50 kΩ/100 kΩ)1

(R

AB

±500 µA/

±100 µA/±50 µA
Operating Temperature Range −40°C to +105°C
Maximum Junction Temperature (TJmax) 150°C
Storage Temperature −65°C to +150°C
Lead Temperature (Soldering, 10 s – 30 s) 245°C
Thermal Resistance2 θJA 230°C/W

1

Maximum terminal current is bounded by the maximum applied voltage
across any two of the A, B, and W terminals at a given resistance, the
maximum current handling of the switches, and the maximum power
dissipation of the package. VDD = 5 V.

2

Package power dissipation = (TJmax – TA) / θJA.

Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

ESD CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.

Rev. 0 | Page 5 of 16

AD5227

G

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

CLK

U/D

2

A

3
4

ND

Figure 5. SOT-23-8 Pin Configuration

Table 4. Pin Function Descriptions

Pin No. Mnemonic Description

1 CLK

Clock Input. Each clock pulse executes the step-up or step-down of the resistance. The direction is determined
by the state of the U/D

pin. CLK is a negative-edge trigger. Logic high signal can be higher than VDD, but lower

than 5.5 V.

2

U/D

Up/Down Selections. Logic 1 selects up and Logic 0 selects down. U can be higher than V
3 A Resistor Terminal A. GND ≤ VA ≤ VDD.
4 GND Common Ground.
5 W Wiper Terminal W. GND ≤ VW ≤ VDD.
6 B Resistor Terminal B. GND ≤ VB ≤ VDD.
7

CS

Chip Select. Active Low. Logic high signal can be higher than V
8 VDD Positive Power Supply, 2.7 V to 5.5 V.

AD5227

TOP VIEW

(Not to Scale)

V

8

DD

CS

7

B

6
5

W

04419-0-003

, but lower than 5.5 V.

DD

, but lower than 5.5 V.

DD

Rev. 0 | Page 6 of 16

AD5227

TYPICAL PERFORMANCE CHARACTERISTICS

0.25

0.20

0.15

0.10

0.05

0

–0.05

–0.10

RHEOSTAT MODE INL (LSB)

–0.15

–0.20

–0.25

0645648403224168

CODE (Decimal)

Figure 6. R-INL vs. Code vs. Temperature, V

0.25

0.20

0.15

0.10

0.05

0

–0.05

–0.10

RHEOSTAT MODE DNL (LSB)

–0.15

–0.20

–0.25

0645648403224168

CODE (Decimal)

Figure 7. R-DNL vs. Code vs. Temperature, V

0.25

0.20

0.15

0.10

0.05

0

–0.05

–0.10

–0.15

POTENTIOMETER MODE INL (LSB)

–0.20

–0.25

0645648403224168

CODE (Decimal)

Figure 8. INL vs. Code, V

DD

= 5 V

–40°C
+25°C
+85°C
+105°C

VDD = 5.5V

= 5 V

DD

–40°C
+25°C
+85°C
+105°C

VDD = 5.5V

= 5 V

DD

–40°C
+25°C
+85°C
+105°C

VDD = 5.5V

04419-0-007

04419-0-008

04419-0-010

0.25

0.20

0.15

0.10

0.05

0

–0.05

–0.10

–0.15

POTENTIOMETER MODE DNL (LSB)

–0.20

–0.25

0645648403224168

CODE (Decimal)

Figure 9. DNL vs. Code vs. Temperature, V

0

–0.1

–0.2

–0.3

–0.4

–0.5

FSE (LSB)

–0.6

–0.7

–0.8

–0.9

–40 –20 0 20 40 60 10080

TEMPERATURE (°C)

V

Figure 10. Full-Scale Error vs. Temperature

1.0

0.9

0.8

0.7

0.6

0.5

ZSE (LSB)

0.4

0.3

0.2

0.1

0

–40 –20 0 20 40 60 10080

VDD = 5.5V

TEMPERATURE (°C)

V

DD

Figure 11. Zero-Scale Error vs. Temperature

= 2.7V

DD

= 2.7V

VDD = 5.5V

= 5 V

DD

VDD = 5.5V

–40°C
+25°C
+85°C
+105°C

04419-0-012

04419-0-013

04419-0-014

Rev. 0 | Page 7 of 16

AD5227

/DIV

R

z

1

A)

µ

SUPPLY CURRENT (

0.1
–40 –20 0 20 40 60 10080

Figure 12. Supply Current vs. Temperature

1

)

Ω

(k

AB

TEMPERATURE (°C)

= 100kΩ

R

AB

VDD = 5.5V

VDD = 5.5V

04419-0-015

20

15

10

5

0

–5

–10

RHEOSTAT MODE TEMPCO (ppm/°C)

–15

–20

0 8 16 24 32 40 48 56 64

Figure 15. Rheostat Mode Tempco ∆R

CODE (Decimal)

/∆T vs. Code

WB

20

15

10

5

10kΩ
50kΩ
100kΩ

VDD = 5.5V

10kΩ
50kΩ
100kΩ

VDD = 5.5V

04419-0-018

RAB = 50kΩ

NOMINAL RESISTANCE, R

0.1
–40 –20 0 20 40 60 10080

R

= 10kΩ

AB

TEMPERATURE (°C)

Figure 13. Nominal Resistance vs. Temperature

120

V

100

(Ω)

W

80

60

40

WIPER RESISTANCE, R

20

0

–40 –20 0 20 40 60 10080

VDD = 5.5V

TEMPERATURE (°C)

DD

Figure 14. Wiper Resistance vs. Temperature

= 2.7V

04419-0-016

04419-0-017

0

–5

–10

–15

POTENTIOMETER MODE TEMPCO (ppm/°C)

–20

0 8 16 24 32 40 48 56 64

Figure 16. Potentiometer Mode Tempco ∆R

CODE (Decimal)

/∆T vs. Code

WB

REF LEVEL
0dB

6

0

–6

–12

–18

–24

dB

–30

–36

–42

–48

–54

1k 10k 1M

START 1 000.000Hz STOP 1 000 000.000Hz

6.0dB

32 STEPS

16 STEPS

8 STEPS

4 STEPS

2 STEPS
1 STEP

Figure 17. Gain vs. Frequency vs. Code, R

MARKE
MAG (A/R)

100k

TA = 25°C
V

DD

= 50mV rms

V

A

= 10 kΩ

AB

461 441.868H
–8.957dB

= 5.5V

04419-0-019

04419-0-042

Rev. 0 | Page 8 of 16

AD5227

/DIV

R

z

/DIV

R

z

REF LEVEL
0dB

6

6.0dB

0

–6

–12

–18

–24

dB

–30

–36

32 STEPS

16 STEPS

8 STEPS

4 STEPS

2 STEPS

1 STEP

–42

–48

–54

1k 10k 1M

START 1 000.000Hz STOP 1 000 000.000Hz

Figure 18. Gain vs. Frequency vs. Code, R

REF LEVEL
0dB

6

6.0dB

0

–6

–12

–18

–24

dB

–30

–36

32 STEPS

16 STEPS

8 STEPS

4 STEPS

2 STEPS

1 STEP

–42

–48

–54

1k 10k 1M

START 1 000.000Hz STOP 1 000 000.000Hz

Figure 19. Gain vs. Frequency vs. Code, R

0

STEP = MIDSCALE, VA = VDD, VB = 0V

MARKE
MAG (A/R)

100k

MARKE
MAG (A/R)

100k

AB

100 885.289H
–9.060dB

TA = 25°C

= 5.5V

V

DD

= 50mV rms

V

A

= 50 kΩ

AB

52 246.435H
–9.139dB

TA = 25°C

= 5.5V

V

DD

= 50mV rms

V

A

= 100 kΩ

04419-0-043

04419-0-044

200

150

A)

µ

100

(

DD

I

VDD = 5V

50

0

10k 100k 10M1M

FREQUENCY (Hz)

Figure 21. I

vs. CLK Frequency

DD

1.2

1.0

vs. Code

WB

RAB = 10kΩ

(mA)

0.8

WB_MAX

0.6

0.4
R

AB

= 50kΩ

THEORETICAL I

0.2

= 100kΩ

R

AB

0

0 8 16 24 32 40 48 56 64

CODE (Decimal)

Figure 22. Maximum I

1

V

= 3V

DD

A = OPEN

= 25°C

T

A

VB = 0V

04419-0-024

04419-0-025

VA

–20

PSRR (dB)

VDD = 3V DC ±10% p-p AC

–40

STEP N+1

STEP N

2

VDD = 5V

= 5V

V

A

= 0V

V

B

V

W

VDD = 5V DC ±10% p-p AC

–60

100 1k 10k 100k 1M

FREQUENCY (Hz)

Figure 20. PSRR

04419-0-023

CH1 2.00V CH2 50.0mV M 400ns A CH2 60.0mV

T 0.00000s

Figure 23. Step Change Settling Time

04419-0-022

Rev. 0 | Page 9 of 16

AD5227

THEORY OF OPERATION

The AD5227 is a 64-position 3-terminal digitally controlled
potentiometer device. It presets to a midscale at system power­on. When

achieved by clocking the CLK pin. It is negative-edge triggered,
and the direction of stepping is determined by the state of the

input. When the wiper reaches the maximum or the

U/

D

minimum setting, additional CLK pulses do not change the
wiper setting.

is enabled, changing the resistance settings is

CS

V

DD

AD5227

The end-to-end resistance, RAB, has 64 contact points accessed
by the wiper terminal, plus the B terminal contact, assuming
that R
R

pin. The change of R

is used (see Figure 25). Clocking the CLK input steps,

WB

by one step. The direction is determined by the state of U/D

WB

can be determined by the number of

WB

clock pulses, provided that the AD5227 has not reached its
maximum or minimum scale. ∆R

can, therefore, be

WB

approximated as

R

WB

⎛
⎜

⎝

AB

CPR

64

⎞

+×±=∆

R

(1)

⎟

W

⎠

CS

U/D

CLK

GND

6-BIT UP/DOWN

CONTROL

LOGIC

POR

MIDSCALE

WIPER

REGISTER

A

W

B

04419-0-026

Figure 24. Functional Block Diagram

A

R

S

D0

R

S

D1
D2
D3

R

S

D4
D5

RDAC

UP/DOWN

CTRL AND

DECODE

R

W

R

S

R

=

RAB/64

S

W

B

04419-0-027

Figure 25. AD5227 Equivalent RDAC Circuit

PROGRAMMING THE DIGITAL POTENTIOMETERS

Rheostat Operation

If only the W-to-B or W-to-A terminals are used as variable
resistors, the unused terminal can be opened or shorted with W.
This operation is called rheostat mode and is shown in Figure 26.

A

B

Figure 26. Rheostat Mode Configuration

A

W

B

A

W

W

B

04419-0-028

where:

CP is the number of clock pulses.
R

is the end-to-end resistance.

AB

is the wiper resistance contributed by the on-resistance of

R

W

the internal switch.

Since in the lowest end of the resistor string a finite wiper
resistance is present, care should be taken to limit the current
flow between W and B in this state to a maximum pulse current
of no more than 20 mA. Otherwise, degradation or possible
destruction of the internal switches can occur.

Similar to the mechanical potentiometer, the resistance of the
RDAC between the Wiper W and Terminal A also produces a
digitally controlled complementary resistance, R

. When these

WA

terminals are used, the B terminal can be opened or shorted to
W. S im il ar l y , ∆R

WA

can be approximated as

WA

⎛

()

64 (2)

⎜
⎝

R

AB

CPR

64

⎞

R

+−±=∆

⎟

W

⎠

Equations 1 and 2 do not apply when CP = 0.

The typical distribution of the resistance tolerance from device
to device is process lot dependent. It is possible to have ±20%
tolerance.

Potentiometer Mode Operation

If all three terminals are used, the operation is called
potentiometer mode. The most common configuration is the
voltage divider operation as shown in Figure 27.

V

I

A

V

C

W

B

Figure 27. Potentiometer Mode Configuration

04419-0-029

Rev. 0 | Page 10 of 16

AD5227

The change of VWB is known provided that the AD5227 has not
reached the maximum or minimum scale. If one ignores the
effect of the wiper resistance, the transfer functions can be
simplified as

CP

U/D = 1 (3)

V64+=∆

V64−=∆

V

AWB

CP

U/D = 0 (4)

V

AWB

Unlike rheostat mode operation where the absolute tolerance is
high, potentiometer mode operation yields an almost ratiometric
function of CP/64 with a relatively small error contributed by
the R

term. The tolerance effect is, therefore, almost canceled.

W

Although the thin film step resistor, R
resistance, R

, have very different temperature coefficients, the

W

, and CMOS switches

S

ratiometric adjustment also reduces the overall temperature
coefficient to 5 ppm/°C except at low value codes where R

W

dominates.

Potentiometer mode operation includes an op amp gain
configuration among others. The A, W, and B terminals can be
input or output terminals and have no polarity constraint
provided that |V

|, |VWA|, and |VWB| do not exceed VDD-to-GND.

AB

DIGITAL INTERFACE

The AD5227 contains a 3-wire serial input interface. The three
inputs are clock (CLK), chip select (

). These inputs can be controlled digitally for optimum

(U/

D

speed and flexibility

When

is pulled low, a clock pulse increments or decrements

CS

the up/down counter. The direction is determined by the state
of the U/

pin. When a specific state of the U/D remains, the

D

device continues to change in the same direction under con­secutive clocks until it comes to the end of the resistance setting.
All digital inputs,

, CLK, and U/D pins, are protected with a

CS

series input resistor and a parallel Zener ESD structure as
shown in Figure 28.

1kΩ

Figure 28. Equivalent ESD Protection Digital Pins

), and up/down control

CS

LOGIC

04419-0-030

TERMINAL VOLTAGE OPERATION RANGE

The AD5227 is designed with internal ESD protection diodes
(Figure 29), but the diodes also set the boundary of the terminal
operating voltages. Voltage present on Terminal A, B, or W that
exceeds V
therefore, elevates V

, VWA, and VWB, but they cannot be higher than VDD-to-GND.

V

AB

by more than 0.5 V is clamped by the diode and,

DD

. There is no polarity constraint between

DD

POWER-UP AND POWER-DOWN SEQUENCES

Because of the ESD protection diodes, it is important to power
on V

before applying any voltage to Terminals A, B, and W.

DD

Otherwise, the diodes are forward-biased such that V

can be

DD

powered unintentionally and can affect the rest of the system
circuit. Similarly, V
power-on sequence is in the following order: GND, V

should be powered down last. The ideal

DD

DD

, V

A/B/W

,

and digital inputs.

V

DD

A
W
B

GND

04419-0-031

Figure 29. Maximum Terminal Voltages Set by V

and GND

DD

LAYOUT AND POWER SUPPLY BIASING

It is a good practice to use compact, minimum lead length
layout design. The leads to the input should be as direct as
possible with a minimum conductor length. Ground paths
should have low resistance and low inductance. It is also good
practice to bypass the power supplies with quality capacitors.
Low ESR (equivalent series resistance) 1 µF to 10 µF tantalum
or electrolytic capacitors should be applied at the supplies to
minimize any transient disturbance and filter low frequency
ripple.

Figure 30 illustrates the basic supply bypassing configuration
for the AD5227. The ground pin of the AD5227 is a digital
ground reference that should be joined to the common ground
at a single point to minimize the digital ground bounce.

AD5227

V

DD

+

C2
10µFC10.1µF

V

DD

GND

04419-0-032

Figure 30. Power Supply Bypassing

Rev. 0 | Page 11 of 16

AD5227

APPLICATIONS

MANUAL CONTROL WITH TOGGLE AND PUSHBUTTON SWITCHES

The AD5227’s simple interface allows it to be used with
mechanical switches for simple manual operation. The states of
the

and U/D can be selected by toggle switches and the CLK

CS

input can be controlled by a pushbutton switch. Because of the
numerous bounces due to contact closure, the pushbutton
switch should be debounced by flip-flops or by the ADM812 as
shown in Figure 31.

U/D

B

AD5227

CS

U/D

CLK

A1

8
7
6
5

DIGITAL

POTENTIOMETER

U3

AD5227

CLK1V
U/D2CS

A13 B1 6

4

GND

04419-0-033

8

DD

7

5

W1

B1
W1

UP/DOWN

INCREMENT

5V

V

CC

MR RESET

ADM812

GND

Figure 31. Manual Push Button Up/Down Control

MANUAL CONTROL WITH ROTARY ENCODER

Figure 32 shows another way of using AD5227 to emulate
mechanical potentiometer in a rotary knob operation. The
rotary encoder U1 has a C ground terminal and two out-of­phase signals, A and B. When U1 is turned clockwise, a pulse
generated from the B terminal leads a pulse generated from the
A terminal and vice versa. Signals A and B of U1 pass through a
quadrature decoder U2 that translates the phase difference
between A and B of U1 into compatible inputs for U3 AD5227.
Therefore, when B leads A (clockwise), U2 provides the AD5227
with a logic high U/

noise, jitter, and other transients as well as debouncing the
contact bounces generated by U1.

5V

R1

10kΩR210kΩ

U1

ROTARY

ENCODER

B
C

RE11CT-V1Y12-EF2CS

A

signal, and vice versa. U2 also filters

D

QUADRATURE

DECODER

LS7084

RBIAS1CLK

2

V

DD

VSS3X4/X1

4

A

U2

R3

10kΩ

Figure 32. Manual Rotary Control

04419-0-034

ADJUSTABLE LED DRIVER

The AD5227 can be used in many electronics-level adjustments
such as LED drivers for LCD panel backlight control. Figure 33
shows an adjustable LED driver. The AD5227 sets the voltage
across the white LED D1 for the brightness control. Since U2
handles up to 250 mA, a typical white LED with V

of 3.5 V

F

requires a resistor, R1, to limit the U2 current. This circuit is
simple but not power-efficient, therefore the U2 shutdown pin
can be toggled with a PWM signal to conserve power.

5V

C1
1µFC20.1µF

CS
CLK
U/D

V

DD

U1

AD5227

A

W

10kΩ

B

GND

Figure 33. Low Cost Adjustable LED Driver

5V

V+

–

U2

AD8591

+

V–

C3

0.1µF

PWM

SD

R1
6Ω

WHITE
LED
D1

04419-0-035

ADJUSTABLE CURRENT SOURCE FOR LED DRIVER

Since LED brightness is a function of current rather than
forward voltage, an adjustable current source is preferred over a
voltage source as shown in Figure 34.

V

5V

INVOUT

U1

ADP3333

ARM-1.5

V

5V

DD

CS
CLK
U/D

GND

PWM

SD

GND

Figure 34. Adjustable Current Source for LED Driver

The load current can be found as the VWB of the AD5227
divided by R

SET

.

U2

AD5227

B

W

10kΩ
A

R1
418kΩ

5V

V+

U3

AD8591

V–

R

SET

0.1Ω

–

+

VL

D1

ID

04419-0-036

Rev. 0 | Page 12 of 16

I =

D

V

WB

(5)

R

SET

AD5227

The U1 ADP3333ARM-1.5 is a 1.5 V LDO that is lifted above or
lowered below 0 V. When V

of the AD5227 is at minimum,

WB

there is no current through D1, so the GND pin of U1 would be
at –1.5 V if U3 were biased with the dual supplies. As a result,
some of the U2 low resistance steps have no effect on the output
until the U1 GND pin is lifted above 0 V. When V
AD5227 is at its maximum, V

becomes VL + VAB, so the U1

OUT

of the

WB

supply voltage must be biased with adequate headroom.
Similarly, a PWM signal can be applied at the U1 shutdown pin
for power efficiency. This circuit works well for a single LED.

ADJUSTABLE HIGH POWER LED DRIVER

Figure 35 shows a circuit that can drive three to four high power
LEDs. ADP1610 is an adjustable boost regulator that provides
the voltage headroom and current for the LEDs. The AD5227
and the op amp form an average gain of 12 feedback network
that servos the R
gap reference voltage. As the loop is set, the voltage across R
regulated around 0.1 V and adjusted by the digital
potentiometer.

I

=

LED

should be small enough to conserve power but large

R

SET

enough to limit maximum LED current. R3 should also be used
in parallel with AD5227 to limit the LED current within an
achievable range. A wider current adjustment range is possible
by lowering the R2 to R1 ratio, as well as changing R3 accordingly.

voltage and ADP1610’s FB pin 1.2 V band

SET

is

SET

V

R

SET

(6)

R

SET

AUTOMATIC LCD PANEL BACKLIGHT CONTROL

With the addition of a photocell sensor, an automatic brightness
control can be achieved. As shown in Figure 36, the resistance of
the photocell changes linearly but inversely with the light output.
The brighter the light output, the lower the photocell resistance
and vice versa. The AD5227 sets the voltage level that is gained
up by U2 to drive N1 to a desirable brightness. With the photocell
acting as the variable feedback resistor, the change in the light
output changes the R2 resistance, therefore causing U2 to drive
N1 accordingly to regulate the output. This simple low cost
implementation of the LED controller can compensate for the
temperature and aging effects typically found in high power
LEDs. Similarly, for power efficiency, a PWM signal can be
applied at the gate of N2 to switch the LED on and off without
any noticeable effect.

5V

5V

R2

R1

PHOTOCELL

1kΩ

C1
1µFC20.1µF

CS
CLK
U/D

V

DD

5V

AD5227

A

10kΩ
B

GND

U1

W

5V

V+

–

U2

AD8591

+

V–

0.1µF

PWM

Figure 36. Automatic LCD Panel Backlight Control

C3

SD

D1

WHITE
LED

N1

2N7002

04419-0-038

5V

C2

10µF

L1–SLF6025-100M1R0
D1–MBR0520LT1

13.5kΩ

R4

Figure 35. Adjustable Current Source for LEDs in Series

PWM

1.2V

100kΩ

390pF

C

R

C

C

0.1µF

1.1kΩ

ADP1610

SD
FB

COMP
SS RT GND

C

SS

10nF

C8

5V

V+

AD8541

U1

V–

R2

IN

U2

SW

U3

+

–

W

BA

10kΩ

200Ω

AD5227

R3

L1
10µF

D1

U1

C3
10µF

R

0.25Ω

R1

100Ω

SET

6-BIT CONTROLLER

The AD5227 can form a simple 6-bit controller with a clock

V

OUT

D2

D3

D4

04419-0-037

generator, a comparator, and some output components. Figure 37
shows a generic 6-bit controller with a comparator that first
compares the sampling output with the reference level and
outputs either a high or low level to the AD5227 U/

pin. The

D

AD5227 then changes step at every clock cycle in the direction
indicated by the U/

state. Although this circuit is not as elegant

D

as the one shown in Figure 36, it is self-contained, very easy to
design, and can adapt to various applications.

5V

V
CLK
U/D

U2

COMPARATOR

DD

U1

AD5227

–

B

GNDCS

SAMPLING_OUTPUT

–

+

REF

U3

AD8531

+

OP AMP

Figure 37. 6-Bit Controller

OUTPUT

04419-0-039

Rev. 0 | Page 13 of 16

AD5227

V

CONSTANT BIAS WITH SUPPLY TO RETAIN RESISTANCE SETTING

Users who consider EEMEM potentiometers but cannot justify
the additional cost and programming for their designs can con­sider constantly biasing the AD5227 with the supply to retain
the resistance setting as shown in Figure 38. The AD5227 is
designed specifically with low power to allow power conservation
even in battery-operated systems. As shown in Figure 39, a
similar low power digital potentiometer is biased with a 3.4 V
450 mA/hour Li-Ion cell phone battery. The measurement shows
that the device drains negligible power. Constantly biasing the
potentiometer is a practical approach because most portable
devices do not require detachable batteries for charging. Although
the resistance setting of the AD5227 is lost when the battery
needs to be replaced, this event occurs so infrequently that the
inconvenience is minimal for most applications.

DD

SW1

U1

AD5227

V

DD

+

U2

V

DD

COMPONENT X

U3

V

DD

COMPONENT Y

3.50

3.49

3.48

3.47

3.46

3.45

3.44

3.43

BATTERY VOLTAGE (V)

3.42

3.41

3.40
024681012

DAYS

TA = 25°C

Figure 39. Battery Consumption Measurement

04419-0-041

BATTERY OR

GND

SYSTEM POWER

–

GND

GND

GND

04419-0-040

Figure 38. Constant Bias AD5227 for Resistance Retention

Rev. 0 | Page 14 of 16

AD5227

OUTLINE DIMENSIONS

2.90 BSC

847

1.60 BSC

1 3562

PIN 1

0.90

0.87

0.84

0.10 MAX

1.95
BSC

0.38

0.22

COMPLIANT TO JEDEC STANDARDS MO-193BA

Figure 40. 8-Lead Small Outline Transistor Package TSOT-8 [ Thin SOT-23-8]

Dimensions shown in millimeters

2.80 BSC

0.65 BSC

1.00MAX 0.20

SEATING
PLANE

(UJ-8)

0.08
8°
4°
0°

0.60

0.45

0.30

ORDERING GUIDE

Model R

AD5227BUJZ10-RL72

1

AB

10 −40°C to +105°C UJ TSOT-8 3000 D3G

kΩ)

Temperature
Range

AD5227BUJZ10-R22 10 −40°C to +105°C UJ TSOT-8 250 D3G
AD5227BUJZ50-RL72 50 −40°C to +105°C UJ TSOT-8 3000 D3H
AD5227BUJZ50-R22 50 −40°C to +105°C UJ TSOT-8 250 D3H
AD5227BUJZ100-RL72 100 −40°C to +105°C UJ TSOT-8 3000 D3J
AD5227BUJZ100-R22 100 −40°C to +105°C UJ TSOT-8 250 D3J
AD5227EVAL 10 Evaluation Board 1

1

The end-to-end resistance RAB is available in 10 kΩ, 50 kΩ, and 100 kΩ versions. The final three characters of the part number determine the nominal resistance value,

for example, 10 kΩ = 10.

2

Z = Pb-free part.

Package
Code Package Description

Full Container
Quantity Branding

Rev. 0 | Page 15 of 16

AD5227

NOTES

© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.

D04419–0–3/04(0)

Rev. 0 | Page 16 of 16