Datasheet AD5222 Datasheet (Analog Devices)

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Page 1

Increment /Decrement

DECODE

UP/DOWN COUNTER

AD5222

W1 B1

DECODE

UP/DOWN COUNTER

W2 B2

POR

DAC

SELECT

AND

ENABLE

CLK

U/D

DACSEL

MODE

GND

W1 B1

W2 B2

CLK

U/D

DACSEL

MODE

GND

U/D

INCREMENT

FEATURES 128-Position, 2-Channel Potentiometer Replacement 10 k⍀, 50 k⍀, 100 k⍀, 1 M⍀ Very Low Power: 40 ␮A Max ⴞ2.7 V Dual Supply Operation or

2.7 V to 5.5 V Single Supply Operation

Increment/Decrement Count Control

APPLICATIONS Stereo Channel Audio Level Control Mechanical Potentiometer Replacement Remote Incremental Adjustment Applications Instrumentation: Gain, Offset Adjustment Programmable Voltage-to-Current Conversion Line Impedance Matching

GENERAL DESCRIPTION

The AD5222 provides a dual channel, 128-position, digitally controlled variable-resistor (VR) device. This device performs the same electronic adjustment function as a potentiometer or variable resistor. These products were optimized for instrument and test equipment push-button applications. Choices between bandwidth or power dissipation are available as a result of the wide selection of end-to-end terminal resistance values.

The AD5222 contains two fixed resistors with wiper contacts that tap the fixed resistor value at a point determined by a digitally controlled up/down counter. The resistance between the wiper and either end point of the fixed resistor provides a constant resistance step size that is equal to the end-to-end resistance divided by the number of positions (e.g., R

78 Ω). The variable resistor offers a true adjustable value of

resistance, between Terminal A and the wiper, or Terminal B

and the wiper. The fixed A-to-B terminal resistance of 10 kΩ, 50 kΩ, 100 kΩ, or 1 MΩ has a nominal temperature coefficient of –35 ppm/°C.

The chip select CS, count CLK and U/D direction control inputs set the variable resistor position. The MODE determines whether both VRs are incremented together or independently. With MODE at logic zero, both wipers are incremented UP or DOWN without changing the relative settings between the wipers. Also, the relative ratio between the wipers is preserved if either wiper reaches the end of the resistor array. In the independent MODE (Logic 1) only the VR determined by the DACSEL pin is changed. DACSEL (Logic 0) changes RDAC 1. These inputs, which control the internal up/down counter, can be easily generated with

REV. 0

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

STEP

= 10 kΩ/128 =

Dual Digital Potentiometer

AD5222

FUNCTIONAL BLOCK DIAGRAM

mechanical or push-button switches (or other contact closure devices). This simple digital interface eliminates the need for microcontrollers in front panel interface designs.

The AD5222 is available in the surface-mount (SO-14) package. For ultracompact solutions, selected models are available in the thin TSSOP-14 package. All parts are guaranteed to operate

over the extended industrial temperature range of –40°C to +85°C. For 3-wire, SPI-compatible interface applications, see

the AD5203/AD5204/AD5206, AD7376, and AD8400/AD8402/ AD8403 products.

Figure 1. Typical Push-Button Control Application

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1999

Page 2

(VDD = 3 V ⴞ 10% or 5 V ⴞ 10%, VSS = 0 V, VA = +VDD, VB = 0 V, –40ⴗC < TA < +85ⴗC,

AD5222–SPECIFICATIONS

Parameter Symbol Condition Min Typ1Max Unit

DC CHARACTERISTICS RHEOSTAT MODE (Specifications Apply to All VRs)

Resistor Differential NL Resistor Nonlinearity

Nominal Resistor Tolerance ∆RV

Resistance Temperature Coefficient R Wiper Resistance

Nominal Resistance Match ∆R/R

DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE (Specifications Apply to All VRs)

Resolution N 7 Bits Integral Nonlinearity

Differential Nonlinearity

Voltage Divider Temperature Coefficient ∆V

Full-Scale Error V Zero-Scale Error V

RESISTOR TERMINALS

Voltage Range Capacitance Capacitance

A, B C

Common-Mode Leakage I

DIGITAL INPUTS AND OUTPUTS

Input Logic High V Input Logic Low V Input Current I Input Capacitance

POWER SUPPLIES

Power Single-Supply Range V Power Dual-Supply Range V Positive Supply Current I Negative Supply Current I Power Dissipation Power Supply Sensitivity PSS 0.002 0.05 %/%

DYNAMIC CHARACTERISTICS

Bandwidth –3 dB BW_10K R

Total Harmonic Distortion THD

Settling Time t

Resistor Noise Voltage e

INTERFACE TIMING CHARACTERISTICS (Applies to All Parts)

Input Clock Pulsewidth tCH, t

CS to CLK Setup Time t CS Rise to CLK Hold Time t

U/D to Clock Fall Setup Time t U/D to Clock Fall Hold Time t DACSEL to Clock Fall Setup Time t DACSEL to Clock Fall Hold Time t MODE to Clock Fall Setup Time t MODE to Clock Fall Hold Time t

NOTES

Typicals represent average readings at 25°C, V

Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions.

R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Figure 22 test circuit.

Wiper resistance is not measured on the R

INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V. DNL

specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. See Figure 21 test circuit.

Resistor Terminals A, B, W have no limitations on polarity with respect to each other.

Guaranteed by design and not subject to production test.

is calculated from (I

DISS

Bandwidth, noise and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest bandwidth.

The highest R value results in the minimum overall power consumption.

All dynamic characteristics use VDD = 5 V.

See timing diagram for location of measured values. All input control voltages are specified with tR = tF = 2.5 ns (10% to 90% of +3 V) and timed from a voltage level

of 1.5 V. Switching characteristics are measured using both V

Specifications subject to change without notice.

R-DNL RWB, V R-INL RWB, V

INL R INL R

DNL –1 ±1/4 +1 LSB

6, 8, 9

BW_50K R BW_100K R BW_1M R

N_WB

CSS

CSH

UDS

UDH

DSS

DSH

MDS

MDH

= 5 V.

= 1 MΩ models.

× V

). CMOS logic level inputs result in minimum power dissipation.

unless otherwise noted.)

/∆TV

/∆T Code = 40

WFSE

WZSE

A, B, W

A, B

DD RANGEVSS

DD/SS RANGE

DISS

IW = VDD/R, V CH 1 to 2, VAB = VDD, T

Code = 7F Code = 00

f = 1 MHz, Measured to GND, Code = 40 f = 1 MHz, Measured to GND, Code = 40 VA = VB = V

VDD = 5 V/3 V 2.4/2.1 V VDD = 5 V/3 V 0.8/0.6 V V

= 0 V or 5 V ±1 µA

= 0 V 2.7 5.5 V

VIH = 5 V or V VSS = –2.5 V, V VIH = 5 V or VIL = 0 V, V

VA = 1 V rms + 2 V dc, VB = 2 V dc, f = 1 kHz 0.005 % R

Clock Level High or Low 30 ns

= 5 V or VDD = 3 V.

= NC –1 ±1/4 +1 LSB

= NC –1 ±0.4 +1 LSB

= VDD, Wiper = No Connect, T = V

, Wiper = No Connect –35 ppm/°C

= 3 V or 5 V 45 100 Ω

= 25°C0.21%

= 25°C –30 +30 %

= 10 kΩ, 50 kΩ, or 100 kΩ –1 ±1/4 +1 LSB = 1 MΩ –2 ±1/2 +2 LSB

–1 –0.5 +0 LSB 0 0.5 1 LSB

20 ppm/°C

V 45 pF 60 pF 1nA

5pF

±2.3 ±2.7 V

= 0 V 15 40 µA

= +2.7 V 15 40 µA

= 10 kΩ, Code = 40 = 50 kΩ, Code = 40 = 100 kΩ, Code = 40 = 500 kΩ, Code = 40

= 5 V 150 400 µW

1000 kHz 180 kHz 78 kHz 7kHz

= 10 kΩ, ±1 LSB Error Band 2 µs

= 5 kΩ, f = 1 kHz 14 nV√Hz

6, 10

20 ns 20 ns 10 ns 30 ns 20 ns 30 ns 20 ns 40 ns

–2–

REV. 0

Page 3

AD5222

ABSOLUTE MAXIMUM RATINGS

= 25°C, unless otherwise noted)

VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +7 V

to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, –5 V

to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V

, VB, VW to GND . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, V

AX – BX, AX – WX, BX – W

. . . . . . . . . . . . . . . . . . . ±20 mA

Digital Input Voltage to GND . . . . . . . . . . . . 0 V, V

+ 0.3 V

Operating Temperature Range . . . . . . . . . . . –40°C to +85°C

Maximum Junction Temperature (T

max) . . . . . . . . . . 150°C

Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . 300°C

Package Power Dissipation . . . . . . . . . . . . . (T

Thermal Resistance θ

max – T

)/θ

SOIC (SO-14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158°C/W

TSSOP-14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206°C/W

UDH

DSH

MDH

CSH

CLK

U/D

DACSEL

MODE

CSS

UDS

DSS

MDS

Figure 2. Detail Timing Diagram

Truth Table

CS CLK U/D Operation

L t H Wiper Increment Toward Terminal A L t L Wiper Decrement Toward Terminal B H X X Wiper Position Fixed

Common Mode (MODE = 0) moves both wipers together either UP or DOWN the resistor array without changing the relative distance between the wipers. Also, the distance between both wipers is preserved if either reaches the end of the array. Independent Mode (MODE = 1) allows user to control each RDAC individually: DACSEL = 0 sets RDAC1; DACSEL = 1: sets RDAC2.

ORDERING GUIDE

Kilo Package Package

Model Ohms Temperature Description Option

AD5222BR10 10 –40°C/+85°C SO-14 R-14 AD5222BRU10 10 –40°C/+85°C TSSOP-14 RU-14 AD5222BR50 50 –40°C/+85°C SO-14 R-14 AD5222BRU50 50 –40°C/+85°C TSSOP-14 RU-14 AD5222BR100 100 –40°C/+85°C SO-14 R-14 AD5222BRU100 100 –40°C/+85°C TSSOP-14 RU-14 AD5222BR1M 1,000 –40°C/+85°C SO-14 R-14 AD5222BRU1M 1,000 –40°C/+85°C TSSOP-14 RU-14

The AD5222 die size is 56 mil × 60 mil, 3360 sq. mil; 1.4224 mm × 1.524 mm,

2.1677 sq. mm. Contains 1503 transistors. Patent Number 5495245 applies.

PIN FUNCTION DESCRIPTIONS

Pin Name Description

1 B1 B Terminal RDAC #1. 2 A1 A Terminal RDAC #1. 3 W1 Wiper RDAC #1, DACSEL = 0. 4V

Negative Power Supply. Specified for operation at both 0 V or –2.7 V (Sum of |V

| + |VSS|

< 5.5 V). 5 W2 Wiper RDAC #2, DACSEL = 1. 6 A2 A Terminal RDAC #2. 7 B2 B Terminal RDAC #2. 8 GND Ground. 9 MODE Common MODE = 0, Independent MODE = 1. 10 DACSEL DAC Select determines which wiper is incre-

mented in the Independent MODE = 1.

DACSEL = 0 sets RDAC1, DACSEL = 1 sets

RDAC2. 11 U/D UP/DOWN Direction Control. 12 CLK Serial Clock Input, Negative Edge Triggered. 13 CS Chip Select Input, Active Low. When CS is

high, the UP/DOWN counter is disabled. 14 V

Positive Power Supply. Specified for operation

at both +3 V or +5 V. (Sum of |V

| + |VSS|

< 5.5 V).

PIN CONFIGURATION

1 2

AD5222

TOP VIEW

(Not to Scale)

14 13 12 11 10

CLK U/D DACSEL MODE GND

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD5222 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

REV. 0

–3–

WARNING!

ESD SENSITIVE DEVICE

Page 4

AD5222–

CODE – Decimal

0.25

–0.25

0 12816

R-DNL ERROR – LSB

32 48 64 80 96 112

0.20

0.05

–0.05

–0.15

–0.20

0.15

0.10

–0.10

TA = +258C

TA = +858C

TA = –558C

VDD = +15V V

= –15V

= 50kV

CODE – Decimal

1.0

–1.0

0 12816

R-INL ERROR – LSB

32 48 64 80 96 112

0.8

0.2

–0.2

–0.6

–0.8

0.6

0.4

–0.4

VDD/VSS = 2.7V/0V T

= 258C

50kV VERSION

100kV VERSION

1MV VERSION

10kV VERSION

CODE – Decimal

–1.0

0 12816

INL

– LSB

32 48 64 80 96 112

0.2

–0.2

–0.6

–0.8

0.6

0.4

–0.4

VDD/VSS = 2.7V/0V T

= 258C

50kV VERSION

100kV VERSION

1MV VERSION

10kV VERSION

100

PERCENT OF NOMINAL

Typical Performance Characteristics

END-TO-END RESISTANCE – % R

32 128

64 96

CODE – Decimal

Figure 3. Wiper-To-End Terminal Resistance vs. Code

4.5

3.5

2.5

VOLTAGE – V

1.5

0.5

RAB = 10kV

= 5V

= 258C

234567

IWA CURRENT – mA

Figure 4. Resistance Linearity vs. Conduction Current

Figure 6. R-DNL Relative Resistance Step Position Change vs. Code

Figure 7. R-INL Resistance Nonlinearity Error vs. Code

180

150

120

FREQUENCY

403041 42 47 48 50 51 53 54 6044 45 56 57 59

Figure 5. Wiper Contact Resistance

WIPER RESISTANCE – V

SS = 600 UNITS VDD = 2.7V

= 258C

–4–

Figure 8. Potentiometer Divider INL Error vs. Code

REV. 0

Page 5

AD5222

FREQUENCY – Hz

–12

GAIN – dB

–6

100 1k 10k 100k

–3

–9

–15 –18

–21

VDD = +2.7V V

= –2.7V

DATA = 40

VA = 50mV rms V

= 0V

10kV 764kHz 50kV 132kHz 100kV 64kHz 1MV 6.6kHz

OP42

50kV

100kV

10kV

1MV

FREQUENCY – Hz

100k

THD + NOISE – %

10 100 1k 10k

0.001

FILTER = 22kHz VDD = 62.7V

= 1V rms

= 258C

SEE TEST CIRCUIT FIGURE 26

SEE TEST CIRCUIT FIGURE 25

0.01

0.1

1.0

FREQUENCY – Hz

10 1M

NORMALIZED GAIN FLATNESS – 0.1dB/DIV

100 1k 10k 100k

SEE TEST CIRUIT 27 VDD = 2.7V

= –2.7V

= 50mV rms

= 0V

DATA = 40

OP42

10kV

50kV

100kV

1MV

1MV VERSION

–10

–20

POTENTIOMETER MODE TEMPCO – ppm/8C

–30

0 12816

10kV VERSION

100kV VERSION

50kV VERSION

32 48 64 80 96 112

CODE – Decimal

VDD/VSS = 2.7V/0V TA = 258C

Figure 9.⌬VWB/⌬T Potentiometer Mode Tempco

120 100

1MV VERSION

0 12816

100kV VERSION

50kV VERSION

10kV VERSION

32 48 64 80 96 112

CODE – Decimal

80 60

–20

–40

RHEOSTAT MODE TEMPCO – ppm/8C

–60

–80

Figure 10.⌬RWB/⌬T Rheostat Mode Tempco

–10

–20

GAIN - dB

–30

REV. 0

–40

TA = 258C SEE TEST CIRCUIT FIGURE 32

–50

100 1k 10k 100k

10 1M

Figure 11. 10 kΩ Gain vs. Frequency vs. Code

CODE = 3F

FREQUENCY – Hz

VDD/VSS = 2.7V/0V T

= 258C

10M

Figure 12. Gain vs. Frequency vs. R

Figure 13. Total Harmonic Distortion Plus Noise vs. Frequency

Figure 14. Normalized Gain Flatness vs. Frequency

–5–

Page 6

AD5222

INPUT LOGIC VOLTAGE – V

0.001 051

SUPPLY CURRENT – mA

0.01

234

VDD = 5.5V V

= 5.5V

VDD/VSS = 62.5V V

= 2.5V

VDD = 2.7V V

= 2.7V

0.1

20mV/DIV

CLK

2V/DIV

VDD = 2.7V V

= 2.7V

= 0V

1200

CODE = 15

1000

CODE = 15

CODE = 3F

800

CODE = 3F

600

400

– SUPPLY CURRENT – mA

200

A – VDD = 5.5V

B – VDD = 3.3V

C – VDD = 5.5V

D – VDD = 3.3V

10k 100k 1M

FREQUENCY – Hz

TA = 258C

10M

Figure 15. IDD, ISS Supply Current vs. Clock Frequency

100

TA = 258C

SWITCH RESISTANCE – V

–3

–2–10123456

COMMON MODE – Volts

VDD/VSS = 2.7V/0V

VDD/VSS = 62.7V

VDD/VSS = 5.5V/0V

Figure 16. Incremental Wiper Contact Resistance vs. V

DD/VSS

Figure 18. Supply Current vs. Input Logic Voltage

Figure 19. Midscale Transition 3FH to 40

SUPPLY CURRENT – mA

0.001

LOGIC = 0V OR V

0.1

0.01

–40 85–15

VDD = 2.7V

TEMPERATURE – 8C

VDD = 5.5V OR VDD/VSS = 62.7V

10 35 60

Figure 17. Supply Current vs. Temperature

–6–

VDD = 2.7V V

= 2.7V

= 0V

Figure 20. Stereo Step Transition, Mode = 0

20mV/DIV

CLK

2V/DIV

REV. 0

Page 7

Parametric Test Circuits–AD5222

OP279

+5V

OUT

DUT

–5V

DUT

OP42

+15V

OUT

–15V

0 TO V

0.1V I

CODE = 00

0.1V

DUT

DUT A

V+

V+ = V

1LSB = V+/128

Figure 21. Potentiometer Divider Nonlinearity Error Test Circuit (INL, DNL)

NO CONNECT

DUT A

Figure 22. Resistor Position Nonlinearity Error (Rheostat Operation; R-INL, R-DNL)

DUT

MS2

IW = VDD/R

MS1

NOMINAL

RW = [V

MS1

– V

MS2

]/I

Figure 25. Inverting Programmable Gain Test Circuit

+5V

DUT

–5V

OP279

OUT

Figure 26. Noninverting Programmable Gain Test Circuit

Figure 23. Wiper Resistance Test Circuit

V+ = V

± 10%

V+

PSRR (dB) = 20 LOG ( ––––– )

PSS (%/%) = –––––––

DVMS% DVDD%

Figure 24. Power Supply Sensitivity Test Circuit (PSS, PSRR)

Figure 27. Gain vs. Frequency Test Circuit

Figure 28. Incremental ON Resistance Test Circuit

REV. 0

–7–

Page 8

RDAC 1

U/D

COUNTER

RDAC 2

U/D

COUNTER

CLK

U/D

DACSEL

MODE

D0 D1 D2 D3 D4 D5 D6

RDAC

UP/DOWN

CNTR

DECODE

= R

NOMINAL

/128

AD5222

OPERATION

The AD5222 provides a 128-position, digitally-controlled, variable resistor (VR) device. Changing the VR settings is accomplished by pulsing the CLK pin while CS is active low. The U/D (UP/ DOWN) control input pin controls the direction of the increment. When the wiper hits the end of the resistor (Terminal A or B) additional CLK pulses no longer change the wiper setting. The wiper position is immediately decoded by the wiper decode logic changing the wiper resistance. Appropriate debounce circuitry is required when push-button switches are used to control the count sequence and direction of count. The exact timing requirements are shown in Figure 2. The AD5222 powers ON in a centered wiper position, exhibiting nearly equal resistances of

and RWB.

AD5222

U/D

MODE

DACSEL

CLK

GND

POR

DAC

SELECT

AND

ENABLE

UP/DOWN COUNTER

DECODE

Figure 29. Block Diagram

DIGITAL INTERFACING OPERATION

The AD5222 contains a push-button controllable interface. The active inputs are clock (CLK), CS and up/down (U/D). While the MODE, and DACSEL pins control common updates or individual updates. The negative-edge sensitive CLK input requires clean transitions to avoid clocking multiple pulses into the internal UP/DOWN counter register, Figure 30. Standard logic families work well. If mechanical switches are used for product evaluation a flip-flop or other suitable means should debounce them. When CS is taken active low, the clock begins to increment or decrement the internal up/down counter, dependent upon the state of the U/D control pin. The UP/DOWN counter value (D) starts at 40

at system power ON. Each new

CLK pulse will increment the value of the internal counter by 1 LSB until the full-scale value of 7F

is reached, as long as the

U/D pin is logic high. If the U/D pin is taken to logic low, the counter will count down, stopping at code 00

Additional clock pulses on the CLK pin are ignored when the wiper is at either the 00 detailed digital logic interface circuitry is shown in Figure 30.

position or the 7FH position. The

W1 B1

W2 B2

(zero-scale).

Figure 30. Detailed Digital Logic Interface Circuit

All digital inputs (CS, U/D, CLK, MODE, DACSEL) are protected with a series input resistor and parallel Zener ESD structure shown in Figure 31. All potentiometer terminal pins (A, B, W) are protected from ESD as shown in Figure 32.

1kV

LOGIC

Figure 31. Equivalent ESD Protection Digital Pins

A, B, W

20V

Figure 32. Equivalent ESD Protection Analog Pins

Figure 33. AD5222 Equivalent RDAC Circuit

–8–

REV. 0

Page 9

AD5222

PROGRAMMING THE VARIABLE RESISTOR Rheostat Operation

The nominal resistance of the RDAC between Terminals A and

B are available with values of 10 kΩ, 50 kΩ, 100 kΩ, and 1 MΩ

The final three characters of the part number determine the

nominal resistance value, e.g., 10 kΩ = 10; 50 kΩ = 50; 100 kΩ = 100; 1 MΩ = 1M. The nominal resistance (R

) of the VR

has 128 contact points accessed by the wiper terminal, plus the B terminal contact. At power ON, the resistance from the wiper to either end Terminal A or B is approximately equal. Pulsing the CLK pin will increase the resistance from the wiper W to Terminal B by one unit of R resistance R

is determined by the number of pulses applied to

resistance, see Figure 33. The

the clock pin. Each segment of the internal resistor string has a

= R

nominal resistance value of R

/128, which becomes 78 Ω

in the case of the 10 kΩ AD5222BR10 product. Care should be

taken to limit the current flow between W and B in the direct contact state (R

code = 0) to a maximum value of 20 mA to

avoid degradation or possible destruction of the internal switch contact.

Like the mechanical potentiometer the RDAC replaces, it is totally symmetrical (see Figure 3). The resistance between the wiper W and Terminal A also produces a digitally controlled resistance R

. When these terminals are used the B-terminal

should be tied to the wiper.

The typical part-to-part distribution of R

dependent having a ±30% variation. The change in R

is process-lot-

with

temperature has a –35 ppm/°C temperature coefficient.

The R

temperature coefficient increases as the wiper is pro-

grammed near the B-terminal due to the larger percentage contribution of the wiper contact switch resistance, which has a

0.5%/°C temperature coefficient. Figures 9 and 10 show the

effect of the wiper contact resistance as a function of code setting.

PROGRAMMING THE POTENTIOMETER DIVIDER Voltage Output Operation

The digital potentiometer easily generates an output voltage proportional to the input voltage applied to a given terminal. For example connecting A-terminal to 5 V and B-terminal to ground produces an output voltage at the wiper which can be any value starting at zero volts up to 1 LSB less than 5 V. Each LSB of voltage is equal to the voltage applied across Terminals AB divided by the 128-position resolution of the potentiometer divider. The general equation defining the output voltage with respect to ground for any given input voltage applied to Terminals AB is:

(D) = D/128 × V

+ V

(1)

D represents the current contents of the internal up/down counter.

Operation of the digital potentiometer in the divider mode results in more accurate operation over temperature. Here the output voltage is dependent on the ratio of the internal resistors

not the absolute value, therefore, the drift improves to 20 ppm/°C.

REV. 0

–9–

Page 10

AD5222

0.256 (6.50)

0.246 (6.25)

0.177 (4.50)

0.169 (4.30)

PIN 1

0.201 (5.10)

0.193 (4.90)

SEATING

PLANE

0.006 (0.15)

0.002 (0.05)

0.0118 (0.30)

0.0075 (0.19)

0.0256 (0.65)

BSC

0.0433 (1.10) MAX

0.0079 (0.20)

0.0035 (0.090)

0.028 (0.70)

0.020 (0.50)

88 08

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

0.1574 (4.00)

0.1497 (3.80)

PIN 1

0.0098 (0.25)

0.0040 (0.10)

14-Lead Narrow Body SOIC

(R-14)

0.3444 (8.75)

0.3367 (8.55)

0.050 (1.27) BSC

0.0688 (1.75)

0.0532 (1.35)

0.0192 (0.49)

0.0138 (0.35)

0.2440 (6.20)

0.2284 (5.80)

SEATING PLANE

0.0099 (0.25)

0.0075 (0.19)

0.0196 (0.50)

0.0099 (0.25)

88 08

0.0500 (1.27)

0.0160 (0.41)

14-Lead TSSOP

(RU-14)

C3715–8–10/99

3 458

PRINTED IN U.S.A.

–10–

REV. 0

Datasheet AD5222 Datasheet (Analog Devices)

Specifications and Main Features

Frequently Asked Questions

User Manual