Page 1
Increment/Decrement
a
FEATURES
128 Position
Potentiometer Replacement
10 k⍀, 50 k⍀, 100 k⍀
Very Low Power: 40 A Max
Increment/Decrement Count Control
APPLICATIONS
Mechanical Potentiometer Replacement
Remote Incremental Adjustment Applications
Instrumentation: Gain, Offset Adjustment
Programmable Voltage-to-Current Conversion
Programmable Filters, Delays, Time Constants
Line Impedance Matching
Power Supply Adjustment
GENERAL DESCRIPTION
The AD5220 provides a single channel, 128-position digitally
controlled variable resistor (VR) device. This device performs
the same electronic adjustment function as a potentiometer or
variable resistor. These products were optimized for instrument
and test equipment push-button applications. A choice between
bandwidth or power dissipation are available as a result of the
wide selection of end-to-end terminal resistance values.
The AD5220 contains a fixed resistor with a wiper contact that
taps the fixed resistor value at a point determined by a digitally
controlled UP/DOWN counter. The resistance between the
wiper and either end point of the fixed resistor provides a constant resistance step size that is equal to the end-to-end resistance divided by the number of positions (e.g., R
128 = 78 Ω). The variable resistor offers a true adjustable value
of resistance, between the A terminal and the wiper, or the B
terminal and the wiper. The fixed A-to-B terminal resistance of
10 kΩ, 50 kΩ, or 100 kΩ has a nominal temperature coefficient
of 800 ppm/°C.
The chip select CS, count CLK and U/D direction control
inputs set the variable resistor position. These inputs that control the internal UP/DOWN counter can be easily generated
with mechanical or push button switches (or other contact closure
devices). External debounce circuitry is required for the negative-edge sensitive CLK pin. This simple digital interface eliminates the need for microcontrollers in front panel interface designs.
The AD5220 is available in both surface mount (SO-8) and the
8-lead plastic DIP package. For ultracompact solutions selected
models are available in the thin µSOIC package. All parts are
guaranteed to operate over the extended industrial temperature
range of –40°C to +85°C. For 3-wire, SPI compatible inter-
face applications, see the AD7376/AD8400/AD8402/AD8403
products.
STEP
= 10 kΩ/
Digital Potentiometer
AD5220
FUNCTIONAL BLOCK DIAGRAM
V
CLK
CS
U/D
UP/DOWN
INCREMENT
EN
POR
DOWN
CNTR
40
H
UP/
RS
D
E
7
C
O
D
E
AD5220
+5V
Figure 1. Typical Push-Button Control Application
UPCOUNT DETAIL
= 5.5V
V
DD
= 5.5V
V
A
V
= 0V
50mV/DIV
5V/DIV
B
f = 100kHz
Figure 2a. Stair-Step Increment Output
VDD = 5.5V
= 5.5V
V
A
= 0V
V
B
f = 60kHz
COUNT
00
H
f
= 60kHz
CLK
Figure 2b. Full-Scale Up/Down Count
A
W
B
GND
CS
U/D
CLK
AD5220
v 3FH v 00
DD
V
WB
CLK
H
V
WR
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703 © Analog Devices, Inc., 1998
Page 2
AD5220–SPECIFICATIONS
(VDD = +3 V ⴞ 10% or +5 V ⴞ 10%, VA = +VDD, VB = 0 V, –40ⴗC < TA < +85ⴗC unless
ELECTRICAL CHARACTERISTICS
Parameter Symbol Conditions Min Typ1Max Units
DC CHARACTERISTICS RHEOSTAT MODE Specifications Apply to All VRs
Resistor Differential NL
Resistor Nonlinearity
Nominal Resistor Tolerance ∆RT
Resistance Temperature Coefficient ∆R
Wiper Resistance R
DC CHARACTERISTICS POTENTIOMETER DIVIDER MODE Specifications Apply to All VRs
Resolution N 7 Bits
Integral Nonlinearity
Differential Nonlinearity Error
Voltage Divider Temperature Coefficient ∆V
Full-Scale Error V
Zero-Scale Error V
RESISTOR TERMINALS
Voltage Range
Capacitance
Capacitance
4
5
A, B C
5
WC
Common-Mode Leakage I
DIGITAL INPUTS AND OUTPUTS
Input Logic High V
Input Logic Low V
Input Current I
Input Capacitance
POWER SUPPLIES
Power Supply Range V
Supply Current I
Power Dissipation
Power Supply Sensitivity PSS 0.004 0.015 %/%
DYNAMIC CHARACTERISTICS
Bandwidth –3 dB BW_10K R
Total Harmonic Distortion THD
Settling Time t
V
W
Resistor Noise Voltage e
INTERFACE TIMING CHARACTERISTICS Applies to All Parts
Input Clock Pulsewidth tCH, t
CS to CLK Setup Time t
CS Rise to Clock Hold Time t
U/D to Clock Fall Setup Time t
NOTES
1
Typicals represent average readings at +25°C and V
2
Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See Figure 29 test circuit.
3
INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. V
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. See Figure 28 test circuit.
4
Resistor terminals A, B, W have no limitations on polarity with respect to each other.
5
Guaranteed by design and not subject to production test.
6
P
is calculated from (I
DISS
7
Bandwidth, noise and settling time are dependent on the terminal resistance value chosen. The lowest R value results in the fastest settling time and highest bandwidth. The highest R value results in the minimum overall power consumption.
8
All dynamic characteristics use VDD = +5 V.
9
See timing diagrams for location of measured values. All input control voltages are specified with tR = tF = 1 ns (10% to 90% of VDD) and timed from a voltage level
of 1.6 V. Switching characteristics are measured using both VDD = +3 V or +5 V.
Specifications subject to change without notice.
2
2
3
3
5
6
5, 7, 8
× V
). CMOS logic level inputs result in minimum power dissipation.
DD
DD
otherwise noted)
R-DNL RWB, VA = NC, R
R-INL RWB, VA = NC, R
/∆TV
AB
W
INL R
DNL R
/∆T Code = 40
W
WFSE
WZSE
VA, VB, V
A, CB
W
CM
IH
IL
IL
C
IL
DD
DD
P
DISS
BW_50K R
BW_100K R
W
S
NWB
CL
CSS
CSH
UDS
= +5 V.
DD
, VA = NC, R
R
WB
, VA = NC, R
R
WB
= +25°C –30 +30 %
A
= V
AB
IW = VDD/R, V
AB
R
AB
AB
R
AB
Code = 7F
Code = 00
W
, Wiper = No Connect 800 ppm/°C
DD
DD
= 10 kΩ –1 ±0.5 +1 LSB
= 50 kΩ, 100 kΩ –0.5 ±0.2 +0.5 LSB
= 10 kΩ –1 ±0.4 +1 LSB
= 50 kΩ, 100 kΩ –0.5 ±0.1 +0.5 LSB
H
H
H
f = 1 MHz, Measured to GND, Code = 40
f = 1 MHz, Measured to GND, Code = 40
VA = VB = V
W
VDD = +5 V/+3 V 2.4/2.1 V
VDD = +5 V/+3 V 0.8/0.6 V
V
= 0 V or +5 V ±1 µA
IN
VIH = +5 V or VIL = 0 V, V
VIH = +5 V or VIL = 0 V, V
= 10 kΩ, Code = 40
AB
= 50 kΩ, Code = 40
AB
= 100 kΩ, Code = 40
AB
VA =1 V rms + 2.5 V dc, VB = 2.5 V dc, f = 1 kHz 0.002 %
VA = VDD, VB = 0 V, 50% of Final Value,
10K/50K/100K 0.6/3/6 µs
R
= 5 kΩ, f = 1 kHz 14 nV/√Hz
WB
5, 9
Clock Level High or Low 25 ns
= 10 kΩ –1 ±0.4 +1 LSB
AB
= 50 kΩ or 100 kΩ –0.5 ±0.1 +0.5 LSB
AB
= 10 kΩ –1 ±0.5 +1 LSB
AB
= 50 kΩ or 100 kΩ –0.5 ±0.1 +0.5 LSB
AB
= +3 V or +5 V 40 100 Ω
20 ppm/°C
–2 –0.5 0 LSB
0 +0.5 +1 LSB
0V
H
H
10 pF
48 pF
DD
7.5 nA
5pF
2.7 5.5 V
= +5 V 15 40 µA
DD
= +5 V 75 200 µW
DD
H
H
H
650 kHz
142 kHz
69 kHz
20 ns
20 ns
10 ns
= VDD and VB = 0 V.
A
V
–2–
REV. 0
Page 3
AD5220
WARNING!
ESD SENSITIVE DEVICE
TOP VIEW
(Not to Scale)
8
7
6
5
1
2
3
4
CLK
U/D
A1
GND
V
DD
CS
B1
W1
AD5220
ABSOLUTE MAXIMUM RATINGS*
(T
= +25°C, unless otherwise noted)
A
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +7 V
, VB, VW to GND . . . . . . . . . . . . . . . . . . . . . . . . . . 0 V, V
V
A
AX–BX, AX–WX, BX–W
. . . . . . . . . . . . . . . . . . . . . . ±20 mA
X
Digital Input Voltage to GND . . . . . . . . . . . 0 V, V
DD
DD
+ 0.3 V
Operating Temperature Range . . . . . . . . . . . –40°C to +85°C
Maximum Junction Temperature (T
MAX) . . . . . . . .+150°C
J
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300°C
Package Power Dissipation . . . . . . . . . . . . . . (T
Thermal Resistance θ
JA
max–T
J
)/θ
A
JA
P-DIP (N-8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103°C/W
SOIC (SO-8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158°C/W
µSOIC (RM-8) . . . . . . . . . . . . . . . . . . . . . . . . . . . 206°C/W
*Stresses above those listed under Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Table I. Truth Table
CS CLK U/D Operation
L t H Wiper Increment Toward Terminal A
L t L Wiper Decrement Toward Terminal B
H X X Wiper Position Fixed
1
CS
CLK
U/D
0
1
0
1
0
t
CSS
t
CH
t
CL
t
UDS
t
CSH
Figure 3. Detail Timing Diagram
PIN CONFIGURATION
PIN FUNCTION DESCRIPTIONS
Pin
No. Name Description
1 CLK Serial Clock Input, Negative Edge Triggered
2U/D UP/DOWN Direction Increment Control
3 A1 Terminal A1
4 GND Ground
5 W1 Wiper Terminal
6 B1 Terminal B1
7 CS Chip Select Input, Active Low
8VDDPositive Power Supply
ORDERING GUIDE
Model k⍀ Temperature Range Package Descriptions Package Options
AD5220BN10 10 –40°C to +85°C 8-Lead Plastic DIP N-8
AD5220BR10 10 –40°C to +85°C 8-Lead (SOIC) SO-8
AD5220BRM10 10 –40°C to +85°C 8-Lead µSOIC RM-8
AD5220BN50 50 –40°C to +85°C 8-Lead Plastic DIP N-8
AD5220BR50 50 –40°C to +85°C 8-Lead (SOIC) SO-8
AD5220BRM50 50 –40°C to +85°C 8-Lead µSOIC RM-8
AD5220BN100 100 –40°C to +85°C 8-Lead Plastic DIP N-8
AD5220BR100 100 –40°C to +85°C 8-Lead (SOIC) SO-8
AD5220BRM100 100 –40°C to +85°C 8-Lead µSOIC RM-8
NOTE
The AD5220 die size is 37 mil × 54 mil, 1998 sq mil; 0.938 mm × 1.372 mm, 1.289 sq mm. Contains 754 transistors. Patent Number 5495245 applies.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD5220 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
–3–REV. 0
Page 4
AD5220
–Typical Performance Characteristics
100
AB
75
50
PERCENT OF NOMINAL
25
END-TO-END RESISTANCE – % R
R
WB
0
0
32 128
64 96
CODE – Decimal
R
WA
Figure 4. Wiper to End Terminal
Resistance vs. Code
0.5
0.4
0.3
0.2
50kV VERSION
0.1
0.0
–0.1
RDNL – LSB
–0.2
–0.3
–0.4
–0.5
0
16 128
32 48 64 80 96 112
CODE – Decimal
TA = +258C
V
= +5.5V
DD
100kV VERSION
10kV VERSION
Figure 7. R-DNL Relative Resistance
Step Position Nonlinearity Error vs.
Code
6
VDD = 5.5V
= 50kV
R
AB
5
4
– V
3
WB
V
2
7F
1
0
0
H
40
H
08
H
20
H
10
H
40 60 80 100
20 120
CONDUCTION CURRENT, IWB – mA
01
02
H
04
H
Figure 5. Resistance Linearity vs.
Conduction Current
0.5
0.4
0.3
0.2
0.1
0.0
–0.1
RINL – LSB
–0.2
–0.3
–0.4
–0.5
100kV VERSION
0
16 128
32 48 64 80 96 112
CODE – Decimal
TA = +258C
V
= +5.5V
DD
50kV VERSION
10kV VERSION
Figure 8. R-INL Resistance Non linearity Error vs. Supply Voltage
48
40
32
24
FREQUENCY
16
H
8
0
20
28 36 44 52 60
WIPER RESISTANCE – V
SS = 300 UNITS
V
= +2.7V
DD
T
= +258C
A
Figure 6. Wiper Contact Resistance
0.5
0.4
INL – LSB
–0.1
–0.2
–0.3
–0.4
–0.5
0.3
0.2
0.1
0.0
10kV VERSION
TA = +258C
V
= +5.5V
DD
V
= +5.5V
A
V
= 0V
B
0
16 128
32 48 64 80 96 112
50kV VERSION
100kV VERSION
CODE – Decimal
Figure 9. Potentiometer Divider INL
Error vs. Code
0.5
0.4
0.3
0.2
0.1
0.0
–0.1
DNL – LSB
–0.2
–0.3
–0.4
–0.5
0
100kV VERSION
10kV VERSION
16 128
32 48 64 80 96 112
CODE – Decimal
TA = +258C
V
= +5.5V
DD
V
= +5.5V
A
V
= 0V
B
50kV VERSION
Figure 10. Potentiometer Divider
DNL Error vs. Code
0.600
0.525
0.450
0.375
0.300
0.255
NONLINEARITY – LSB
0.150
POTENTIOMETER DIVIDER
0.075
0.000
2.00 2.50 6.00
3.00 3.50 4.00 4.50 5.00 5.50
SUPPLY VOLTAGE – V
CODE = 40
RAB = 50kV
V
= V
A
DD
Figure 11. Potentiometer Divider
INL Error vs. Supply Voltage
–4–
H
100
80
60
40
20
NOMINAL END-TO-END RESISTANCE – kV
0
–40 –15 85
100kV VERSION
50kV VERSION
10kV VERSION
10 35 60
TEMPERATURE – 8C
Figure 12. Nominal Resistance vs.
Temperature
REV. 0
Page 5
AD5220
60
53
–558C < TA < +858C
= +5.5V
V
DD
46
39
10kV VERSION
32
25
18
50kV AND 100kV VERSION
11
4
–3
POTENTIOMETER MODE TEMPCO – ppm/8C
–10
0
32 48 64 80 96 112
16 128
CODE – Decimal
Figure 13.∆VWB/∆T Potentiometer
Ω
–
W
+
OP42
+
2.5V
–
and 50 kΩ)
00
H
40
H
20
H
10
H
08
H
04
H
02
H
01
H
Mode Tempco (10 k
6
0
–6
–12
–18
–24
GAIN – dB
–30
–36
–42
DATA = 40
H
VDD = +5V
–48
V
= VA = 100mV rms
IN
V
= +2.5V
B
–54
1k 1M
A
B
10k 100k
FREQUENCY – Hz
Figure 16. 50 kΩ Gain vs. Frequency
vs. Code
60
53
46
39
32
10kV VERSION
–558C < TA < +858C
= +5.5V
V
DD
MEASURED
R
WB
= NO CONNECT
V
A
25
18
50kV AND 100kV VERSION
11
4
–3
RHEOSTAT MODE TEMPCO – ppm/8C
–10
0
32 48 64 80 96 112
16 128
CODE – Decimal
Figure 14.∆RWB/∆T Rheostat
6
0
–6
–12
–18
–24
GAIN – dB
–30
–36
–42
DATA = 40
H
VDD = +5V
–48
V
= VA = 100mV rms
IN
= +2.5V
V
B
–54
1k 1M10k 100k
00
H
40
H
20
H
10
H
08
H
04
H
02
H
01
H
–
A
W
+
OP42
B
+
2.5V
–
FREQUENCY – Hz
Figure 17. 100 kΩ Gain vs. Frequency vs. Code
6
0
–6
–12
–18
–24
GAIN – dB
–30
–36
DATA = 40
–42
–48
–54
H
VDD = +5V
= VA = 100mV rms
V
IN
= +2.5V
V
B
1k 1M
10k 100k
FREQUENCY – Hz
–
A
W
+
B
+
2.5V
–
OP42
00
H
40
H
20
H
10
H
08
H
04
H
02
H
01
H
Figure 15. 10 kΩ Gain vs. Frequency
vs. Code
V
WB
VDD = +5.5V
= VB = 0V
V
A
f = 100kHz
TIME 2ms / DIV
20mV/
DIV
Figure 18. Digital Feedthrough
150mV
V
WB
100mV
50mV
v 3F
H
0mV
H
5V
0V
CLK
VDD = +5.5V
= +5.5V
V
A
= 0V
V
B
f = 100kHz
DATA
40
TIME 500ns / DIV
Figure 19. Midscale Transition Glitch
1.00
TA = +258C
V
= +5.0V
DD
OFFSET GND = +2.5V
0.10
R
= 10kV
AB
0.01
NONINVERTING
TEST CKT 32
THD + NOISE – %
0.001
INVERTING
TEST CKT 31
0.0001
100 1k 10k
10
100k
FREQUENCY – Hz
Figure 20. Total Harmonic Distortion
Plus Noise vs. Frequency
–5–REV. 0
–5.8
–5.9
–6.0
–6.1
DATA = 40
–6.2
–6.3
–6.4
–6.5
–6.6
NORMALIZED GAIN FLATNESS – dB
–6.7
–6.8
10 100 1M
H
VDD = +5V
= VA = 50mV rms
V
IN
= +2.5V
V
B
–
A
W
+
B
+
2.5V
–
OP42
1k 10k 100k
10kV
50kV
100kV
FREQUENCY – Hz
Figure 21. Normalized Gain Flatness
vs. Frequency
Page 6
AD5220
80
60
40
PSRR – dB
VDD = +5V DC 61V p-p AC
= +258C
T
A
20
CODE = 40
CL = 10pF
V
0
H
= 4V, VB = 0V
A
FREQUENCY – Hz
100k1k 10k
1M
Figure 22. Power Supply Rejection
vs. Frequency
0.10
LOGIC = 0V OR V
0.01
0.001
SUPPLY CURRENT – mA
DD
I
DD
VD = +5.5V
VDD = +3.3V
400
DATA = 3F
VB = 0V
350
T
300
250
200
150
– SUPPLY CURRENT – mA
100
DD
I
50
0
1k 10M
H
= +258C
A
10k 100k 1M
CLOCK FREQUENCY – Hz
VDD = +5.5V
= +5.5V
V
A
VDD = +2.7V
= +2.7V
V
A
Figure 23. IDD Supply Current vs.
Clock Frequency
10
1
0.1
0.01
SUPPLY CURRENT – mA
TA = +258C
ALL LOGIC INPUT
PINS TIED TOGETHER
VDD = +5V
VDD = +3V
80
60
– V
40
ON
R
20
0
01 6
TA = +258C
SEE FIGURE 34
FOR TEST CIRCUIT
VDD = +2.7V
VDD = +5.5V
23 45
VB – Volts
Figure 24. Incremental Wiper
Contact Resistance vs. V
B
0.0001
–15 10 35 60 85
–40
TEMPERATURE – 8C
Figure 25. Supply Current vs. Temperature I
DD
0.001
0
1.0 2.0 3.0 4.0 5.0
DIGITAL INPUT VOLTAGE – V
Figure 26. Supply Current vs. Input
Logic Voltage
–6–
REV. 0
Page 7
Parametric Test Circuits–
A
B
DUT
DUT
A
V+
W
B
V+ = V
DD
1LSB = V+/128
V
MS
OFFSET
GND
V
~
IN
2.5V DC
+5V
W
OP279
AD5220
V
OUT
Figure 27. Potentiometer Divider Nonlinearity Error Test
Circuit (INL, DNL)
NO CONNECT
DUT
A
B
W
I
W
V
MS
Figure 28. Resistor Position Nonlinearity Error (Rheostat
Operation; R-INL, R-DNL)
DUT
V
MS2
A
B
IW = VDD/R
V
W
W
V
MS1
NOMINAL
RW = [V
MS1
– V
MS2
]/I
W
␣ ␣ Figure 29.␣ Wiper Resistance Test Circuit
V
A
V+ = V
± 10%
A
V
DD
V+
~
W
B
V
MS
DD
PSRR (dB) = 20 LOG ( –––––
PSS (%/%) = –––––––
DVMS%
DV
DD
DV
MS
)
DV
DD
%
Figure 31. Inverting Programmable Gain Test Circuit
+5V
V
OUT
OFFSET
GND
V
2.5V
W
~
IN
DUT
AB
OP279
Figure 32. Noninverting Programmable Gain Test Circuit
+15V
A
DUT
2.5V
W
OP42
B
–15V
V
OUT
OFFSET
GND
V
~
IN
Figure 33. Gain vs. Frequency Test Circuit
0.1V
R
=
SW
DUT
B
W
I
SW
I
CODE = ØØ
SW
H
0.1V
0 TO V
DD
Figure 30. Power Supply Sensitivity Test Circuit (PSS,
PSRR)
Figure 34. Incremental ON Resistance Test Circuit
–7–REV. 0
Page 8
AD5220
OPERATION
The AD5220 provides a 128-position digitally controlled variable resistor (VR) device. Changing the VR settings is accomplished by pulsing the CLK pin while CS is active low. The
direction of the increment is controlled by the U/D (UP/DOWN)
control input pin. When the wiper hits the end of the resistor
(Terminals A or B) additional CLK pulses no longer change
the wiper setting. The wiper position is immediately decoded
by the wiper decode logic changing the wiper resistance. Appropriate debounce circuitry is required when push button
switches are used to control the count sequence and direction
of count. The exact timing requirements are shown in Figure 3.
The AD5220 powers ON in a centered wiper position exhibit-
UP/
RS
and RWB.
WA
D
E
7
C
O
D
E
AD5220
V
DD
A
W
B
GND
ing nearly equal resistances of R
CLK
EN
CS
DOWN
CNTR
U/D
POR
40
H
Figure 35. Block Diagram
DIGITAL INTERFACING OPERATION
The AD5220 contains a three-wire serial input interface. The
three inputs are clock (CLK), CS and UP/DOWN (U/D). The
negative-edge sensitive CLK input requires clean transitions to
avoid clocking multiple pulses into the internal UP/DOWN
counter register, see Figure 35. Standard logic families work
well. If mechanical switches are used for product evaluation
they should be debounced by a flip-flop or other suitable
means. When CS is taken active low the clock begins to incre-
ment or decrement the internal UP/DOWN counter dependent
upon the state of the U/D control pin. The UP/DOWN counter
value (D) starts at 40
at system power ON. Each new CLK
H
pulse will increment the value of the internal counter by one
LSB until the full scale value of 3F
is reached as long as the
H
U/D pin is logic high. If the U/D pin is taken to logic low the
counter will count down stopping at code 00
(zero-scale).
H
Additional clock pulses on the CLK pin are ignored when the
wiper is at either the 00
position or the 3FH position.
H
All digital inputs (CS, U/D, CLK) are protected with a series
input resistor and parallel Zener ESD structure shown in
Figure 36.
1kV
LOGIC
Figure 36. Equivalent ESD Protection Digital Pins
A, B, W
20V
GND
Figure 37. Equivalent ESD Protection Analog Pins
/128
Ax
Wx
Bx
D0
D1
D2
D3
D4
D5
D6
RDAC
UP/DOWN
CNTR
&
DECODE
R
S
R
S
R
S
= R
R
S
NOMINAL
Figure 38. AD5220 Equivalent RDAC Circuit
PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation
The nominal resistance of the RDAC between terminals A and
B is available with values of 10 kΩ, 50 kΩ, and 100 kΩ. The
final three characters of the part number determine the nominal
resistance value, e.g., 10 kΩ =10; 50 kΩ = 50; 100 kΩ = 100.
The nominal resistance (R
) of the VR has 128 contact points
AB
accessed by the wiper terminal, plus the B terminal contact. At
power ON the resistance from the wiper to either end Terminal
A or B is approximately equal. Clocking the CLK pin will increase the resistance from the Wiper W to Terminal B by one
unit of R
resistance (see Figure 38). The resistance RWB is
S
determined by the number of pulses applied to the clock pin.
Each segment of the internal resistor string has a nominal resis-
= R
tance value of R
/128, which becomes 78 Ω in the case of
S
AB
the 10 kΩ AD5220BN10 product. Care should be taken to limit
the current flow between W and B in the direct contact state to
a maximum value of 5 mA to avoid degradation or possible destruction of the internal switch contact.
Like the mechanical potentiometer the RDAC replaces, it is
totally symmetrical (see Figure 38). The resistance between the
Wiper W and Terminal A also produces a digitally controlled
resistance R
. When these terminals are used the B–terminal
WA
should be tied to the wiper.
The typical part-to-part distribution of R
dent having a ±30% variation. The change in R
is process lot depen-
BA
with tempera-
BA
ture has a 800 ppm/°C temperature coefficient.
The R
temperature coefficient increases as the wiper is pro-
BA
grammed near the B-terminal due to the larger percentage contribution of the wiper contact switch resistance, which has a
0.5%/°C temperature coefficient. Figure 14 shows the effect of
the wiper contact resistance as a function of code setting. Another performance factor influenced by the switch contact resistance is the relative linearity error performance between the
10 kΩ, and the 50 kΩ or 100 kΩ versions. The same switch
contact resistance is used in all three versions. Thus the perfor-
mance of the 50 kΩ and 100 kΩ devices which have the least
impact on wiper switch resistance exhibits the best linearity
error, see Figures 7 and 8.
–8–
REV. 0
Page 9
AD5220
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates an output voltage
proportional to the input voltage applied to a given terminal.
For example connecting A Terminal to +5 V and B Terminal to
ground produces an output voltage at the wiper which can be
any value starting at zero volts up to 1 LSB less than +5 V. Each
LSB of voltage is equal to the voltage applied across terminals
AB divided by the 128-position resolution of the potentiometer
divider. The general equation defining the output voltage with
respect to ground for any given input voltage applied to terminals AB is:
V
(D) = D/128 × V
W
AB
+ V
B
(1)
D represents the current contents of the internal UP/DOWN
counter.
Operation of the digital potentiometer in the divider mode results in more accurate operation over temperature. Here the
output voltage is dependent on the ratio of the internal resistors,
not the absolute value, therefore, the drift improves to 20 ppm/°C.
APPLICATIONS INFORMATION
The negative-edge sensitive CLK pin does not contain any
internal debounce circuitry. This standard CMOS logic input
responds to fast negative edges and needs to be debounced
externally with an appropriate circuit designed for the type of
switch closure device being used. Good performance results at
the CLK input pin when the negative logic transition has a
minimum slew rate of 1 V/µs. A wide variety of standard circuits
can be used such as a one-shot multivibrator, Schmitt Triggered
gates, cross coupled flip-flops, or RC filters to drive the CLK
pin with uniform negative edges. This will prevent the digital
potentiometer from skipping output codes while counting due to
switch contact bounce.
–9–REV. 0
Page 10
AD5220
0.210 (5.33)
MAX
0.160 (4.06)
0.115 (2.93)
0.022 (0.558)
0.014 (0.356)
0.1574 (4.00)
0.1497 (3.80)
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead Plastic DIP
(N-8)
0.430 (10.92)
0.348 (8.84)
8
14
PIN 1
0.100
(2.54)
BSC
5
0.280 (7.11)
0.240 (6.10)
0.060 (1.52)
0.015 (0.38)
0.070 (1.77)
0.045 (1.15)
0.130
(3.30)
MIN
SEATING
PLANE
0.325 (8.25)
0.300 (7.62)
0.015 (0.381)
0.008 (0.204)
8-Lead SOIC
(SO-8)
0.1968 (5.00)
0.1890 (4.80)
8
5
0.2440 (6.20)
41
0.2284 (5.80)
C3426–8–10/98
0.195 (4.95)
0.115 (2.93)
PIN 1
0.0098 (0.25)
0.0040 (0.10)
SEATING
PLANE
0.122 (3.10)
0.114 (2.90)
PIN 1
0.006 (0.15)
0.002 (0.05)
SEATING
PLANE
0.0688 (1.75)
0.0532 (1.35)
0.0500
0.0192 (0.49)
(1.27)
0.0138 (0.35)
BSC
8-Lead SOIC
0.122 (3.10)
0.114 (2.90)
85
1
4
0.0256 (0.65) BSC
0.120 (3.05)
0.112 (2.84)
0.018 (0.46)
0.008 (0.20)
0.0098 (0.25)
0.0075 (0.19)
(RM-8)
0.199 (5.05)
0.187 (4.75)
0.043 (1.09)
0.037 (0.94)
0.011 (0.28)
0.003 (0.08)
0.0196 (0.50)
0.0099 (0.25)
88
08
0.0500 (1.27)
0.0160 (0.41)
0.120 (3.05)
0.112 (2.84)
338
278
3 458
0.028 (0.71)
0.016 (0.41)
PRINTED IN U.S.A.
–10–
REV. 0
Loading...